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r36780 Sunday 29th March, 2015 at 16:58:39 UTC by Couriersud

Added two more options to the build system: USE_QT: Compile the QT Debugger. Default is USE_QT=1 (except macosx), use USE_QT=0 to disable. LDOPTS: Optional LDFLAGs. These are mainly used for cross compilation. The following will compile a windows SDL build without QT debugger on linux: make    TARGETOS=windows PTR64=1 OSD=sdl OS=linux \      OVERRIDE_CC="@x86_64-w64-mingw32-gcc" \      OVERRIDE_CXX="@x86_64-w64-mingw32-g++" \      OVERRIDE_LD="x86_64-w64-mingw32-g++" \      WINDRES="x86_64-w64-mingw32-windres" \      USE_QT=0 \      ARCHOPTS="-idirafter ${MINGW64DIR}/x86_64-w64-mingw32/include/  \      -I${MINGW64DIR}/Qt/include/ -v" SUBTARGET=tiny MINGW64=/usr \ \      LDOPTS="-L/mnt/mfhome/andre/mame/w64crosslibs"

[/trunk]	makefile
[hash]	abc80.xml* abc80_cass.xml abc80_flop.xml
[scripts]	genie.lua
[scripts/src/osd]	sdl.lua sdl_cfg.lua windows.lua windows_cfg.lua
[src/emu/cpu/mips]	mips3.c mips3.h mips3drc.c
[src/emu/sound]	tms5220.c tms5220.h
[src/mame]	mame.lst
[src/mame/drivers]	cps2.c hng64.c kinst.c namcos23.c seattle.c vegas.c
[src/mame/machine]	cps2crpt.c n64.c
[src/mess/drivers]	abc80.c ticalc1x.c

trunk/hash/abc80.xml

r0	r245292
	1	<?xml version="1.0"?>
	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
	3	<softwarelist name="abc80" description="Luxor ABC 80 diskettes">
	4
	5	<software name="cpm" supported="no">
	6	<description>CP/M BIOS 3.7</description>
	7	<year>19??</year>
	8	<publisher>Myab</publisher>
	9
	10	<!-- Datadisc 80 format (8 sectors/track, 256 bytes/sector interleave, sector skew 5: 0 5 2 7 4 1 6 3) -->
	11	<part name="flop1" interface="floppy_5_25">
	12	<feature name="part_id" value="Side 0"/>
	13	<dataarea name="flop" size="81920">
	14	<rom name="cpmdisk_myab37_side0.img" size="81920" crc="7065fa91" sha1="f0ca7c2785bd92ed7ede46aaba8b8e2a2d826e47" offset="0" />
	15	</dataarea>
	16	</part>
	17
	18	<part name="flop2" interface="floppy_5_25">
	19	<feature name="part_id" value="Side 1"/>
	20	<dataarea name="flop" size="81920">
	21	<rom name="cpmdisk_myab37_side1.img" size="81920" crc="062e88c7" sha1="2d3baa1f225129474839972b9735444120965e08" offset="0" />
	22	</dataarea>
	23	</part>
	24	</software>
	25
	26	<software name="demo">
	27	<description>Demo</description>
	28	<year>19??</year>
	29	<publisher>Luxor</publisher>
	30
	31	<part name="flop1" interface="floppy_5_25">
	32	<dataarea name="flop" size="82895">
	33	<rom name="demo.td0" size="82895" crc="f581ce62" sha1="2e79e7371d767cb689d1e490f8e1c869dc390a03" offset="0" />
	34	</dataarea>
	35	</part>
	36	</software>
	37
	38	<software name="system10">
	39	<description>System disk v1.0</description>
	40	<year>19??</year>
	41	<publisher>Luxor</publisher>
	42
	43	<part name="flop1" interface="floppy_5_25">
	44	<dataarea name="flop" size="47013">
	45	<rom name="system10.td0" size="47013" crc="be80a5ca" sha1="64bea62668e9b2604732810c0704f52f6c8c3f99" offset="0" />
	46	</dataarea>
	47	</part>
	48	</software>
	49
	50	<software name="dosgen">
	51	<description>Dosgen</description>
	52	<year>19??</year>
	53	<publisher>&lt;unknown&gt;</publisher>
	54
	55	<part name="flop1" interface="floppy_5_25">
	56	<dataarea name="flop" size="10734">
	57	<rom name="fd2_dgen.imd" size="10734" crc="4c6ba75f" sha1="bb009d560089bdc0db2ab86634b4226956a96ac2" offset="0" />
	58	</dataarea>
	59	</part>
	60	</software>
	61
	62	<software name="kundreg">
	63	<description>Kundregister</description>
	64	<year>19??</year>
	65	<publisher>&lt;unknown&gt;</publisher>
	66
	67	<part name="flop1" interface="floppy_5_25">
	68	<dataarea name="flop" size="79143">
	69	<rom name="fd2_bifak.imd" size="79143" crc="a741ad5d" sha1="a0cb8cc31a30fcbea258dd5249845819930e60c2" offset="0" />
	70	</dataarea>
	71	</part>
	72	</software>
	73
	74	</softwarelist>

trunk/hash/abc80_cass.xml

r245291	r245292
1		<?xml version="1.0"?>
2		<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3		<softwarelist name="abc80_cass" description="Luxor ABC 80 cassettes">
4
5		<software name="abcdemo">
6		<description>ABCDemo</description>
7		<year>2015</year>
8		<publisher>Genesis Project</publisher>
9
10		<part name="cass1" interface="abc80_cass">
11		<dataarea name="cass" size="10793090">
12		<rom name="genesisproject_abcdemo.wav" size="10793090" crc="7642349f" sha1="a0a808e9c9c5f3ca162ef22869600e1c735846c2" offset="0" />
13		</dataarea>
14		</part>
15		</software>
16
17		</softwarelist>
		No newline at end of file

trunk/hash/abc80_flop.xml

r245291	r245292
1		<?xml version="1.0"?>
2		<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3		<softwarelist name="abc80_flop" description="Luxor ABC 80 diskettes">
4
5		<software name="cpm" supported="no">
6		<description>CP/M BIOS 3.7</description>
7		<year>19??</year>
8		<publisher>Myab</publisher>
9
10		<!-- Datadisc 80 format (8 sectors/track, 256 bytes/sector interleave, sector skew 5: 0 5 2 7 4 1 6 3) -->
11		<part name="flop1" interface="floppy_5_25">
12		<feature name="part_id" value="Side 0"/>
13		<dataarea name="flop" size="81920">
14		<rom name="cpmdisk_myab37_side0.img" size="81920" crc="7065fa91" sha1="f0ca7c2785bd92ed7ede46aaba8b8e2a2d826e47" offset="0" />
15		</dataarea>
16		</part>
17
18		<part name="flop2" interface="floppy_5_25">
19		<feature name="part_id" value="Side 1"/>
20		<dataarea name="flop" size="81920">
21		<rom name="cpmdisk_myab37_side1.img" size="81920" crc="062e88c7" sha1="2d3baa1f225129474839972b9735444120965e08" offset="0" />
22		</dataarea>
23		</part>
24		</software>
25
26		<software name="demo">
27		<description>Demo</description>
28		<year>19??</year>
29		<publisher>Luxor</publisher>
30
31		<part name="flop1" interface="floppy_5_25">
32		<dataarea name="flop" size="82895">
33		<rom name="demo.td0" size="82895" crc="f581ce62" sha1="2e79e7371d767cb689d1e490f8e1c869dc390a03" offset="0" />
34		</dataarea>
35		</part>
36		</software>
37
38		<software name="system10">
39		<description>System disk v1.0</description>
40		<year>19??</year>
41		<publisher>Luxor</publisher>
42
43		<part name="flop1" interface="floppy_5_25">
44		<dataarea name="flop" size="47013">
45		<rom name="system10.td0" size="47013" crc="be80a5ca" sha1="64bea62668e9b2604732810c0704f52f6c8c3f99" offset="0" />
46		</dataarea>
47		</part>
48		</software>
49
50		<software name="dosgen">
51		<description>Dosgen</description>
52		<year>19??</year>
53		<publisher>&lt;unknown&gt;</publisher>
54
55		<part name="flop1" interface="floppy_5_25">
56		<dataarea name="flop" size="10734">
57		<rom name="fd2_dgen.imd" size="10734" crc="4c6ba75f" sha1="bb009d560089bdc0db2ab86634b4226956a96ac2" offset="0" />
58		</dataarea>
59		</part>
60		</software>
61
62		<software name="kundreg">
63		<description>Kundregister</description>
64		<year>19??</year>
65		<publisher>&lt;unknown&gt;</publisher>
66
67		<part name="flop1" interface="floppy_5_25">
68		<dataarea name="flop" size="79143">
69		<rom name="fd2_bifak.imd" size="79143" crc="a741ad5d" sha1="a0cb8cc31a30fcbea258dd5249845819930e60c2" offset="0" />
70		</dataarea>
71		</part>
72		</software>
73
74		<software name="abcdemo">
75		<description>ABCDemo</description>
76		<year>2015</year>
77		<publisher>Genesis Project</publisher>
78
79		<part name="flop1" interface="floppy_5_25">
80		<dataarea name="flop" size="163840">
81		<rom name="genesisproject_abcdemo.dsk" size="163840" crc="29059d3c" sha1="55b38436a2d3cfe1caf8e35e44775402a1511eec" offset="0" />
82		</dataarea>
83		</part>
84		</software>
85
86		</softwarelist>

trunk/makefile

r245291	r245292
319	319	PARAMS+= --targetos=$(TARGETOS)
320	320	endif
321	321
	322	ifdef USE_QT
	323	PARAMS+= --USE_QT=$(USE_QT)
	324	else
	325	ifneq ($(TARGETOS),macosx)
	326	PARAMS+= --USE_QT=1
	327	else
	328	PARAMS+= --USE_QT=0
	329	endif
	330	endif
	331
	332	ifdef LDOPTS
	333	PARAMS+= --LDOPTS='$(LDOPTS)'
	334	endif
	335
322	336	# extension for executables
323	337	EXE =
324	338
r245291	r245292
367	381
368	382	ifeq ($(TARGETOS),macosx)
369	383	ifneq (,$(findstring 3.,$(CLANG_VERSION)))
370		ifeq ($(ARCHITECTURE),_x64)
	384	ifeq ($(ARCHITECTURE),x64)
371	385	ARCHITECTURE=_x64_clang
372	386	else
373	387	ARCHITECTURE=_x86_clang
r245291	r245292
590	604	$(SILENT) $(MAKE) --no-print-directory -R -C build/projects/$(SUBDIR)/gmake-osx-clang config=$(CONFIG)32
591	605
592	606	$(GENIE):
593		$(SILENT) $(MAKE) --no-print-directory -R -C 3rdparty/genie/build/gmake.$(GENIEOS) -f genie.make
	607	$(SILENT) $(MAKE) --no-print-directory -R -C 3rdparty/genie/build/gmake.$(OS) -f genie.make
594	608
595	609	clean:
596	610	@echo Cleaning...
597	611	-@rm -rf build
598		$(SILENT) $(MAKE) --no-print-directory -R -C 3rdparty/genie/build/gmake.$(GENIEOS) -f genie.make clean
	612	$(SILENT) $(MAKE) --no-print-directory -R -C 3rdparty/genie/build/gmake.$(OS) -f genie.make clean
599	613
600	614	GEN_FOLDERS :=  \
601	615	$(GENDIR) \

trunk/scripts/genie.lua

r245291	r245292
158	158	}
159	159
160	160	newoption {
	161	trigger = "LDOPTS",
	162	description = "Additional linker options",
	163	}
	164
	165	newoption {
161	166	trigger = "MAP",
162	167	description = "Generate a link map.",
163	168	}
r245291	r245292
181	186	}
182	187	}
183	188
	189	newoption {
	190	trigger = "USE_QT",
	191	description = "Use of QT.",
	192	allowed = {
	193	{ "0",   "Disabled"    },
	194	{ "1",   "Enabled"      },
	195	}
	196	}
184	197
185	198	local os_version = str_to_version(_OPTIONS["os_version"])
186	199
r245291	r245292
192	205	USE_BGFX = tonumber(_OPTIONS["USE_BGFX"])
193	206	end
194	207
	208	USE_QT = 1
	209	if(_OPTIONS["USE_QT"]~=nil) then
	210	USE_QT = tonumber(_OPTIONS["USE_QT"])
	211	end
	212
195	213	GEN_DIR = MAME_BUILD_DIR .. "generated/"
196	214
197	215	if (_OPTIONS["target"] == nil) then return false end
r245291	r245292
514	532	--CCOMFLAGS += -Wno-unknown-pragmas
515	533	--endif
516	534
	535	if _OPTIONS["LDOPTS"] then
	536	linkoptions {
	537	_OPTIONS["LDOPTS"]
	538	}
	539	end
	540
517	541	if _OPTIONS["MAP"] then
518	542	if (_OPTIONS["target"] == _OPTIONS["subtarget"]) then
519	543	linkoptions {
r245291	r245292
702	726
703	727	configuration { "osx*" }
704	728	links {
705		"SDL2.framework",
706	729	"Cocoa.framework",
707	730	"OpenGL.framework",
708	731	"CoreAudio.framework",
709	732	"CoreMIDI.framework",
	733	"SDL2.framework",
710	734	"pthread",
711	735	}
712		buildoptions {
713		"-F/Library/Frameworks/",
714		}
715		linkoptions {
716		"-F/Library/Frameworks/",
717		}
718	736
719	737
720	738	configuration { "mingw*" }
	739	defines {
	740	"main=utf8_main",
	741	}
721	742	linkoptions {
722	743	"-static-libgcc",
723	744	"-static-libstdc++",
	745	"-municode",
724	746	}
725	747	if _OPTIONS["osd"]=="sdl" then
726	748	links {
727	749	"opengl32",
728	750	"SDL2",
729		"Imm32",
	751	"imm32",
730	752	"version",
731	753	"ole32",
732	754	"oleaut32",
r245291	r245292
748	770
749	771	configuration { "vs*" }
750	772	defines {
	773	"main=utf8_main",
	774	}
	775	defines {
751	776	"XML_STATIC",
752	777	"WIN32",
753	778	"_WIN32",

trunk/scripts/src/osd/sdl.lua

r245291	r245292
1	1	function maintargetosdoptions(_target)
2		if _OPTIONS["targetos"]=="windows" then
3		linkoptions{
4		"-municode",
5		"-L$(shell qmake -query QT_INSTALL_LIBS)",
6		}
	2	if (USE_QT == 1) then
	3	if _OPTIONS["targetos"]=="windows" then
	4	linkoptions{
	5	"-L$(shell qmake -query QT_INSTALL_LIBS)",
	6	}
7	7
8		links {
9		"qtmain",
10		"QtGui4",
11		"QtCore4",
12		}
13		end
	8	links {
	9	"qtmain",
	10	"QtGui4",
	11	"QtCore4",
	12	}
	13	end
14	14
15		if _OPTIONS["targetos"]=="linux" then
16		links {
17		'QtGui',
18		'QtCore',
19		}
	15	if _OPTIONS["targetos"]=="linux" then
	16	links {
	17	'QtGui',
	18	'QtCore',
	19	}
20	20
21		linkoptions {
22		'$(shell pkg-config --libs QtGui)',
23		}
	21	linkoptions {
	22	'$(shell pkg-config --libs QtGui)',
	23	}
	24	end
24	25	end
25
	26
26	27	configuration { "mingw*" or "vs*" }
27	28	targetprefix "sdl"
28	29
29	30	configuration { }
30	31	end
31	32
32
33	33	configuration { "mingw*" }
34	34	linkoptions {
35	35	"-Wl,--allow-multiple-definition",
r245291	r245292
116	116	MAME_DIR .. "src/osd/modules/opengl/gl_shader_mgr.c",
117	117	}
118	118
119		if not (_OPTIONS["targetos"]=="macosx") then
	119	if (USE_QT == 1) then
120	120	files {
121	121	MAME_DIR .. "src/osd/modules/debugger/qt/debuggerview.c",
122	122	MAME_DIR .. "src/osd/modules/debugger/qt/windowqt.c",

trunk/scripts/src/osd/sdl_cfg.lua

r245291	r245292
11	11	"SDLMAME_SDL2=1",
12	12	"USE_XINPUT=0",
13	13	"USE_OPENGL=1",
14		"USE_QTDEBUG=1",
	14	"USE_QTDEBUG=" .. USE_QT,
15	15	"SDLMAME_NET_PCAP",
16		"main=utf8_main",
17	16	}
18	17
19	18	buildoptions {
r245291	r245292
31	30	"SDLMAME_SDL2=1",
32	31	"USE_XINPUT=0",
33	32	"USE_OPENGL=1",
34		"USE_QTDEBUG=1",
	33	"USE_QTDEBUG=" .. USE_QT,
35	34	"SDLMAME_NET_TAPTUN",
36	35	}
37	36

trunk/scripts/src/osd/windows.lua

r245291	r245292
1	1	function maintargetosdoptions(_target)
2		linkoptions {
3		"-municode",
4		}
5
6	2	local rcfile = MAME_DIR .. "src/" .. _target .. "/osd/windows/" .. _target ..".rc"
7	3
8	4	if os.isfile(rcfile) then

trunk/scripts/src/osd/windows_cfg.lua

r245291	r245292
12	12	"USE_DISPATCH_GL=1",
13	13	"DIRECTINPUT_VERSION=0x0800",
14	14	"SDLMAME_NET_PCAP",
15		"main=utf8_main",
16	15	}

trunk/src/emu/cpu/mips/mips3.c

r245291	r245292
148	148	, m_pfnmask(0)
149	149	, m_tlbentries(0)
150	150	, m_bigendian(endianness == ENDIANNESS_BIG)
151		, m_byte_xor(m_bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0))
152		, m_word_xor(m_bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0))
153	151	, c_icache_size(0)
154	152	, c_dcache_size(0)
155	153	, m_vtlb(NULL)
156		, m_fastram_select(0)
157	154	, m_debugger_temp(0)
158	155	, m_cache(CACHE_SIZE + sizeof(internal_mips3_state))
159	156	, m_drcuml(NULL)
r245291	r245292
164	161	, m_nocode(NULL)
165	162	, m_out_of_cycles(NULL)
166	163	, m_tlb_mismatch(NULL)
	164	, m_fastram_select(0)
167	165	, m_hotspot_select(0)
168	166	{
169	167	memset(m_fpmode, 0, sizeof(m_fpmode));
r245291	r245292
998	996	TLB HANDLING
999	997	***************************************************************************/
1000	998
1001		bool mips3_device::RBYTE(offs_t address, UINT32 *result)
	999	inline int mips3_device::RBYTE(offs_t address, UINT32 *result)
1002	1000	{
1003		const UINT32 tlbval = m_tlb_table[address >> 12];
	1001	UINT32 tlbval = m_tlb_table[address >> 12];
1004	1002	if (tlbval & VTLB_READ_ALLOWED)
1005	1003	{
1006		const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
1007		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
1008		{
1009		if (tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
1010		{
1011		continue;
1012		}
1013		UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
1014		*result = fastbase[tlbaddress ^ m_byte_xor];
1015		return true;
1016		}
1017		*result = (*m_memory.read_byte)(*m_program, tlbaddress);
	1004	*result = (*m_memory.read_byte)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
1018	1005	}
1019	1006	else
1020	1007	{
r245291	r245292
1027	1014	generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
1028	1015	}
1029	1016	*result = 0;
1030		return false;
	1017	return 0;
1031	1018	}
1032		return true;
	1019	return 1;
1033	1020	}
1034	1021
1035		bool mips3_device::RHALF(offs_t address, UINT32 *result)
	1022
	1023	inline int mips3_device::RHALF(offs_t address, UINT32 *result)
1036	1024	{
1037		const UINT32 tlbval = m_tlb_table[address >> 12];
	1025	UINT32 tlbval = m_tlb_table[address >> 12];
1038	1026	if (tlbval & VTLB_READ_ALLOWED)
1039	1027	{
1040		const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
1041		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
1042		{
1043		if (tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
1044		{
1045		continue;
1046		}
1047		UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
1048		*result = ((UINT16*)fastbase)[(tlbaddress ^ m_word_xor) >> 1];
1049		return true;
1050		}
1051		*result = (*m_memory.read_word)(*m_program, tlbaddress);
	1028	*result = (*m_memory.read_word)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
1052	1029	}
1053	1030	else
1054	1031	{
r245291	r245292
1061	1038	generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
1062	1039	}
1063	1040	*result = 0;
1064		return false;
	1041	return 0;
1065	1042	}
1066		return true;
	1043	return 1;
1067	1044	}
1068	1045
1069		bool mips3_device::RWORD(offs_t address, UINT32 *result)
	1046
	1047	inline int mips3_device::RWORD(offs_t address, UINT32 *result)
1070	1048	{
1071		const UINT32 tlbval = m_tlb_table[address >> 12];
	1049	UINT32 tlbval = m_tlb_table[address >> 12];
1072	1050	if (tlbval & VTLB_READ_ALLOWED)
1073	1051	{
1074		const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
1075		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
1076		{
1077		if (tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
1078		{
1079		continue;
1080		}
1081		UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
1082		*result = ((UINT32*)fastbase)[tlbaddress >> 2];
1083		return true;
1084		}
1085		*result = (*m_memory.read_dword)(*m_program, tlbaddress);
	1052	*result = (*m_memory.read_dword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
1086	1053	}
1087	1054	else
1088	1055	{
r245291	r245292
1095	1062	generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
1096	1063	}
1097	1064	*result = 0;
1098		return false;
	1065	return 0;
1099	1066	}
1100		return true;
	1067	return 1;
1101	1068	}
1102	1069
1103		bool mips3_device::RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask)
	1070
	1071	inline int mips3_device::RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask)
1104	1072	{
1105		const UINT32 tlbval = m_tlb_table[address >> 12];
	1073	UINT32 tlbval = m_tlb_table[address >> 12];
1106	1074	if (tlbval & VTLB_READ_ALLOWED)
1107	1075	{
1108	1076	*result = (*m_memory.read_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask);
r245291	r245292
1118	1086	generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
1119	1087	}
1120	1088	*result = 0;
1121		return false;
	1089	return 0;
1122	1090	}
1123		return true;
	1091	return 1;
1124	1092	}
1125	1093
1126		bool mips3_device::RDOUBLE(offs_t address, UINT64 *result)
	1094
	1095	inline int mips3_device::RDOUBLE(offs_t address, UINT64 *result)
1127	1096	{
1128		const UINT32 tlbval = m_tlb_table[address >> 12];
	1097	UINT32 tlbval = m_tlb_table[address >> 12];
1129	1098	if (tlbval & VTLB_READ_ALLOWED)
1130	1099	{
1131	1100	*result = (*m_memory.read_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
r245291	r245292
1141	1110	generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
1142	1111	}
1143	1112	*result = 0;
1144		return false;
	1113	return 0;
1145	1114	}
1146		return true;
	1115	return 1;
1147	1116	}
1148	1117
1149		bool mips3_device::RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask)
	1118
	1119	inline int mips3_device::RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask)
1150	1120	{
1151		const UINT32 tlbval = m_tlb_table[address >> 12];
	1121	UINT32 tlbval = m_tlb_table[address >> 12];
1152	1122	if (tlbval & VTLB_READ_ALLOWED)
1153	1123	{
1154	1124	*result = (*m_memory.read_qword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask);
r245291	r245292
1164	1134	generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
1165	1135	}
1166	1136	*result = 0;
1167		return false;
	1137	return 0;
1168	1138	}
1169		return true;
	1139	return 1;
1170	1140	}
1171	1141
1172		void mips3_device::WBYTE(offs_t address, UINT8 data)
	1142
	1143	inline void mips3_device::WBYTE(offs_t address, UINT8 data)
1173	1144	{
1174		const UINT32 tlbval = m_tlb_table[address >> 12];
	1145	UINT32 tlbval = m_tlb_table[address >> 12];
1175	1146	if (tlbval & VTLB_WRITE_ALLOWED)
1176	1147	{
1177		const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
1178		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
1179		{
1180		if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
1181		{
1182		continue;
1183		}
1184		UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
1185		fastbase[tlbaddress ^ m_byte_xor] = data;
1186		return;
1187		}
1188		(*m_memory.write_byte)(*m_program, tlbaddress, data);
	1148	(*m_memory.write_byte)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
1189	1149	}
1190	1150	else
1191	1151	{
r245291	r245292
1204	1164	}
1205	1165	}
1206	1166
1207		void mips3_device::WHALF(offs_t address, UINT16 data)
	1167
	1168	inline void mips3_device::WHALF(offs_t address, UINT16 data)
1208	1169	{
1209		const UINT32 tlbval = m_tlb_table[address >> 12];
	1170	UINT32 tlbval = m_tlb_table[address >> 12];
1210	1171	if (tlbval & VTLB_WRITE_ALLOWED)
1211	1172	{
1212		const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
1213		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
1214		{
1215		if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
1216		{
1217		continue;
1218		}
1219		void *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
1220		((UINT16*)fastbase)[(tlbaddress ^ m_word_xor) >> 1] = data;
1221		return;
1222		}
1223		(*m_memory.write_word)(*m_program, tlbaddress, data);
	1173	(*m_memory.write_word)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
1224	1174	}
1225	1175	else
1226	1176	{
r245291	r245292
1239	1189	}
1240	1190	}
1241	1191
1242		void mips3_device::WWORD(offs_t address, UINT32 data)
	1192
	1193	inline void mips3_device::WWORD(offs_t address, UINT32 data)
1243	1194	{
1244		const UINT32 tlbval = m_tlb_table[address >> 12];
	1195	UINT32 tlbval = m_tlb_table[address >> 12];
1245	1196	if (tlbval & VTLB_WRITE_ALLOWED)
1246	1197	{
1247		const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
1248		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
1249		{
1250		if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
1251		{
1252		continue;
1253		}
1254		void *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
1255		((UINT32*)fastbase)[tlbaddress >> 2] = data;
1256		return;
1257		}
1258		(*m_memory.write_dword)(*m_program, tlbaddress, data);
	1198	(*m_memory.write_dword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
1259	1199	}
1260	1200	else
1261	1201	{
r245291	r245292
1274	1214	}
1275	1215	}
1276	1216
1277		void mips3_device::WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask)
	1217
	1218	inline void mips3_device::WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask)
1278	1219	{
1279		const UINT32 tlbval = m_tlb_table[address >> 12];
	1220	UINT32 tlbval = m_tlb_table[address >> 12];
1280	1221	if (tlbval & VTLB_WRITE_ALLOWED)
1281	1222	{
1282	1223	(*m_memory.write_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask);
r245291	r245292
1298	1239	}
1299	1240	}
1300	1241
1301		void mips3_device::WDOUBLE(offs_t address, UINT64 data)
	1242
	1243	inline void mips3_device::WDOUBLE(offs_t address, UINT64 data)
1302	1244	{
1303		const UINT32 tlbval = m_tlb_table[address >> 12];
	1245	UINT32 tlbval = m_tlb_table[address >> 12];
	1246	//printf("%08x: %08x\n", (UINT32)address, (UINT32)tlbval);
1304	1247	if (tlbval & VTLB_WRITE_ALLOWED)
1305	1248	{
1306		(*m_memory.write_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
	1249	(*m_memory.write_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
1307	1250	}
1308	1251	else
1309	1252	{
r245291	r245292
1322	1265	}
1323	1266	}
1324	1267
1325		void mips3_device::WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask)
	1268
	1269	inline void mips3_device::WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask)
1326	1270	{
1327		const UINT32 tlbval = m_tlb_table[address >> 12];
	1271	UINT32 tlbval = m_tlb_table[address >> 12];
1328	1272	if (tlbval & VTLB_WRITE_ALLOWED)
1329	1273	{
1330	1274	(*m_memory.write_qword_masked)(*m_program, (tlbval & ~0xfff)  | (address & 0xfff), data, mem_mask);
r245291	r245292
1352	1296	COP0 (SYSTEM) EXECUTION HANDLING
1353	1297	***************************************************************************/
1354	1298
1355		UINT64 mips3_device::get_cop0_reg(int idx)
	1299	inline UINT64 mips3_device::get_cop0_reg(int idx)
1356	1300	{
1357	1301	if (idx == COP0_Count)
1358	1302	{
r245291	r245292
1385	1329	return m_core->cpr[0][idx];
1386	1330	}
1387	1331
1388		void mips3_device::set_cop0_reg(int idx, UINT64 val)
	1332	inline void mips3_device::set_cop0_reg(int idx, UINT64 val)
1389	1333	{
1390	1334	switch (idx)
1391	1335	{
r245291	r245292
1462	1406	m_core->ccr[0][idx] = val;
1463	1407	}
1464	1408
1465		void mips3_device::handle_cop0(UINT32 op)
	1409	inline void mips3_device::handle_cop0(UINT32 op)
1466	1410	{
1467	1411	if ((SR & SR_KSU_MASK) != SR_KSU_KERNEL && !(SR & SR_COP0))
1468	1412	{
r245291	r245292
1597	1541	}
1598	1542	}
1599	1543
1600		void mips3_device::handle_cop1_fr0(UINT32 op)
	1544	inline void mips3_device::handle_cop1_fr0(UINT32 op)
1601	1545	{
1602	1546	double dtemp;
1603	1547
r245291	r245292
1956	1900	}
1957	1901
1958	1902
1959		void mips3_device::handle_cop1_fr1(UINT32 op)
	1903	inline void mips3_device::handle_cop1_fr1(UINT32 op)
1960	1904	{
1961	1905	double dtemp;
1962	1906
r245291	r245292
2320	2264	COP1X (FPU EXTRA) EXECUTION HANDLING
2321	2265	***************************************************************************/
2322	2266
2323		void mips3_device::handle_cop1x_fr0(UINT32 op)
	2267	inline void mips3_device::handle_cop1x_fr0(UINT32 op)
2324	2268	{
2325	2269	UINT64 temp64;
2326	2270	UINT32 temp;
r245291	r245292
2398	2342	}
2399	2343	}
2400	2344
2401		void mips3_device::handle_cop1x_fr1(UINT32 op)
	2345
	2346	inline void mips3_device::handle_cop1x_fr1(UINT32 op)
2402	2347	{
2403	2348	UINT64 temp64;
2404	2349	UINT32 temp;
r245291	r245292
2502	2447	m_core->ccr[2][idx] = val;
2503	2448	}
2504	2449
2505		void mips3_device::handle_cop2(UINT32 op)
	2450	inline void mips3_device::handle_integer_divide_by_zero(UINT32 op)
2506	2451	{
	2452	HIVAL64 = (INT32)RSVAL32;
	2453	if (m_flavor == MIPS3_TYPE_VR4300)
	2454	{
	2455	if (RSVAL32 >= 0)
	2456	{
	2457	LOVAL64 = (INT32)0x7fffffff;
	2458	}
	2459	else
	2460	{
	2461	LOVAL64 = (INT32)0x80000001;
	2462	}
	2463	}
	2464	else
	2465	{
	2466	if (RSVAL32 >= 0)
	2467	{
	2468	LOVAL64 = -1;
	2469	}
	2470	else
	2471	{
	2472	LOVAL64 = 1;
	2473	}
	2474	}
	2475	}
	2476
	2477	inline void mips3_device::handle_cop2(UINT32 op)
	2478	{
2507	2479	if (!(SR & SR_COP2))
2508	2480	{
2509	2481	m_badcop_value = 2;
r245291	r245292
2554	2526	CORE EXECUTION LOOP
2555	2527	***************************************************************************/
2556	2528
2557		void mips3_device::handle_regimm(UINT32 op)
2558		{
2559		switch (RTREG)
2560		{
2561		case 0x00:  /* BLTZ */      if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL);                         break;
2562		case 0x01:  /* BGEZ */      if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL);                        break;
2563		case 0x02:  /* BLTZL */     if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4;        break;
2564		case 0x03:  /* BGEZL */     if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4;   break;
2565		case 0x08:  /* TGEI */      if ((INT64)RSVAL64 >= SIMMVAL) generate_exception(EXCEPTION_TRAP, 1);   break;
2566		case 0x09:  /* TGEIU */     if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
2567		case 0x0a:  /* TLTI */      if ((INT64)RSVAL64 < SIMMVAL) generate_exception(EXCEPTION_TRAP, 1);    break;
2568		case 0x0b:  /* TLTIU */     if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
2569		case 0x0c:  /* TEQI */      if (RSVAL64 == UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
2570		case 0x0e:  /* TNEI */      if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
2571		case 0x10:  /* BLTZAL */    if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31);                     break;
2572		case 0x11:  /* BGEZAL */    if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31);                    break;
2573		case 0x12:  /* BLTZALL */   if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break;
2574		case 0x13:  /* BGEZALL */   if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4;    break;
2575		default:    /* ??? */       invalid_instruction(op);                                        break;
2576		}
2577		}
2578
2579		void mips3_device::handle_special(UINT32 op)
2580		{
2581		switch (op & 63)
2582		{
2583		case 0x00:  /* SLL */       if (RDREG) RDVAL64 = (INT32)(RTVAL32 << SHIFT);                 break;
2584		case 0x01:  /* MOVF - R5000*/if (RDREG && GET_FCC((op >> 18) & 7) == ((op >> 16) & 1)) RDVAL64 = RSVAL64;   break;
2585		case 0x02:  /* SRL */       if (RDREG) RDVAL64 = (INT32)(RTVAL32 >> SHIFT);                 break;
2586		case 0x03:  /* SRA */       if (RDREG) RDVAL64 = (INT32)RTVAL32 >> SHIFT;                   break;
2587		case 0x04:  /* SLLV */      if (RDREG) RDVAL64 = (INT32)(RTVAL32 << (RSVAL32 & 31));        break;
2588		case 0x06:  /* SRLV */      if (RDREG) RDVAL64 = (INT32)(RTVAL32 >> (RSVAL32 & 31));        break;
2589		case 0x07:  /* SRAV */      if (RDREG) RDVAL64 = (INT32)RTVAL32 >> (RSVAL32 & 31);          break;
2590		case 0x08:  /* JR */        SETPC(RSVAL32);                                                 break;
2591		case 0x09:  /* JALR */      SETPCL(RSVAL32,RDREG);                                          break;
2592		case 0x0a:  /* MOVZ - R5000 */if (RTVAL64 == 0) { if (RDREG) RDVAL64 = RSVAL64; }           break;
2593		case 0x0b:  /* MOVN - R5000 */if (RTVAL64 != 0) { if (RDREG) RDVAL64 = RSVAL64; }           break;
2594		case 0x0c:  /* SYSCALL */   generate_exception(EXCEPTION_SYSCALL, 1);                       break;
2595		case 0x0d:  /* BREAK */     generate_exception(EXCEPTION_BREAK, 1);                         break;
2596		case 0x0f:  /* SYNC */      /* effective no-op */                                           break;
2597		case 0x10:  /* MFHI */      if (RDREG) RDVAL64 = HIVAL64;                                   break;
2598		case 0x11:  /* MTHI */      HIVAL64 = RSVAL64;                                              break;
2599		case 0x12:  /* MFLO */      if (RDREG) RDVAL64 = LOVAL64;                                   break;
2600		case 0x13:  /* MTLO */      LOVAL64 = RSVAL64;                                              break;
2601		case 0x14:  /* DSLLV */     if (RDREG) RDVAL64 = RTVAL64 << (RSVAL32 & 63);                 break;
2602		case 0x16:  /* DSRLV */     if (RDREG) RDVAL64 = RTVAL64 >> (RSVAL32 & 63);                 break;
2603		case 0x17:  /* DSRAV */     if (RDREG) RDVAL64 = (INT64)RTVAL64 >> (RSVAL32 & 63);          break;
2604		case 0x18:  /* MULT */
2605		{
2606		UINT64 temp64 = (INT64)(INT32)RSVAL32 * (INT64)(INT32)RTVAL32;
2607		LOVAL64 = (INT32)temp64;
2608		HIVAL64 = (INT32)(temp64 >> 32);
2609		m_core->icount -= 3;
2610		break;
2611		}
2612		case 0x19:  /* MULTU */
2613		{
2614		UINT64 temp64 = (UINT64)RSVAL32 * (UINT64)RTVAL32;
2615		LOVAL64 = (INT32)temp64;
2616		HIVAL64 = (INT32)(temp64 >> 32);
2617		m_core->icount -= 3;
2618		break;
2619		}
2620		case 0x1a:  /* DIV */
2621		if (RTVAL32)
2622		{
2623		LOVAL64 = (INT32)((INT32)RSVAL32 / (INT32)RTVAL32);
2624		HIVAL64 = (INT32)((INT32)RSVAL32 % (INT32)RTVAL32);
2625		}
2626		m_core->icount -= 35;
2627		break;
2628		case 0x1b:  /* DIVU */
2629		if (RTVAL32)
2630		{
2631		LOVAL64 = (INT32)(RSVAL32 / RTVAL32);
2632		HIVAL64 = (INT32)(RSVAL32 % RTVAL32);
2633		}
2634		m_core->icount -= 35;
2635		break;
2636		case 0x1c:  /* DMULT */
2637		{
2638		UINT64 temp64 = (INT64)RSVAL64 * (INT64)RTVAL64;
2639		LOVAL64 = temp64;
2640		HIVAL64 = (INT64)temp64 >> 63;
2641		m_core->icount -= 7;
2642		break;
2643		}
2644		case 0x1d:  /* DMULTU */
2645		{
2646		UINT64 temp64 = (UINT64)RSVAL64 * (UINT64)RTVAL64;
2647		LOVAL64 = temp64;
2648		HIVAL64 = 0;
2649		m_core->icount -= 7;
2650		break;
2651		}
2652		case 0x1e:  /* DDIV */
2653		if (RTVAL64)
2654		{
2655		LOVAL64 = (INT64)RSVAL64 / (INT64)RTVAL64;
2656		HIVAL64 = (INT64)RSVAL64 % (INT64)RTVAL64;
2657		}
2658		m_core->icount -= 67;
2659		break;
2660		case 0x1f:  /* DDIVU */
2661		if (RTVAL64)
2662		{
2663		LOVAL64 = RSVAL64 / RTVAL64;
2664		HIVAL64 = RSVAL64 % RTVAL64;
2665		}
2666		m_core->icount -= 67;
2667		break;
2668		case 0x20:  /* ADD */
2669		if (ENABLE_OVERFLOWS && RSVAL32 > ~RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
2670		else if (RDREG) RDVAL64 = (INT32)(RSVAL32 + RTVAL32);
2671		break;
2672		case 0x21:  /* ADDU */      if (RDREG) RDVAL64 = (INT32)(RSVAL32 + RTVAL32);                break;
2673		case 0x22:  /* SUB */
2674		if (ENABLE_OVERFLOWS && RSVAL32 < RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
2675		else if (RDREG) RDVAL64 = (INT32)(RSVAL32 - RTVAL32);
2676		break;
2677		case 0x23:  /* SUBU */      if (RDREG) RDVAL64 = (INT32)(RSVAL32 - RTVAL32);                break;
2678		case 0x24:  /* AND */       if (RDREG) RDVAL64 = RSVAL64 & RTVAL64;                         break;
2679		case 0x25:  /* OR */        if (RDREG) RDVAL64 = RSVAL64 | RTVAL64;                         break;
2680		case 0x26:  /* XOR */       if (RDREG) RDVAL64 = RSVAL64 ^ RTVAL64;                         break;
2681		case 0x27:  /* NOR */       if (RDREG) RDVAL64 = ~(RSVAL64 | RTVAL64);                      break;
2682		case 0x2a:  /* SLT */       if (RDREG) RDVAL64 = (INT64)RSVAL64 < (INT64)RTVAL64;           break;
2683		case 0x2b:  /* SLTU */      if (RDREG) RDVAL64 = (UINT64)RSVAL64 < (UINT64)RTVAL64;         break;
2684		case 0x2c:  /* DADD */
2685		if (ENABLE_OVERFLOWS && RSVAL64 > ~RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
2686		else if (RDREG) RDVAL64 = RSVAL64 + RTVAL64;
2687		break;
2688		case 0x2d:  /* DADDU */     if (RDREG) RDVAL64 = RSVAL64 + RTVAL64;                         break;
2689		case 0x2e:  /* DSUB */
2690		if (ENABLE_OVERFLOWS && RSVAL64 < RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
2691		else if (RDREG) RDVAL64 = RSVAL64 - RTVAL64;
2692		break;
2693		case 0x2f:  /* DSUBU */     if (RDREG) RDVAL64 = RSVAL64 - RTVAL64;                         break;
2694		case 0x30:  /* TGE */       if ((INT64)RSVAL64 >= (INT64)RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
2695		case 0x31:  /* TGEU */      if (RSVAL64 >= RTVAL64) generate_exception(EXCEPTION_TRAP, 1);  break;
2696		case 0x32:  /* TLT */       if ((INT64)RSVAL64 < (INT64)RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
2697		case 0x33:  /* TLTU */      if (RSVAL64 < RTVAL64) generate_exception(EXCEPTION_TRAP, 1);   break;
2698		case 0x34:  /* TEQ */       if (RSVAL64 == RTVAL64) generate_exception(EXCEPTION_TRAP, 1);  break;
2699		case 0x36:  /* TNE */       if (RSVAL64 != RTVAL64) generate_exception(EXCEPTION_TRAP, 1);  break;
2700		case 0x38:  /* DSLL */      if (RDREG) RDVAL64 = RTVAL64 << SHIFT;                          break;
2701		case 0x3a:  /* DSRL */      if (RDREG) RDVAL64 = RTVAL64 >> SHIFT;                          break;
2702		case 0x3b:  /* DSRA */      if (RDREG) RDVAL64 = (INT64)RTVAL64 >> SHIFT;                   break;
2703		case 0x3c:  /* DSLL32 */    if (RDREG) RDVAL64 = RTVAL64 << (SHIFT + 32);                   break;
2704		case 0x3e:  /* DSRL32 */    if (RDREG) RDVAL64 = RTVAL64 >> (SHIFT + 32);                   break;
2705		case 0x3f:  /* DSRA32 */    if (RDREG) RDVAL64 = (INT64)RTVAL64 >> (SHIFT + 32);            break;
2706		default:    /* ??? */       invalid_instruction(op);                                        break;
2707		}
2708		}
2709
2710	2529	void mips3_device::execute_run()
2711	2530	{
2712	2531	if (m_isdrc)
r245291	r245292
2783	2602	switch (op >> 26)
2784	2603	{
2785	2604	case 0x00:  /* SPECIAL */
2786		handle_special(op);
	2605	switch (op & 63)
	2606	{
	2607	case 0x00:  /* SLL */       if (RDREG) RDVAL64 = (INT32)(RTVAL32 << SHIFT);                 break;
	2608	case 0x01:  /* MOVF - R5000*/if (RDREG && GET_FCC((op >> 18) & 7) == ((op >> 16) & 1)) RDVAL64 = RSVAL64;   break;
	2609	case 0x02:  /* SRL */       if (RDREG) RDVAL64 = (INT32)(RTVAL32 >> SHIFT);                 break;
	2610	case 0x03:  /* SRA */       if (RDREG) RDVAL64 = (INT32)RTVAL32 >> SHIFT;                   break;
	2611	case 0x04:  /* SLLV */      if (RDREG) RDVAL64 = (INT32)(RTVAL32 << (RSVAL32 & 31));        break;
	2612	case 0x06:  /* SRLV */      if (RDREG) RDVAL64 = (INT32)(RTVAL32 >> (RSVAL32 & 31));        break;
	2613	case 0x07:  /* SRAV */      if (RDREG) RDVAL64 = (INT32)RTVAL32 >> (RSVAL32 & 31);          break;
	2614	case 0x08:  /* JR */        SETPC(RSVAL32);                                                 break;
	2615	case 0x09:  /* JALR */      SETPCL(RSVAL32,RDREG);                                          break;
	2616	case 0x0a:  /* MOVZ - R5000 */if (RTVAL64 == 0) { if (RDREG) RDVAL64 = RSVAL64; }           break;
	2617	case 0x0b:  /* MOVN - R5000 */if (RTVAL64 != 0) { if (RDREG) RDVAL64 = RSVAL64; }           break;
	2618	case 0x0c:  /* SYSCALL */   generate_exception(EXCEPTION_SYSCALL, 1);                       break;
	2619	case 0x0d:  /* BREAK */     generate_exception(EXCEPTION_BREAK, 1);                         break;
	2620	case 0x0f:  /* SYNC */      /* effective no-op */                                           break;
	2621	case 0x10:  /* MFHI */      if (RDREG) RDVAL64 = HIVAL64;                                   break;
	2622	case 0x11:  /* MTHI */      HIVAL64 = RSVAL64;                                              break;
	2623	case 0x12:  /* MFLO */      if (RDREG) RDVAL64 = LOVAL64;                                   break;
	2624	case 0x13:  /* MTLO */      LOVAL64 = RSVAL64;                                              break;
	2625	case 0x14:  /* DSLLV */     if (RDREG) RDVAL64 = RTVAL64 << (RSVAL32 & 63);                 break;
	2626	case 0x16:  /* DSRLV */     if (RDREG) RDVAL64 = RTVAL64 >> (RSVAL32 & 63);                 break;
	2627	case 0x17:  /* DSRAV */     if (RDREG) RDVAL64 = (INT64)RTVAL64 >> (RSVAL32 & 63);          break;
	2628	case 0x18:  /* MULT */
	2629	temp64 = (INT64)(INT32)RSVAL32 * (INT64)(INT32)RTVAL32;
	2630	LOVAL64 = (INT32)temp64;
	2631	HIVAL64 = (INT32)(temp64 >> 32);
	2632	m_core->icount -= 3;
	2633	break;
	2634	case 0x19:  /* MULTU */
	2635	temp64 = (UINT64)RSVAL32 * (UINT64)RTVAL32;
	2636	LOVAL64 = (INT32)temp64;
	2637	HIVAL64 = (INT32)(temp64 >> 32);
	2638	m_core->icount -= 3;
	2639	break;
	2640	case 0x1a:  /* DIV */
	2641	if (RTVAL32)
	2642	{
	2643	LOVAL64 = (INT32)((INT32)RSVAL32 / (INT32)RTVAL32);
	2644	HIVAL64 = (INT32)((INT32)RSVAL32 % (INT32)RTVAL32);
	2645	}
	2646	else
	2647	{
	2648	handle_integer_divide_by_zero(op);
	2649	}
	2650	m_core->icount -= 35;
	2651	break;
	2652	case 0x1b:  /* DIVU */
	2653	if (RTVAL32)
	2654	{
	2655	LOVAL64 = (INT32)(RSVAL32 / RTVAL32);
	2656	HIVAL64 = (INT32)(RSVAL32 % RTVAL32);
	2657	}
	2658	else
	2659	{
	2660	handle_integer_divide_by_zero(op);
	2661	}
	2662	m_core->icount -= 35;
	2663	break;
	2664	case 0x1c:  /* DMULT */
	2665	temp64 = (INT64)RSVAL64 * (INT64)RTVAL64;
	2666	LOVAL64 = temp64;
	2667	HIVAL64 = (INT64)temp64 >> 63;
	2668	m_core->icount -= 7;
	2669	break;
	2670	case 0x1d:  /* DMULTU */
	2671	temp64 = (UINT64)RSVAL64 * (UINT64)RTVAL64;
	2672	LOVAL64 = temp64;
	2673	HIVAL64 = 0;
	2674	m_core->icount -= 7;
	2675	break;
	2676	case 0x1e:  /* DDIV */
	2677	if (RTVAL64)
	2678	{
	2679	LOVAL64 = (INT64)RSVAL64 / (INT64)RTVAL64;
	2680	HIVAL64 = (INT64)RSVAL64 % (INT64)RTVAL64;
	2681	}
	2682	m_core->icount -= 67;
	2683	break;
	2684	case 0x1f:  /* DDIVU */
	2685	if (RTVAL64)
	2686	{
	2687	LOVAL64 = RSVAL64 / RTVAL64;
	2688	HIVAL64 = RSVAL64 % RTVAL64;
	2689	}
	2690	m_core->icount -= 67;
	2691	break;
	2692	case 0x20:  /* ADD */
	2693	if (ENABLE_OVERFLOWS && RSVAL32 > ~RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
	2694	else if (RDREG) RDVAL64 = (INT32)(RSVAL32 + RTVAL32);
	2695	break;
	2696	case 0x21:  /* ADDU */      if (RDREG) RDVAL64 = (INT32)(RSVAL32 + RTVAL32);                break;
	2697	case 0x22:  /* SUB */
	2698	if (ENABLE_OVERFLOWS && RSVAL32 < RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
	2699	else if (RDREG) RDVAL64 = (INT32)(RSVAL32 - RTVAL32);
	2700	break;
	2701	case 0x23:  /* SUBU */      if (RDREG) RDVAL64 = (INT32)(RSVAL32 - RTVAL32);                break;
	2702	case 0x24:  /* AND */       if (RDREG) RDVAL64 = RSVAL64 & RTVAL64;                         break;
	2703	case 0x25:  /* OR */        if (RDREG) RDVAL64 = RSVAL64 | RTVAL64;                         break;
	2704	case 0x26:  /* XOR */       if (RDREG) RDVAL64 = RSVAL64 ^ RTVAL64;                         break;
	2705	case 0x27:  /* NOR */       if (RDREG) RDVAL64 = ~(RSVAL64 | RTVAL64);                      break;
	2706	case 0x2a:  /* SLT */       if (RDREG) RDVAL64 = (INT64)RSVAL64 < (INT64)RTVAL64;           break;
	2707	case 0x2b:  /* SLTU */      if (RDREG) RDVAL64 = (UINT64)RSVAL64 < (UINT64)RTVAL64;         break;
	2708	case 0x2c:  /* DADD */
	2709	if (ENABLE_OVERFLOWS && RSVAL64 > ~RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
	2710	else if (RDREG) RDVAL64 = RSVAL64 + RTVAL64;
	2711	break;
	2712	case 0x2d:  /* DADDU */     if (RDREG) RDVAL64 = RSVAL64 + RTVAL64;                         break;
	2713	case 0x2e:  /* DSUB */
	2714	if (ENABLE_OVERFLOWS && RSVAL64 < RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
	2715	else if (RDREG) RDVAL64 = RSVAL64 - RTVAL64;
	2716	break;
	2717	case 0x2f:  /* DSUBU */     if (RDREG) RDVAL64 = RSVAL64 - RTVAL64;                         break;
	2718	case 0x30:  /* TGE */       if ((INT64)RSVAL64 >= (INT64)RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
	2719	case 0x31:  /* TGEU */      if (RSVAL64 >= RTVAL64) generate_exception(EXCEPTION_TRAP, 1);  break;
	2720	case 0x32:  /* TLT */       if ((INT64)RSVAL64 < (INT64)RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
	2721	case 0x33:  /* TLTU */      if (RSVAL64 < RTVAL64) generate_exception(EXCEPTION_TRAP, 1);   break;
	2722	case 0x34:  /* TEQ */       if (RSVAL64 == RTVAL64) generate_exception(EXCEPTION_TRAP, 1);  break;
	2723	case 0x36:  /* TNE */       if (RSVAL64 != RTVAL64) generate_exception(EXCEPTION_TRAP, 1);  break;
	2724	case 0x38:  /* DSLL */      if (RDREG) RDVAL64 = RTVAL64 << SHIFT;                          break;
	2725	case 0x3a:  /* DSRL */      if (RDREG) RDVAL64 = RTVAL64 >> SHIFT;                          break;
	2726	case 0x3b:  /* DSRA */      if (RDREG) RDVAL64 = (INT64)RTVAL64 >> SHIFT;                   break;
	2727	case 0x3c:  /* DSLL32 */    if (RDREG) RDVAL64 = RTVAL64 << (SHIFT + 32);                   break;
	2728	case 0x3e:  /* DSRL32 */    if (RDREG) RDVAL64 = RTVAL64 >> (SHIFT + 32);                   break;
	2729	case 0x3f:  /* DSRA32 */    if (RDREG) RDVAL64 = (INT64)RTVAL64 >> (SHIFT + 32);            break;
	2730	default:    /* ??? */       invalid_instruction(op);                                        break;
	2731	}
2787	2732	break;
2788	2733
2789	2734	case 0x01:  /* REGIMM */
2790		handle_regimm(op);
	2735	switch (RTREG)
	2736	{
	2737	case 0x00:  /* BLTZ */      if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL);                         break;
	2738	case 0x01:  /* BGEZ */      if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL);                        break;
	2739	case 0x02:  /* BLTZL */     if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4;        break;
	2740	case 0x03:  /* BGEZL */     if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4;   break;
	2741	case 0x08:  /* TGEI */      if ((INT64)RSVAL64 >= SIMMVAL) generate_exception(EXCEPTION_TRAP, 1);   break;
	2742	case 0x09:  /* TGEIU */     if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
	2743	case 0x0a:  /* TLTI */      if ((INT64)RSVAL64 < SIMMVAL) generate_exception(EXCEPTION_TRAP, 1);    break;
	2744	case 0x0b:  /* TLTIU */     if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
	2745	case 0x0c:  /* TEQI */      if (RSVAL64 == UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
	2746	case 0x0e:  /* TNEI */      if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
	2747	case 0x10:  /* BLTZAL */    if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31);                     break;
	2748	case 0x11:  /* BGEZAL */    if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31);                    break;
	2749	case 0x12:  /* BLTZALL */   if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break;
	2750	case 0x13:  /* BGEZALL */   if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4;    break;
	2751	default:    /* ??? */       invalid_instruction(op);                                        break;
	2752	}
2791	2753	break;
2792	2754
2793	2755	case 0x02:  /* J */         ABSPC(LIMMVAL);                                                         break;
r245291	r245292
2857	2819	case 0x36:  /* LDC2 */      if (RDOUBLE(SIMMVAL+RSVAL32, &temp64)) set_cop2_reg(RTREG, temp64);     break;
2858	2820	case 0x37:  /* LD */        if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64;       break;
2859	2821	case 0x38:  /* SC */        if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG)
2860		{
2861		if (temp == m_ll_value)
2862		{
2863		WWORD(SIMMVAL+RSVAL32, RTVAL32);
2864		RTVAL64 = (UINT32)1;
2865		}
2866		else
2867		{
2868		RTVAL64 = (UINT32)0;
2869		}
2870		}
2871		break;
	2822	{
	2823	if (temp == m_ll_value)
	2824	{
	2825	WWORD(SIMMVAL+RSVAL32, RTVAL32);
	2826	RTVAL64 = (UINT32)1;
	2827	}
	2828	else
	2829	{
	2830	RTVAL64 = (UINT32)0;
	2831	}
	2832	}
	2833	break;
2872	2834	case 0x39:  /* SWC1 */      WWORD(SIMMVAL+RSVAL32, get_cop1_reg32(RTREG));                          break;
2873	2835	case 0x3a:  /* SWC2 */      WWORD(SIMMVAL+RSVAL32, get_cop2_reg(RTREG));                            break;
2874	2836	case 0x3b:  /* SWC3 */      invalid_instruction(op);                                                break;
2875	2837	case 0x3c:  /* SCD */       if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG)
2876		{
2877		if (temp64 == m_lld_value)
2878		{
2879		WDOUBLE(SIMMVAL+RSVAL32, RTVAL64);
2880		RTVAL64 = 1;
2881		}
2882		else
2883		{
2884		RTVAL64 = 0;
2885		}
2886		}
2887		break;
	2838	{
	2839	if (temp64 == m_lld_value)
	2840	{
	2841	WDOUBLE(SIMMVAL+RSVAL32, RTVAL64);
	2842	RTVAL64 = 1;
	2843	}
	2844	else
	2845	{
	2846	RTVAL64 = 0;
	2847	}
	2848	}
	2849	break;
2888	2850	case 0x3d:  /* SDC1 */      WDOUBLE(SIMMVAL+RSVAL32, get_cop1_reg64(RTREG));                            break;
2889	2851	case 0x3e:  /* SDC2 */      WDOUBLE(SIMMVAL+RSVAL32, get_cop2_reg(RTREG));                          break;
2890	2852	case 0x3f:  /* SD */        WDOUBLE(SIMMVAL+RSVAL32, RTVAL64);                                      break;

trunk/src/emu/cpu/mips/mips3.h

r245291	r245292
194	194	MIPS3_BADVADDR
195	195	};
196	196
197		#define MIPS3_MAX_FASTRAM       3
	197	#define MIPS3_MAX_FASTRAM       4
198	198	#define MIPS3_MAX_HOTSPOTS      16
199	199
200	200	enum
r245291	r245292
296	296
297	297	TIMER_CALLBACK_MEMBER(compare_int_callback);
298	298
299		void add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
300
301	299	void mips3drc_set_options(UINT32 options);
	300	void mips3drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
302	301	void mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
303	302
304	303	protected:
r245291	r245292
327	326	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
328	327	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
329	328
330
331	329	private:
332	330	struct internal_mips3_state
333	331	{
r245291	r245292
396	394
397	395	/* memory accesses */
398	396	bool            m_bigendian;
399		UINT32         m_byte_xor;
400		UINT32         m_word_xor;
401	397	data_accessors  m_memory;
402	398
403	399	/* cache memory */
r245291	r245292
408	404	vtlb_state *    m_vtlb;
409	405	mips3_tlb_entry m_tlb[MIPS3_MAX_TLB_ENTRIES];
410	406
411		/* fast RAM */
412		UINT32              m_fastram_select;
413		struct
414		{
415		offs_t              start;                      /* start of the RAM block */
416		offs_t              end;                        /* end of the RAM block */
417		UINT8               readonly;                   /* TRUE if read-only */
418		void *              base;                       /* base in memory where the RAM lives */
419		}       m_fastram[MIPS3_MAX_FASTRAM];
420
421	407	UINT64 m_debugger_temp;
422	408
423	409	/* core state */
r245291	r245292
456	442	uml::code_handle *   m_exception[18/*EXCEPTION_COUNT*/]; /* array of exception handlers */
457	443	uml::code_handle *   m_exception_norecover[18/*EXCEPTION_COUNT*/];   /* array of no-recover exception handlers */
458	444
	445	/* fast RAM */
	446	UINT32              m_fastram_select;
	447	struct
	448	{
	449	offs_t              start;                      /* start of the RAM block */
	450	offs_t              end;                        /* end of the RAM block */
	451	UINT8               readonly;                   /* TRUE if read-only */
	452	void *              base;                       /* base in memory where the RAM lives */
	453	}       m_fastram[MIPS3_MAX_FASTRAM];
	454
459	455	/* hotspots */
460	456	UINT32              m_hotspot_select;
461	457	struct
r245291	r245292
481	477	private:
482	478	UINT32 compute_config_register();
483	479	UINT32 compute_prid_register();
484
485	480	void tlb_map_entry(int tlbindex);
486	481	void tlb_write_common(int tlbindex);
487
488		bool RBYTE(offs_t address, UINT32 *result);
489		bool RHALF(offs_t address, UINT32 *result);
490		bool RWORD(offs_t address, UINT32 *result);
491		bool RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask);
492		bool RDOUBLE(offs_t address, UINT64 *result);
493		bool RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask);
	482	int RBYTE(offs_t address, UINT32 *result);
	483	int RHALF(offs_t address, UINT32 *result);
	484	int RWORD(offs_t address, UINT32 *result);
	485	int RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask);
	486	int RDOUBLE(offs_t address, UINT64 *result);
	487	int RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask);
494	488	void WBYTE(offs_t address, UINT8 data);
495	489	void WHALF(offs_t address, UINT16 data);
496	490	void WWORD(offs_t address, UINT32 data);
497	491	void WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask);
498	492	void WDOUBLE(offs_t address, UINT64 data);
499	493	void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask);
500
501	494	UINT64 get_cop0_reg(int idx);
502	495	void set_cop0_reg(int idx, UINT64 val);
503	496	UINT64 get_cop0_creg(int idx);
504	497	void set_cop0_creg(int idx, UINT64 val);
505	498	void handle_cop0(UINT32 op);
506
507	499	UINT32 get_cop1_reg32(int idx);
508	500	UINT64 get_cop1_reg64(int idx);
509	501	void set_cop1_reg32(int idx, UINT32 val);
r245291	r245292
514	506	void handle_cop1_fr1(UINT32 op);
515	507	void handle_cop1x_fr0(UINT32 op);
516	508	void handle_cop1x_fr1(UINT32 op);
517
518	509	UINT64 get_cop2_reg(int idx);
519	510	void set_cop2_reg(int idx, UINT64 val);
520	511	UINT64 get_cop2_creg(int idx);
521	512	void set_cop2_creg(int idx, UINT64 val);
522	513	void handle_cop2(UINT32 op);
523
524		void handle_special(UINT32 op);
525		void handle_regimm(UINT32 op);
526
	514	void handle_integer_divide_by_zero(UINT32 op);
527	515	void lwl_be(UINT32 op);
528	516	void lwr_be(UINT32 op);
529	517	void ldl_be(UINT32 op);

trunk/src/emu/cpu/mips/mips3drc.c

r245291	r245292
160	160	region
161	161	-------------------------------------------------*/
162	162
163		void mips3_device::add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base)
	163	void mips3_device::mips3drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base)
164	164	{
	165	if (!machine().options().drc()) return;
165	166	if (m_fastram_select < ARRAY_LENGTH(m_fastram))
166	167	{
167	168	m_fastram[m_fastram_select].start = start;
r245291	r245292
2053	2054	return TRUE;
2054	2055
2055	2056	case 0x1a:  /* DIV - MIPS I */
2056		UML_DIVS(block, I0, I1, R32(RSREG), R32(RTREG));                    // divs    i0,i1,<rsreg>,<rtreg>
2057		UML_DSEXT(block, LO64, I0, SIZE_DWORD);                             // dsext   lo,i0,dword
2058		UML_DSEXT(block, HI64, I1, SIZE_DWORD);                             // dsext   hi,i1,dword
	2057	{
	2058	if (m_drcoptions & MIPS3DRC_ACCURATE_DIVZERO)
	2059	{
	2060	code_label divzero, done;
	2061
	2062	UML_CMP(block, R32(RTREG), 0);                                      // cmp     <rtreg>, 0
	2063	UML_JMPc(block, COND_E, divzero = compiler->labelnum++);         // jmp     divzero,E
	2064
	2065	UML_DIVS(block, I0, I1, R32(RSREG), R32(RTREG));                    // divs    i0,i1,<rsreg>,<rtreg>
	2066	UML_DSEXT(block, LO64, I0, SIZE_DWORD);                             // dsext   lo,i0,dword
	2067	UML_DSEXT(block, HI64, I1, SIZE_DWORD);                             // dsext   hi,i1,dword
	2068	UML_JMP(block, done = compiler->labelnum++);                        // jmp     done
	2069
	2070	UML_LABEL(block, divzero);                                          // divzero:
	2071	if (m_flavor != MIPS3_TYPE_VR4300)
	2072	{
	2073	UML_MOVc(block, COND_L, I0, 0x00000001);                        // mov     i0,0x00000001,L
	2074	UML_MOVc(block, COND_GE, I0, 0xffffffff);                       // mov     i0,0xffffffff,GE
	2075	}
	2076	else
	2077	{
	2078	UML_MOVc(block, COND_L, I0, 0x80000001);                        // mov     i0,0x80000001,L
	2079	UML_MOVc(block, COND_GE, I0, 0x7fffffff);                       // mov     i0,0x7fffffff,GE
	2080	}
	2081	UML_DSEXT(block, HI64, R32(RSREG), SIZE_DWORD);                     // dsext   hi,<rsreg>,dword
	2082	UML_DSEXT(block, LO64, I0, SIZE_DWORD);                             // dsext   lo,i0,dword
	2083
	2084	UML_LABEL(block, done);                                             // done:
	2085	}
	2086	else
	2087	{
	2088	UML_DIVS(block, I0, I1, R32(RSREG), R32(RTREG));                    // divs    i0,i1,<rsreg>,<rtreg>
	2089	UML_DSEXT(block, LO64, I0, SIZE_DWORD);                             // dsext   lo,i0,dword
	2090	UML_DSEXT(block, HI64, I1, SIZE_DWORD);                             // dsext   hi,i1,dword
	2091	}
2059	2092	return TRUE;
	2093	}
2060	2094
2061	2095	case 0x1b:  /* DIVU - MIPS I */
2062		UML_DIVU(block, I0, I1, R32(RSREG), R32(RTREG));                    // divu    i0,i1,<rsreg>,<rtreg>
2063		UML_DSEXT(block, LO64, I0, SIZE_DWORD);                             // dsext   lo,i0,dword
2064		UML_DSEXT(block, HI64, I1, SIZE_DWORD);                             // dsext   hi,i1,dword
	2096	if (m_drcoptions & MIPS3DRC_ACCURATE_DIVZERO)
	2097	{
	2098	code_label divzero, done;
	2099
	2100	UML_CMP(block, R32(RTREG), 0);                                      // cmp     <rtreg>, 0
	2101	UML_JMPc(block, COND_E, divzero = compiler->labelnum++);         // jmp     divzero,E
	2102
	2103	UML_DIVU(block, I0, I1, R32(RSREG), R32(RTREG));                    // divu    i0,i1,<rsreg>,<rtreg>
	2104	UML_DSEXT(block, LO64, I0, SIZE_DWORD);                             // dsext   lo,i0,dword
	2105	UML_DSEXT(block, HI64, I1, SIZE_DWORD);                             // dsext   hi,i1,dword
	2106	UML_JMP(block, done = compiler->labelnum++);                        // jmp     done
	2107
	2108	UML_LABEL(block, divzero);                                          // divzero:
	2109	if (m_flavor != MIPS3_TYPE_VR4300)
	2110	{
	2111	UML_MOVc(block, COND_L, I0, 0x00000001);                        // mov     i0,0x00000001,L
	2112	UML_MOVc(block, COND_GE, I0, 0xffffffff);                       // mov     i0,0xffffffff,GE
	2113	}
	2114	else
	2115	{
	2116	UML_MOVc(block, COND_L, I0, 0x80000001);                        // mov     i0,0x80000001,L
	2117	UML_MOVc(block, COND_GE, I0, 0x7fffffff);                       // mov     i0,0x7fffffff,GE
	2118	}
	2119	UML_DSEXT(block, HI64, R32(RSREG), SIZE_DWORD);                     // dsext   hi,<rsreg>,dword
	2120	UML_DSEXT(block, LO64, I0, SIZE_DWORD);                             // dsext   lo,i0,dword
	2121
	2122	UML_LABEL(block, done);                                             // done:
	2123	}
	2124	else
	2125	{
	2126	UML_DIVU(block, I0, I1, R32(RSREG), R32(RTREG));                    // divu    i0,i1,<rsreg>,<rtreg>
	2127	UML_DSEXT(block, LO64, I0, SIZE_DWORD);                             // dsext   lo,i0,dword
	2128	UML_DSEXT(block, HI64, I1, SIZE_DWORD);                             // dsext   hi,i1,dword
	2129	}
2065	2130	return TRUE;
2066	2131
2067	2132	case 0x1e:  /* DDIV - MIPS III */

trunk/src/emu/sound/tms5220.c

r245291	r245292
322	322	#define TMS5220_IS_CD2501E  TMS5220_IS_5200
323	323
324	324	#define TMS5220_HAS_RATE_CONTROL ((m_variant == TMS5220_IS_5220C) || (m_variant == TMS5220_IS_CD2501ECD))
325		#define TMS5220_IS_52xx ((m_variant == TMS5220_IS_5220C) || (m_variant == TMS5220_IS_5200) || (m_variant == TMS5220_IS_5220) || (m_variant == TMS5220_IS_CD2501ECD))
326	325
327	326	static const UINT8 reload_table[4] = { 0, 2, 4, 6 }; //sample count reload for 5220c and cd2501ecd only; 5200 and 5220 always reload with 0; keep in mind this is loaded on IP=0 PC=12 subcycle=1 so it immediately will increment after one sample, effectively being 1,3,5,7 as in the comments above.
328	327
r245291	r245292
475	474	#ifdef DEBUG_FIFO
476	475	logerror("data_write: Added byte to FIFO (current count=%2d)\n", m_fifo_count);
477	476	#endif
478		update_fifo_status_and_ints();
	477	update_status_and_ints();
479	478	if ((m_talk_status == 0) && (m_buffer_low == 0)) // we just unset buffer low with that last write, and talk status *was* zero...
480	479	{
481	480	int i;
r245291	r245292
515	514
516	515	/**********************************************************************************************
517	516
518		update_fifo_status_and_ints -- check to see if the various flags should be on or off
	517	update_status_and_ints -- check to see if the various flags should be on or off
519	518	Description of flags, and their position in the status register:
520	519	From the data sheet:
521	520	bit D0(bit 7) = TS - Talk Status is active (high) when the VSP is processing speech data.
r245291	r245292
536	535
537	536	***********************************************************************************************/
538	537
539		void tms5220_device::update_fifo_status_and_ints()
	538	void tms5220_device::update_status_and_ints()
540	539	{
541		/* update 52xx fifo flags and set ints if needed */
542		if (!TMS5220_IS_52xx) return; // bail out if not a 52xx chip
	540	/* update flags and set ints if needed */
	541
543	542	update_ready_state();
544	543
545	544	/* BL is set if neither byte 9 nor 8 of the fifo are in use; this
r245291	r245292
606	605	m_fifo[m_fifo_head] = 0; // zero the newly depleted fifo head byte
607	606	m_fifo_head = (m_fifo_head + 1) % FIFO_SIZE;
608	607	m_fifo_bits_taken = 0;
609		update_fifo_status_and_ints();
	608	update_status_and_ints();
610	609	}
611	610	}
612	611	}
r245291	r245292
798	797	{
799	798	m_talk_status = m_speak_external = 0;
800	799	set_interrupt_state(1);
801		update_fifo_status_and_ints();
	800	update_status_and_ints();
802	801	}
803	802
804	803	/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
r245291	r245292
1251	1250	}
1252	1251
1253	1252	/* update the buffer low state */
1254		update_fifo_status_and_ints();
	1253	update_status_and_ints();
1255	1254	}
1256	1255
1257	1256	/******************************************************************************************
r245291	r245292
1280	1279	else // non-5220C and 5220C in fixed rate mode
1281	1280	m_IP = reload_table[m_c_variant_rate&0x3];
1282	1281
1283		update_fifo_status_and_ints();
	1282	update_status_and_ints();
1284	1283	if (!m_talk_status) goto ranout;
1285	1284
1286	1285	// attempt to extract the energy index
r245291	r245292
1289	1288	printbits(m_new_frame_energy_idx,m_coeff->energy_bits);
1290	1289	fprintf(stderr," ");
1291	1290	#endif
1292		update_fifo_status_and_ints();
	1291	update_status_and_ints();
1293	1292	if (!m_talk_status) goto ranout;
1294	1293	// if the energy index is 0 or 15, we're done
1295	1294	if ((m_new_frame_energy_idx == 0) || (m_new_frame_energy_idx == 15))
r245291	r245292
1309	1308	printbits(m_new_frame_pitch_idx,m_coeff->pitch_bits);
1310	1309	fprintf(stderr," ");
1311	1310	#endif
1312		update_fifo_status_and_ints();
	1311	update_status_and_ints();
1313	1312	if (!m_talk_status) goto ranout;
1314	1313	// if this is a repeat frame, just do nothing, it will reuse the old coefficients
1315	1314	if (rep_flag)
r245291	r245292
1323	1322	printbits(m_new_frame_k_idx[i],m_coeff->kbits[i]);
1324	1323	fprintf(stderr," ");
1325	1324	#endif
1326		update_fifo_status_and_ints();
	1325	update_status_and_ints();
1327	1326	if (!m_talk_status) goto ranout;
1328	1327	}
1329	1328
r245291	r245292
1342	1341	printbits(m_new_frame_k_idx[i],m_coeff->kbits[i]);
1343	1342	fprintf(stderr," ");
1344	1343	#endif
1345		update_fifo_status_and_ints();
	1344	update_status_and_ints();
1346	1345	if (!m_talk_status) goto ranout;
1347	1346	}
1348	1347	#ifdef VERBOSE
r245291	r245292
1368	1367
1369	1368	void tms5220_device::set_interrupt_state(int state)
1370	1369	{
1371		if (!TMS5220_IS_52xx) return; // bail out if not a 52xx chip, since there's no int pin
1372	1370	#ifdef DEBUG_PIN_READS
1373	1371	logerror("irq pin set to state %d\n", state);
1374	1372	#endif

trunk/src/emu/sound/tms5220.h

r245291	r245292
73	73	private:
74	74	void register_for_save_states();
75	75	void data_write(int data);
76		void update_fifo_status_and_ints();
	76	void update_status_and_ints();
77	77	int extract_bits(int count);
78	78	int status_read();
79	79	int ready_read();

trunk/src/mame/drivers/cps2.c

r245291	r245292
6787	6787
6788	6788	ROM_START( spf2t )
6789	6789	ROM_REGION(CODE_SIZE, "maincpu", 0 )      /* 68000 code */
6790		ROM_LOAD16_WORD_SWAP( "pzfe.03", 0x000000, 0x80000, CRC(2af51954) SHA1(51f8797918391e772cf3cc27074ed6ca419806bd) )
6791		ROM_LOAD16_WORD_SWAP( "pzf.04",  0x080000, 0x80000, CRC(b80649e2) SHA1(5bfccd656aea7ff82e9a20bb5856f4ab99b5a007) ) // marked pzfe.04 but same as pzf.04
6792
6793		ROM_REGION( 0xC00000, "gfx", 0 )
6794		ROM_FILL(             0x000000, 0x800000, 0 )
6795		ROMX_LOAD( "pzf.14m", 0x800000, 0x100000, CRC(2d4881cb) SHA1(fd3baa183c25bed153b19c251980e2fb761600e2) , ROM_GROUPWORD | ROM_SKIP(6) )
6796		ROMX_LOAD( "pzf.16m", 0x800002, 0x100000, CRC(4b0fd1be) SHA1(377aafdcdb7a866b1c8487670e3598d8197976e4) , ROM_GROUPWORD | ROM_SKIP(6) )
6797		ROMX_LOAD( "pzf.18m", 0x800004, 0x100000, CRC(e43aac33) SHA1(d041e0688c3807d3363861a7f216de43b34d846c) , ROM_GROUPWORD | ROM_SKIP(6) )
6798		ROMX_LOAD( "pzf.20m", 0x800006, 0x100000, CRC(7f536ff1) SHA1(905b9d62ef7bef47297c7f4a4dd697aed6df38a5) , ROM_GROUPWORD | ROM_SKIP(6) )
6799
6800		ROM_REGION(QSOUND_SIZE, "audiocpu", 0 ) /* 64k for the audio CPU (+banks) */
6801		ROM_LOAD( "pzf.01",   0x00000, 0x08000, CRC(600fb2a3) SHA1(1fab1c2a23bf6ad8309d29ddbbc29435a8aeea13) )
6802		ROM_CONTINUE(         0x10000, 0x18000 )
6803		ROM_LOAD( "pzf.02",   0x28000, 0x20000, CRC(496076e0) SHA1(1ee4e135140afd0e8e03231e570cd77d140f6367) )
6804
6805		ROM_REGION( 0x400000, "qsound", 0 ) /* QSound samples */
6806		ROM_LOAD16_WORD_SWAP( "pzf.11m",   0x000000, 0x200000, CRC(78442743) SHA1(b61190bb586871de6d54af580e3e1d9cc0de0acb) )
6807		ROM_LOAD16_WORD_SWAP( "pzf.12m",   0x200000, 0x200000, CRC(399d2c7b) SHA1(e849dea97b8d16540415c0d9bbc4f9f4eb755ec4) )
6808		ROM_END
6809
6810		ROM_START( spf2tu )
6811		ROM_REGION(CODE_SIZE, "maincpu", 0 )      /* 68000 code */
6812	6790	ROM_LOAD16_WORD_SWAP( "pzfu.03a", 0x000000, 0x80000, CRC(346e62ef) SHA1(9db5ea0aac2d459be957f8b6e2e0d18421587d4d) )
6813	6791	ROM_LOAD16_WORD_SWAP( "pzf.04",   0x080000, 0x80000, CRC(b80649e2) SHA1(5bfccd656aea7ff82e9a20bb5856f4ab99b5a007) )
6814	6792
r245291	r245292
6829	6807	ROM_LOAD16_WORD_SWAP( "pzf.12m",   0x200000, 0x200000, CRC(399d2c7b) SHA1(e849dea97b8d16540415c0d9bbc4f9f4eb755ec4) )
6830	6808	ROM_END
6831	6809
6832
6833	6810	ROM_START( spf2xj )
6834	6811	ROM_REGION(CODE_SIZE, "maincpu", 0 )      /* 68000 code */
6835	6812	ROM_LOAD16_WORD_SWAP( "pzfj.03a", 0x000000, 0x80000, CRC(2070554a) SHA1(fa818e6bd2e11667345d3d8f2397b60802ef72f9) )
r245291	r245292
8827	8804	GAME( 1996, sfz2alj,    sfz2al,   cps2, cps2_2p6b, cps_state, cps2,     ROT0,   "Capcom", "Street Fighter Zero 2 Alpha (Japan 960805)", GAME_SUPPORTS_SAVE )
8828	8805	GAME( 1996, sfz2alh,    sfz2al,   cps2, cps2_2p6b, cps_state, cps2,     ROT0,   "Capcom", "Street Fighter Zero 2 Alpha (Hispanic 960813)", GAME_SUPPORTS_SAVE )
8829	8806	GAME( 1996, sfz2alb,    sfz2al,   cps2, cps2_2p6b, cps_state, cps2,     ROT0,   "Capcom", "Street Fighter Zero 2 Alpha (Brazil 960813)", GAME_SUPPORTS_SAVE )
8830		GAME( 1996, spf2t,      0,        cps2, cps2_2p2b, cps_state, cps2,     ROT0,   "Capcom", "Super Puzzle Fighter II Turbo (Euro 960529)", GAME_SUPPORTS_SAVE )
8831		GAME( 1996, spf2tu,     spf2t,    cps2, cps2_2p2b, cps_state, cps2,     ROT0,   "Capcom", "Super Puzzle Fighter II Turbo (USA 960620)", GAME_SUPPORTS_SAVE )
	8807	GAME( 1996, spf2t,      0,        cps2, cps2_2p2b, cps_state, cps2,     ROT0,   "Capcom", "Super Puzzle Fighter II Turbo (USA 960620)", GAME_SUPPORTS_SAVE )
8832	8808	GAME( 1996, spf2xj,     spf2t,    cps2, cps2_2p2b, cps_state, cps2,     ROT0,   "Capcom", "Super Puzzle Fighter II X (Japan 960531)", GAME_SUPPORTS_SAVE )
8833	8809	GAME( 1996, spf2ta,     spf2t,    cps2, cps2_2p2b, cps_state, cps2,     ROT0,   "Capcom", "Super Puzzle Fighter II Turbo (Asia 960529)", GAME_SUPPORTS_SAVE )
8834	8810	GAME( 1996, spf2th,     spf2t,    cps2, cps2_2p2b, cps_state, cps2,     ROT0,   "Capcom", "Super Puzzle Fighter II Turbo (Hispanic 960531)", GAME_SUPPORTS_SAVE )

trunk/src/mame/drivers/hng64.c

r245291	r245292
1490	1490	/* set the fastest DRC options */
1491	1491	m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
1492	1492
1493		/* configure fast RAM regions */
1494		m_maincpu->add_fastram(0x00000000, 0x00ffffff, FALSE, m_mainram);
1495		m_maincpu->add_fastram(0x04000000, 0x05ffffff, TRUE,  m_cart);
1496		m_maincpu->add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
	1493	/* configure fast RAM regions for DRC */
	1494	m_maincpu->mips3drc_add_fastram(0x00000000, 0x00ffffff, FALSE, m_mainram);
	1495	m_maincpu->mips3drc_add_fastram(0x04000000, 0x05ffffff, TRUE,  m_cart);
	1496	m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
1497	1497
1498	1498	m_comm_rom = memregion("user2")->base();
1499	1499	m_comm_ram = auto_alloc_array(machine(),UINT8,0x10000);

trunk/src/mame/drivers/kinst.c

r245291	r245292
203	203	/* set the fastest DRC options */
204	204	m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
205	205
206		/* configure fast RAM regions */
207		m_maincpu->add_fastram(0x08000000, 0x087fffff, FALSE, m_rambase2);
208		m_maincpu->add_fastram(0x00000000, 0x0007ffff, FALSE, m_rambase);
209		m_maincpu->add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
	206	/* configure fast RAM regions for DRC */
	207	m_maincpu->mips3drc_add_fastram(0x08000000, 0x087fffff, FALSE, m_rambase2);
	208	m_maincpu->mips3drc_add_fastram(0x00000000, 0x0007ffff, FALSE, m_rambase);
	209	m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
210	210	}
211	211
212	212

trunk/src/mame/drivers/namcos23.c

r245291	r245292
3223	3223	m_c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this));
3224	3224	m_c361.timer->adjust(attotime::never);
3225	3225
3226		m_maincpu->add_fastram(0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr()));
	3226	m_maincpu->mips3drc_add_fastram(0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr()));
3227	3227	}
3228	3228
3229	3229

trunk/src/mame/drivers/seattle.c

r245291	r245292
566	566	/* set the fastest DRC options, but strict verification */
567	567	m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
568	568
569		/* configure fast RAM regions */
570		m_maincpu->add_fastram(0x00000000, 0x007fffff, FALSE, m_rambase);
571		m_maincpu->add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
	569	/* configure fast RAM regions for DRC */
	570	m_maincpu->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, m_rambase);
	571	m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
572	572
573	573	/* register for save states */
574	574	save_item(NAME(m_galileo.reg));

trunk/src/mame/drivers/vegas.c

r245291	r245292
595	595	/* set the fastest DRC options, but strict verification */
596	596	m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC);
597	597
598		/* configure fast RAM regions */
599		m_maincpu->add_fastram(0x00000000, m_rambase.bytes() - 1, FALSE, m_rambase);
600		m_maincpu->add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
	598	/* configure fast RAM regions for DRC */
	599	m_maincpu->mips3drc_add_fastram(0x00000000, m_rambase.bytes() - 1, FALSE, m_rambase);
	600	m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
601	601
602	602	/* register for save states */
603	603	save_item(NAME(m_nile_irq_state));

trunk/src/mame/machine/cps2crpt.c

r245291	r245292
899	899	{ "sfz2alj",  { 0x99450c88,0xa00a2c4d }, 0x100000 },    // 0C80 8E73 9110  cmpi.l  #$8E739110,D0
900	900	{ "sfz2alh",  { 0x95f15b7c,0x200c08c6 }, 0x100000 },    // 0C80 8E73 9110  cmpi.l  #$8E739110,D0
901	901	{ "sfz2alb",  { 0x73cd4a28,0xff83af1c }, 0x100000 },    // 0C80 8E73 9110  cmpi.l  #$8E739110,D0
902		{ "spf2t",    { 0xdde26f09,0x55821ee7 }, 0x040000 },    // 0C80 3039 9819  cmpi.l  #$30399819,D0
903		{ "spf2tu",   { 0x706a8750,0x7d0fc185 }, 0x040000 },    // 0C80 3039 9819  cmpi.l  #$30399819,D0
	902	{ "spf2t",    { 0x706a8750,0x7d0fc185 }, 0x040000 },    // 0C80 3039 9819  cmpi.l  #$30399819,D0
904	903	{ "spf2xj",   { 0xb12c835a,0xe90976ff }, 0x040000 },    // 0C80 3039 9819  cmpi.l  #$30399819,D0
905	904	{ "spf2ta",   { 0x9c48e1ab,0xd60f34fb }, 0x040000 },    // 0C80 3039 9819  cmpi.l  #$30399819,D0
906	905	{ "spf2th",   { 0x51ed8cab,0x228f85b6 }, 0x040000 },    // 0C80 3039 9819  cmpi.l  #$30399819,D0

trunk/src/mame/machine/n64.c

r245291	r245292
1458	1458	//pi_status |= 8; // Set INTERRUPT ?? Does this bit exist ??
1459	1459
1460	1460	if(update_bm)
1461		dd_update_bm();
	1461	dd_update_bm();
1462	1462
1463	1463	signal_rcp_interrupt(PI_INTERRUPT);
1464	1464
r245291	r245292
2189	2189	{
2190	2190	if(((dd_track_reg & 0xFFF) == 6) && (dd_start_block == 0))
2191	2191	{
2192		dd_status_reg &= ~DD_ASIC_STATUS_DREQ;
	2192	dd_status_reg &= ~DD_ASIC_STATUS_DREQ;
2193	2193	}
2194	2194	else if(dd_current_reg < SECTORS_PER_BLOCK)
2195	2195	{
r245291	r245292
2239	2239	sector += (dd_current_reg - 1) * ddZoneSecSize[dd_zone];
2240	2240
2241	2241	//logerror("Write Block %d, Sector %d\n", dd_start_block, dd_current_reg - 1);
2242
	2242
2243	2243	for(int i = 0; i < ddZoneSecSize[dd_zone]/4; i++)
2244	2244	{
2245	2245	sector[i*4 + 0] = (dd_sector_data[i] >> 24) & 0xFF;
r245291	r245292
2492	2492	logerror("dd BM Status write\n");
2493	2493	dd_start_sector = (data >> 16) & 0xFF;
2494	2494	if(dd_start_sector == 0x00)
2495		{
	2495	{
2496	2496	dd_start_block = 0;
2497	2497	dd_current_reg = 0;
2498	2498	}
2499	2499	else if (dd_start_sector == 0x5A)
2500		{
	2500	{
2501	2501	dd_start_block = 1;
2502	2502	dd_current_reg = 0;
2503	2503	}
r245291	r245292
2620	2620
2621	2621	dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS);
2622	2622
2623		/* configure fast RAM regions */
2624		dynamic_cast<mips3_device *>(machine().device("maincpu"))->add_fastram(0x00000000, 0x007fffff, FALSE, rdram);
	2623	/* configure fast RAM regions for DRC */
	2624	dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, rdram);
2625	2625
2626	2626	rsp_device *rsp = machine().device<rsp_device>("rsp");
2627	2627	rsp->rspdrc_set_options(RSPDRC_STRICT_VERIFY);

trunk/src/mame/mame.lst

r245291	r245292
3439	3439	sfz2br1         // 04/03/1996 (c) 1996 (Brazil)
3440	3440	sfz2h           // 04/03/1996 (c) 1996 (Hispanic)
3441	3441	sfz2n           // 29/02/1996 (c) 1996 (Oceania)
3442		spf2t           // 29/05/1996 (c) 1996 (Europe)
3443		spf2tu          // 20/06/1996 (c) 1996 (USA)
	3442	spf2t           // 20/06/1996 (c) 1996 (USA)
3444	3443	spf2xj          // 31/05/1996 (c) 1996 (Japan)
3445	3444	spf2ta          // 29/05/1996 (c) 1996 (Asia)
3446	3445	spf2th          // 31/05/1996 (c) 1996 (Hispanic)

trunk/src/mess/drivers/abc80.c

r245291	r245292
518	518
519	519	MCFG_CASSETTE_ADD("cassette")
520	520	MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_MOTOR_DISABLED | CASSETTE_SPEAKER_MUTED)
521		MCFG_CASSETTE_INTERFACE("abc80_cass")
522	521
523	522	MCFG_DEVICE_ADD(ABC80_KEYBOARD_TAG, ABC80_KEYBOARD, 0)
524	523	MCFG_ABC80_KEYBOARD_KEYDOWN_CALLBACK(WRITELINE(abc80_state, keydown_w))
r245291	r245292
533	532	MCFG_RAM_DEFAULT_SIZE("16K")
534	533
535	534	// software list
536		MCFG_SOFTWARE_LIST_ADD("cass_list", "abc80_cass")
537		MCFG_SOFTWARE_LIST_ADD("flop_list", "abc80_flop")
	535	MCFG_SOFTWARE_LIST_ADD("flop_list", "abc80")
538	536	MACHINE_CONFIG_END
539	537
540	538

trunk/src/mess/drivers/ticalc1x.c

r245291	r245292
946	946	ROM_LOAD( "tmc1993nl", 0x0000, 0x0400, CRC(e941316b) SHA1(7e1542045d1e731cea81a639c9ac9e91bb233b15) )
947	947
948	948	ROM_REGION( 782, "maincpu:ipla", 0 )
949		ROM_LOAD( "tms0970_lilprof78_ipla.pla", 0, 782, CRC(05306ef8) SHA1(60a0a3c49ce330bce0c27f15f81d61461d0432ce) )
	949	ROM_LOAD( "tms0970_lilprof78_ipla.pla", 0, 782, BAD_DUMP CRC(05306ef8) SHA1(60a0a3c49ce330bce0c27f15f81d61461d0432ce) ) // not verified
950	950	ROM_REGION( 860, "maincpu:mpla", 0 )
951	951	ROM_LOAD( "tms0970_lilprof78_mpla.pla", 0, 860, CRC(7f50ab2e) SHA1(bff3be9af0e322986f6e545b567c97d70e135c93) )
952	952	ROM_REGION( 352, "maincpu:opla", 0 )

https://github.com/mamedev/mame/commit/4a6023e471d6fbbecfce6fb6ebd00746c26cc34b

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