MAME SVN History

199869 Revisions

r36722 Saturday 28th March, 2015 at 00:12:44 UTC by hap
ssimon speed switch

[src/mess/drivers]	hh_tms1k.c hh_ucom4.c
[src/mess/includes]	hh_tms1k.h

trunk/src/mess/drivers/hh_tms1k.c
r245233	r245234
1051	1051	// MCU clock is from an RC circuit(R=47K, C=33pf) oscillating by default at ~340kHz,
1052	1052	// but on PRO, the difficulty switch adds an extra 150K resistor to Vdd to speed
1053	1053	// it up to around ~440kHz.
1054		m_maincpu->set_unscaled_clock(m_inp_matrix[3]->read() & 1 ? 440000 : 340000);
	1054	m_maincpu->set_unscaled_clock((m_inp_matrix[3]->read() & 1) ? 440000 : 340000);
1055	1055	}
1056	1056
1057	1057	INPUT_CHANGED_MEMBER(hh_tms1k_state::ebball3_difficulty_switch)
r245233	r245234
1570	1570	PORT_BIT( 0x0d, IP_ACTIVE_HIGH, IPT_UNUSED )
1571	1571
1572	1572	PORT_START("IN.6") // fake
1573		PORT_CONFNAME( 0x03, 0x00, "Speed" ) //PORT_CHANGED_MEMBER(DEVICE_SELF, hh_tms1k_state, ssimon_speed_switch, NULL)
	1573	PORT_CONFNAME( 0x03, 0x01, "Speed" ) PORT_CHANGED_MEMBER(DEVICE_SELF, hh_tms1k_state, ssimon_speed_switch, NULL)
1574	1574	PORT_CONFSETTING( 0x00, "Simple" )
1575	1575	PORT_CONFSETTING( 0x01, "Normal" )
1576	1576	PORT_CONFSETTING( 0x02, "Super" )
1577	1577	INPUT_PORTS_END
1578	1578
1579	1579
	1580	void hh_tms1k_state::ssimon_set_clock()
	1581	{
	1582	// MCU clock is from an RC circuit with C=100pf, R=x depending on speed switch:
	1583	// 0 Simple: R=51K -> ~200kHz
	1584	// 1 Normal: R=37K -> ~275kHz
	1585	// 2 Super: R=22K -> ~400kHz
	1586	UINT8 inp = m_inp_matrix[6]->read();
	1587	m_maincpu->set_unscaled_clock((inp & 2) ? 400000 : ((inp & 1) ? 275000 : 200000));
	1588	}
	1589
	1590	INPUT_CHANGED_MEMBER(hh_tms1k_state::ssimon_speed_switch)
	1591	{
	1592	ssimon_set_clock();
	1593	}
	1594
	1595	MACHINE_RESET_MEMBER(hh_tms1k_state, ssimon)
	1596	{
	1597	machine_reset();
	1598	ssimon_set_clock();
	1599	}
	1600
1580	1601	static MACHINE_CONFIG_START( ssimon, hh_tms1k_state )
1581	1602
1582	1603	/* basic machine hardware */
1583		MCFG_CPU_ADD("maincpu", TMS1100, 350000) // x
	1604	MCFG_CPU_ADD("maincpu", TMS1100, 275000) // see ssimon_set_clock
1584	1605	MCFG_TMS1XXX_READ_K_CB(READ8(hh_tms1k_state, ssimon_read_k))
1585	1606	MCFG_TMS1XXX_WRITE_R_CB(WRITE16(hh_tms1k_state, ssimon_write_r))
1586	1607	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(hh_tms1k_state, ssimon_write_o))
r245233	r245234
1588	1609	MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_tms1k_state, display_decay_tick, attotime::from_msec(1))
1589	1610	MCFG_DEFAULT_LAYOUT(layout_ssimon)
1590	1611
	1612	MCFG_MACHINE_RESET_OVERRIDE(hh_tms1k_state, ssimon)
	1613
1591	1614	/* no video! */
1592	1615
1593	1616	/* sound hardware */

trunk/src/mess/drivers/hh_ucom4.c
r245233	r245234
770	770	// MCU clock is from an LC circuit oscillating by default at ~360kHz,
771	771	// but on PRO1, the difficulty switch puts a capacitor across the LC circuit
772	772	// to slow it down to ~260kHz.
773		m_maincpu->set_unscaled_clock(m_inp_matrix[1]->read() & 0x100 ? 260000 : 360000);
	773	m_maincpu->set_unscaled_clock((m_inp_matrix[1]->read() & 0x100) ? 260000 : 360000);
774	774	}
775	775
776	776	INPUT_CHANGED_MEMBER(hh_ucom4_state::tmtennis_difficulty_switch)

trunk/src/mess/includes/hh_tms1k.h
r245233	r245234
112	112	DECLARE_WRITE16_MEMBER(ssimon_write_r);
113	113	DECLARE_WRITE16_MEMBER(ssimon_write_o);
114	114	DECLARE_READ8_MEMBER(ssimon_read_k);
	115	void ssimon_set_clock();
	116	DECLARE_INPUT_CHANGED_MEMBER(ssimon_speed_switch);
	117	DECLARE_MACHINE_RESET(ssimon);
115	118
116	119	DECLARE_WRITE16_MEMBER(cnsector_write_r);
117	120	DECLARE_WRITE16_MEMBER(cnsector_write_o);

https://github.com/mamedev/mame/commit/3a42563d21a01ee49a6b6637732a2b5e2c3034cc

199869 Revisions