trunk/src/emu/cpu/arm7/arm7ops.c
| r245158 | r245159 | |
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| 253 | 253 | } /* storeInc */ |
| 254 | 254 | |
| 255 | 255 | |
| 256 | // classic CV: 3005aa0 does the DMA thing |
| 256 | 257 | int arm7_cpu_device::storeDec(UINT32 pat, UINT32 rbv, int mode) |
| 257 | 258 | { |
| 258 | | int i, result; |
| 259 | int i, result = 0, cnt; |
| 259 | 260 | |
| 260 | | result = 0; |
| 261 | // pre-count the # of registers doing DMA |
| 261 | 262 | for (i = 15; i >= 0; i--) |
| 262 | 263 | { |
| 263 | 264 | if ((pat >> i) & 1) |
| 264 | 265 | { |
| 266 | result++; |
| 267 | |
| 268 | // starting address |
| 269 | rbv -= 4; |
| 270 | } |
| 271 | } |
| 272 | |
| 273 | cnt = 0; |
| 274 | for (i = 0; i <= 15; i++) |
| 275 | { |
| 276 | if ((pat >> i) & 1) |
| 277 | { |
| 265 | 278 | #if ARM7_DEBUG_CORE |
| 266 | 279 | if (i == 15) /* R15 is plus 12 from address of STM */ |
| 267 | 280 | LOG(("%08x: StoreDec on R15\n", R15)); |
| 268 | 281 | #endif |
| 269 | | WRITE32(rbv -= 4, GET_MODE_REGISTER(mode, i)); |
| 270 | | result++; |
| 282 | WRITE32(rbv + (cnt * 4), GET_MODE_REGISTER(mode, i)); |
| 283 | cnt++; |
| 271 | 284 | } |
| 272 | 285 | } |
| 273 | 286 | return result; |
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| 1421 | 1434 | } /* Loading */ |
| 1422 | 1435 | else |
| 1423 | 1436 | { |
| 1424 | | /* Storing */ |
| 1437 | /* Storing - STM */ |
| 1425 | 1438 | if (insn & (1 << eR15)) |
| 1426 | 1439 | { |
| 1427 | 1440 | #if ARM7_DEBUG_CORE |
| r245158 | r245159 | |
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| 1461 | 1474 | } |
| 1462 | 1475 | else |
| 1463 | 1476 | { |
| 1464 | | /* Decrementing */ |
| 1477 | /* Decrementing - but real CPU writes in incrementing order */ |
| 1465 | 1478 | if (!(insn & INSN_BDT_P)) |
| 1466 | 1479 | { |
| 1467 | 1480 | rbp = rbp - (-4); |