MAME SVN History

199869 Revisions

r36631 Wednesday 25th March, 2015 at 10:12:10 UTC by Miodrag Milanović
Merge pull request #151 from Happy-yappH/master (MESS)Adding support for the N64DD [Happy]

[hash]	nes.xml pasogo.xml
[src]	version.c
[src/build]	flags_clang.mak
[src/emu]	mame.c render.c video.c video.h
[src/emu/bus/a2bus]	ezcgi.c
[src/emu/bus/scsi]	omti5100.c
[src/emu/cpu/hmcs40]	hmcs40.c hmcs40.h hmcs40d.c hmcs40op.inc
[src/emu/cpu/i386]	i386ops.h pentops.inc
[src/emu/cpu/nec]	v53.c v53.h
[src/emu/cpu/pic16c5x]	pic16c5x.c pic16c5x.h
[src/emu/cpu/z80]	kl5c80a12.c kl5c80a12.h
[src/emu/machine]	am9517a.c am9517a.h i8251.c i8257.c machine.mak mcf5206e.c tmp68301.c upd71071.c vrc4373.c vrc4373.h
[src/emu/sound]	es1373.h flt_rc.c okim9810.c okim9810.h
[src/emu/video]	tms34061.c voodoo_pci.c
[src/lib/formats]	d88_dsk.c flex_dsk.c fmtowns_dsk.c nfd_dsk.c
[src/mame]	mame.lst
[src/mame/audio]	hng64.c
[src/mame/drivers]	argus.c astrcorp.c cabal.c capbowl.c cocoloco.c dynax.c fgoal.c flyball.c goldstar.c hng64.c hotblock.c iteagle.c jankenmn.c jchan.c junofrst.c m72.c madalien.c mgolf.c neogeo.c neogeo_noslot.c paradise.c peplus.c playmark.c psychic5.c pturn.c re900.c rltennis.c sandscrp.c scobra.c seta.c seta2.c shougi.c sidearms.c simple_st0016.c sothello.c speglsht.c srmp2.c srmp5.c srmp6.c srumbler.c sstrangr.c ssv.c sub.c suna16.c suna8.c supdrapo.c supertnk.c superwng.c suprgolf.c suprslam.c tankbust.c taotaido.c tbowl.c tgtpanic.c thunderx.c toaplan2.c tryout.c tsamurai.c ttchamp.c tugboat.c twins.c usgames.c vamphalf.c vigilant.c wc90b.c xain.c xtheball.c
[src/mame/includes]	argus.h bbusters.h cabal.h capbowl.h fgoal.h hng64.h ironhors.h mosaic.h paradise.h pooyan.h psychic5.h realbrk.h rltennis.h seta2.h shuuz.h sidearms.h simple_st0016.h speedbal.h srmp2.h srumbler.h ssozumo.h ssrj.h ssv.h subs.h suna16.h suprloco.h suprridr.h tankbatt.h tankbust.h taotaido.h tbowl.h thunderx.h timelimt.h tryout.h tsamurai.h usgames.h vigilant.h vulgus.h wc90b.h
[src/mame/machine]	hng64_net.c iteagle_fpga.c iteagle_fpga.h
[src/mame/video]	bbusters.c deadang.c decmxc06.c dynax.c hng64.c hng64_3d.c hng64_sprite.c jalblend.c jalblend.h pc080sn.c psychic5.c realbrk.c rltennis.c seta001.c seta2.c sidearms.c srumbler.c ssv.c suna16.c suprloco.c suprridr.c tankbust.c tbowl.c thedeep.c timelimt.c tryout.c tsamurai.c vulgus.c xain.c
[src/mess]	mess.lst mess.mak
[src/mess/audio]	gamate.c
[src/mess/drivers]	a7800.c apple2.c apple2e.c gamate.c hh_hmcs40.c hh_pic16.c hh_tms1k.c hh_ucom4.c imds2.c mbdtower.c snes.c ticalc1x.c tispeak.c
[src/mess/includes]	hh_tms1k.h imds2.h
[src/mess/layout]	mbdtower.lay
[src/osd/modules]	osdwindow.h
[src/osd/modules/opengl]	osd_opengl.h
[src/osd/modules/render]	draw13.c drawogl.c
[src/osd/sdl]	sdl.mak video.h window.c
[src/osd/windows]	video.h windows.mak

trunk/hash/nes.xml
r245142	r245143
57391	57391	<publisher>Union Bond</publisher>
57392	57392	<info name="serial" value="G-0005"/>
57393	57393	<part name="cart" interface="nes_cart">
57394		<feature name="slot" value="nanjing" /> <!-- header actually says 164... -->
	57394	<feature name="slot" value="nanjing" /> <!-- header actually says 164... -->
57395	57395	<feature name="pcb" value="UNL-NANJING" />
57396	57396	<dataarea name="prg" size="524288">
57397	57397	<rom name="ying tao xiao wan zi (g-005) (ch).prg" size="524288" crc="8209ba79" sha1="fa56608d8dcf5a144dd1fc81282cd86fd51060fe" offset="00000" status="baddump" />
r245142	r245143
75420	75420	<year>19??</year>
75421	75421	<publisher><unknown></publisher>
75422	75422	<part name="cart" interface="nes_cart">
75423		<feature name="slot" value="fk23ca" /> <!-- UNIF header pointed to FK23C, but the menu does not appear with that mapper... investigate! -->
	75423	<feature name="slot" value="fk23ca" /> <!-- UNIF header pointed to FK23C, but the menu does not appear with that mapper... investigate! -->
75424	75424	<feature name="pcb" value="BMC-FK23C" />
75425	75425	<dataarea name="prg" size="8388608">
75426	75426	<rom name="120-in-1 (unl)[u].prg" size="8388608" crc="678de5aa" sha1="01da22ddf1897b47d6b03ecb4ff0c093f9b39dfc" offset="00000" status="baddump" />

trunk/hash/pasogo.xml
r245142	r245143
9	9	歴代棋聖戦名曲集 (Rekidai Kisei Sen Meikyokushuu)
10	10	棋界覇王伝・古典編 (Kikai Haoh Den - Koten-hen)
11	11	棋界覇王伝・現代編 (Kikai Haoh Den - Gendai-hen)
12
	12
13	13	The undumped cart numbers are KS-1005, KS-1006, KS-1007 and KS-1008
14	14	For the remaining undumped games, the game to cart number match is unknown.
15	15	-->

trunk/src/build/flags_clang.mak
r245142	r245143
2	2	-Wno-cast-align \
3	3	-Wno-tautological-compare
4	4
	5	# caused by dynamic_array being generally awful
	6	CCOMFLAGS += -Wno-dynamic-class-memaccess
	7
5	8	# caused by obj/sdl64d/emu/cpu/tms57002/tms57002.inc
6	9	CCOMFLAGS += -Wno-self-assign-field
7	10

trunk/src/emu/bus/a2bus/ezcgi.c
r245142	r245143
43	43	#define MSX2_VISIBLE_YBORDER_PIXELS 14 * 2
44	44
45	45	MACHINE_CONFIG_FRAGMENT( ezcgi9938 )
46		MCFG_V9938_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
	46	MCFG_V9938_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
47	47	MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9938_device, tms_irq_w))
48	48
49	49	MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
r245142	r245143
57	57	MACHINE_CONFIG_END
58	58
59	59	MACHINE_CONFIG_FRAGMENT( ezcgi9958 )
60		MCFG_V9958_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
	60	MCFG_V9958_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
61	61	MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9958_device, tms_irq_w))
62	62
63	63	MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
r245142	r245143
311	311	lower_slot_irq();
312	312	}
313	313	}
314

trunk/src/emu/bus/scsi/omti5100.c
r245142	r245143
20	20
21	21	omti5100_device::omti5100_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
22	22	: scsihd_device(mconfig, OMTI5100, "OMTI 5100", tag, owner, clock, "omti5100", __FILE__),
23		m_image0(*this, "image0"),
24		m_image1(*this, "image1")
	23	m_image0(*this, "image0"),
	24	m_image1(*this, "image1")
25	25	{
26	26	}
27	27

trunk/src/emu/cpu/hmcs40/hmcs40.c
r245142	r245143
187	187
188	188	m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hmcs40_cpu_device::simple_timer_cb), this));
189	189	reset_prescaler();
190
	190
191	191	m_read_r0.resolve_safe(0);
192	192	m_read_r1.resolve_safe(0);
193	193	m_read_r2.resolve_safe(0);
r245142	r245143
196	196	m_read_r5.resolve_safe(0);
197	197	m_read_r6.resolve_safe(0);
198	198	m_read_r7.resolve_safe(0);
199
	199
200	200	m_write_r0.resolve_safe();
201	201	m_write_r1.resolve_safe();
202	202	m_write_r2.resolve_safe();
r245142	r245143
290	290	{
291	291	m_pc = m_pcmask;
292	292	m_prev_op = m_op = 0;
293
	293
294	294	// clear i/o
295	295	m_d = m_polarity;
296	296	for (int i = 0; i < 16; i++)
297	297	hmcs40_cpu_device::write_d(i, 0);
298
	298
299	299	for (int i = 0; i < 8; i++)
300	300	hmcs40_cpu_device::write_r(i, 0);
301
	301
302	302	// clear interrupts
303	303	m_cf = 0;
304	304	m_ie = 0;
r245142	r245143
316	316	{
317	317	index &= 7;
318	318	UINT8 inp = 0;
319
	319
320	320	switch (index)
321	321	{
322	322	case 0: inp = m_read_r0(index, 0xff); break;
r245142	r245143
328	328	case 6: inp = m_read_r6(index, 0xff); break;
329	329	case 7: inp = m_read_r7(index, 0xff); break;
330	330	}
331
	331
332	332	return ((inp ^ m_polarity) \| m_r[index]) & 0xf;
333	333	}
334	334
r245142	r245143
337	337	index &= 7;
338	338	data = (data ^ m_polarity) & 0xf;
339	339	m_r[index] = data;
340
	340
341	341	switch (index)
342	342	{
343	343	case 0: m_write_r0(index, data, 0xff); break;
r245142	r245143
354	354	int hmcs40_cpu_device::read_d(int index)
355	355	{
356	356	index &= 15;
357
	357
358	358	return ((m_read_d(index, 0xffff) ^ m_polarity) \| m_d) >> index & 1;
359	359	}
360	360
r245142	r245143
362	362	{
363	363	index &= 15;
364	364	state = (((state) ? 1 : 0) ^ m_polarity) & 1;
365
	365
366	366	m_d = (m_d & ~(1 << index)) \| state << index;
367	367	m_write_d(index, m_d, 0xffff);
368	368	}
r245142	r245143
374	374	UINT8 hmcs43_cpu_device::read_r(int index)
375	375	{
376	376	index &= 7;
377
	377
378	378	if (index >= 2)
379	379	logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc);
380	380
r245142	r245143
394	394	int hmcs43_cpu_device::read_d(int index)
395	395	{
396	396	index &= 15;
397
	397
398	398	if (index >= 4)
399	399	logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc);
400	400
r245142	r245143
408	408	UINT8 hmcs44_cpu_device::read_r(int index)
409	409	{
410	410	index &= 7;
411
	411
412	412	if (index >= 6)
413	413	logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc);
414
	414
415	415	return hmcs40_cpu_device::read_r(index);
416	416	}
417	417
r245142	r245143
432	432	UINT8 hmcs45_cpu_device::read_r(int index)
433	433	{
434	434	index &= 7;
435
	435
436	436	if (index >= 6)
437	437	logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc);
438
	438
439	439	return hmcs40_cpu_device::read_r(index);
440	440	}
441	441
r245142	r245143
460	460	m_icount--;
461	461	push_stack();
462	462	m_ie = 0;
463
	463
464	464	// line 0/1 for external interrupt, let's use 2 for t/c interrupt
465	465	int line = (m_iri) ? m_eint_line : 2;
466
	466
467	467	// vector $3f, on page 0(timer/counter), or page 1(external)
468	468	// external interrupt has priority over t/c interrupt
469	469	m_pc = 0x3f \| (m_iri ? 0x40 : 0);
r245142	r245143
480	480	if (line != 0 && line != 1)
481	481	return;
482	482	state = (state) ? 1 : 0;
483
	483
484	484	// external interrupt request on rising edge
485	485	if (state && !m_int[line])
486	486	{
r245142	r245143
490	490	m_iri = 1;
491	491	m_if[line] = 1;
492	492	}
493
	493
494	494	// clock tc if it is in counter mode
495	495	if (m_cf && line == 1)
496	496	increment_tc();
497	497	}
498
	498
499	499	m_int[line] = state;
500	500	}
501	501
r245142	r245143
511	511	// timer prescaler overflow
512	512	if (!m_cf)
513	513	increment_tc();
514
	514
515	515	reset_prescaler();
516	516	}
517	517
r245142	r245143
519	519	{
520	520	// increment timer/counter
521	521	m_tc = (m_tc + 1) & 0xf;
522
	522
523	523	// timer interrupt request on overflow
524	524	if (m_tc == 0 && !m_tf)
525	525	{
r245142	r245143
554	554	while (m_icount > 0)
555	555	{
556	556	m_icount--;
557
	557
558	558	// LPU is handled 1 cycle later
559	559	if ((m_prev_op & 0x3e0) == 0x340)
560	560	{
r245142	r245143
571	571	// remember previous state
572	572	m_prev_op = m_op;
573	573	m_prev_pc = m_pc;
574
	574
575	575	// fetch next opcode
576	576	debugger_instruction_hook(this, m_pc);
577	577	m_op = m_program->read_word(m_pc << 1) & 0x3ff;
r245142	r245143
582	582	switch (m_op)
583	583	{
584	584	/* 0x000 */
585
	585
586	586	case 0x000: case 0x001: case 0x002: case 0x003:
587	587	op_xsp(); break;
588	588	case 0x004: case 0x005: case 0x006: case 0x007:
r245142	r245143
602	602	op_am(); break;
603	603	case 0x03c:
604	604	op_lta(); break;
605
	605
606	606	case 0x040:
607	607	op_lxa(); break;
608	608	case 0x045:
r245142	r245143
626	626	case 0x070: case 0x071: case 0x072: case 0x073: case 0x074: case 0x075: case 0x076: case 0x077:
627	627	case 0x078: case 0x079: case 0x07a: case 0x07b: case 0x07c: case 0x07d: case 0x07e: case 0x07f:
628	628	op_lai(); break;
629
	629
630	630	case 0x080: case 0x081: case 0x082: case 0x083: case 0x084: case 0x085: case 0x086: case 0x087:
631	631	case 0x088: case 0x089: case 0x08a: case 0x08b: case 0x08c: case 0x08d: case 0x08e: case 0x08f:
632	632	op_ai(); break;
r245142	r245143
655	655	case 0x0f0: case 0x0f1: case 0x0f2: case 0x0f3: case 0x0f4: case 0x0f5: case 0x0f6: case 0x0f7:
656	656	case 0x0f8: case 0x0f9: case 0x0fa: case 0x0fb: case 0x0fc: case 0x0fd: case 0x0fe: case 0x0ff:
657	657	op_xamr(); break;
658
659
	658
	659
660	660	/* 0x100 */
661
	661
662	662	case 0x110: case 0x111:
663	663	op_lmaiy(); break;
664	664	case 0x114: case 0x115:
r245142	r245143
682	682	case 0x170: case 0x171: case 0x172: case 0x173: case 0x174: case 0x175: case 0x176: case 0x177:
683	683	case 0x178: case 0x179: case 0x17a: case 0x17b: case 0x17c: case 0x17d: case 0x17e: case 0x17f:
684	684	op_lti(); break;
685
	685
686	686	case 0x1a0:
687	687	op_tif1(); break;
688	688	case 0x1a1:
r245142	r245143
706	706
707	707
708	708	/* 0x200 */
709
	709
710	710	case 0x200: case 0x201: case 0x202: case 0x203:
711	711	op_tm(); break;
712	712	case 0x204: case 0x205: case 0x206: case 0x207:
r245142	r245143
728	728	op_alem(); break;
729	729	case 0x23c:
730	730	op_lat(); break;
731
	731
732	732	case 0x240:
733	733	op_laspx(); break;
734	734	case 0x244:
r245142	r245143
804	804	case 0x3f0: case 0x3f1: case 0x3f2: case 0x3f3: case 0x3f4: case 0x3f5: case 0x3f6: case 0x3f7:
805	805	case 0x3f8: case 0x3f9: case 0x3fa: case 0x3fb: case 0x3fc: case 0x3fd: case 0x3fe: case 0x3ff:
806	806	op_cal(); break;
807
808
	807
	808
809	809	default:
810	810	op_illegal(); break;
811	811	} /* big switch */

trunk/src/emu/cpu/hmcs40/hmcs40.h
r245142	r245143
182	182	int m_eint_line; // which input_line caused an interrupt
183	183	emu_timer *m_timer;
184	184	int m_icount;
185
	185
186	186	UINT16 m_pc; // Program Counter
187	187	UINT16 m_prev_pc;
188	188	UINT8 m_page; // LPU prepared page
r245142	r245143
213	213
214	214	// misc internal helpers
215	215	void increment_pc();
216
	216
217	217	UINT8 ram_r();
218	218	void ram_w(UINT8 data);
219	219	void pop_stack();

trunk/src/emu/cpu/hmcs40/hmcs40d.c
r245142	r245143
3	3	/*
4	4
5	5	Hitachi HMCS40 MCU family disassembler
6
	6
7	7	NOTE: start offset(basepc) is $3F, not 0
8	8
9	9	*/
r245142	r245143
92	92	{
93	93	/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
94	94	/* 0x000 */
95		mNOP, mXSP, mXSP, mXSP, mSEM, mSEM, mSEM, mSEM, mLAM, mLAM, mLAM, mLAM, m, m, m, m,
	95	mNOP, mXSP, mXSP, mXSP, mSEM, mSEM, mSEM, mSEM, mLAM, mLAM, mLAM, mLAM, m, m, m, m,
96	96	mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,
97		mLBM, mLBM, mLBM, mLBM, mBLEM, m, m, m, m, m, m, m, m, m, m, m,
98		mAMC, m, m, m, mAM, m, m, m, m, m, m, m, mLTA, m, m, m,
	97	mLBM, mLBM, mLBM, mLBM, mBLEM, m, m, m, m, m, m, m, m, m, m, m,
	98	mAMC, m, m, m, mAM, m, m, m, m, m, m, m, mLTA, m, m, m,
99	99	/* 0x040 */
100	100	mLXA, m, m, m, m, mDAS, mDAA, m, m, m, m, m, mREC, m, m, mSEC,
101		mLYA, m, m, m, mIY, m, m, m, mAYY, m, m, m, m, m, m, m,
102		mLBA, m, m, m, mIB, m, m, m, m, m, m, m, m, m, m, m,
	101	mLYA, m, m, m, mIY, m, m, m, mAYY, m, m, m, m, m, m, m,
	102	mLBA, m, m, m, mIB, m, m, m, m, m, m, m, m, m, m, m,
103	103	mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI,
104	104	/* 0x080 */
105	105	mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI,
106		mSED, m, m, m, mTD, m, m, m, m, m, m, m, m, m, m, m,
107		mSEIF1,mSECF, mSEIF0,m, mSEIE, mSETF, m, m, m, m, m, m, m, m, m, m,
108		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	106	mSED, m, m, m, mTD, m, m, m, m, m, m, m, m, m, m, m,
	107	mSEIF1,mSECF, mSEIF0,m, mSEIE, mSETF, m, m, m, m, m, m, m, m, m, m,
	108	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
109	109	/* 0x0c0 */
110		mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, m, m, m, m, m, m, m, m,
	110	mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, m, m, m, m, m, m, m, m,
111	111	mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD,
112		mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, m, m, m, m, m, m, m, m,
	112	mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, m, m, m, m, m, m, m, m,
113	113	mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR,
114	114
115	115	/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
116	116	/* 0x100 */
117		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
118		mLMAIY,mLMAIY,m, m, mLMADY,mLMADY,m, m, mLAY, m, m, m, m, m, m, m,
119		mOR, m, m, m, mANEM, m, m, m, m, m, m, m, m, m, m, m,
120		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	117	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	118	mLMAIY,mLMAIY,m, m, mLMADY,mLMADY,m, m, mLAY, m, m, m, m, m, m, m,
	119	mOR, m, m, m, mANEM, m, m, m, m, m, m, m, m, m, m, m,
	120	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
121	121	/* 0x140 */
122	122	mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI,
123	123	mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI,
124	124	mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI,
125	125	mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI,
126	126	/* 0x180 */
127		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
128		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
129		mTIF1, mTI1, mTIF0, mTI0, m, mTTF, m, m, m, m, m, m, m, m, m, m,
130		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	127	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	128	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	129	mTIF1, mTI1, mTIF0, mTI0, m, mTTF, m, m, m, m, m, m, m, m, m, m,
	130	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
131	131	/* 0x1c0 */
132	132	mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR,
133	133	mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR,
r245142	r245143
136	136
137	137	/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
138	138	/* 0x200 */
139		mTM, mTM, mTM, mTM, mREM, mREM, mREM, mREM, mXMA, mXMA, mXMA, mXMA, m, m, m, m,
	139	mTM, mTM, mTM, mTM, mREM, mREM, mREM, mREM, mXMA, mXMA, mXMA, mXMA, m, m, m, m,
140	140	mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI,
141		mXMB, mXMB, mXMB, mXMB, mROTR, mROTL, m, m, m, m, m, m, m, m, m, m,
142		mSMC, m, m, m, mALEM, m, m, m, m, m, m, m, mLAT, m, m, m,
	141	mXMB, mXMB, mXMB, mXMB, mROTR, mROTL, m, m, m, m, m, m, m, m, m, m,
	142	mSMC, m, m, m, mALEM, m, m, m, m, m, m, m, mLAT, m, m, m,
143	143	/* 0x240 */
144	144	mLASPX,m, m, m, mNEGA, m, m, m, m, m, m, m, m, m, m, mTC,
145		mLASPY,m, m, m, mDY, m, m, m, mSYY, m, m, m, m, m, m, m,
146		mLAB, m, m, m, m, m, m, mDB, m, m, m, m, m, m, m, m,
	145	mLASPY,m, m, m, mDY, m, m, m, mSYY, m, m, m, m, m, m, m,
	146	mLAB, m, m, m, m, m, m, mDB, m, m, m, m, m, m, m, m,
147	147	mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI,
148	148	/* 0x280 */
149	149	mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI,
150		mRED, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
151		mREIF1,mRECF, mREIF0,m, mREIE, mRETF, m, m, m, m, m, m, m, m, m, m,
152		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	150	mRED, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	151	mREIF1,mRECF, mREIF0,m, mREIE, mRETF, m, m, m, m, m, m, m, m, m, m,
	152	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
153	153	/* 0x2c0 */
154		mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, m, m, m, m, m, m, m, m,
	154	mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, m, m, m, m, m, m, m, m,
155	155	mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD,
156		mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, m, m, m, m, m, m, m, m,
157		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	156	mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, m, m, m, m, m, m, m, m,
	157	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
158	158
159	159	/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
160	160	/* 0x300 */
161		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
162		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
163		mCOMB, m, m, m, mBNEM, m, m, m, m, m, m, m, m, m, m, m,
164		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	161	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	162	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	163	mCOMB, m, m, m, mBNEM, m, m, m, m, m, m, m, m, m, m, m,
	164	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
165	165	/* 0x340 */
166	166	mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU,
167	167	mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU,
168	168	mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mP, mP, mP, mP, mP, mP, mP, mP,
169		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	169	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
170	170	/* 0x380 */
171		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
172		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
173		m, m, m, m, mRTNI, m, m, mRTN, m, m, m, m, m, m, m, m,
174		m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	171	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	172	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
	173	m, m, m, m, mRTNI, m, m, mRTN, m, m, m, m, m, m, m, m,
	174	m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
175	175	/* 0x3c0 */
176	176	mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL,
177	177	mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL,
r245142	r245143
188	188	char *dst = buffer;
189	189	UINT8 instr = hmcs40_mnemonic[op];
190	190	INT8 bits = s_bits[instr];
191
	191
192	192	// special case for (XY) opcode
193	193	if (bits == 99)
194	194	{
r245142	r245143
202	202	else
203	203	{
204	204	dst += sprintf(dst, "%-6s ", s_mnemonics[instr]);
205
	205
206	206	// opcode parameter
207	207	if (bits != 0)
208	208	{
209	209	UINT8 param = op;
210
	210
211	211	// reverse bits
212	212	if (bits < 0)
213	213	{
r245142	r245143
215	215	param >>= (8 + bits);
216	216	bits = -bits;
217	217	}
218
	218
219	219	param &= ((1 << bits) - 1);
220
	220
221	221	if (bits > 5)
222	222	dst += sprintf(dst, "$%02X", param);
223	223	else
224	224	dst += sprintf(dst, "%d", param);
225	225	}
226	226	}
227
	227
228	228	int pos = s_next_pc[pc & 0x3f] & DASMFLAG_LENGTHMASK;
229	229	return pos \| s_flags[instr] \| DASMFLAG_SUPPORTED;
230	230	}

trunk/src/emu/cpu/hmcs40/hmcs40op.inc
r245142	r245143
73	73	void hmcs40_cpu_device::op_xamr()
74	74	{
75	75	// XAMR m: Exchange A and MR(m)
76
	76
77	77	// determine MR(Memory Register) location
78	78	UINT8 address = m_op & 0xf;
79
	79
80	80	// HMCS42: MR0 on file 0, MR4-MR15 on file 4 (there is no file 1-3)
81	81	// HMCS43: MR0-MR3 on file 0-3, MR4-MR15 on file 4
82	82	if (m_family == FAMILY_HMCS42 \|\| m_family == FAMILY_HMCS43)
83	83	address \|= (address < 4) ? (address << 4) : 0x40;
84
	84
85	85	// HMCS44/45/46/47: all on last file
86	86	else
87	87	address \|= 0xf0;
88
	88
89	89	address &= m_datamask;
90	90	UINT8 old_a = m_a;
91	91	m_a = m_data->read_byte(address) & 0xf;
r245142	r245143
657	657	m_icount--;
658	658	UINT16 address = m_a \| m_b << 4 \| m_c << 8 \| (m_op & 7) << 9 \| (m_pc & ~0x3f);
659	659	UINT16 o = m_program->read_word((address & m_prgmask) << 1);
660
	660
661	661	// destination is determined by the 2 highest bits
662	662	if (o & 0x100)
663	663	{

trunk/src/emu/cpu/i386/i386ops.h
r245142	r245143
333	333	{ 0x3B, OP_2BYTE\|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
334	334	{ 0x3C, OP_2BYTE\|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
335	335	{ 0x3D, OP_2BYTE\|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
336		{ 0x40, OP_2BYTE\|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false},
	336	{ 0x40, OP_2BYTE\|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false},
337	337	{ 0x41, OP_2BYTE\|OP_PENTIUM, &i386_device::pentium_cmovno_r16_rm16, &i386_device::pentium_cmovno_r32_rm32, false},
338	338	{ 0x42, OP_2BYTE\|OP_PENTIUM, &i386_device::pentium_cmovb_r16_rm16, &i386_device::pentium_cmovb_r32_rm32, false},
339	339	{ 0x43, OP_2BYTE\|OP_PENTIUM, &i386_device::pentium_cmovae_r16_rm16, &i386_device::pentium_cmovae_r32_rm32, false},

trunk/src/emu/cpu/i386/pentops.inc
r245142	r245143
1065	1065	void i386_device::i386_cyrix_special() // Opcode 0x0f 3a-3d
1066	1066	{
1067	1067	/*
1068		0f 3a BB0_RESET (set BB0 pointer = base)
1069		0f 3b BB1_RESET (set BB1 pointer = base)
1070		0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax)
1071		0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx])
	1068	0f 3a BB0_RESET (set BB0 pointer = base)
	1069	0f 3b BB1_RESET (set BB1 pointer = base)
	1070	0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax)
	1071	0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx])
1072	1072	*/
1073	1073
1074	1074	CYCLES(1);

trunk/src/emu/cpu/nec/v53.c
r245142	r245143
237	237
238	238	if (m_SCTL & 0x02) // uPD71037 mode
239	239	{
240		if (IOAG) // 8-bit
	240	if (IOAG) // 8-bit
241	241	{
242
243	242	}
244	243	else
245	244	{
r245142	r245143
256	255	UINT16 base = (m_OPHA << 8) \| m_IULA;
257	256	base &= 0xfffe;
258	257
259		if (IOAG) // 8-bit
	258	if (IOAG) // 8-bit
260	259	{
261
262	260	}
263	261	else
264	262	{
r245142	r245143
272	270	//printf("installing TCU to %04x\n", base);
273	271	base &= 0xfffe;
274	272
275		if (IOAG) // 8-bit
	273	if (IOAG) // 8-bit
276	274	{
277
278	275	}
279	276	else
280	277	{
r245142	r245143
290	287	UINT16 base = (m_OPHA << 8) \| m_SULA;
291	288	base &= 0xfffe;
292	289
293		if (IOAG) // 8-bit
	290	if (IOAG) // 8-bit
294	291	{
295
296	292	}
297	293	else
298	294	{
r245142	r245143
333	329	WRITE8_MEMBER(v53_base_device::tmu_tmd_w) { m_v53tcu->write(space, 3, data); }
334	330
335	331
336		READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(space, 0); }
337		READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); }
338		READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); }
	332	READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(space, 0); }
	333	READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); }
	334	READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); }
339	335
340	336
341	337
r245142	r245143
343	339
344	340	/* DMA */
345	341
346		// could be wrong / nonexistent
	342	// could be wrong / nonexistent
347	343	WRITE_LINE_MEMBER(v53_base_device::dreq0_w)
348	344	{
349	345	if (!(m_SCTL & 0x02))
r245142	r245143
409	405	static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
410	406	AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 // uPD71037 DMA mode bank selection register
411	407	AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA)
412		// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2
413		// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3
414		// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4
415		// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5
416		// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6
417		// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7
418		// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8
	408	// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2
	409	// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3
	410	// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4
	411	// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5
	412	// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6
	413	// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7
	414	// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8
419	415	AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 // baud rate counter (used for serial peripheral)
420	416	AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea // waitstate control
421	417	AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb // waitstate control
422	418	AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec // waitstate control
423	419	AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed // waitstate control
424		// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee
425		// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef
	420	// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee
	421	// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef
426	422	AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 // timer clocks
427	423	AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 // internal clock divider, halt behavior etc.
428	424	AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 // ram refresh control
r245142	r245143
430	426	AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 // waitstate control
431	427	AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 // waitstate control
432	428	AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 // waitstate control
433		// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7
	429	// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7
434	430	AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 // peripheral mapping
435	431	AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 // peripheral mapping
436	432	AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa // peripheral mapping
r245142	r245143
438	434	AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc // peripheral mapping (upper bits, common)
439	435	AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd // peripheral enabling
440	436	AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe // peripheral configuration (& byte / word mapping)
441		// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff
	437	// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff
442	438	ADDRESS_MAP_END
443	439
444	440
r245142	r245143
486	482	MCFG_PIT8253_OUT0_HANDLER(WRITELINE( v53_base_device, tcu_out0_trampoline_cb ))
487	483	MCFG_PIT8253_OUT1_HANDLER(WRITELINE( v53_base_device, tcu_out1_trampoline_cb ))
488	484	MCFG_PIT8253_OUT2_HANDLER(WRITELINE( v53_base_device, tcu_out2_trampoline_cb ))
489
490	485
	486
491	487	MCFG_DEVICE_ADD("upd71071dma", V53_DMAU, 4000000)
492	488	MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(v53_base_device, hreq_trampoline_cb))
493	489	MCFG_AM9517A_OUT_EOP_CB(WRITELINE(v53_base_device, eop_trampoline_cb))
r245142	r245143
506	502	MCFG_AM9517A_OUT_DACK_2_CB(WRITELINE(v53_base_device, dma_dack2_trampoline_w))
507	503	MCFG_AM9517A_OUT_DACK_3_CB(WRITELINE(v53_base_device, dma_dack3_trampoline_w))
508	504
509
	505
510	506	MCFG_PIC8259_ADD( "upd71059pic", WRITELINE(v53_base_device, internal_irq_w), VCC, READ8(v53_base_device,get_pic_ack))
511	507
512	508
513	509
514		MCFG_DEVICE_ADD("v53scu", V53_SCU, 0)
	510	MCFG_DEVICE_ADD("v53scu", V53_SCU, 0)
515	511	MCFG_I8251_TXD_HANDLER(WRITELINE(v53_base_device, scu_txd_trampoline_cb))
516	512	MCFG_I8251_DTR_HANDLER(WRITELINE(v53_base_device, scu_dtr_trampoline_cb))
517	513	MCFG_I8251_RTS_HANDLER(WRITELINE(v53_base_device, scu_rts_trampoline_cb))
r245142	r245143
578	574	: v53_base_device(mconfig, V53A, "V53A", tag, owner, clock, "v53a", BYTE_XOR_LE(0), 6, 1, V33_TYPE)
579	575	{
580	576	}
581

trunk/src/emu/cpu/nec/v53.h
r245142	r245143
131	131
132	132	UINT8 m_SCTL;
133	133	UINT8 m_OPSEL;
134
	134
135	135	UINT8 m_SULA;
136	136	UINT8 m_TULA;
137	137	UINT8 m_IULA;
r245142	r245143
151	151	template<class _Object> static devcb_base &set_syndet_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_syndet_handler.set_callback(object); }
152	152	DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb) { m_txd_handler(state); }
153	153	DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb) { m_dtr_handler(state); }
154		DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); }
	154	DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); }
155	155	DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb) { m_rxrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
156	156	DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb) { m_txrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
157		DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); }
	157	DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); }
158	158	DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb) { m_syndet_handler(state); }
159	159
160	160	// TCU
r245142	r245143
165	165	DECLARE_READ8_MEMBER(tmu_tst2_r);
166	166	DECLARE_WRITE8_MEMBER(tmu_tct2_w);
167	167	DECLARE_WRITE8_MEMBER(tmu_tmd_w);
168		// static void set_clk0(device_t &device, double clk0) { downcast<v53_base_device &>(device).m_clk0 = clk0; }
169		// static void set_clk1(device_t &device, double clk1) { downcast<v53_base_device &>(device).m_clk1 = clk1; }
170		// static void set_clk2(device_t &device, double clk2) { downcast<v53_base_device &>(device).m_clk2 = clk2; }
	168	// static void set_clk0(device_t &device, double clk0) { downcast<v53_base_device &>(device).m_clk0 = clk0; }
	169	// static void set_clk1(device_t &device, double clk1) { downcast<v53_base_device &>(device).m_clk1 = clk1; }
	170	// static void set_clk2(device_t &device, double clk2) { downcast<v53_base_device &>(device).m_clk2 = clk2; }
171	171	template<class _Object> static devcb_base &set_out0_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out0_handler.set_callback(object); }
172	172	template<class _Object> static devcb_base &set_out1_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out1_handler.set_callback(object); }
173	173	template<class _Object> static devcb_base &set_out2_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out2_handler.set_callback(object); }
r245142	r245143
195	195	DECLARE_WRITE_LINE_MEMBER(hreq_trampoline_cb) { m_out_hreq_cb(state); }
196	196	DECLARE_WRITE_LINE_MEMBER(eop_trampoline_cb) { m_out_eop_cb(state); }
197	197	DECLARE_READ8_MEMBER(dma_memr_trampoline_r) { return m_in_memr_cb(space, offset); }
198		DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); }
	198	DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); }
199	199	DECLARE_READ8_MEMBER(dma_io_0_trampoline_r) { return m_in_ior_0_cb(space, offset); }
200	200	DECLARE_READ8_MEMBER(dma_io_1_trampoline_r) { return m_in_ior_1_cb(space, offset); }
201	201	DECLARE_READ8_MEMBER(dma_io_2_trampoline_r) { return m_in_ior_2_cb(space, offset); }
r245142	r245143
204	204	DECLARE_WRITE8_MEMBER(dma_io_1_trampoline_w) { m_out_iow_1_cb(space, offset, data); }
205	205	DECLARE_WRITE8_MEMBER(dma_io_2_trampoline_w) { m_out_iow_2_cb(space, offset, data); }
206	206	DECLARE_WRITE8_MEMBER(dma_io_3_trampoline_w) { m_out_iow_3_cb(space, offset, data); }
207		DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); }
208		DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); }
209		DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); }
210		DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); }
	207	DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); }
	208	DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); }
	209	DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); }
	210	DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); }
211	211
212	212
213	213	DECLARE_WRITE_LINE_MEMBER(dreq0_w);
r245142	r245143
221	221	void install_peripheral_io();
222	222
223	223	const address_space_config m_io_space_config;
224
	224
225	225	const address_space_config *memory_space_config(address_spacenum spacenum) const
226	226	{
227	227	switch (spacenum)
r245142	r245143
260	260	devcb_write_line m_syndet_handler;
261	261
262	262	// TCU
263		// double m_clk0;
264		// double m_clk1;
265		// double m_clk2;
	263	// double m_clk0;
	264	// double m_clk1;
	265	// double m_clk2;
266	266	devcb_write_line m_out0_handler;
267	267	devcb_write_line m_out1_handler;
268	268	devcb_write_line m_out2_handler;
r245142	r245143
285	285	devcb_write_line m_out_dack_1_cb;
286	286	devcb_write_line m_out_dack_2_cb;
287	287	devcb_write_line m_out_dack_3_cb;
288
289	288
290	289
	290
291	291	};
292	292
293	293

trunk/src/emu/cpu/pic16c5x/pic16c5x.c
r245142	r245143
799	799	m_program = &space(AS_PROGRAM);
800	800	m_direct = &m_program->direct();
801	801	m_data = &space(AS_DATA);
802
	802
803	803	m_read_a.resolve_safe(0);
804	804	m_read_b.resolve_safe(0);
805	805	m_read_c.resolve_safe(0);

trunk/src/emu/cpu/pic16c5x/pic16c5x.h
r245142	r245143
81	81	* the value if known (available in HEX dumps of the ROM).
82	82	*/
83	83	void pic16c5x_set_config(UINT16 data);
84
	84
85	85	// or with a macro
86	86	static void set_config_static(device_t &device, UINT16 data) { downcast<pic16c5x_device &>(device).m_temp_config = data; }
87	87
r245142	r245143
155	155	address_space *m_program;
156	156	direct_read_data *m_direct;
157	157	address_space *m_data;
158
	158
159	159	// i/o handlers
160	160	devcb_read8 m_read_a;
161	161	devcb_read8 m_read_b;

trunk/src/emu/cpu/z80/kl5c80a12.c
r245142	r245143
1	1	/***************************************************************************
2	2
3		Kawasaki LSI
4		KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
	3	Kawasaki LSI
	4	KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
5	5
6		Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
7		Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
	6	Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
	7	Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
8	8
9		(is this different enough to need it's own core?)
10		(todo: everything, some code currently lives in machine/hng64_net.c but not much)
	9	(is this different enough to need it's own core?)
	10	(todo: everything, some code currently lives in machine/hng64_net.c but not much)
11	11
12	12	***************************************************************************/
13	13

trunk/src/emu/cpu/z80/kl5c80a12.h
r245142	r245143
1	1	/***************************************************************************
2	2
3		Kawasaki LSI
4		KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
	3	Kawasaki LSI
	4	KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
5	5
6		Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
7		Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
	6	Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
	7	Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
8	8
9		(is this different enough to need it's own core?)
10		(todo: everything, some code currently lives in machine/hng64_net.c but not much)
	9	(is this different enough to need it's own core?)
	10	(todo: everything, some code currently lives in machine/hng64_net.c but not much)
11	11
12	12	***************************************************************************/
13	13

trunk/src/emu/machine/am9517a.c
r245142	r245143
3	3	/***************************************************************************
4	4
5	5	AMD AM9517A
6		Intel 8237A
7		NEC uPD71037
	6	Intel 8237A
	7	NEC uPD71037
8	8
9		NEC uPD71071 (extended version of above)
	9	NEC uPD71071 (extended version of above)
10	10
11		a variant is used in the V53 CPU which offers subsets of both the
12		uPD71071 and uPD71037 functionality depending on a mode bit.
13
14		Multimode DMA Controller emulation
	11	a variant is used in the V53 CPU which offers subsets of both the
	12	uPD71071 and uPD71037 functionality depending on a mode bit.
15	13
	14	Multimode DMA Controller emulation
	15
16	16	Copyright the MESS Team.
17	17	Visit http://mamedev.org for licensing and usage restrictions.
18	18
r245142	r245143
28	28
29	29	/*
30	30
31		When the V53 operates in uPD71071 compatible mode there are the following
32		differences from a real uPD71071
	31	When the V53 operates in uPD71071 compatible mode there are the following
	32	differences from a real uPD71071
33	33
34		V53 Real uPD71071
35		Software Reqs No Yes
36		Memory-to-Memory DMA No Yes
37		DMARQ active level High programmable
38		DMAAK active level Low programmable
39		Bus Cycle 4 4 or 3
	34	V53 Real uPD71071
	35	Software Reqs No Yes
	36	Memory-to-Memory DMA No Yes
	37	DMARQ active level High programmable
	38	DMAAK active level Low programmable
	39	Bus Cycle 4 4 or 3
40	40
41		we don't currently handle the differences
	41	we don't currently handle the differences
42	42
43	43	*/
44	44
r245142	r245143
1158	1158	ret = m_command & 0xff;
1159	1159	break;
1160	1160	case 0x09: // Device control (high) // UPD71071 only?
1161		ret = m_command_high & 0xff;
	1161	ret = m_command_high & 0xff;
1162	1162	break;
1163	1163	case 0x0b: // Status
1164	1164	ret = m_status;
r245142	r245143
1187	1187	WRITE8_MEMBER(upd71071_v53_device::write)
1188	1188	{
1189	1189	int channel = m_selected_channel;
1190
	1190
1191	1191	switch (offset)
1192	1192	{
1193	1193	case 0x00: // Initialise
1194	1194	// TODO: reset (bit 0)
1195	1195	//m_buswidth = data & 0x02;
1196	1196	//if (data & 0x01)
1197		// soft_reset();
	1197	// soft_reset();
1198	1198	logerror("DMA: Initialise [%02x]\n", data);
1199	1199	break;
1200	1200	case 0x01: // Channel
r245142	r245143
1279	1279	}
1280	1280	trigger(1);
1281	1281
1282		}
		No newline at end of file
	1282	}

trunk/src/emu/machine/am9517a.h
r245142	r245143
172	172	virtual void device_start();
173	173	virtual void device_reset();
174	174
175		int m_selected_channel;
	175	int m_selected_channel;
176	176	int m_base;
177	177	UINT8 m_command_high;
178	178

trunk/src/emu/machine/i8251.c
r245142	r245143
3	3	i8251.c
4	4
5	5	Intel 8251 Universal Synchronous/Asynchronous Receiver Transmitter code
6		NEC uPD71051 is a clone
	6	NEC uPD71051 is a clone
7	7
8		The V53/V53A use a customized version with only the Asynchronous mode
9		and a split command / mode register
	8	The V53/V53A use a customized version with only the Asynchronous mode
	9	and a split command / mode register
10	10
11	11
12	12
r245142	r245143
428	428
429	429
430	430	/* bit 7:
431		0 = normal operation
432		1 = hunt mode
433		bit 6:
434		0 = normal operation
435		1 = internal reset
436		bit 5:
437		0 = /RTS set to 1
438		1 = /RTS set to 0
439		bit 4:
440		0 = normal operation
441		1 = reset error flag
442		bit 3:
443		0 = normal operation
444		1 = send break character
445		bit 2:
446		0 = receive disable
447		1 = receive enable
448		bit 1:
449		0 = /DTR set to 1
450		1 = /DTR set to 0
451		bit 0:
452		0 = transmit disable
453		1 = transmit enable
	431	0 = normal operation
	432	1 = hunt mode
	433	bit 6:
	434	0 = normal operation
	435	1 = internal reset
	436	bit 5:
	437	0 = /RTS set to 1
	438	1 = /RTS set to 0
	439	bit 4:
	440	0 = normal operation
	441	1 = reset error flag
	442	bit 3:
	443	0 = normal operation
	444	1 = send break character
	445	bit 2:
	446	0 = receive disable
	447	1 = receive enable
	448	bit 1:
	449	0 = /DTR set to 1
	450	1 = /DTR set to 0
	451	bit 0:
	452	0 = transmit disable
	453	1 = transmit enable
454	454	*/
455	455
456	456	m_rts_handler(!BIT(data, 5));
r245142	r245143
484	484	{
485	485	/* Asynchronous
486	486
487		bit 7,6: stop bit length
488		0 = inhibit
489		1 = 1 bit
490		2 = 1.5 bits
491		3 = 2 bits
492		bit 5: parity type
493		0 = parity odd
494		1 = parity even
495		bit 4: parity test enable
496		0 = disable
497		1 = enable
498		bit 3,2: character length
499		0 = 5 bits
500		1 = 6 bits
501		2 = 7 bits
502		3 = 8 bits
503		bit 1,0: baud rate factor
504		0 = defines command byte for synchronous or asynchronous
505		1 = x1
506		2 = x16
507		3 = x64
508		*/
	487	bit 7,6: stop bit length
	488	0 = inhibit
	489	1 = 1 bit
	490	2 = 1.5 bits
	491	3 = 2 bits
	492	bit 5: parity type
	493	0 = parity odd
	494	1 = parity even
	495	bit 4: parity test enable
	496	0 = disable
	497	1 = enable
	498	bit 3,2: character length
	499	0 = 5 bits
	500	1 = 6 bits
	501	2 = 7 bits
	502	3 = 8 bits
	503	bit 1,0: baud rate factor
	504	0 = defines command byte for synchronous or asynchronous
	505	1 = x1
	506	2 = x16
	507	3 = x64
	508	*/
509	509
510	510	LOG(("I8251: Asynchronous operation\n"));
511	511
r245142	r245143
597	597	else
598	598	{
599	599	/* bit 7: Number of sync characters
600		0 = 1 character
601		1 = 2 character
602		bit 6: Synchronous mode
603		0 = Internal synchronisation
604		1 = External synchronisation
605		bit 5: parity type
606		0 = parity odd
607		1 = parity even
608		bit 4: parity test enable
609		0 = disable
610		1 = enable
611		bit 3,2: character length
612		0 = 5 bits
613		1 = 6 bits
614		2 = 7 bits
615		3 = 8 bits
616		bit 1,0 = 0
617		*/
	600	0 = 1 character
	601	1 = 2 character
	602	bit 6: Synchronous mode
	603	0 = Internal synchronisation
	604	1 = External synchronisation
	605	bit 5: parity type
	606	0 = parity odd
	607	1 = parity even
	608	bit 4: parity test enable
	609	0 = disable
	610	1 = enable
	611	bit 3,2: character length
	612	0 = 5 bits
	613	1 = 6 bits
	614	2 = 7 bits
	615	3 = 8 bits
	616	bit 1,0 = 0
	617	*/
618	618	LOG(("I8251: Synchronous operation\n"));
619	619
620	620	/* setup for sync byte(s) */

trunk/src/emu/machine/i8257.c
r245142	r245143
79	79	}
80	80	else
81	81	{
82		m_request &= ~(1 << channel);
	82	m_request &= ~(1 << channel);
83	83	}
84	84	trigger(1);
85	85	}

trunk/src/emu/machine/machine.mak
r245142	r245143
1369	1369
1370	1370	#-------------------------------------------------
1371	1371	#
1372		#@src/emu/machine/64h156.h,MACHINES += R~~P5C~~15
	1372	#@src/emu/machine/64h156.h,MACHINES += R64H156
1373	1373	#-------------------------------------------------
1374	1374
1375	1375	ifneq ($(filter R64H156,$(MACHINES)),)

trunk/src/emu/machine/mcf5206e.c
r245142	r245143
860	860	init_regs(true);
861	861
862	862	m_timer1 = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( mcf5206e_peripheral_device::timer1_callback ), this) );
863
	863
864	864	save_item(NAME(m_ICR));
865	865	save_item(NAME(m_CSAR));
866	866	save_item(NAME(m_CSMR));

trunk/src/emu/machine/tmp68301.c
r245142	r245143
123	123
124	124	m_in_parallel_cb.resolve_safe(0);
125	125	m_out_parallel_cb.resolve_safe();
126
	126
127	127	save_item(NAME(m_regs));
128	128	save_item(NAME(m_IE));
129	129	save_item(NAME(m_irq_vector));

trunk/src/emu/machine/upd71071.c
r245142	r245143
1	1
2	2	/*
3	3
4		am9517a.c is a more complete implementation of this, the uPD71071 appears to be a clone of it
	4	am9517a.c is a more complete implementation of this, the uPD71071 appears to be a clone of it
5	5
6	6	NEC uPD71071 DMA Controller
7	7	Used on the Fujitsu FM-Towns
r245142	r245143
31	31	Self-explanatory, I hope. :)
32	32	NOTE: Datasheet clearly shows this as 24-bit, with register 7 unused.
33	33	But the FM-Towns definitely uses reg 7 as bits 24-31.
34		The documentation on the V53A manual doesn't show these bits either, maybe it's
35		an external connection on the FMT? might be worth checking overflow behavior etc.
	34	The documentation on the V53A manual doesn't show these bits either, maybe it's
	35	an external connection on the FMT? might be worth checking overflow behavior etc.
36	36
37	37	0x08:
38	38	0x09: Device Control register (16-bit)
r245142	r245143
77	77	0x0f: Mask register
78	78	bit 0-3: DMARQ mask
79	79	bits 1 and 0 only in MTM transfers
80
81		Note, the uPD71071 compatible mode of the V53 CPU differs from a real uPD71071 in the following ways
82	80
	81	Note, the uPD71071 compatible mode of the V53 CPU differs from a real uPD71071 in the following ways
83	82
84	83
	84
85	85	*/
86	86
87	87	#include "emu.h"

trunk/src/emu/machine/vrc4373.c
r245142	r245143
13	13
14	14	// cpu i/f map
15	15	DEVICE_ADDRESS_MAP_START(cpu_map, 32, vrc4373_device)
16		AM_RANGE(0x00000000, 0x0000007b) AM_READWRITE( vrc~~4373_device::c~~pu_if_r, ~~vrc4373_device::~~cpu_if_w)
	16	AM_RANGE(0x00000000, 0x0000007b) AM_READWRITE( cpu_if_r, cpu_if_w)
17	17	ADDRESS_MAP_END
18	18
19	19	// Target Window 1 map
20	20	DEVICE_ADDRESS_MAP_START(target1_map, 32, vrc4373_device)
21		AM_RANGE(0x00000000, 0xFFFFFFFF) AM_READWRITE( ~~vrc4373_device::~~target1_r, ~~vrc4373_device::~~target1_w)
	21	AM_RANGE(0x00000000, 0xFFFFFFFF) AM_READWRITE( target1_r, target1_w)
22	22	ADDRESS_MAP_END
23	23
24	24	// Target Window 2 map
25	25	DEVICE_ADDRESS_MAP_START(target2_map, 32, vrc4373_device)
26		AM_RANGE(0x00000000, 0xFFFFFFFF) AM_READWRITE( ~~vrc4373_device::~~target2_r, ~~vrc4373_device::~~target2_w)
	26	AM_RANGE(0x00000000, 0xFFFFFFFF) AM_READWRITE( target2_r, target2_w)
27	27	ADDRESS_MAP_END
28	28
29	29	vrc4373_device::vrc4373_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
r245142	r245143
111	111	if (LOG_NILE)
112	112	logerror("%s: map_extra Master Window 2 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci2_laddr);
113	113	}
114		// PCI IO Window
	114	// PCI IO Window
115	115	if (m_cpu_regs[NREG_PCIMIOW]&0x1000) {
116	116	winStart = m_cpu_regs[NREG_PCIMIOW]&0xff000000;
117	117	winEnd = winStart \| (~(0x80000000 \| (((m_cpu_regs[NREG_PCIMIOW]>>13)&0x7f)<<24)));
r245142	r245143
122	122	logerror("%s: map_extra IO Window start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci_io_laddr);
123	123	}
124	124	// PCI Target Window 1
125		if (m_cpu_regs[NREG_PCITW1]&0x1000) {
	125	if (m_cpu_regs[NREG_PCITW1]&0x1000) {
126	126	winStart = m_cpu_regs[NREG_PCITW1]&0xffe00000;
127	127	winEnd = winStart \| (~(0xf0000000 \| (((m_cpu_regs[NREG_PCITW1]>>13)&0x7f)<<21)));
128	128	winSize = winEnd - winStart + 1;
r245142	r245143
242	242	logerror("%06X:nile target2 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
243	243	}
244	244
245		// CPU I/F
	245	// CPU I/F
246	246	READ32_MEMBER (vrc4373_device::cpu_if_r)
247	247	{
248	248	UINT32 result = m_cpu_regs[offset];
r245142	r245143
290	290	case NREG_PCICAR:
291	291	// Bits in reserved area are used for device selection of type 0 config transactions
292	292	// Assuming 23:11 get mapped into device number for configuration
293		if ((data&0x3) == 0x0) {
	293	if ((data&0x3) == 0x0) {
294	294	// Type 0 transaction
295	295	modData = 0;
296	296	// Select the device based on one hot bit
r245142	r245143
341	341	}
342	342
343	343	}
344

trunk/src/emu/machine/vrc4373.h
r245142	r245143
10	10	downcast<vrc4373_device *>(device)->set_cpu_tag(_cpu_tag);
11	11
12	12	#define VRC4373_PAGESHIFT 12
13
	13
14	14	/* NILE 3 registers 0x000-0x0ff */
15		#define NREG_BMCR (0x000/4)
16		#define NREG_SIMM1 (0x004/4)
17		#define NREG_SIMM2 (0x008/4)
18		#define NREG_SIMM3 (0x00C/4)
19		#define NREG_SIMM4 (0x010/4)
	15	#define NREG_BMCR (0x000/4)
	16	#define NREG_SIMM1 (0x004/4)
	17	#define NREG_SIMM2 (0x008/4)
	18	#define NREG_SIMM3 (0x00C/4)
	19	#define NREG_SIMM4 (0x010/4)
20	20	#define NREG_PCIMW1 (0x014/4)
21	21	#define NREG_PCIMW2 (0x018/4)
22	22	#define NREG_PCITW1 (0x01C/4)
r245142	r245143
57	57	void set_cpu_tag(const char *tag);
58	58
59	59	virtual DECLARE_ADDRESS_MAP(config_map, 32);
60
	60
61	61	DECLARE_READ32_MEMBER( pcictrl_r);
62	62	DECLARE_WRITE32_MEMBER( pcictrl_w);
63	63	//cpu bus registers
r245142	r245143
76	76	virtual DECLARE_ADDRESS_MAP(target1_map, 32);
77	77	DECLARE_READ32_MEMBER (target1_r);
78	78	DECLARE_WRITE32_MEMBER(target1_w);
79
	79
80	80	virtual DECLARE_ADDRESS_MAP(target2_map, 32);
81	81	DECLARE_READ32_MEMBER (target2_r);
82	82	DECLARE_WRITE32_MEMBER(target2_w);

trunk/src/emu/mame.c
r245142	r245143
286	286
287	287	// pop it in the UI
288	288	machine_manager::instance()->machine()->ui().popup_time(temp.len() / 40 + 2, "%s", temp.cstr());
289
	289
290	290	/*
291	291	// also write to error.log
292	292	logerror("popmessage: %s\n", temp.cstr());
293
	293
294	294	#ifdef MAME_DEBUG
295	295	// and to command-line in a DEBUG build
296	296	osd_printf_info("popmessage: %s\n", temp.cstr());

trunk/src/emu/render.c
r245142	r245143
2494	2494	orient = orientation_add(m_ui_target->orientation(), m_ui_container->orientation());
2495	2495	// based on the orientation of the target, compute height/width or width/height
2496	2496	if (!(orient & ORIENTATION_SWAP_XY))
2497		aspect = (float)m_ui_target->height() / (float)m_ui_target->width();
	2497	aspect = (float)m_ui_target->height() / (float)m_ui_target->width();
2498	2498	else
2499		aspect = (float)m_ui_target->width() / (float)m_ui_target->height();
	2499	aspect = (float)m_ui_target->width() / (float)m_ui_target->height();
2500	2500
2501	2501	// if we have a valid pixel aspect, apply that and return
2502	2502	if (m_ui_target->pixel_aspect() != 0.0f)
2503		return (aspect / m_ui_target->pixel_aspect());
	2503	return (aspect / m_ui_target->pixel_aspect());
2504	2504	} else {
2505	2505	// single screen container
2506	2506

trunk/src/emu/sound/es1373.h
r245142	r245143
9	9	MCFG_PCI_DEVICE_ADD(_tag, ES1373, 0x12741371, 0x04, 0x040100, 0x12741371)
10	10
11	11	/* Ensonic ES1373 registers 0x00-0x3f */
12		#define ES_INT_CS_CTRL (0x00/4)
13		#define ES_INT_CS_STATUS (0x04/4)
14		#define ES_UART_DATA (0x08/4)
15		#define ES_UART_STATUS (0x09/4)
16		#define ES_UART_CTRL (0x09/4)
17		#define ES_UART_RSVD (0x0A/4)
18		#define ES_MEM_PAGE (0x0C/4)
19		#define ES_SRC_IF (0x10/4)
20		#define ES_CODEC (0x14/4)
21		#define ES_LEGACY (0x18/4)
22		#define ES_CHAN_CTRL (0x1C/4)
23		#define ES_SERIAL_CTRL (0x20/4)
24		#define ES_DAC1_CNT (0x24/4)
25		#define ES_DAC2_CNT (0x28/4)
26		#define ES_ADC_CNT (0x2C/4)
27		#define ES_ADC_CNT (0x2C/4)
28		#define ES_HOST_IF0 (0x30/4)
29		#define ES_HOST_IF1 (0x34/4)
30		#define ES_HOST_IF2 (0x38/4)
31		#define ES_HOST_IF3 (0x3C/4)
	12	#define ES_INT_CS_CTRL (0x00/4)
	13	#define ES_INT_CS_STATUS (0x04/4)
	14	#define ES_UART_DATA (0x08/4)
	15	#define ES_UART_STATUS (0x09/4)
	16	#define ES_UART_CTRL (0x09/4)
	17	#define ES_UART_RSVD (0x0A/4)
	18	#define ES_MEM_PAGE (0x0C/4)
	19	#define ES_SRC_IF (0x10/4)
	20	#define ES_CODEC (0x14/4)
	21	#define ES_LEGACY (0x18/4)
	22	#define ES_CHAN_CTRL (0x1C/4)
	23	#define ES_SERIAL_CTRL (0x20/4)
	24	#define ES_DAC1_CNT (0x24/4)
	25	#define ES_DAC2_CNT (0x28/4)
	26	#define ES_ADC_CNT (0x2C/4)
	27	#define ES_ADC_CNT (0x2C/4)
	28	#define ES_HOST_IF0 (0x30/4)
	29	#define ES_HOST_IF1 (0x34/4)
	30	#define ES_HOST_IF2 (0x38/4)
	31	#define ES_HOST_IF3 (0x3C/4)
32	32
33	33	struct frame_reg {
34	34	UINT32 pci_addr;

trunk/src/emu/sound/flt_rc.c
r245142	r245143
37	37	{
38	38	m_stream = stream_alloc(1, 1, machine().sample_rate());
39	39	recalc();
40
	40
41	41	save_item(NAME(m_k));
42	42	save_item(NAME(m_memory));
43	43	save_item(NAME(m_type));

trunk/src/emu/sound/okim9810.c
r245142	r245143
115	115	save_item(NAME(m_global_volume));
116	116	save_item(NAME(m_filter_type));
117	117	save_item(NAME(m_output_level));
118
	118
119	119	for (int i = 0; i < OKIM9810_VOICES; i++)
120	120	{
121	121	okim_voice *voice = get_voice(i);
122
	122
123	123	save_item(NAME(voice->m_adpcm.m_signal), i);
124	124	save_item(NAME(voice->m_adpcm.m_step), i);
125	125	save_item(NAME(voice->m_adpcm2.m_signal), i);

trunk/src/emu/sound/okim9810.h
r245142	r245143
135	135	};
136	136
137	137	okim_voice *get_voice(int which);
138
	138
139	139	// internal state
140	140	const address_space_config m_space_config;
141	141

trunk/src/emu/video.c
r245142	r245143
153	153	filename = machine.options().avi_write();
154	154	if (filename[0] != 0)
155	155	begin_recording(filename, MF_AVI);
156
	156
157	157	#ifdef MAME_DEBUG
158	158	m_dummy_recording = machine.options().dummy_write();
159	159	#endif

trunk/src/emu/video.h
r245142	r245143
176	176	attotime m_avi_frame_period; // period of a single movie frame
177	177	attotime m_avi_next_frame_time; // time of next frame
178	178	UINT32 m_avi_frame; // current movie frame number
179
	179
180	180	// movie recording - dummy
181		bool m_dummy_recording; // indicates if snapshot should be created of every frame
	181	bool m_dummy_recording; // indicates if snapshot should be created of every frame
182	182
183	183	static const UINT8 s_skiptable[FRAMESKIP_LEVELS][FRAMESKIP_LEVELS];
184	184

trunk/src/emu/video/tms34061.c
r245142	r245143
60	60
61	61	/* allocate memory for VRAM */
62	62	m_vram = auto_alloc_array_clear(machine(), UINT8, m_vramsize + 256 * 2);
63
	63
64	64	/* allocate memory for latch RAM */
65	65	m_latchram = auto_alloc_array_clear(machine(), UINT8, m_vramsize + 256 * 2);
66	66
r245142	r245143
93	93
94	94	/* start vertical interrupt timer */
95	95	m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tms34061_device::interrupt), this));
96
	96
97	97	save_item(NAME(m_regs));
98	98	save_item(NAME(m_xmask));
99	99	save_item(NAME(m_yshift));

trunk/src/emu/video/voodoo_pci.c
r245142	r245143
56	56	return;
57	57	if(UINT32(bi.adr) == UINT32(~(bi.size - 1)))
58	58	return;
59
	59
60	60	UINT64 start;
61	61	address_space *space;
62	62	if(bi.flags & M_IO) {

trunk/src/lib/formats/d88_dsk.c
r245142	r245143
27	27	*
28	28	*/
29	29
30		#include <assert.h>
31
	30	#include <assert.h>
	31
32	32	#include "flopimg.h"
33	33	#include "imageutl.h"
34	34

trunk/src/lib/formats/flex_dsk.c
r245142	r245143
4	4	* Created on: 24/06/2014
5	5	*/
6	6
7		#include "emu.h" // logerror
	7	#include "emu.h" // logerror
8	8	#include "flex_dsk.h"
9	9
10	10	flex_format::flex_format()

trunk/src/lib/formats/fmtowns_dsk.c
r245142	r245143
6	6	* Created on: 23/03/2014
7	7	*/
8	8
9		#include <assert.h>
10
	9	#include <assert.h>
	10
11	11	#include "formats/fmtowns_dsk.h"
12	12
13	13	fmtowns_format::fmtowns_format() : wd177x_format(formats)

trunk/src/lib/formats/nfd_dsk.c
r245142	r245143
77	77
78	78	*********************************************************************/
79	79
80		#include <assert.h>
81
	80	#include <assert.h>
	81
82	82	#include "nfd_dsk.h"
83	83
84	84	nfd_format::nfd_format()

trunk/src/mame/audio/hng64.c
r245142	r245143
191	191
192	192	WRITE16_MEMBER(hng64_state::hng64_sound_port_0008_w)
193	193	{
194		// logerror("hng64_sound_port_0008_w %04x %04x\n", data, mem_mask);
	194	// logerror("hng64_sound_port_0008_w %04x %04x\n", data, mem_mask);
195	195	// seems to one or more of the DMARQ on the V53, writes here when it expects DMA channel 3 to transfer ~0x20 bytes just after startup
196	196
197	197
198	198	m_audiocpu->dreq3_w(data&1);
199		// m_audiocpu->hack_w(1);
	199	// m_audiocpu->hack_w(1);
200	200
201	201	}
202	202
r245142	r245143
262	262	{
263	263	m_audiodat[m_audiochannel].dat[2] = data;
264	264
265		// if ((m_audiochannel & 0xff00) == 0x0a00)
266		// printf("write port 0x0002 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
	265	// if ((m_audiochannel & 0xff00) == 0x0a00)
	266	// printf("write port 0x0002 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
267	267	}
268	268
269	269	WRITE16_MEMBER(hng64_state::hng64_sound_data_04_w)
270	270	{
271	271	m_audiodat[m_audiochannel].dat[1] = data;
272	272
273		// if ((m_audiochannel & 0xff00) == 0x0a00)
274		// printf("write port 0x0004 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
	273	// if ((m_audiochannel & 0xff00) == 0x0a00)
	274	// printf("write port 0x0004 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
275	275	}
276	276	WRITE16_MEMBER(hng64_state::hng64_sound_data_06_w)
277	277	{
278	278	m_audiodat[m_audiochannel].dat[0] = data;
279	279
280		// if ((m_audiochannel & 0xff00) == 0x0a00)
281		// printf("write port 0x0006 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
	280	// if ((m_audiochannel & 0xff00) == 0x0a00)
	281	// printf("write port 0x0006 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
282	282	}
283	283
284	284	// but why not just use the V33/V53 XA mode??
r245142	r245143
414	414	WRITE_LINE_MEMBER(hng64_state::tcu_tm1_cb)
415	415	{
416	416	// these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1
417		// logerror("tcu_tm1_cb %02x\n", state);
	417	// logerror("tcu_tm1_cb %02x\n", state);
418	418	m_audiocpu->set_input_line(5, state? ASSERT_LINE:CLEAR_LINE); // not accurate, just so we have a trigger
419	419	}
420	420
421	421	WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb)
422	422	{
423	423	// these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1
424		// logerror("tcu_tm2_cb %02x\n", state);
	424	// logerror("tcu_tm2_cb %02x\n", state);
425	425
426	426	// NOT ACCURATE, just so that all the interrupts get triggered for now.
427	427	static int i = 0;
428		m_audiocpu->set_input_line(i, state? ASSERT_LINE:CLEAR_LINE);
	428	m_audiocpu->set_input_line(i, state? ASSERT_LINE:CLEAR_LINE);
429	429	i++;
430	430	if (i == 3) i = 0;
431	431	}
r245142	r245143
445	445	MCFG_V53_TCU_OUT2_HANDLER(WRITELINE(hng64_state, tcu_tm2_cb))
446	446
447	447	MACHINE_CONFIG_END
448
449

trunk/src/mame/drivers/argus.c
r245142	r245143
548	548
549	549	MCFG_GFXDECODE_ADD("gfxdecode", "palette", argus)
550	550	MCFG_PALETTE_ADD("palette", 896)
551
	551
552	552	MCFG_DEVICE_ADD("blend", JALECO_BLEND, 0)
553	553
554	554	MCFG_VIDEO_START_OVERRIDE(argus_state,argus)
r245142	r245143
594	594
595	595	MCFG_GFXDECODE_ADD("gfxdecode", "palette", valtric)
596	596	MCFG_PALETTE_ADD("palette", 768)
597
	597
598	598	MCFG_DEVICE_ADD("blend", JALECO_BLEND, 0)
599	599
600	600	MCFG_VIDEO_START_OVERRIDE(argus_state,valtric)
r245142	r245143
640	640
641	641	MCFG_GFXDECODE_ADD("gfxdecode", "palette", butasan)
642	642	MCFG_PALETTE_ADD("palette", 768)
643
	643
644	644	MCFG_DEVICE_ADD("blend", JALECO_BLEND, 0)
645	645
646	646	MCFG_VIDEO_START_OVERRIDE(argus_state,butasan)

trunk/src/mame/drivers/astrcorp.c
r245142	r245143
1159	1159	for (i = 0x25100/2; i < 0x25200/2; i++)
1160	1160	{
1161	1161	x = 0x0000;
1162		if ( (i & 0x0001) ) x \|= 0x0200;
1163		if ( (i & 0x0004) && !(i & 0x0001) ) x \|= 0x0080;
1164		if ( (i & 0x0040) \|\| (i & 0x0001) ) x \|= 0x0040;
1165		if ( (i & 0x0010) && !(i & 0x0001) ) x \|= 0x0020;
1166		if ( !(i & 0x0020) \|\| (i & 0x0001) ) x \|= 0x0010;
1167		if ( (i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0008;
1168		if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0004;
1169		if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0002;
1170		if ( (i & 0x0040) && !(i & 0x0001) ) x \|= 0x0001;
	1162	if ( (i & 0x0001) ) x \|= 0x0200;
	1163	if ( (i & 0x0004) && !(i & 0x0001) ) x \|= 0x0080;
	1164	if ( (i & 0x0040) \|\| (i & 0x0001) ) x \|= 0x0040;
	1165	if ( (i & 0x0010) && !(i & 0x0001) ) x \|= 0x0020;
	1166	if ( !(i & 0x0020) \|\| (i & 0x0001) ) x \|= 0x0010;
	1167	if ( (i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0008;
	1168	if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0004;
	1169	if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0002;
	1170	if ( (i & 0x0040) && !(i & 0x0001) ) x \|= 0x0001;
1171	1171	rom[i] ^= x;
1172	1172	}
1173	1173
1174	1174	/*
1175		for (i = 0x25300/2; i < 0x25400/2; i++)
1176		{
1177		x = 0x1300;
1178		rom[i] ^= x;
1179		}
	1175	for (i = 0x25300/2; i < 0x25400/2; i++)
	1176	{
	1177	x = 0x1300;
	1178	rom[i] ^= x;
	1179	}
1180	1180	*/
1181	1181
1182	1182	for (i = 0x25400/2; i < 0x25500/2; i++)
1183	1183	{
1184	1184	x = 0x4200;
1185		if ( (i & 0x0001) ) x \|= 0x0400;
1186		if ( (i & 0x0020) && !(i & 0x0001) ) x \|= 0x0080;
1187		if ( !(i & 0x0010) \|\| (i & 0x0001) ) x \|= 0x0040;
1188		if ( (i & 0x0040) && !(i & 0x0001) ) x \|= 0x0020;
1189		if ( !(i & 0x0004) \|\| (i & 0x0001) ) x \|= 0x0010;
1190		if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0004;
1191		if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0002;
1192		if ( (i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0001;
	1185	if ( (i & 0x0001) ) x \|= 0x0400;
	1186	if ( (i & 0x0020) && !(i & 0x0001) ) x \|= 0x0080;
	1187	if ( !(i & 0x0010) \|\| (i & 0x0001) ) x \|= 0x0040;
	1188	if ( (i & 0x0040) && !(i & 0x0001) ) x \|= 0x0020;
	1189	if ( !(i & 0x0004) \|\| (i & 0x0001) ) x \|= 0x0010;
	1190	if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0004;
	1191	if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0002;
	1192	if ( (i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0001;
1193	1193	rom[i] ^= x;
1194	1194	}
1195	1195
1196	1196	for (i = 0x25500/2; i < 0x25600/2; i++)
1197	1197	{
1198	1198	x = 0x4200;
1199		if ( (i & 0x0001) ) x \|= 0x0400;
1200		if ( (i & 0x0010) && !(i & 0x0001) ) x \|= 0x0080;
1201		if ( (i & 0x0040) && !(i & 0x0001) ) x \|= 0x0040;
1202		if ( !(i & 0x0002) && !(i & 0x0001) ) x \|= 0x0020;
1203		if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0010;
1204		if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0008;
1205		if ( (i & 0x0020) && !(i & 0x0001) ) x \|= 0x0004;
1206		if ( (i & 0x0004) && !(i & 0x0001) ) x \|= 0x0002;
1207		if ( (i & 0x0001) ) x \|= 0x0001;
	1199	if ( (i & 0x0001) ) x \|= 0x0400;
	1200	if ( (i & 0x0010) && !(i & 0x0001) ) x \|= 0x0080;
	1201	if ( (i & 0x0040) && !(i & 0x0001) ) x \|= 0x0040;
	1202	if ( !(i & 0x0002) && !(i & 0x0001) ) x \|= 0x0020;
	1203	if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0010;
	1204	if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0008;
	1205	if ( (i & 0x0020) && !(i & 0x0001) ) x \|= 0x0004;
	1206	if ( (i & 0x0004) && !(i & 0x0001) ) x \|= 0x0002;
	1207	if ( (i & 0x0001) ) x \|= 0x0001;
1208	1208	rom[i] ^= x;
1209	1209	}
1210	1210
1211	1211	/*
1212		for (i = 0x25700/2; i < 0x25800/2; i++)
1213		{
1214		x = 0x6800;
1215		if ( !(i & 0x0001) ) x \|= 0x8000;
	1212	for (i = 0x25700/2; i < 0x25800/2; i++)
	1213	{
	1214	x = 0x6800;
	1215	if ( !(i & 0x0001) ) x \|= 0x8000;
1216	1216
1217		if ( !(i & 0x0040) \|\| ((i & 0x0001) \|\| !(i & 0x0001)) ) x \|= 0x0100;
	1217	if ( !(i & 0x0040) \|\| ((i & 0x0001) \|\| !(i & 0x0001)) ) x \|= 0x0100;
1218	1218
1219		rom[i] ^= x;
1220		}
	1219	rom[i] ^= x;
	1220	}
1221	1221	*/
1222	1222
1223	1223	for (i = 0x25800/2; i < 0x25900/2; i++)
1224	1224	{
1225	1225	x = 0x8300;
1226		if ( (i & 0x0040) \|\| (i & 0x0001) ) x \|= 0x2000;
1227		if ( (i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0080;
1228		if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0040;
1229		if ( (i & 0x0020) && !(i & 0x0001) ) x \|= 0x0020;
1230		if ( !(i & 0x0004) \|\| (i & 0x0001) ) x \|= 0x0010;
1231		if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0008;
1232		if ( (i & 0x0010) && !(i & 0x0001) ) x \|= 0x0004;
1233		if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0002;
1234		if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0001;
	1226	if ( (i & 0x0040) \|\| (i & 0x0001) ) x \|= 0x2000;
	1227	if ( (i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0080;
	1228	if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0040;
	1229	if ( (i & 0x0020) && !(i & 0x0001) ) x \|= 0x0020;
	1230	if ( !(i & 0x0004) \|\| (i & 0x0001) ) x \|= 0x0010;
	1231	if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0008;
	1232	if ( (i & 0x0010) && !(i & 0x0001) ) x \|= 0x0004;
	1233	if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0002;
	1234	if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0001;
1235	1235	rom[i] ^= x;
1236	1236	}
1237	1237
1238		// for (i = 0x25900/2; i < 0x25a00/2; i++)
	1238	// for (i = 0x25900/2; i < 0x25a00/2; i++)
1239	1239
1240	1240	for (i = 0x25c00/2; i < 0x25d00/2; i++)
1241	1241	{
1242	1242	// changed from 25400
1243		// x = 0x4200;
	1243	// x = 0x4200;
1244	1244	x = 0x4000;
1245		// if ( (i & 0x0001) ) x \|= 0x0400;
1246		if ( (i & 0x0020) && !(i & 0x0001) ) x \|= 0x0080;
1247		if ( !(i & 0x0010) \|\| (i & 0x0001) ) x \|= 0x0040;
1248		if ( (i & 0x0040) && !(i & 0x0001) ) x \|= 0x0020;
1249		if ( !(i & 0x0004) \|\| (i & 0x0001) ) x \|= 0x0010;
1250		if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0004;
1251		if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0002;
1252		if ( (i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0001;
	1245	// if ( (i & 0x0001) ) x \|= 0x0400;
	1246	if ( (i & 0x0020) && !(i & 0x0001) ) x \|= 0x0080;
	1247	if ( !(i & 0x0010) \|\| (i & 0x0001) ) x \|= 0x0040;
	1248	if ( (i & 0x0040) && !(i & 0x0001) ) x \|= 0x0020;
	1249	if ( !(i & 0x0004) \|\| (i & 0x0001) ) x \|= 0x0010;
	1250	if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0004;
	1251	if ( (i & 0x0008) && !(i & 0x0001) ) x \|= 0x0002;
	1252	if ( (i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0001;
1253	1253	rom[i] ^= x;
1254	1254	}
1255	1255
1256	1256	/*
1257		for (i = 0x25d00/2; i < 0x25e00/2; i++)
1258		{
1259		x = 0x4000;
1260		if ( !(i & 0x0040) ) x \|= 0x0800;
	1257	for (i = 0x25d00/2; i < 0x25e00/2; i++)
	1258	{
	1259	x = 0x4000;
	1260	if ( !(i & 0x0040) ) x \|= 0x0800;
1261	1261
1262		if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0100; // almost!!
	1262	if ( !(i & 0x0040) && !(i & 0x0001) ) x \|= 0x0100; // almost!!
1263	1263
1264		if ( ((i & 0x0040)&&((i & 0x0020)\|\|(i & 0x0010))) \|\| !(i & 0x0001) ) x \|= 0x0200; // almost!!
1265		if ( (!(i & 0x0040) \|\| !(i & 0x0008)) && !(i & 0x0001) ) x \|= 0x0008;
1266		if ( (i & 0x0040) \|\| !(i & 0x0020) \|\| (i & 0x0001) ) x \|= 0x0001; // almost!!
1267		rom[i] ^= x;
1268		}
	1264	if ( ((i & 0x0040)&&((i & 0x0020)\|\|(i & 0x0010))) \|\| !(i & 0x0001) ) x \|= 0x0200; // almost!!
	1265	if ( (!(i & 0x0040) \|\| !(i & 0x0008)) && !(i & 0x0001) ) x \|= 0x0008;
	1266	if ( (i & 0x0040) \|\| !(i & 0x0020) \|\| (i & 0x0001) ) x \|= 0x0001; // almost!!
	1267	rom[i] ^= x;
	1268	}
1269	1269	*/
1270	1270
1271	1271	/*
1272		for (i = 0x25e00/2; i < 0x25f00/2; i++)
1273		{
1274		x = 0xa600;
	1272	for (i = 0x25e00/2; i < 0x25f00/2; i++)
	1273	{
	1274	x = 0xa600;
1275	1275
1276		if ( (i & 0x0040) && (i & 0x0001) ) x \|= 0x4000;
1277		if ( (i & 0x0040) && (i & 0x0001) ) x \|= 0x0800;
1278		if ( !(i & 0x0001) ) x \|= 0x0100;
	1276	if ( (i & 0x0040) && (i & 0x0001) ) x \|= 0x4000;
	1277	if ( (i & 0x0040) && (i & 0x0001) ) x \|= 0x0800;
	1278	if ( !(i & 0x0001) ) x \|= 0x0100;
1279	1279
1280		if ( ( (i & 0x0040) && (i & 0x0008) && !(i & 0x0001)) \|\|
1281		( !(i & 0x0040) && ((i & 0x0004) ^ (i & 0x0002)) && !(i & 0x0001) ) ) x \|= 0x0002; // almost!!
	1280	if ( ( (i & 0x0040) && (i & 0x0008) && !(i & 0x0001)) \|\|
	1281	( !(i & 0x0040) && ((i & 0x0004) ^ (i & 0x0002)) && !(i & 0x0001) ) ) x \|= 0x0002; // almost!!
1282	1282
1283		if ( !(i & 0x0040) \|\| !(i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0001;
1284		rom[i] ^= x;
1285		}
	1283	if ( !(i & 0x0040) \|\| !(i & 0x0002) \|\| (i & 0x0001) ) x \|= 0x0001;
	1284	rom[i] ^= x;
	1285	}
1286	1286	*/
1287	1287
1288	1288	for (i = 0x26f00/2; i < 0x27000/2; i++)

trunk/src/mame/drivers/cabal.c
r245142	r245143
475	475
476	476	MCFG_CPU_ADD("audiocpu", Z80, XTAL_3_579545MHz) /* verified on pcb */
477	477	MCFG_CPU_PROGRAM_MAP(sound_map)
478
	478
479	479	MCFG_MACHINE_START_OVERRIDE(cabal_state,cabal)
480	480
481	481	/* video hardware */

trunk/src/mame/drivers/capbowl.c
r245142	r245143
293	293	void capbowl_state::machine_start()
294	294	{
295	295	m_update_timer = timer_alloc(TIMER_UPDATE);
296
	296
297	297	save_item(NAME(m_blitter_addr));
298	298	save_item(NAME(m_last_trackball_val));
299	299	}

trunk/src/mame/drivers/cocoloco.c
r245142	r245143
192	192
193	193	required_device<cpu_device> m_maincpu;
194	194	required_device<palette_device> m_palette;
195
	195
196	196	UINT8 *m_videoram;
197	197	UINT8 m_videobank;
198
	198
199	199	DECLARE_READ8_MEMBER(vram_r);
200	200	DECLARE_WRITE8_MEMBER(vram_w);
201	201	DECLARE_WRITE8_MEMBER(vbank_w);
202	202	DECLARE_WRITE8_MEMBER(vram_clear_w);
203	203	DECLARE_WRITE8_MEMBER(coincounter_w);
204
	204
205	205	DECLARE_INPUT_CHANGED_MEMBER(coin_inserted);
206
	206
207	207	virtual void video_start();
208	208	DECLARE_PALETTE_INIT(cocoloco);
209
	209
210	210	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
211	211	};
212	212

trunk/src/mame/drivers/dynax.c
r245142	r245143
1564	1564	ADDRESS_MAP_GLOBAL_MASK(0xff)
1565	1565	AM_RANGE( 0x01, 0x07 ) AM_WRITE(cdracula_blitter_rev2_w) // Blitter + Destination Layers
1566	1566	AM_RANGE( 0x10, 0x10 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1567		AM_RANGE( 0x11, 0x11 ) AM_NOP // unpopulated oki
	1567	AM_RANGE( 0x11, 0x11 ) AM_NOP // unpopulated oki
1568	1568	// AM_RANGE( 0x12, 0x12 ) AM_WRITENOP // CRT Controller
1569	1569	// AM_RANGE( 0x13, 0x13 ) AM_WRITENOP // CRT Controller
1570	1570	AM_RANGE( 0x20, 0x20 ) AM_READ_PORT("P1") // P1
1571	1571	AM_RANGE( 0x21, 0x21 ) AM_READ_PORT("P2") // P2
1572	1572	AM_RANGE( 0x22, 0x22 ) AM_READ_PORT("COINS") // Coins
1573	1573	AM_RANGE( 0x30, 0x30 ) AM_WRITE(dynax_layer_enable_w) // Layers Enable
1574		// AM_RANGE( 0x31, 0x31 ) AM_WRITE(dynax_rombank_w) // BANK ROM Select
	1574	// AM_RANGE( 0x31, 0x31 ) AM_WRITE(dynax_rombank_w) // BANK ROM Select
1575	1575	AM_RANGE( 0x32, 0x32 ) AM_WRITE(dynax_blit_pen_w) // Destination Pen
1576	1576	AM_RANGE( 0x33, 0x33 ) AM_WRITE(dynax_blit_flags_w) // Flags + Do Blit
1577	1577	AM_RANGE( 0x34, 0x34 ) AM_WRITE(dynax_blit_palette01_w) // Layers Palettes (Low Bits)
r245142	r245143
2042	2042	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
2043	2043	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
2044	2044
2045		PORT_START("DSW1") // port $61 -> c217
	2045	PORT_START("DSW1") // port $61 -> c217
2046	2046	PORT_DIPNAME( 0x03, 0x02, DEF_STR( Difficulty ) ) PORT_DIPLOCATION( "SW1:1,2" )
2047	2047	PORT_DIPSETTING( 0x03, DEF_STR( Easy ) ) // 44
2048	2048	PORT_DIPSETTING( 0x02, DEF_STR( Normal ) ) // 47
r245142	r245143
2062	2062	PORT_DIPNAME( 0x40, 0x40, "Unknown 1-7" ) PORT_DIPLOCATION( "SW1:7" )
2063	2063	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
2064	2064	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2065		PORT_SERVICE( 0x80, IP_ACTIVE_LOW ) PORT_DIPLOCATION( "SW1:8" )
	2065	PORT_SERVICE( 0x80, IP_ACTIVE_LOW ) PORT_DIPLOCATION( "SW1:8" )
2066	2066
2067		PORT_START("DSW2") // port $60 -> c216
	2067	PORT_START("DSW2") // port $60 -> c216
2068	2068	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) PORT_DIPLOCATION( "SW2:1,2" )
2069	2069	PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
2070	2070	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
r245142	r245143
3190	3190	PORT_DIPSETTING( 0x00, "12:00" )
3191	3191	PORT_DIPNAME( 0x08, 0x00, "Nudity" )
3192	3192	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
3193		PORT_DIPSETTING( 0x08, DEF_STR( No ) ) // Moles On Gal's Face
	3193	PORT_DIPSETTING( 0x08, DEF_STR( No ) ) // Moles On Gal's Face
3194	3194	PORT_DIPNAME( 0x10, 0x10, "Buy Screen Bonus Points" ) /* Sets your points to 100 every time you arrive at the screen for buying special items. */
3195	3195	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
3196	3196	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r245142	r245143
3363	3363	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3364	3364	PORT_DIPNAME( 0x80, 0x00, "Nudity" )
3365	3365	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
3366		PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
	3366	PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
3367	3367
3368	3368	PORT_START("FAKE") /* IN10 - Fake DSW */
3369	3369	PORT_DIPNAME( 0xff, 0xff, "Allow Bets" )
r245142	r245143
3500	3500	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3501	3501	PORT_DIPNAME( 0x80, 0x00, "Nudity" )
3502	3502	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
3503		PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
	3503	PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
3504	3504
3505	3505	PORT_START("FAKE") /* IN10 - Fake DSW */
3506	3506	PORT_DIPNAME( 0xff, 0xff, "Allow Bets" )
r245142	r245143
4354	4354	MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax)
4355	4355	MCFG_MACHINE_RESET_OVERRIDE(dynax_state,dynax)
4356	4356
4357		// MCFG_NVRAM_ADD_0FILL("nvram") // no battery
	4357	// MCFG_NVRAM_ADD_0FILL("nvram") // no battery
4358	4358
4359	4359	/* video hardware */
4360	4360	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mame/drivers/fgoal.c
r245142	r245143
339	339	void fgoal_state::machine_start()
340	340	{
341	341	m_interrupt_timer = timer_alloc(TIMER_INTERRUPT);
342
	342
343	343	save_item(NAME(m_xpos));
344	344	save_item(NAME(m_ypos));
345	345	save_item(NAME(m_current_color));

trunk/src/mame/drivers/flyball.c
r245142	r245143
61	61	/* misc */
62	62	UINT8 m_potmask;
63	63	UINT8 m_potsense;
64
	64
65	65	emu_timer *m_pot_clear_timer;
66	66	emu_timer *m_quarter_timer;
67
	67
68	68	DECLARE_READ8_MEMBER(input_r);
69	69	DECLARE_READ8_MEMBER(scanline_r);
70	70	DECLARE_READ8_MEMBER(potsense_r);
r245142	r245143
75	75	DECLARE_WRITE8_MEMBER(pitcher_vert_w);
76	76	DECLARE_WRITE8_MEMBER(pitcher_horz_w);
77	77	DECLARE_WRITE8_MEMBER(misc_w);
78
	78
79	79	TILEMAP_MAPPER_MEMBER(get_memory_offset);
80	80	TILE_GET_INFO_MEMBER(get_tile_info);
81
	81
82	82	virtual void machine_start();
83	83	virtual void machine_reset();
84	84	virtual void video_start();
85	85	DECLARE_PALETTE_INIT(flyball);
86
	86
87	87	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
88
	88
89	89	TIMER_CALLBACK_MEMBER(joystick_callback);
90	90	TIMER_CALLBACK_MEMBER(quarter_callback);
91	91
r245142	r245143
428	428	for (int i = 0; i < len; i++)
429	429	buf[i ^ 0x1ff] = ROM[i];
430	430	memcpy(ROM, buf, len);
431
	431
432	432	m_pot_clear_timer = timer_alloc(TIMER_POT_CLEAR);
433	433	m_quarter_timer = timer_alloc(TIMER_QUARTER);
434	434

trunk/src/mame/drivers/goldstar.c
r245142	r245143
2993	2993	PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
2994	2994	PORT_DIPSETTING( 0x10, DEF_STR( 1C_4C ) )
2995	2995	PORT_DIPSETTING( 0x18, DEF_STR( 1C_5C ) )
2996		PORT_DIPSETTING( 0x20, DEF_STR( 1C_6C ) ) // manual says 1c/8c
2997		PORT_DIPSETTING( 0x28, "1 Coin/10 Credits" )
	2996	PORT_DIPSETTING( 0x20, DEF_STR( 1C_6C ) ) // manual says 1c/8c
	2997	PORT_DIPSETTING( 0x28, "1 Coin/10 Credits" )
2998	2998	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7") /* not checked */
2999	2999	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
3000	3000	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
r245142	r245143
3375	3375	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
3376	3376	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3377	3377	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3378		/* On a W-4 PCB these are used as: "Special Odds-Prohibition Of Winning...(Odds B)" - see DSW2-7
3379		PORT_DIPNAME( 0x80, 0x00, "Special Odds" ) PORT_DIPLOCATION("DSW1:7,8")
3380		PORT_DIPSETTING( 0x00, "None" )
3381		PORT_DIPSETTING( 0x40, "x300 (x1000)" )
3382		PORT_DIPSETTING( 0x80, "x500 (x5000" )
3383		PORT_DIPSETTING( 0xc0, "x1000 (x10000)
	3378	/* On a W-4 PCB these are used as: "Special Odds-Prohibition Of Winning...(Odds B)" - see DSW2-7
	3379	PORT_DIPNAME( 0x80, 0x00, "Special Odds" ) PORT_DIPLOCATION("DSW1:7,8")
	3380	PORT_DIPSETTING( 0x00, "None" )
	3381	PORT_DIPSETTING( 0x40, "x300 (x1000)" )
	3382	PORT_DIPSETTING( 0x80, "x500 (x5000" )
	3383	PORT_DIPSETTING( 0xc0, "x1000 (x10000)
3384	3384	*/
3385	3385
3386	3386	PORT_START("DSW2")
r245142	r245143
3406	3406	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8")
3407	3407	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3408	3408	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3409		/* On a W-4 PCB these are used as:
3410		PORT_DIPNAME( 0x40, 0x40, "Odds" ) PORT_DIPLOCATION("DSW2:7")
3411		PORT_DIPSETTING( 0x40, "Type A" )
3412		PORT_DIPSETTING( 0x00, "Type B" )
3413		PORT_DIPNAME( 0x80, 0x80, "Type Of W-Up Game" ) PORT_DIPLOCATION("DSW2:8")
3414		PORT_DIPSETTING( 0x80, "Slots" )
3415		PORT_DIPSETTING( 0x00, "Big/Small Card" )
	3409	/* On a W-4 PCB these are used as:
	3410	PORT_DIPNAME( 0x40, 0x40, "Odds" ) PORT_DIPLOCATION("DSW2:7")
	3411	PORT_DIPSETTING( 0x40, "Type A" )
	3412	PORT_DIPSETTING( 0x00, "Type B" )
	3413	PORT_DIPNAME( 0x80, 0x80, "Type Of W-Up Game" ) PORT_DIPLOCATION("DSW2:8")
	3414	PORT_DIPSETTING( 0x80, "Slots" )
	3415	PORT_DIPSETTING( 0x00, "Big/Small Card" )
3416	3416	*/
3417	3417
3418	3418	/* On a W-4 PCB DSW3 & DSW4 are reversed and all dips on DSW4 are set to off! */
r245142	r245143
3672	3672	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Key Out / Attendant")
3673	3673	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
3674	3674	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings")
3675		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats") // doesn't work in v352c4
	3675	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats") // doesn't work in v352c4
3676	3676
3677	3677	PORT_START("DSW1")
3678	3678	PORT_DIPNAME( 0x07, 0x03, "Game Level (Difficulty)" ) PORT_DIPLOCATION("DSW1:1,2,3") /* OK */
r245142	r245143
4335	4335	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
4336	4336	PORT_DIPSETTING( 0x10, DEF_STR( On ) )
4337	4337	PORT_DIPNAME( 0x20, 0x00, "Unused - leave off" ) PORT_DIPLOCATION("DSW5:6")
4338		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	4338	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
4339	4339	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
4340	4340	PORT_DIPNAME( 0x40, 0x00, "Reset Remaining Score To Zero" ) PORT_DIPLOCATION("DSW5:7")
4341		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
4342		PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
	4341	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	4342	PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
4343	4343	PORT_DIPNAME( 0x80, 0x00, "Count Game To Issue Ticket" ) PORT_DIPLOCATION("DSW5:8")
4344		PORT_DIPSETTING( 0x00, DEF_STR( No ) )
4345		PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
	4344	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	4345	PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
4346	4346	INPUT_PORTS_END
4347	4347
4348	4348
r245142	r245143
4472	4472	PORT_DIPNAME( 0x10, 0x10, "Auto Ticket Dispense" ) PORT_DIPLOCATION("DSW4:5") /* not checked */
4473	4473	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
4474	4474	PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
4475		PORT_DIPNAME( 0xe0, 0xe0, "Ticket Dispense Mode" ) PORT_DIPLOCATION("DSW4:6,7,8")
	4475	PORT_DIPNAME( 0xe0, 0xe0, "Ticket Dispense Mode" ) PORT_DIPLOCATION("DSW4:6,7,8")
4476	4476	PORT_DIPSETTING( 0xe0, "Continuous" )
4477	4477	PORT_DIPSETTING( 0xc0, "Max 1 Ticket Per Game" )
4478	4478	PORT_DIPSETTING( 0xa0, "Max 2 Ticket Per Game" )

trunk/src/mame/drivers/hng64.c
r245142	r245143
918	918
919	919	WRITE32_MEMBER(hng64_state::hng64_vregs_w)
920	920	{
921		// printf("hng64_vregs_w %02x, %08x %08x\n", offset * 4, data, mem_mask);
	921	// printf("hng64_vregs_w %02x, %08x %08x\n", offset * 4, data, mem_mask);
922	922	COMBINE_DATA(&m_videoregs[offset]);
923	923	}
924	924
r245142	r245143
1503	1503	{
1504	1504	m_videoregs[i] = 0xdeadbeef;
1505	1505	}
1506
	1506
1507	1507	}
1508	1508
1509	1509
r245142	r245143
1569	1569	ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS */ \
1570	1570	ROM_LOAD ( "from1.bin", 0x000000, 0x080000, CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) ) \
1571	1571	ROM_REGION( 0x0100000, "fpga", 0 ) /* FPGA data */ \
1572		ROM_LOAD ( "rom1.bin", 0x000000, 0x01ff32, CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) ) \
	1572	ROM_LOAD ( "rom1.bin", 0x000000, 0x01ff32, CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
1573	1573
1574
1575	1574	ROM_START( hng64 )
1576	1575	/* BIOS */
1577	1576	HNG64_BIOS

trunk/src/mame/drivers/hotblock.c
r245142	r245143
57	57	/* devices */
58	58	required_device<cpu_device> m_maincpu;
59	59	required_device<palette_device> m_palette;
60
	60
61	61	/* memory pointers */
62	62	required_shared_ptr<UINT8> m_vram;
63	63
r245142	r245143
67	67
68	68	/* memory */
69	69	UINT8 m_pal[0x10000];
70
	70
71	71	DECLARE_READ8_MEMBER(video_read);
72	72	DECLARE_READ8_MEMBER(port4_r);
73	73	DECLARE_WRITE8_MEMBER(port4_w);
74	74	DECLARE_WRITE8_MEMBER(port0_w);
75	75	DECLARE_WRITE8_MEMBER(video_write);
76
	76
77	77	virtual void video_start();
78
	78
79	79	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
80	80	};
81	81

trunk/src/mame/drivers/iteagle.c
r245142	r245143
105	105	public:
106	106	iteagle_state(const machine_config &mconfig, device_type type, const char *tag)
107	107	: driver_device(mconfig, type, tag),
108		m_maincpu(*this, "maincpu")
	108	m_maincpu(*this, "maincpu")
109	109	{}
110
	110
111	111	required_device<mips3_device> m_maincpu;
112	112
113	113	virtual void machine_start();
r245142	r245143
129	129	MCFG_CPU_ADD("maincpu", VR4310LE, 166666666)
130	130	MCFG_MIPS3_ICACHE_SIZE(16384)
131	131	MCFG_MIPS3_DCACHE_SIZE(16384)
132
	132
133	133	MCFG_PCI_ROOT_ADD( ":pci")
134	134	MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu")
135	135	MCFG_ITEAGLE_FPGA_ADD( ":pci:06.0")
r245142	r245143
144	144	MCFG_SCREEN_SIZE(640, 350)
145	145	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 349)
146	146	MCFG_SCREEN_UPDATE_DEVICE(":pci:09.0", voodoo_pci_device, screen_update)
147
148	147
	148
149	149	MACHINE_CONFIG_END
150	150
151	151
r245142	r245143
167	167	PORT_DIPNAME( 0x0F00, 0x0000, "GAME" )
168	168	PORT_DIPNAME( 0x00F0, 0x0000, "MAJOR" )
169	169	PORT_DIPNAME( 0x000F, 0x0000, "MINOR" )
170
	170
171	171	INPUT_PORTS_END
172	172
173	173	static INPUT_PORTS_START( gtfore05 )
r245142	r245143
263	263	DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
264	264	DISK_IMAGE( "golf_fore_2002_v2.01.04_umv", 0, SHA1(e902b91bd739daee0b95b10e5cf33700dd63a76b) ) /* Labeled Golf Fore! V2.01.04 UMV */
265	265	//DISK_REGION( "ide:1:cdrom" ) // program CD-ROM
266
	266
267	267	ROM_END
268	268
269	269	ROM_START( gtfore02o )

trunk/src/mame/drivers/jankenmn.c
r245142	r245143
153	153	m_maincpu(*this, "maincpu") { }
154	154
155	155	required_device<cpu_device> m_maincpu;
156
	156
157	157	DECLARE_WRITE8_MEMBER(lamps1_w);
158	158	DECLARE_WRITE8_MEMBER(lamps2_w);
159	159	DECLARE_WRITE8_MEMBER(lamps3_w);
160
	160
161	161	DECLARE_CUSTOM_INPUT_MEMBER(hopper_status_r);
162	162	};
163	163

trunk/src/mame/drivers/jchan.c
r245142	r245143
228	228
229	229	DECLARE_DRIVER_INIT(jchan);
230	230	virtual void video_start();
231
	231
232	232	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
233
	233
234	234	TIMER_DEVICE_CALLBACK_MEMBER(vblank);
235	235	};
236	236
r245142	r245143
290	290
291	291	m_spritegen1->skns_sprite_kludge(0,0);
292	292	m_spritegen2->skns_sprite_kludge(0,0);
293
	293
294	294	save_item(NAME(m_irq_sub_enable));
295	295	save_pointer(NAME(m_sprite_ram32_1), 0x4000/4);
296	296	save_pointer(NAME(m_sprite_ram32_2), 0x4000/4);

trunk/src/mame/drivers/junofrst.c
r245142	r245143
105	105	required_device<filter_rc_device> m_filter_0_0;
106	106	required_device<filter_rc_device> m_filter_0_1;
107	107	required_device<filter_rc_device> m_filter_0_2;
108
	108
109	109	UINT8 m_blitterdata[4];
110	110	int m_i8039_status;
111	111	int m_last_irq;
112
	112
113	113	DECLARE_WRITE8_MEMBER(blitter_w);
114	114	DECLARE_WRITE8_MEMBER(bankselect_w);
115	115	DECLARE_WRITE8_MEMBER(sh_irqtrigger_w);

trunk/src/mame/drivers/m72.c
r245142	r245143
1785	1785	MCFG_CPU_ADD("soundcpu",Z80, SOUND_CLOCK)
1786	1786	MCFG_CPU_PROGRAM_MAP(sound_ram_map)
1787	1787	MCFG_CPU_IO_MAP(sound_portmap)
1788
1789	1788
	1789
1790	1790	/* video hardware */
1791	1791	MCFG_GFXDECODE_ADD("gfxdecode", "palette", m72)
1792	1792	MCFG_PALETTE_ADD("palette", 512)
r245142	r245143
1834	1834	MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 12855) / clocked by V1? (Vigilante) */
1835	1835	/* IRQs are generated by main Z80 and YM2151 */
1836	1836
1837
	1837
1838	1838	MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
1839	1839	MACHINE_CONFIG_END
1840	1840
r245142	r245143
1852	1852
1853	1853
1854	1854	static MACHINE_CONFIG_DERIVED( dkgenm72, m72 ) // dervices from 'm72' because we use 'fake nmi' on the soundcpu
1855
	1855
1856	1856	MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
1857	1857	MACHINE_CONFIG_END
1858	1858
r245142	r245143
1871	1871	MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 12855) / clocked by V1? (Vigilante) */
1872	1872	/* IRQs are generated by main Z80 and YM2151 */
1873	1873
1874
	1874
1875	1875	MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
1876	1876
1877	1877	MCFG_VIDEO_START_OVERRIDE(m72_state,xmultipl)
r245142	r245143
1948	1948	MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 12855) / clocked by V1? (Vigilante) */
1949	1949	/* IRQs are generated by main Z80 and YM2151 */
1950	1950
1951
	1951
1952	1952	MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
1953	1953
1954	1954	/* video hardware */
r245142	r245143
1979	1979	MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 12855) / clocked by V1? (Vigilante) */
1980	1980	/* IRQs are generated by main Z80 and YM2151 */
1981	1981
1982
	1982
1983	1983	MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
1984	1984
1985	1985	/* video hardware */
r245142	r245143
2011	2011	MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 12855) / clocked by V1? (Vigilante) */
2012	2012	/* IRQs are generated by main Z80 and YM2151 */
2013	2013
2014
	2014
2015	2015	MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
2016	2016
2017	2017	/* video hardware */

trunk/src/mame/drivers/madalien.c
r245142	r245143
437	437	ROM_LOAD( "mc-1.3k", 0x0000, 0x0400, BAD_DUMP CRC(2710c47e) SHA1(337e4f160c7db143ec3bfae3e08e8789b9e41cc5) ) // taken from chwy, see below, tile 2 is mismatched with the 2 roms from the actual PCB.
438	438	ROM_LOAD( "me-1.3l", 0x0400, 0x0400, CRC(7328a425) SHA1(327adc8b0e25d93f1ae98a44c26d0aaaac1b1a9c) )
439	439	ROM_LOAD( "md-1.3m", 0x0800, 0x0400, CRC(b5329929) SHA1(86890e1b7cc8cb31fc0dcbc2d3cff02e4cf95619) )
440
	440
441	441	/* for reference, this is the data used by Highway Chase on the cassette system when extracted
442	442	ROM_REGION( 0x0400, "user1", 0 ) // background tile map
443	443	ROM_LOAD( "rom1", 0x0000, 0x0400, CRC(9b04c446) SHA1(918013f3c0244ab6a670b9d1b6b642298e2c5ab8) )

trunk/src/mame/drivers/mgolf.c
r245142	r245143
47	47	DECLARE_READ8_MEMBER(dial_r);
48	48	DECLARE_READ8_MEMBER(misc_r);
49	49	DECLARE_WRITE8_MEMBER(wram_w);
50
	50
51	51	TILE_GET_INFO_MEMBER(get_tile_info);
52
	52
53	53	virtual void machine_start();
54	54	virtual void machine_reset();
55	55	virtual void video_start();
56	56	DECLARE_PALETTE_INIT(mgolf);
57
	57
58	58	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
59
	59
60	60	TIMER_CALLBACK_MEMBER(interrupt_callback);
61
	61
62	62	void update_plunger( );
63	63	double calc_plunger_pos();
64	64
r245142	r245143
343	343	void mgolf_state::machine_start()
344	344	{
345	345	m_interrupt_timer = timer_alloc(TIMER_INTERRUPT);
346
	346
347	347	save_item(NAME(m_prev));
348	348	save_item(NAME(m_mask));
349	349	save_item(NAME(m_time_pushed));

trunk/src/mame/drivers/neogeo.c
r245142	r245143
238	238	. NEO-AEG CHA42G-3
239	239	. NEO-AEG CHA42G-4
240	240	. NEO-AEG CHA256
241		. NEO-AEG CHA256 B
	241	. NEO-AEG CHA256 B
242	242	. NEO-AEG CHA256[B]
243		. NEO-AEG CHA256BY
	243	. NEO-AEG CHA256BY
244	244	. NEO-AEG CHA256RY
245	245	. NEO-AEG CHA512Y
246	246	. NEO-AEG CHAFIO (1999.8.10) - used with NEO-CMC 90G06C7042 or NEO-CMC 90G06C7050
r245142	r245143
263	263	. NEO-AEG PROG4096 B
264	264	. NEO-AEG PROGGS
265	265	. NEO-AEG PROGTOP2
266		. NEO-AEG PROGTOP2Y
	266	. NEO-AEG PROGTOP2Y
267	267	. NEO-AEG PROGEOP (1999.4.2)
268	268	. NEO-AEG PROGLBA (1999.7.6)
269	269	. NEO-AEG PROGRK
r245142	r245143
310	310	GIGA PROG Board 1.0
311	311	GIGA PROG Board 1.5
312	312
313
314		Unofficial pcb's from NEOBITZ:
315
316		MVS CHA:
317		CHARBITZ1 2013.12.01
318
319		MVS PROG:
320		PROGBITZ1 2013.12.01
321
322
	313
	314	Unofficial pcb's from NEOBITZ:
	315
	316	MVS CHA:
	317	CHARBITZ1 2013.12.01
	318
	319	MVS PROG:
	320	PROGBITZ1 2013.12.01
	321
	322
323	323	Neo-Geo game PCB infos by Johnboy
324	324
325	325

trunk/src/mame/drivers/neogeo_noslot.c
r245142	r245143
1237	1237	ID-0023
1238	1238	. NGM-023
1239	1239	NEO-MVS PROG42G / NEO-MVS CHA42G
1240		NEO-MVS PROGTOP / NEO-MVS CHA-256
	1240	NEO-MVS PROGTOP / NEO-MVS CHA-256
1241	1241	Boards used for the Korean release
1242	1242	. NGH-023
1243	1243	NEO-AEG PROG42G-1 / NEO-AEG CHA42G-1
r245142	r245143
1915	1915	ROM_REGION( 0x100000, "maincpu", 0 )
1916	1916	ROM_LOAD16_WORD_SWAP( "044-p1.p1", 0x000000, 0x080000, CRC(ca9f7a6d) SHA1(4d28ef86696f7e832510a66d3e8eb6c93b5b91a1) ) /* TC534200 */
1917	1917	/* also found sets with ep1 or p1 on eprom. */
1918
	1918
1919	1919	NEO_SFIX_128K( "044-s1.s1", CRC(89903f39) SHA1(a04a0c244a5d5c7a595fcf649107969635a6a8b6) ) /* TC531000 */
1920	1920
1921	1921	NEO_BIOS_AUDIO_128K( "044-m1.m1", CRC(0987e4bb) SHA1(8fae4b7fac09d46d4727928e609ed9d3711dbded) ) /* TC531001 */
r245142	r245143
1950	1950	ROM_LOAD16_WORD_SWAP( "045-p1.p1", 0x000000, 0x100000, CRC(dfe51bf0) SHA1(2243af3770a516ae698b69bcd9daf53632d9128d) ) /* TC538200 */
1951	1951	ROM_LOAD16_WORD_SWAP( "045-pg2.sp2", 0x100000, 0x100000, CRC(46745b94) SHA1(d9e959fd1f88c9402915c1d0dcdb4a9e3d49cdcb) ) /* TC538200 */
1952	1952	/* also found set with ep1 / ep2 on eprom and sp2 on maskrom; same rom data as samshoh is used. */
1953
	1953
1954	1954	NEO_SFIX_128K( "045-s1.s1", CRC(9142a4d3) SHA1(54088e99fcfd75fd0f94852890a56350066a05a3) ) /* TC531000 */
1955	1955
1956	1956	NEO_BIOS_AUDIO_128K( "045-m1.m1", CRC(95170640) SHA1(125c502db0693e8d11cef619b090081c14a9a300) ) /* TC531001 */
r245142	r245143
2271	2271	ROM_REGION( 0x100000, "maincpu", 0 )
2272	2272	ROM_LOAD16_WORD_SWAP( "053-p1.p1", 0x000000, 0x080000, CRC(95b574cb) SHA1(b7b7af6a04c3d902e7f8852897741ecaf0b1062c) ) /* TC534200 */
2273	2273	ROM_LOAD16_WORD_SWAP( "053-p2.p2", 0x080000, 0x080000, CRC(f198ed45) SHA1(24ccc091e97f63796562bb5b30df51f39bd504ef) ) /* TC534200 */
2274
	2274
2275	2275	NEO_SFIX_128K( "053-s1.s1", CRC(8c2c2d6b) SHA1(87fa79611c6f8886dcc8766814829c669c65b40f) ) /* TC531000 */
2276	2276
2277	2277	NEO_BIOS_AUDIO_128K( "053-m1.m1", CRC(1bd9d04b) SHA1(65cd7b002123ed1a3111e3d942608d0082799ff3) ) /* TC531001 */
r245142	r245143
2615	2615	ROM_REGION( 0x100000, "maincpu", 0 )
2616	2616	ROM_LOAD16_WORD_SWAP( "061-p1.p1", 0x000000, 0x100000, CRC(5969e0dc) SHA1(78abea880c125ec5a85bef6404478512a34b5513) ) /* mask rom TC538200 */
2617	2617	/* also found MVS sets with ep1 / ep2 on eprom; correct chip label unknown. */
2618
	2618
2619	2619	NEO_SFIX_128K( "061-s1.s1", CRC(226d1b68) SHA1(de010f6fda3ddadb181fe37daa6105f22e78b970) ) /* mask rom TC531000 */
2620	2620
2621	2621	NEO_BIOS_AUDIO_128K( "061-m1.m1", CRC(156f6951) SHA1(49686f615f109a02b4f23931f1c84fee13872ffd) ) /* mask rom TC531001 */
r245142	r245143
2679	2679	ROM_LOAD16_WORD_SWAP( "063-p1.p1", 0x100000, 0x100000, CRC(22368892) SHA1(0997f8284aa0f57a333be8a0fdea777d0d01afd6) ) /* TC5316200 */
2680	2680	ROM_CONTINUE( 0x000000, 0x100000 )
2681	2681	/* also found MVS sets with ep1 / ep2 on eprom and p1 / sp2 on maskrom; correct chip label unknown */
2682
	2682
2683	2683	NEO_SFIX_128K( "063-s1.s1", CRC(64a5cd66) SHA1(12cdfb27bf9ccd5a8df6ddd4628ef7cf2c6d4964) ) /* TC531000 */
2684	2684
2685	2685	NEO_BIOS_AUDIO_128K( "063-m1.m1", CRC(56675098) SHA1(90429fc40d056d480d0e2bbefbc691d9fa260fc4) ) /* TC531001 */
r245142	r245143
2965	2965	BANK 3 NOT USED
2966	2966	****************************************/
2967	2967
2968		ROM_START( b2b )
	2968	ROM_START( b2b )
2969	2969	ROM_REGION( 0x100000, "maincpu", 0 )
2970	2970	ROM_LOAD16_WORD_SWAP( "071.p1", 0x000000, 0x080000, CRC(7687197d) SHA1(4bb9cb7819807f7a7e1f85f1c4faac4a2f8761e8) )
2971	2971
r245142	r245143
4252	4252	ROM_LOAD16_WORD_SWAP( "214-p1.p1", 0x000000, 0x100000, CRC(52755d74) SHA1(4232d627f1d2e6ea9fc8cf01571d77d4d5b8a1bb) ) /* TC538200 */
4253	4253	ROM_LOAD16_WORD_SWAP( "214-p2.sp2", 0x100000, 0x200000, CRC(002ccb73) SHA1(3ae8df682c75027ca82db25491021eeba00a267e) ) /* TC5316200 */
4254	4254	/* also found sets with ep1 / ep2 / ep3 / ep4 on eprom and 214-P5 on TC5316200; correct chip labels for eproms is unknown */
4255
	4255
4256	4256	NEO_SFIX_128K( "214-s1.s1", CRC(1254cbdb) SHA1(fce5cf42588298711a3633e9c9c1d4dcb723ac76) ) /* TC531000 */
4257	4257
4258	4258	NEO_BIOS_AUDIO_128K( "214-m1.m1", CRC(dabc427c) SHA1(b76722ed142ee7addceb4757424870dbd003e8b3) ) /* TC531001 */
r245142	r245143
5013	5013	ROM_REGION( 0x500000, "maincpu", 0 )
5014	5014	ROM_LOAD16_WORD_SWAP( "234-p1.p1", 0x000000, 0x100000, CRC(e123a5a3) SHA1(a3ddabc00feeb54272b145246612ad4632b0e413) ) /* TC538200 */
5015	5015	ROM_LOAD16_WORD_SWAP( "234-p2.sp2", 0x100000, 0x400000, CRC(0fdc289e) SHA1(1ff31c0b0f4f9ddbedaf4bcf927faaae81892ec7) ) /* TC5332205 */
5016		/* also found sets with p1 / sp2 / ep1 / ep2 / m1 on eprom with sticker */
	5016	/* also found sets with p1 / sp2 / ep1 / ep2 / m1 on eprom with sticker */
5017	5017	/* chip label is 0234-P1, 0234-SP2, 0234-EP1, 0234-EP2 and 0234-M1 */
5018
	5018
5019	5019	NEO_SFIX_128K( "234-s1.s1", CRC(95561412) SHA1(995de272f572fd08d909d3d0af4251b9957b3640) ) /* TC531000 */
5020	5020
5021	5021	NEO_BIOS_AUDIO_128K( "234-m1.m1", CRC(087628ea) SHA1(48dcf739bb16699af4ab8ed632b7dcb25e470e06) ) /* TC531001 */
r245142	r245143
6193	6193	/* The SMA for this release has a green colour marking; the older revision has a white colour marking */
6194	6194	ROM_LOAD16_WORD_SWAP( "256-pg1.p1", 0x100000, 0x400000, CRC(b07edfd5) SHA1(dcbd9e500bfae98d754e55cdbbbbf9401013f8ee) ) /* TC5332202 */
6195	6195	ROM_LOAD16_WORD_SWAP( "256-pg2.p2", 0x500000, 0x400000, CRC(6097c26b) SHA1(248ec29d21216f29dc6f5f3f0e1ad1601b3501b6) ) /* TC5332202 */
6196
	6196
6197	6197	ROM_Y_ZOOM
6198	6198
6199	6199	/* The Encrypted Boards do not have an s1 rom, data for it comes from the Cx ROMs */
r245142	r245143
6230	6230	ROM_LOAD16_WORD_SWAP( "256-ph2.sp2", 0x100000, 0x400000, CRC(1f3d8ce8) SHA1(08b05a8abfb86ec09a5e758d6273acf1489961f9) )
6231	6231	/* also found AES set with p1 / p2 on maskrom on NEO-AEG PROGLBA (NEO-SMA); chip labels is 256-PG1 and 256-PG2 */
6232	6232	/* The SMA for this release has a pink color marking */
6233
	6233
6234	6234	ROM_Y_ZOOM
6235	6235
6236	6236	/* The Encrypted Boards do not have an s1 rom, data for it comes from the Cx ROMs */
r245142	r245143
6748	6748	ROM_REGION( 0x100000, "maincpu", 0 )
6749	6749	ROM_LOAD16_WORD_SWAP( "267-p1.p1", 0x000000, 0x100000, CRC(112fe2c0) SHA1(01420e051f0bdbd4f68ce306a3738161b96f8ba8) ) /* mask rom TC538200 */
6750	6750	/* also found set with p1 and m1 on eprom with sticker; chip labels is PN 2.02 and M1 */
6751
	6751
6752	6752	ROM_Y_ZOOM
6753	6753
6754	6754	/* The Encrypted Boards do not have an s1 rom, data for it comes from the Cx ROMs */
r245142	r245143
6820	6820	ROM_LOAD32_WORD_SWAP( "268-p1c.p1", 0x000000, 0x400000, CRC(3636690a) SHA1(e0da714b4bdc6efffe1250ded02ebddb3ab6d7b3) )
6821	6821	ROM_LOAD32_WORD_SWAP( "268-p2c.p2", 0x000002, 0x400000, CRC(8dfc47a2) SHA1(27d618cfbd0107a4d2a836797e967b39d2eb4851) )
6822	6822	/* also found AES set with p1 / p2 on maskrom; chip labels is 268-P1CR2 and 268-P2CR2 */
6823
	6823
6824	6824	ROM_Y_ZOOM
6825	6825
6826	6826	/* The Encrypted Boards do not have an s1 rom, data for it comes from the Cx ROMs */

trunk/src/mame/drivers/paradise.c
r245142	r245143
660	660	void paradise_state::machine_start()
661	661	{
662	662	int bank_n = memregion("maincpu")->bytes() / 0x4000;
663
	663
664	664	membank("prgbank")->configure_entries(0, bank_n, memregion("maincpu")->base(), 0x4000);
665	665
666	666	save_item(NAME(m_palbank));

trunk/src/mame/drivers/peplus.c
r245142	r245143
5930	5930	Programs Available: PP0055, X000055P, PP0723
5931	5931	*/
5932	5932	ROM_REGION( 0x10000, "maincpu", 0 )
5933		ROM_LOAD( "xp000098.u67", 0x00000, 0x10000, CRC(12257ad8) SHA1(8f613377519850f8f711ccb827685dece018c735) )
	5933	ROM_LOAD( "xp000098.u67", 0x00000, 0x10000, CRC(12257ad8) SHA1(8f613377519850f8f711ccb827685dece018c735) ) /* 01/29/98 @ IGT L98-0643 */
5934	5934
5935	5935	ROM_REGION( 0x10000, "user1", 0 )
5936	5936	ROM_LOAD( "x000055p.u66", 0x00000, 0x10000, CRC(e06819df) SHA1(36590c4588b8036908e63714fbb3e77d23e60eae) ) /* Deuces Wild Poker */
r245142	r245143
8020	8020	PayTable Js+ 2PR STR FL FH 4K SF 4K 4K 4A 4K 4K 4A RF (Bonus)
8021	8021	-----------------------------------------------------------------------------
8022	8022	P870BB 1 1 3 4 7 9 50 25 80 160 160 400 400 400 800
8023		% Range: 95.4-97.4% Optimum: 99.4% Hit Frequency: ~~???~~%
	8023	% Range: 95.4-97.4% Optimum: 99.4% Hit Frequency: 43.2%
8024	8024	Programs Available: X002272P
8025	8025	*/
8026	8026	ROM_REGION( 0x10000, "maincpu", 0 )
r245142	r245143
8047	8047	PayTable Js+ 2PR STR FL FH 4K SF 4K 4K 4A 4K 4K 4A RF (Bonus)
8048	8048	-----------------------------------------------------------------------------
8049	8049	P873BB 1 1 3 4 5 8 50 25 80 160 160 400 400 400 800
8050		% Range: 92.0-94.0% Optimum: 96.0% Hit Frequency: ~~???~~%
	8050	% Range: 92.0-94.0% Optimum: 96.0% Hit Frequency: 44.8%
8051	8051	Programs Available: X002275P
8052	8052	*/
8053	8053	ROM_REGION( 0x10000, "maincpu", 0 )
r245142	r245143
8074	8074	PayTable Js+ 2PR STR FL FH 4K SF 4K 4K 4A 4K 4K 4A RF (Bonus)
8075	8075	-----------------------------------------------------------------------------
8076	8076	P874BB 1 1 3 4 5 7 50 25 80 160 160 400 400 400 800
8077		% Range: 91.0-93.0% Optimum: 95.0% Hit Frequency: ~~???~~%
	8077	% Range: 91.0-93.0% Optimum: 95.0% Hit Frequency: 44.9%
8078	8078	Programs Available: X002276P
8079	8079	*/
8080	8080	ROM_REGION( 0x10000, "maincpu", 0 )
r245142	r245143
9075	9075	Double Deuce Poker P236A 99.60%
9076	9076	*/
9077	9077	ROM_REGION( 0x10000, "maincpu", 0 )
9078		ROM_LOAD( "xmp00002.u67", 0x00000, 0x10000, CRC(d5624ac8) SHA1(6b778b0e7ddb81123c6038920b3447e05a0556b2) ) /* Linkable Progressive */
	9078	ROM_LOAD( "xmp00002.u67", 0x00000, 0x10000, CRC(d5624ac8) SHA1(6b778b0e7ddb81123c6038920b3447e05a0556b2) ) /* 09/07/95 @ IGT L95-2183 - Linkable Progressive */
9079	9079
9080	9080	ROM_REGION( 0x10000, "user1", 0 )
9081	9081	ROM_LOAD( "xm00004p.u66", 0x00000, 0x10000, CRC(bafd160f) SHA1(7454fbf992d4d0668ef375b76ce2cae3324a5f75) )
r245142	r245143
9104	9104	*/
9105	9105	ROM_REGION( 0x10000, "maincpu", 0 )
9106	9106	ROM_LOAD( "xmp00004.u67", 0x00000, 0x10000, CRC(83184999) SHA1(b8483917b338be4fd3641b3990eea37072d36885) ) /* Linkable Progressive */
9107		/* Also known to be found with XMP00024 programs */
	9107	/* Also known to be found with XMP00024 program */
9108	9108
9109	9109	ROM_REGION( 0x10000, "user1", 0 )
9110	9110	ROM_LOAD( "xm00005p.u66", 0x00000, 0x10000, CRC(c832eac7) SHA1(747d57de602b44ae1276fe1009db1b6de0d2c64c) )
r245142	r245143
9162	9162	*/
9163	9163	ROM_REGION( 0x10000, "maincpu", 0 )
9164	9164	ROM_LOAD( "xmp00006.u67", 0x00000, 0x10000, CRC(d61f1677) SHA1(2eca1315d6aa310a54de2dfa369e443a07495b76) ) /* 07/25/96 @ IGT L96-2041 - Linkable Progressive */
	9165	/* Also known to be found with XMP00002 program */
9165	9166
9166	9167	ROM_REGION( 0x10000, "user1", 0 )
9167		ROM_LOAD( "xm00007p.u66", 0x00000, 0x10000, CRC(85a76416) SHA1(1bc3b9c2f687e68a085bfc5cf86d99fbd18cb9c7) )
	9168	ROM_LOAD( "xm00007p.u66", 0x00000, 0x10000, CRC(85a76416) SHA1(1bc3b9c2f687e68a085bfc5cf86d99fbd18cb9c7) ) /* 03/09/96 @ IGT L96-0737 */
9168	9169
9169	9170	ROM_REGION( 0x020000, "gfx1", 0 )
9170		ROM_LOAD( "mro-cg2233.u77", 0x00000, 0x8000, CRC(8758866a) SHA1(49146560a7e79593a2ac0378dc3b300b96ef1015) )
	9171	ROM_LOAD( "mro-cg2233.u77", 0x00000, 0x8000, CRC(8758866a) SHA1(49146560a7e79593a2ac0378dc3b300b96ef1015) ) /* 03/07/96 @ IGT L96-0686 */
9171	9172	ROM_LOAD( "mgo-cg2233.u78", 0x08000, 0x8000, CRC(45ac6cfd) SHA1(25ff276320fe51c56aea0cff099be17e4ce8f404) )
9172	9173	ROM_LOAD( "mbo-cg2233.u79", 0x10000, 0x8000, CRC(9e9d702f) SHA1(75bb9adb49095b7cb87d2615bcf725e4a4774e25) )
9173	9174	ROM_LOAD( "mxo-cg2233.u80", 0x18000, 0x8000, CRC(2f05ebcb) SHA1(90d00ee4ce2dcbfbe33e221efe4db45a4e484baa) )
r245142	r245143
9221	9222	Double Aces & Faces ????? 99.30%
9222	9223	*/
9223	9224	ROM_REGION( 0x10000, "maincpu", 0 )
9224		ROM_LOAD( "xmp00002.u67", 0x00000, 0x10000, CRC(d5624ac8) SHA1(6b778b0e7ddb81123c6038920b3447e05a0556b2) ) /* Linkable Progressive */
	9225	ROM_LOAD( "xmp00002.u67", 0x00000, 0x10000, CRC(d5624ac8) SHA1(6b778b0e7ddb81123c6038920b3447e05a0556b2) ) /* 09/07/95 @ IGT L95-2183 - Linkable Progressive */
9225	9226
9226	9227	ROM_REGION( 0x10000, "user1", 0 )
9227	9228	ROM_LOAD( "xm00009p.u66", 0x00000, 0x10000, CRC(e133d0bb) SHA1(7ed4fa335e230c28e6fc66f0c990bc7ead2b279d) )
r245142	r245143
9255	9256	ROM_REGION( 0x10000, "maincpu", 0 )
9256	9257	ROM_LOAD( "xmp00025.u67", 0x00000, 0x10000, CRC(5d39ff71) SHA1(0a5f67e61ae0e8a08cc551ab4271ffc97c343ae3) ) /* International multi currency version - Auto Hold always on */
9257	9258	/* Also compatible with XMP00002, XMP00003, XMP00004, XMP00006 and XMP00024 programs */
9258
	9259
9259	9260	ROM_REGION( 0x10000, "user1", 0 )
9260	9261	ROM_LOAD( "xm00013p.u66", 0x00000, 0x10000, CRC(4fde73f9) SHA1(f8eb6fb0585e8df9a7eb2ddc65bb20b120753d7a) )
9261	9262
r245142	r245143
9341	9342
9342	9343	*/
9343	9344	ROM_REGION( 0x10000, "maincpu", 0 )
9344		ROM_LOAD( "xmp00017.u67", 0x00000, 0x10000, CRC(129e6eaa) SHA1(1dd2b83a672a618f338b553a6cbd598b6d4ce672) )
	9345	ROM_LOAD( "xmp00017.u67", 0x00000, 0x10000, CRC(129e6eaa) SHA1(1dd2b83a672a618f338b553a6cbd598b6d4ce672) ) /* 09/17/97 @ IGT L97-2154 */
9345	9346
9346	9347	ROM_REGION( 0x10000, "user1", 0 )
9347	9348	ROM_LOAD( "x000055p.u66", 0x00000, 0x10000, CRC(e06819df) SHA1(36590c4588b8036908e63714fbb3e77d23e60eae) ) /* Deuces Wild Poker */
r245142	r245143
9375	9376
9376	9377	*/
9377	9378	ROM_REGION( 0x10000, "maincpu", 0 )
9378		ROM_LOAD( "xmp00017.u67", 0x00000, 0x10000, CRC(129e6eaa) SHA1(1dd2b83a672a618f338b553a6cbd598b6d4ce672) )
	9379	ROM_LOAD( "xmp00017.u67", 0x00000, 0x10000, CRC(129e6eaa) SHA1(1dd2b83a672a618f338b553a6cbd598b6d4ce672) ) /* 09/17/97 @ IGT L97-2154 */
9379	9380
9380	9381	ROM_REGION( 0x10000, "user1", 0 )
9381	9382	ROM_LOAD( "x000430p.u66", 0x00000, 0x10000, CRC(905571e3) SHA1(fd506516fed22842df8e9dbb3683dcb4c459719b) ) /* Dueces Joker Wild Poker */
r245142	r245143
9412	9413
9413	9414	*/
9414	9415	ROM_REGION( 0x10000, "maincpu", 0 )
9415		ROM_LOAD( "xmp00017.u67", 0x00000, 0x10000, CRC(129e6eaa) SHA1(1dd2b83a672a618f338b553a6cbd598b6d4ce672) )
	9416	ROM_LOAD( "xmp00017.u67", 0x00000, 0x10000, CRC(129e6eaa) SHA1(1dd2b83a672a618f338b553a6cbd598b6d4ce672) ) /* 09/17/97 @ IGT L97-2154 */
9416	9417
9417	9418	ROM_REGION( 0x10000, "user1", 0 )
9418	9419	ROM_LOAD( "x002272p.u66", 0x00000, 0x10000, CRC(ee4f27b9) SHA1(1ee105430358ea27badd943bb6b18663e4029388) ) /* Black Jack Bonus Poker */
r245142	r245143
9430	9431	ROM_LOAD( "x002307p.u66", 0x00000, 0x10000, CRC(c6d5db70) SHA1(017e1e382fb789e4cd8b410362ad5e82b61f61db) ) /* Triple Double Bonus Poker */
9431	9432
9432	9433	ROM_REGION( 0x040000, "gfx1", 0 )
9433		ROM_LOAD( "mro-cg2426.u77", 0x00000, 0x10000, CRC(e7622901) SHA1(f653aaf02de840aef56d3efd7680572356e94da7) )
	9434	ROM_LOAD( "mro-cg2426.u77", 0x00000, 0x10000, CRC(e7622901) SHA1(f653aaf02de840aef56d3efd7680572356e94da7) ) /* 05/29/98 @ IGT L98-1765 */
9434	9435	ROM_LOAD( "mgo-cg2426.u78", 0x10000, 0x10000, CRC(5c8388a0) SHA1(c883bf7969850d07f37fa0fd58f82cda4cf15654) )
9435	9436	ROM_LOAD( "mbo-cg2426.u79", 0x20000, 0x10000, CRC(dc6e39aa) SHA1(7a7188757f5be25521a023d1315cfd7c395b6c25) )
9436	9437	ROM_LOAD( "mxo-cg2426.u80", 0x30000, 0x10000, CRC(a32f42a2) SHA1(87ddc4dda7c198ed62a2a065507efe4d3a016236) )
r245142	r245143
9488	9489	ROM_LOAD( "x002440p.u66", 0x00000, 0x10000, CRC(2ecb28cc) SHA1(a7b902bdfbf8f5ceedc778b8408c39ee279a1a1d) ) /* Deuces Wild Poker */
9489	9490
9490	9491	ROM_REGION( 0x040000, "gfx1", 0 )
9491		ROM_LOAD( "mro-cg2426.u77", 0x00000, 0x10000, CRC(e7622901) SHA1(f653aaf02de840aef56d3efd7680572356e94da7) )
	9492	ROM_LOAD( "mro-cg2426.u77", 0x00000, 0x10000, CRC(e7622901) SHA1(f653aaf02de840aef56d3efd7680572356e94da7) ) /* 05/29/98 @ IGT L98-1765 */
9492	9493	ROM_LOAD( "mgo-cg2426.u78", 0x10000, 0x10000, CRC(5c8388a0) SHA1(c883bf7969850d07f37fa0fd58f82cda4cf15654) )
9493	9494	ROM_LOAD( "mbo-cg2426.u79", 0x20000, 0x10000, CRC(dc6e39aa) SHA1(7a7188757f5be25521a023d1315cfd7c395b6c25) )
9494	9495	ROM_LOAD( "mxo-cg2426.u80", 0x30000, 0x10000, CRC(a32f42a2) SHA1(87ddc4dda7c198ed62a2a065507efe4d3a016236) )

trunk/src/mame/drivers/playmark.c
r245142	r245143
1375	1375	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold)
1376	1376
1377	1377	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
1378		// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
	1378	// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
1379	1379	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
1380	1380	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
1381	1381	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
r245142	r245143
1416	1416	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold) // irq 2 and 6 point to the same location on hotmind
1417	1417
1418	1418	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
1419		// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
	1419	// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
1420	1420	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
1421	1421	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
1422	1422	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
r245142	r245143
1462	1462	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold)
1463	1463
1464	1464	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
1465		// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
	1465	// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
1466	1466	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
1467	1467	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
1468	1468	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))

trunk/src/mame/drivers/psychic5.c
r245142	r245143
318	318	MACHINE_START_MEMBER(psychic5_state, psychic5)
319	319	{
320	320	membank("mainbank")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x4000);
321
	321
322	322	save_item(NAME(m_bank_latch));
323	323	}
324	324
325	325	MACHINE_START_MEMBER(psychic5_state, bombsa)
326	326	{
327	327	membank("mainbank")->configure_entries(0, 8, memregion("maincpu")->base() + 0x10000, 0x4000);
328
	328
329	329	save_item(NAME(m_bank_latch));
330	330	}
331	331
r245142	r245143
707	707	MCFG_CPU_IO_MAP(psychic5_soundport_map)
708	708
709	709	MCFG_QUANTUM_TIME(attotime::from_hz(600)) /* Allow time for 2nd cpu to interleave */
710
	710
711	711	MCFG_MACHINE_START_OVERRIDE(psychic5_state,psychic5)
712	712
713	713	/* video hardware */
r245142	r245143
763	763	MCFG_CPU_IO_MAP(bombsa_soundport_map)
764	764
765	765	MCFG_QUANTUM_TIME(attotime::from_hz(600))
766
	766
767	767	MCFG_MACHINE_START_OVERRIDE(psychic5_state,bombsa)
768	768
769	769	/* video hardware */

trunk/src/mame/drivers/pturn.c
r245142	r245143
123	123
124	124	TILE_GET_INFO_MEMBER(get_tile_info);
125	125	TILE_GET_INFO_MEMBER(get_bg_tile_info);
126
	126
127	127	DECLARE_DRIVER_INIT(pturn);
128	128	virtual void machine_start();
129	129	virtual void machine_reset();
130	130	virtual void video_start();
131
	131
132	132	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
133
	133
134	134	INTERRUPT_GEN_MEMBER(sub_intgen);
135	135	INTERRUPT_GEN_MEMBER(main_intgen);
136	136	};
r245142	r245143
174	174	m_fgmap->set_transparent_pen(0);
175	175	m_bgmap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(pturn_state::get_bg_tile_info),this),TILEMAP_SCAN_ROWS,8, 8,32,32*8);
176	176	m_bgmap->set_transparent_pen(0);
177
	177
178	178	save_item(NAME(m_bgbank));
179	179	save_item(NAME(m_fgbank));
180	180	save_item(NAME(m_bgpalette));

trunk/src/mame/drivers/re900.c
r245142	r245143
101	101	UINT8 m_ledant;
102	102	UINT8 m_player;
103	103	UINT8 m_stat_a;
104
	104
105	105	// common
106	106	DECLARE_READ8_MEMBER(rom_r);
107	107	DECLARE_WRITE8_MEMBER(cpu_port_0_w);
108	108	DECLARE_WRITE8_MEMBER(watchdog_reset_w);
109
	109
110	110	// re900 specific
111	111	DECLARE_READ8_MEMBER(re_psg_portA_r);
112	112	DECLARE_READ8_MEMBER(re_psg_portB_r);
113	113	DECLARE_WRITE8_MEMBER(re_mux_port_A_w);
114	114	DECLARE_WRITE8_MEMBER(re_mux_port_B_w);
115
	115
116	116	DECLARE_DRIVER_INIT(re900);
117	117	};
118	118
r245142	r245143
432	432	m_player = 1;
433	433	m_stat_a = 1;
434	434	m_psg_pa = m_psg_pb = m_mux_data = m_ledant = 0;
435
	435
436	436	save_item(NAME(m_psg_pa));
437	437	save_item(NAME(m_psg_pb));
438	438	save_item(NAME(m_mux_data));

trunk/src/mame/drivers/rltennis.c
r245142	r245143
157	157	m_samples_2 = memregion("samples2")->base();
158	158	m_gfx = memregion("gfx1")->base();
159	159	m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rltennis_state::sample_player),this));
160
	160
161	161	save_item(NAME(m_data760000));
162	162	save_item(NAME(m_data740000));
163	163	save_item(NAME(m_dac_counter));

trunk/src/mame/drivers/sandscrp.c
r245142	r245143
102	102	UINT8 m_vblank_irq;
103	103	UINT8 m_latch1_full;
104	104	UINT8 m_latch2_full;
105
	105
106	106	DECLARE_READ16_MEMBER(irq_cause_r);
107	107	DECLARE_WRITE16_MEMBER(irq_cause_w);
108	108	DECLARE_WRITE16_MEMBER(coincounter_w);
r245142	r245143
114	114	DECLARE_READ8_MEMBER(latchstatus_r);
115	115	DECLARE_READ8_MEMBER(soundlatch_r);
116	116	DECLARE_WRITE8_MEMBER(soundlatch_w);
117
	117
118	118	virtual void machine_start();
119
	119
120	120	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
121	121	void screen_eof(screen_device &screen, bool state);
122
	122
123	123	INTERRUPT_GEN_MEMBER(interrupt);
124	124	void update_irq_state();
125	125	};
r245142	r245143
150	150	void sandscrp_state::machine_start()
151	151	{
152	152	membank("bank1")->configure_entries(0, 8, memregion("audiocpu")->base(), 0x4000);
153
	153
154	154	save_item(NAME(m_sprite_irq));
155	155	save_item(NAME(m_unknown_irq));
156	156	save_item(NAME(m_vblank_irq));

trunk/src/mame/drivers/scobra.c
r245142	r245143
1253	1253
1254	1254	GAME( 1982, mimonkey, 0, mimonkey, mimonkey, scramble_state, mimonkey, ROT90, "Universal Video Games", "Mighty Monkey", GAME_SUPPORTS_SAVE )
1255	1255	GAME( 1982, mimonsco, mimonkey, mimonkey, mimonsco, scramble_state, mimonsco, ROT90, "bootleg", "Mighty Monkey (bootleg on Super Cobra hardware)", GAME_SUPPORTS_SAVE )
1256

trunk/src/mame/drivers/seta.c
r245142	r245143
7796	7796	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
7797	7797	MCFG_SETA001_SPRITE_PALETTE("palette")
7798	7798	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
7799
	7799
7800	7800	/* video hardware */
7801	7801	MCFG_SCREEN_ADD("screen", RASTER)
7802	7802	MCFG_SCREEN_REFRESH_RATE(57.42) /* verified on pcb */
r245142	r245143
7857	7857	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
7858	7858	MCFG_SETA001_SPRITE_PALETTE("palette")
7859	7859	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
7860
	7860
7861	7861	/* video hardware */
7862	7862	MCFG_SCREEN_ADD("screen", RASTER)
7863	7863	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
7912	7912	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
7913	7913	MCFG_SETA001_SPRITE_PALETTE("palette")
7914	7914	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
7915
	7915
7916	7916	/* video hardware */
7917	7917	MCFG_SCREEN_ADD("screen", RASTER)
7918	7918	MCFG_SCREEN_REFRESH_RATE(57.42) /* verified on pcb */
r245142	r245143
7956	7956	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
7957	7957	MCFG_SETA001_SPRITE_PALETTE("palette")
7958	7958	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
7959
	7959
7960	7960	/* video hardware */
7961	7961	MCFG_SCREEN_ADD("screen", RASTER)
7962	7962	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8040	8040	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8041	8041	MCFG_SETA001_SPRITE_PALETTE("palette")
8042	8042	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8043
	8043
8044	8044	/* video hardware */
8045	8045	MCFG_SCREEN_ADD("screen", RASTER)
8046	8046	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8078	8078	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8079	8079	MCFG_SETA001_SPRITE_PALETTE("palette")
8080	8080	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8081
	8081
8082	8082	/* video hardware */
8083	8083	MCFG_SCREEN_ADD("screen", RASTER)
8084	8084	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8196	8196	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8197	8197	MCFG_SETA001_SPRITE_PALETTE("palette")
8198	8198	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8199
	8199
8200	8200	/* video hardware */
8201	8201	MCFG_SCREEN_ADD("screen", RASTER)
8202	8202	MCFG_SCREEN_REFRESH_RATE(57.42) /* verified on PCB */
r245142	r245143
8235	8235	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8236	8236	MCFG_SETA001_SPRITE_PALETTE("palette")
8237	8237	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8238
	8238
8239	8239	/* video hardware */
8240	8240	MCFG_SCREEN_ADD("screen", RASTER)
8241	8241	MCFG_SCREEN_REFRESH_RATE(57.42) /* verified on PCB */
r245142	r245143
8279	8279	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8280	8280	MCFG_SETA001_SPRITE_PALETTE("palette")
8281	8281	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8282
	8282
8283	8283	/* video hardware */
8284	8284	MCFG_SCREEN_ADD("screen", RASTER)
8285	8285	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8317	8317	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8318	8318	MCFG_SETA001_SPRITE_PALETTE("palette")
8319	8319	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8320
	8320
8321	8321	/* video hardware */
8322	8322	MCFG_SCREEN_ADD("screen", RASTER)
8323	8323	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8368	8368	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8369	8369	MCFG_SETA001_SPRITE_PALETTE("palette")
8370	8370	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8371
	8371
8372	8372	MCFG_NVRAM_ADD_RANDOM_FILL("nvram")
8373	8373
8374	8374	/* video hardware */
r245142	r245143
8412	8412	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8413	8413	MCFG_SETA001_SPRITE_PALETTE("palette")
8414	8414	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8415
	8415
8416	8416	/* video hardware */
8417	8417	MCFG_SCREEN_ADD("screen", RASTER)
8418	8418	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8456	8456	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8457	8457	MCFG_SETA001_SPRITE_PALETTE("palette")
8458	8458	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8459
	8459
8460	8460	/* video hardware */
8461	8461	MCFG_SCREEN_ADD("screen", RASTER)
8462	8462	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8522	8522	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8523	8523	MCFG_SETA001_SPRITE_PALETTE("palette")
8524	8524	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8525
	8525
8526	8526	/* video hardware */
8527	8527	MCFG_SCREEN_ADD("screen", RASTER)
8528	8528	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8568	8568	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8569	8569	MCFG_SETA001_SPRITE_PALETTE("palette")
8570	8570	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8571
	8571
8572	8572	/* video hardware */
8573	8573	MCFG_SCREEN_ADD("screen", RASTER)
8574	8574	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8605	8605	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8606	8606	MCFG_SETA001_SPRITE_PALETTE("palette")
8607	8607	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8608
	8608
8609	8609	/* video hardware */
8610	8610	MCFG_SCREEN_ADD("screen", RASTER)
8611	8611	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8651	8651	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8652	8652	MCFG_SETA001_SPRITE_PALETTE("palette")
8653	8653	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8654
	8654
8655	8655	/* video hardware */
8656	8656	MCFG_SCREEN_ADD("screen", RASTER)
8657	8657	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8820	8820	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8821	8821	MCFG_SETA001_SPRITE_PALETTE("palette")
8822	8822	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8823
	8823
8824	8824	/* video hardware */
8825	8825	MCFG_SCREEN_ADD("screen", RASTER)
8826	8826	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8866	8866	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8867	8867	MCFG_SETA001_SPRITE_PALETTE("palette")
8868	8868	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8869
	8869
8870	8870	/* video hardware */
8871	8871	MCFG_SCREEN_ADD("screen", RASTER)
8872	8872	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8915	8915	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8916	8916	MCFG_SETA001_SPRITE_PALETTE("palette")
8917	8917	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8918
	8918
8919	8919	/* video hardware */
8920	8920	MCFG_SCREEN_ADD("screen", RASTER)
8921	8921	MCFG_SCREEN_REFRESH_RATE(56.66) /* between 56 and 57 to match a real PCB's game speed */
r245142	r245143
8956	8956	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8957	8957	MCFG_SETA001_SPRITE_PALETTE("palette")
8958	8958	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8959
	8959
8960	8960	/* video hardware */
8961	8961	MCFG_SCREEN_ADD("screen", RASTER)
8962	8962	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
8996	8996	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
8997	8997	MCFG_SETA001_SPRITE_PALETTE("palette")
8998	8998	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
8999
	8999
9000	9000	/* video hardware */
9001	9001	MCFG_SCREEN_ADD("screen", RASTER)
9002	9002	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
9077	9077	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
9078	9078	MCFG_SETA001_SPRITE_PALETTE("palette")
9079	9079	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
9080
	9080
9081	9081	/* video hardware */
9082	9082	MCFG_SCREEN_ADD("screen", RASTER)
9083	9083	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
9313	9313	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
9314	9314	MCFG_SETA001_SPRITE_PALETTE("palette")
9315	9315	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
9316
	9316
9317	9317	/* video hardware */
9318	9318	MCFG_SCREEN_ADD("screen", RASTER)
9319	9319	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
9365	9365	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
9366	9366	MCFG_SETA001_SPRITE_PALETTE("palette")
9367	9367	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
9368
	9368
9369	9369	/* video hardware */
9370	9370	MCFG_SCREEN_ADD("screen", RASTER)
9371	9371	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
9411	9411	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
9412	9412	MCFG_SETA001_SPRITE_PALETTE("palette")
9413	9413	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
9414
	9414
9415	9415	/* video hardware */
9416	9416	MCFG_SCREEN_ADD("screen", RASTER)
9417	9417	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
9519	9519	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
9520	9520	MCFG_SETA001_SPRITE_PALETTE("palette")
9521	9521	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
9522
	9522
9523	9523	/* video hardware */
9524	9524	MCFG_SCREEN_ADD("screen", RASTER)
9525	9525	MCFG_SCREEN_REFRESH_RATE(60)
r245142	r245143
9585	9585	MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
9586	9586	MCFG_SETA001_SPRITE_PALETTE("palette")
9587	9587	MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
9588
	9588
9589	9589	/* video hardware */
9590	9590	MCFG_SCREEN_ADD("screen", RASTER)
9591	9591	MCFG_SCREEN_REFRESH_RATE(60)

trunk/src/mame/drivers/seta2.c
r245142	r245143
585	585	emu_timer *tm = timer_alloc(0);
586	586	tm->adjust(attotime::from_ticks(1, clock()), 0, attotime::from_ticks(1, clock()));
587	587	m_tx_cb.resolve_safe();
588
	588
589	589	save_item(NAME(m_button_state));
590	590	save_item(NAME(m_serial_pos));
591	591	save_item(NAME(m_serial));

trunk/src/mame/drivers/shougi.c
r245142	r245143
107	107	int m_r;
108	108	//UINT8 *m_cpu_sharedram;
109	109	//UINT8 m_cpu_sharedram_control_val;
110
	110
111	111	DECLARE_WRITE8_MEMBER(cpu_sharedram_sub_w);
112	112	DECLARE_WRITE8_MEMBER(cpu_sharedram_main_w);
113	113	DECLARE_READ8_MEMBER(cpu_sharedram_r);
r245142	r245143
118	118	DECLARE_WRITE8_MEMBER(nmi_disable_and_clear_line_w);
119	119	DECLARE_WRITE8_MEMBER(nmi_enable_w);
120	120	DECLARE_READ8_MEMBER(dummy_r);
121
	121
122	122	DECLARE_PALETTE_INIT(shougi);
123	123	virtual void machine_start();
124
	124
125	125	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
126
	126
127	127	INTERRUPT_GEN_MEMBER(vblank_nmi);
128	128	};
129	129

trunk/src/mame/drivers/sidearms.c
r245142	r245143
43	43
44	44	void sidearms_state::machine_start()
45	45	{
46		membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x8000, 0x4000);
	46	membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x8000, 0x4000);
47	47	}
48	48
49	49	WRITE8_MEMBER(sidearms_state::bankswitch_w)
50	50	{
51		membank("bank1")->set_entry(data & 0x07);
	51	membank("bank1")->set_entry(data & 0x07);
52	52	}
53	53
54	54
r245142	r245143
119	119
120	120	WRITE8_MEMBER(sidearms_state::whizz_bankswitch_w)
121	121	{
122		int bank = 0;
	122	int bank = 0;
123	123	switch (data & 0xC0)
124	124	{
125	125	case 0x00 : bank = 0; break;
r245142	r245143
127	127	case 0x80 : bank = 1; break;
128	128	case 0xC0 : bank = 3; break;
129	129	}
130		membank("bank1")->set_entry(bank);
	130	membank("bank1")->set_entry(bank);
131	131	}
132	132
133	133	static ADDRESS_MAP_START( whizz_map, AS_PROGRAM, 8, sidearms_state )

trunk/src/mame/drivers/simple_st0016.c
r245142	r245143
33	33
34	34	void st0016_state::machine_start()
35	35	{
36		membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
	36	membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
37	37	}
38	38
39	39	static ADDRESS_MAP_START( st0016_mem, AS_PROGRAM, 8, st0016_state )
r245142	r245143
81	81
82	82	WRITE8_MEMBER(st0016_state::st0016_rom_bank_w)
83	83	{
84		membank("bank1")->set_entry(data);
85		// st0016_rom_bank = data;
	84	membank("bank1")->set_entry(data);
	85	// st0016_rom_bank = data;
86	86	}
87	87
88	88	static ADDRESS_MAP_START( st0016_io, AS_IO, 8, st0016_state )

trunk/src/mame/drivers/sothello.c
r245142	r245143
72	72	DECLARE_READ8_MEMBER(subcpu_status_r);
73	73	DECLARE_WRITE8_MEMBER(msm_cfg_w);
74	74
75		virtual void machine_start();
	75	virtual void machine_start();
76	76	virtual void machine_reset();
77	77	TIMER_CALLBACK_MEMBER(subcpu_suspend);
78	78	TIMER_CALLBACK_MEMBER(subcpu_resume);
r245142	r245143
101	101
102	102	void sothello_state::machine_start()
103	103	{
104		membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x8000, 0x4000);
	104	membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x8000, 0x4000);
105	105	}
106	106
107	107	WRITE8_MEMBER(sothello_state::bank_w)
r245142	r245143
114	114	case 4: bank=2; break;
115	115	case 8: bank=3; break;
116	116	}
117		membank("bank1")->set_entry(bank);
	117	membank("bank1")->set_entry(bank);
118	118	}
119	119
120	120	TIMER_CALLBACK_MEMBER(sothello_state::subcpu_suspend)

trunk/src/mame/drivers/speglsht.c
r245142	r245143
134	134	DECLARE_READ32_MEMBER(irq_ack_clear);
135	135	DECLARE_DRIVER_INIT(speglsht);
136	136	DECLARE_MACHINE_RESET(speglsht);
137		virtual void machine_start();
	137	virtual void machine_start();
138	138	DECLARE_VIDEO_START(speglsht);
139	139	UINT32 screen_update_speglsht(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
140	140	required_device<palette_device> m_palette;
r245142	r245143
160	160
161	161	void speglsht_state::machine_start()
162	162	{
163		membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
	163	membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
164	164	}
165	165
166	166	// common rombank? should go in machine/st0016 with larger address space exposed?
167	167	WRITE8_MEMBER(speglsht_state::st0016_rom_bank_w)
168	168	{
169		membank("bank1")->set_entry(data);
	169	membank("bank1")->set_entry(data);
170	170	}
171	171
172	172

trunk/src/mame/drivers/srmp2.c
r245142	r245143
83	83	MACHINE_START_MEMBER(srmp2_state,srmp2)
84	84	{
85	85	machine_start();
86
	86
87	87	m_iox.reset = 0x1f;
88	88	m_iox.ff_event = -1;
89	89	m_iox.ff_1 = 0x00;
r245142	r245143
92	92	m_iox.protcheck[1] = -1; m_iox.protlatch[1] = -1;
93	93	m_iox.protcheck[2] = -1; m_iox.protlatch[2] = -1;
94	94	m_iox.protcheck[3] = -1; m_iox.protlatch[3] = -1;
95
	95
96	96	save_item(NAME(m_color_bank));
97	97	}
98	98
99	99	MACHINE_START_MEMBER(srmp2_state,srmp3)
100	100	{
101	101	machine_start();
102
	102
103	103	m_iox.reset = 0xc8;
104	104	m_iox.ff_event = 0xef;
105	105	m_iox.ff_1 = -1;
r245142	r245143
107	107	m_iox.protcheck[1] = 0x4c; m_iox.protlatch[1] = 0x00;
108	108	m_iox.protcheck[2] = 0x1c; m_iox.protlatch[2] = 0x04;
109	109	m_iox.protcheck[3] = 0x45; m_iox.protlatch[3] = 0x00;
110
111		membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base(), 0x2000);
112
	110
	111	membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base(), 0x2000);
	112
113	113	save_item(NAME(m_gfx_bank));
114	114	}
115	115
116	116	MACHINE_START_MEMBER(srmp2_state,rmgoldyh)
117	117	{
118	118	machine_start();
119
	119
120	120	m_iox.reset = 0xc8;
121	121	m_iox.ff_event = 0xff;
122	122	m_iox.ff_1 = -1;
r245142	r245143
125	125	m_iox.protcheck[2] = -1; m_iox.protlatch[2] = -1;
126	126	m_iox.protcheck[3] = -1; m_iox.protlatch[3] = -1;
127	127
128		membank("bank1")->configure_entries(0, 32, memregion("maincpu")->base(), 0x2000);
129
	128	membank("bank1")->configure_entries(0, 32, memregion("maincpu")->base(), 0x2000);
	129
130	130	save_item(NAME(m_gfx_bank));
131	131	}
132	132
133	133	MACHINE_START_MEMBER(srmp2_state,mjyuugi)
134	134	{
135	135	machine_start();
136
	136
137	137	m_iox.reset = 0x1f;
138	138	m_iox.ff_event = -1;
139	139	m_iox.ff_1 = 0x00;

trunk/src/mame/drivers/srmp5.c
r245142	r245143
114	114	DECLARE_READ8_MEMBER(cmd1_r);
115	115	DECLARE_READ8_MEMBER(cmd2_r);
116	116	DECLARE_READ8_MEMBER(cmd_stat8_r);
117		virtual void machine_start();
	117	virtual void machine_start();
118	118	DECLARE_DRIVER_INIT(srmp5);
119	119	UINT32 screen_update_srmp5(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
120	120
r245142	r245143
240	240
241	241	void srmp5_state::machine_start()
242	242	{
243		membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
	243	membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
244	244	}
245	245
246	246	WRITE32_MEMBER(srmp5_state::bank_w)
r245142	r245143
400	400	// common rombank? should go in machine/st0016 with larger address space exposed?
401	401	WRITE8_MEMBER(srmp5_state::st0016_rom_bank_w)
402	402	{
403		membank("bank1")->set_entry(data);
	403	membank("bank1")->set_entry(data);
404	404	}
405	405
406	406

trunk/src/mame/drivers/srmp6.c
r245142	r245143
107	107	DECLARE_WRITE16_MEMBER(paletteram_w);
108	108	DECLARE_READ16_MEMBER(srmp6_irq_ack_r);
109	109	DECLARE_DRIVER_INIT(INIT);
110		virtual void machine_start();
	110	virtual void machine_start();
111	111	virtual void video_start();
112	112	UINT32 screen_update_srmp6(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
113	113	void update_palette();
r245142	r245143
309	309
310	310	void srmp6_state::machine_start()
311	311	{
312		membank("bank1")->configure_entries(0, 16, memregion("nile")->base(), 0x200000);
	312	membank("bank1")->configure_entries(0, 16, memregion("nile")->base(), 0x200000);
313	313	}
314	314
315	315	WRITE16_MEMBER(srmp6_state::srmp6_input_select_w)
r245142	r245143
340	340	{
341	341	case 0x5e/2: // bank switch, used by ROM check
342	342	{
343		LOG(("%x\n",data));
344		membank("bank1")->set_entry(data & 0x0f);
	343	LOG(("%x\n",data));
	344	membank("bank1")->set_entry(data & 0x0f);
345	345	break;
346	346	}
347	347

trunk/src/mame/drivers/srumbler.c
r245142	r245143
32	32
33	33	for (int i = 0x05;i < 0x10;i++)
34	34	{
35		/* bit 2 of prom1 selects ROM or RAM - not supported */
	35	/* bit 2 of prom1 selects ROM or RAM - not supported */
36	36	int bank = ((prom1[i] & 0x03) << 4) \| (prom2[i] & 0x0f);
37	37
38		char bankname[10];
	38	char bankname[10];
39	39	sprintf(bankname, "%04x", i*0x1000);
40		membank(bankname)->set_entry(bank);
	40	membank(bankname)->set_entry(bank);
41	41	}
42	42	}
43	43
44	44	void srumbler_state::machine_start()
45	45	{
46		for (int i = 0x05; i < 0x10; i++)
	46	for (int i = 0x05; i < 0x10; i++)
47	47	{
48		char bankname[10];
	48	char bankname[10];
49	49	sprintf(bankname, "%04x", i*0x1000);
50		membank(bankname)->configure_entries(0, 64, memregion("user1")->base(), 0x1000);
	50	membank(bankname)->configure_entries(0, 64, memregion("user1")->base(), 0x1000);
51	51	}
52	52
53		/* initialize banked ROM pointers */
	53	/* initialize banked ROM pointers */
54	54	bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0);
55	55	}
56	56

trunk/src/mame/drivers/sstrangr.c
r245142	r245143
24	24	required_device<cpu_device> m_maincpu;
25	25
26	26	required_shared_ptr<UINT8> m_ram;
27
	27
28	28	UINT8 m_flip_screen;
29
	29
30	30	DECLARE_WRITE8_MEMBER(port_w);
31
	31
32	32	virtual void video_start();
33
	33
34	34	UINT32 screen_update_sstrangr(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
35	35	UINT32 screen_update_sstrngr2(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
36	36	};

trunk/src/mame/drivers/ssv.c
r245142	r245143
2491	2491	( (i & 1) ? (8 << 16) : 0 ) ;
2492	2492	enable_video(1);
2493	2493	m_interrupt_ultrax = interrupt_ultrax;
2494
	2494
2495	2495	save_item(NAME(m_requested_int));
2496	2496	save_item(NAME(m_irq_enable));
2497	2497	}

trunk/src/mame/drivers/sub.c
r245142	r245143
139	139	required_shared_ptr<UINT8> m_spriteram;
140	140	required_shared_ptr<UINT8> m_spriteram2;
141	141	required_shared_ptr<UINT8> m_scrolly;
142
	142
143	143	UINT8 m_nmi_en;
144
	144
145	145	DECLARE_WRITE8_MEMBER(to_sound_w);
146	146	DECLARE_WRITE8_MEMBER(nmi_mask_w);
147
	147
148	148	virtual void machine_start();
149	149	DECLARE_PALETTE_INIT(sub);
150
	150
151	151	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
152	152	INTERRUPT_GEN_MEMBER(sound_irq);
153	153	};

trunk/src/mame/drivers/suna16.c
r245142	r245143
215	215
216	216	MACHINE_START_MEMBER(suna16_state,bestbest)
217	217	{
218		save_item(NAME(m_prot));
	218	save_item(NAME(m_prot));
219	219	}
220	220
221	221
r245142	r245143
294	294
295	295	MACHINE_START_MEMBER(suna16_state, bssoccer)
296	296	{
297		membank("bank1")->configure_entries(0, 8, memregion("pcm1")->base() + 0x1000, 0x10000);
298		membank("bank2")->configure_entries(0, 8, memregion("pcm2")->base() + 0x1000, 0x10000);
	297	membank("bank1")->configure_entries(0, 8, memregion("pcm1")->base() + 0x1000, 0x10000);
	298	membank("bank2")->configure_entries(0, 8, memregion("pcm2")->base() + 0x1000, 0x10000);
299	299	}
300	300
301	301	/* Bank Switching */
r245142	r245143
304	304	{
305	305	const int bank = data & 7;
306	306	if (bank & ~7) logerror("CPU#2 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
307		printf("%d %d\n", 1, bank);
308		membank("bank1")->set_entry(bank);
	307	printf("%d %d\n", 1, bank);
	308	membank("bank1")->set_entry(bank);
309	309	}
310	310
311	311	WRITE8_MEMBER(suna16_state::bssoccer_pcm_2_bankswitch_w)
312	312	{
313	313	const int bank = data & 7;
314	314	if (bank & ~7) logerror("CPU#3 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
315		printf("%d %d\n", 2, bank);
316		membank("bank2")->set_entry(bank);
	315	printf("%d %d\n", 2, bank);
	316	membank("bank2")->set_entry(bank);
317	317	}
318	318
319	319
r245142	r245143
378	378	{
379	379	const int bank = data & 1;
380	380	if (bank & ~1) logerror("CPU#2 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
381		membank("bank1")->set_entry(bank);
	381	membank("bank1")->set_entry(bank);
382	382	}
383	383
384	384	/* Memory maps: Yes, no RAM */
r245142	r245143
398	398
399	399	MACHINE_START_MEMBER(suna16_state,uballoon)
400	400	{
401		membank("bank1")->configure_entries(0, 2, memregion("pcm1")->base() + 0x400, 0x10000);
402
	401	membank("bank1")->configure_entries(0, 2, memregion("pcm1")->base() + 0x400, 0x10000);
	402
403	403	save_item(NAME(m_prot));
404	404	}
405	405
r245142	r245143
828	828
829	829	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
830	830
831		MCFG_MACHINE_START_OVERRIDE(suna16_state,bssoccer)
	831	MCFG_MACHINE_START_OVERRIDE(suna16_state,bssoccer)
832	832
833	833	/* video hardware */
834	834	MCFG_SCREEN_ADD("screen", RASTER)
r245142	r245143
887	887
888	888	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
889	889
890		MCFG_MACHINE_START_OVERRIDE(suna16_state,uballoon)
	890	MCFG_MACHINE_START_OVERRIDE(suna16_state,uballoon)
891	891	MCFG_MACHINE_RESET_OVERRIDE(suna16_state,uballoon)
892	892
893	893	/* video hardware */
r245142	r245143
992	992	/* 2nd PCM Z80 missing */
993	993
994	994	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
995
	995
996	996	MCFG_MACHINE_START_OVERRIDE(suna16_state, bestbest)
997	997
998	998	/* video hardware */

trunk/src/mame/drivers/suna8.c
r245142	r245143
735	735	AM_RANGE(0xc060, 0xc060) AM_WRITE(brickzn_rombank_w ) // ROM Bank
736	736	AM_RANGE(0xc080, 0xc080) AM_WRITE(brickzn_leds_w ) // Leds
737	737	AM_RANGE(0xc0a0, 0xc0a0) AM_WRITE(brickzn_palbank_w ) // Palette RAM Bank
738		// AM_RANGE(0xc0c0, 0xc0c0) AM_WRITE(brickzn_prot2_w ) // Protection 2
	738	// AM_RANGE(0xc0c0, 0xc0c0) AM_WRITE(brickzn_prot2_w ) // Protection 2
739	739
740	740	AM_RANGE(0xc100, 0xc100) AM_READ_PORT("P1") // P1 (Buttons)
741	741	AM_RANGE(0xc101, 0xc101) AM_READ_PORT("P2") // P2 (Buttons)
r245142	r245143
771	771	else if (protselect == 0x90)
772	772	{
773	773	/*
774		0d brick hit NO! 25?
775		2c side wall hit OK
776		3b paddle hit OK
777		44 death OK?
778		53 death OK?
779		56 coin in OK?
780		70 monster hit NO? 58?
	774	0d brick hit NO! 25?
	775	2c side wall hit OK
	776	3b paddle hit OK
	777	44 death OK?
	778	53 death OK?
	779	56 coin in OK?
	780	70 monster hit NO? 58?
781	781	*/
782	782	UINT8 remap = (m_remap_sound ? BITSWAP8(data, 7,6,3,4,5,2,1,0) : data);
783	783
r245142	r245143
1975	1975	MACHINE_RESET_MEMBER(suna8_state,brickzn)
1976	1976	{
1977	1977	m_protection_val = m_prot2 = m_prot2_prev = 0xff;
1978		m_paletteram_enab = 1; // for brickzn11
	1978	m_paletteram_enab = 1; // for brickzn11
1979	1979	m_remap_sound = 0;
1980	1980	membank("bank1")->set_entry(0);
1981	1981	}
r245142	r245143
2015	2015	/* sound hardware */
2016	2016	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
2017	2017
2018		MCFG_SOUND_ADD("ymsnd", YM3812, SUNA8_MASTER_CLOCK / 8) // 3MHz (measured)
	2018	MCFG_SOUND_ADD("ymsnd", YM3812, SUNA8_MASTER_CLOCK / 8) // 3MHz (measured)
2019	2019	MCFG_YM3812_IRQ_HANDLER(INPUTLINE("audiocpu", 0))
2020	2020	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
2021	2021	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
2022	2022
2023		MCFG_SOUND_ADD("aysnd", AY8910, SUNA8_MASTER_CLOCK / 16) // 1.5MHz (measured)
	2023	MCFG_SOUND_ADD("aysnd", AY8910, SUNA8_MASTER_CLOCK / 16) // 1.5MHz (measured)
2024	2024	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.33)
2025	2025	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.33)
2026	2026

trunk/src/mame/drivers/supdrapo.c
r245142	r245143
82	82	required_device<cpu_device> m_maincpu;
83	83	required_device<gfxdecode_device> m_gfxdecode;
84	84	required_device<palette_device> m_palette;
85
	85
86	86	required_shared_ptr<UINT8> m_col_line;
87	87	required_shared_ptr<UINT8> m_videoram;
88	88	required_shared_ptr<UINT8> m_char_bank;
89
	89
90	90	UINT8 m_wdog;
91
	91
92	92	DECLARE_READ8_MEMBER(rng_r);
93	93	DECLARE_WRITE8_MEMBER(wdog8000_w);
94	94	DECLARE_WRITE8_MEMBER(debug8004_w);
r245142	r245143
97	97	DECLARE_WRITE8_MEMBER(payout_w);
98	98	DECLARE_WRITE8_MEMBER(ay8910_outputa_w);
99	99	DECLARE_WRITE8_MEMBER(ay8910_outputb_w);
100
	100
101	101	virtual void machine_start();
102	102	virtual void machine_reset();
103	103	virtual void video_start();
104	104	DECLARE_PALETTE_INIT(supdrapo);
105
	105
106	106	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
107	107	};
108	108

trunk/src/mame/drivers/supertnk.c
r245142	r245143
124	124	DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_0_w);
125	125	DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_1_w);
126	126	DECLARE_DRIVER_INIT(supertnk);
127		virtual void machine_start();
	127	virtual void machine_start();
128	128	virtual void machine_reset();
129	129	virtual void video_start();
130	130	UINT32 screen_update_supertnk(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
r245142	r245143
135	135
136	136	void supertnk_state::machine_start()
137	137	{
138		membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x1000);
	138	membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x1000);
139	139	}
140	140
141	141
r245142	r245143
148	148	WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_0_w)
149	149	{
150	150	m_rom_bank = (m_rom_bank & 0x02) \| ((data << 0) & 0x01);
151		membank("bank1")->set_entry(m_rom_bank);
	151	membank("bank1")->set_entry(m_rom_bank);
152	152	}
153	153
154	154
155	155	WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_1_w)
156	156	{
157	157	m_rom_bank = (m_rom_bank & 0x01) \| ((data << 1) & 0x02);
158		membank("bank1")->set_entry(m_rom_bank);
	158	membank("bank1")->set_entry(m_rom_bank);
159	159	}
160	160
161	161

trunk/src/mame/drivers/superwng.c
r245142	r245143
10	10	TODO:
11	11	- unused rom 6.8s (located on the pcb near the gfx rom 7.8p, but contains
12	12	data (similar to the one in roms 4.5p and 5.5r)
13
	13
14	14	The game currently crashes after the bonus round rather than moving on to
15	15	the next level, it writes 01 to 0xa187 which is probably ROM bank, however
16	16	banking the ROM in there results in the game crashing anyway, and looking
r245142	r245143
101	101
102	102	WRITE8_MEMBER(superwng_state::superwng_unk_a185_w)
103	103	{
104		// printf("superwng_unk_a185_w %02x\n", data);
	104	// printf("superwng_unk_a185_w %02x\n", data);
105	105	}
106	106
107	107	TILE_GET_INFO_MEMBER(superwng_state::get_bg_tile_info)
r245142	r245143
456	456	save_item(NAME(m_tile_bank));
457	457	save_item(NAME(m_sound_byte));
458	458	save_item(NAME(m_nmi_enable));
459		membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base()+0x4000, 0x4000);
	459	membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base()+0x4000, 0x4000);
460	460	}
461	461
462	462	void superwng_state::machine_reset()

trunk/src/mame/drivers/suprgolf.c
r245142	r245143
60	60	UINT8 m_palette_switch;
61	61	UINT8 m_bg_vreg_test;
62	62	UINT8 m_toggle;
63
	63
64	64	DECLARE_READ8_MEMBER(videoram_r);
65	65	DECLARE_WRITE8_MEMBER(videoram_w);
66	66	DECLARE_READ8_MEMBER(bg_vram_r);
r245142	r245143
78	78	DECLARE_WRITE8_MEMBER(writeA);
79	79	DECLARE_WRITE8_MEMBER(writeB);
80	80	DECLARE_WRITE_LINE_MEMBER(adpcm_int);
81
	81
82	82	TILE_GET_INFO_MEMBER(get_tile_info);
83	83
84	84	DECLARE_DRIVER_INIT(suprgolf);
85		virtual void machine_start();
	85	virtual void machine_start();
86	86	virtual void machine_reset();
87	87	virtual void video_start();
88
	88
89	89	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
90	90	};
91	91
r245142	r245143
109	109	m_fg_fb = auto_alloc_array(machine(), UINT16, 0x2000*0x20);
110	110
111	111	m_tilemap->set_transparent_pen(15);
112
	112
113	113	save_item(NAME(m_bg_bank));
114	114	save_item(NAME(m_vreg_bank));
115	115	save_item(NAME(m_vreg_pen));
r245142	r245143
267	267
268	268	void suprgolf_state::machine_start()
269	269	{
270		membank("bank1")->configure_entries(0, 16, memregion("user2")->base(), 0x4000);
271		membank("bank2")->configure_entries(0, 64, memregion("user1")->base(), 0x4000);
272
	270	membank("bank1")->configure_entries(0, 16, memregion("user2")->base(), 0x4000);
	271	membank("bank2")->configure_entries(0, 64, memregion("user1")->base(), 0x4000);
	272
273	273	save_item(NAME(m_rom_bank));
274	274	save_item(NAME(m_msm5205next));
275	275	save_item(NAME(m_msm_nmi_mask));
r245142	r245143
293	293
294	294	WRITE8_MEMBER(suprgolf_state::rom_bank_select_w)
295	295	{
296		m_rom_bank = data;
	296	m_rom_bank = data;
297	297
298		//popmessage("%08x %02x",((data & 0x3f) * 0x4000),data);
299		//osd_printf_debug("ROM_BANK 0x8000 - %X @%X\n",data,space.device().safe_pcbase());
300		membank("bank2")->set_entry(data & 0x3f);
	298	//popmessage("%08x %02x",((data & 0x3f) * 0x4000),data);
	299	//osd_printf_debug("ROM_BANK 0x8000 - %X @%X\n",data,space.device().safe_pcbase());
	300	membank("bank2")->set_entry(data & 0x3f);
301	301
302	302	m_msm_nmi_mask = data & 0x40;
303	303	flip_screen_set(data & 0x80);
r245142	r245143
305	305
306	306	WRITE8_MEMBER(suprgolf_state::rom2_bank_select_w)
307	307	{
308		//osd_printf_debug("ROM_BANK 0x4000 - %X @%X\n",data,space.device().safe_pcbase());
309		membank("bank1")->set_entry(data & 0x0f);
310
	308	//osd_printf_debug("ROM_BANK 0x4000 - %X @%X\n",data,space.device().safe_pcbase());
	309	membank("bank1")->set_entry(data & 0x0f);
	310
311	311	if(data & 0xf0)
312	312	printf("Rom bank select 2 with data %02x activated\n",data);
313	313	}

trunk/src/mame/drivers/suprslam.c
r245142	r245143
115	115
116	116	WRITE8_MEMBER(suprslam_state::suprslam_sh_bankswitch_w)
117	117	{
118		membank("bank1")->set_entry(data & 0x03);
	118	membank("bank1")->set_entry(data & 0x03);
119	119	}
120	120
121	121	/* MEMORY MAPS ***********************************************************/
r245142	r245143
285	285	save_item(NAME(m_bg_bank));
286	286	save_item(NAME(m_pending_command));
287	287
288		membank("bank1")->configure_entries(0, 4, memregion("audiocpu")->base() + 0x10000, 0x8000);
	288	membank("bank1")->configure_entries(0, 4, memregion("audiocpu")->base() + 0x10000, 0x8000);
289	289	}
290	290
291	291	void suprslam_state::machine_reset()

trunk/src/mame/drivers/tankbust.c
r245142	r245143
24	24
25	25	void tankbust_state::machine_start()
26	26	{
27		membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x4000);
28		membank("bank2")->configure_entries(0, 2, memregion("maincpu")->base() + 0x18000, 0x2000);
29
	27	membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x4000);
	28	membank("bank2")->configure_entries(0, 2, memregion("maincpu")->base() + 0x18000, 0x2000);
	29
30	30	save_item(NAME(m_latch));
31	31	save_item(NAME(m_timer1));
32	32	save_item(NAME(m_e0xx_data));
r245142	r245143
107	107
108	108	case 7: /* 0xe007 bankswitch */
109	109	/* bank 1 at 0x6000-9fff = from 0x10000 when bit0=0 else from 0x14000 */
110		membank("bank1")->set_entry(data & 1);
	110	membank("bank1")->set_entry(data & 1);
111	111
112	112	/* bank 2 at 0xa000-bfff = from 0x18000 when bit0=0 else from 0x1a000 */
113	113	membank("bank2")->set_entry(data & 1); /* verified (the game will reset after the "game over" otherwise) */

trunk/src/mame/drivers/taotaido.c
r245142	r245143
76	76	void taotaido_state::machine_start()
77	77	{
78	78	membank("soundbank")->configure_entries(0, 4, memregion("audiocpu")->base(), 0x8000);
79
	79
80	80	save_item(NAME(m_pending_command));
81	81	}
82	82

trunk/src/mame/drivers/tbowl.c
r245142	r245143
418	418	{
419	419	membank("mainbank")->configure_entries(0, 32, memregion("maincpu")->base() + 0x10000, 0x800);
420	420	membank("subbank")->configure_entries(0, 32, memregion("sub")->base() + 0x10000, 0x800);
421
	421
422	422	save_item(NAME(m_adpcm_pos));
423	423	save_item(NAME(m_adpcm_end));
424	424	save_item(NAME(m_adpcm_data));

trunk/src/mame/drivers/tgtpanic.c
r245142	r245143
24	24
25	25	required_device<cpu_device> m_maincpu;
26	26	required_device<screen_device> m_screen;
27
	27
28	28	required_shared_ptr<UINT8> m_ram;
29
	29
30	30	UINT8 m_color;
31
	31
32	32	DECLARE_WRITE8_MEMBER(color_w);
33
	33
34	34	virtual void machine_start();
35
	35
36	36	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
37	37	};
38	38

trunk/src/mame/drivers/thunderx.c
r245142	r245143
317	317	WRITE8_MEMBER(thunderx_state::scontra_bankswitch_w)
318	318	{
319	319	// bits 0-3 select ROM bank at 6000-7fff
320		m_rombank->set_entry(data & 0x0f);
	320	m_rombank->set_entry(data & 0x0f);
321	321
322	322	// bit 4 selects work RAM or palette RAM at 5800-5fff
323	323	m_bank5800->set_bank((data & 0x10) >> 4);

trunk/src/mame/drivers/toaplan2.c
r245142	r245143
5370	5370	GAME( 1996, bgareggat2, bgaregga, bgaregga, bgaregga, toaplan2_state, bgaregga, ROT270, "Raizing / Eighting", "Battle Garegga - Type 2 (Europe / USA / Japan / Asia) (Sat Mar 2 1996)" , GAME_SUPPORTS_SAVE ) // displays Type 2 only when set to Europe
5371	5371	GAME( 1996, bgareggacn, bgaregga, bgaregga, bgareggacn, toaplan2_state, bgaregga, ROT270, "Raizing / Eighting", "Battle Garegga - Type 2 (Denmark / China) (Tue Apr 2 1996)", GAME_SUPPORTS_SAVE ) // displays Type 2 only when set to Denmark
5372	5372	GAME( 1996, bgareggabl, bgaregga, bgareggabl,bgareggacn, toaplan2_state,bgaregga, ROT270, "bootleg", "1945 Part-2 (Chinese hack of Battle Garegga)", GAME_SUPPORTS_SAVE )
5373		GAME( 1996, bgareggabla,bgaregga, bgareggabl,bgareggacn, toaplan2_state,bgaregga, ROT270, "bootleg", "Thunder Deity Biography (Chinese hack of Battle Garegga)", GAME_SUPPORTS_SAVE )
	5373	GAME( 1996, bgareggabla,bgaregga, bgareggabl,bgareggacn, toaplan2_state,bgaregga, ROT270, "bootleg", "Lei Shen Zhuan Thunder Deity Biography (Chinese hack of Battle Garegga)", GAME_SUPPORTS_SAVE )
5374	5374
5375	5375	// these are all based on Version B, even if only the Japan version states 'version B'
5376	5376	GAME( 1998, batrider, 0, batrider, batrider, toaplan2_state, batrider, ROT270, "Raizing / Eighting", "Armed Police Batrider (Europe) (Fri Feb 13 1998)", GAME_SUPPORTS_SAVE )

trunk/src/mame/drivers/tryout.c
r245142	r245143
45	45
46	46	void tryout_state::machine_start()
47	47	{
48		membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x2000);
	48	membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x2000);
49	49	}
50	50
51	51	WRITE8_MEMBER(tryout_state::bankswitch_w)
52	52	{
53		membank("bank1")->set_entry(data & 0x01);
	53	membank("bank1")->set_entry(data & 0x01);
54	54	}
55	55
56	56	static ADDRESS_MAP_START( main_cpu, AS_PROGRAM, 8, tryout_state )

trunk/src/mame/drivers/tsamurai.c
r245142	r245143
711	711
712	712	MCFG_CPU_ADD("audio2", Z80, XTAL_24MHz/8)
713	713	MCFG_CPU_PROGRAM_MAP(sound2_map)
714
	714
715	715	MCFG_MACHINE_START_OVERRIDE(tsamurai_state,tsamurai)
716	716
717	717	/* video hardware */
r245142	r245143
752	752	MCFG_CPU_PROGRAM_MAP(sound_vsgongf_map)
753	753	MCFG_CPU_IO_MAP(vsgongf_audio_io_map)
754	754	MCFG_CPU_PERIODIC_INT_DRIVER(tsamurai_state, vsgongf_sound_interrupt, 3*60)
755
	755
756	756	MCFG_MACHINE_START_OVERRIDE(tsamurai_state,vsgongf)
757	757
758	758	/* video hardware */
r245142	r245143
797	797	MCFG_CPU_PROGRAM_MAP(sound3_m660_map)
798	798	MCFG_CPU_IO_MAP(sound3_m660_io_map)
799	799	MCFG_CPU_VBLANK_INT_DRIVER("screen", tsamurai_state, nmi_line_pulse)
800
	800
801	801	MCFG_MACHINE_START_OVERRIDE(tsamurai_state,m660)
802	802
803	803	/* video hardware */

trunk/src/mame/drivers/ttchamp.c
r245142	r245143
51	51
52	52
53	53
54		- works in a very similar way to 'Spider' (twins.c)
	54	- works in a very similar way to 'Spider' (twins.c)
55	55	including the blitter (seems to be doubled up hardware tho, twice as many layers?)
56	56	- need to work out how it selects between upper/lower
57	57	program roms as blitter source
r245142	r245143
85	85
86	86	DECLARE_WRITE16_MEMBER(port20_w);
87	87	DECLARE_WRITE16_MEMBER(port62_w);
88
	88
89	89	DECLARE_READ16_MEMBER(port1e_r);
90	90
91	91
92	92	UINT16 m_port10;
	93	UINT8 m_rombank;
93	94
94	95	DECLARE_DRIVER_INIT(ttchamp);
95	96
r245142	r245143
99	100	DECLARE_WRITE16_MEMBER(ttchamp_mem_w);
100	101
101	102	UINT16 m_videoram0[0x10000 / 2];
102		// UINT16 m_videoram1[0x10000 / 2];
	103	// UINT16 m_videoram1[0x10000 / 2];
103	104	UINT16 m_videoram2[0x10000 / 2];
104	105
105	106
106	107
107
108	108	UINT16 m_mainram[0x10000 / 2];
109	109
110	110	int m_spritesinit;
r245142	r245143
130	130
131	131	void ttchamp_state::video_start()
132	132	{
133
134	133	}
135	134
136	135	UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
r245142	r245143
143	142	bitmap.fill(m_palette->black_pen());
144	143	UINT8 *videoramfg;
145	144	UINT8* videorambg;
146
	145
147	146	count=0;
148	147	videorambg = (UINT8*)m_videoram0;
149	148	videoramfg = (UINT8*)m_videoram2;
r245142	r245143
156	155	count++;
157	156	}
158	157	}
159
	158
160	159	/*
161	160	count=0;
162	161	videoram = (UINT8*)m_videoram1;
163	162	for (y=0;y<yyy;y++)
164	163	{
165		for(x=0;x<xxx;x++)
166		{
167		UINT8 pix = videoram[BYTE_XOR_LE(count)];
168		if (pix) bitmap.pix16(y, x) = pix+0x200;
169		count++;
170		}
	164	for(x=0;x<xxx;x++)
	165	{
	166	UINT8 pix = videoram[BYTE_XOR_LE(count)];
	167	if (pix) bitmap.pix16(y, x) = pix+0x200;
	168	count++;
	169	}
171	170	}
172	171	*/
173
	172
174	173	count=0;
175	174	for (y=0;y<yyy;y++)
176	175	{
r245142	r245143
204	203	count++;
205	204	}
206	205	}
207
	206
208	207	#if 0
209	208	for (int i = 0; i < 0x8000; i++)
210	209	{
r245142	r245143
212	211	// I think it actually does more blit operations with
213	212	// different bits of m_port10 set to redraw the backgrounds using the video ram data as a source rather than ROM - notice the garbage you see behind 'sprites' right now
214	213	// this method also removes the text layer, which we don't want
215		// m_videoram1[i] = 0x0000;
216		// m_videoram2[i] = 0x0000;
	214	// m_videoram1[i] = 0x0000;
	215	// m_videoram2[i] = 0x0000;
217	216	}
218	217	#endif
219
	218
220	219	return 0;
221	220	}
222	221
r245142	r245143
289	288
290	289	if (m_spritesinit == 1)
291	290	{
292		// printf("%06x: spider_blitter_w %08x %04x %04x (init?) (base?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
	291	// printf("%06x: spider_blitter_w %08x %04x %04x (init?) (base?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
293	292
294	293	m_spritesinit = 2;
295	294	m_spritesaddr = offset;
	295
296	296	}
297	297	else if (m_spritesinit == 2)
298	298	{
299		// printf("%06x: spider_blitter_w %08x %04x %04x (init2) (width?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
	299	// printf("%06x: spider_blitter_w %08x %04x %04x (init2) (width?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
300	300	m_spriteswidth = offset & 0xff;
	301	//printf("%08x\n",(offset*2) & 0xfff00);
301	302
302		m_spritesinit = 0;
303
	303	m_spritesinit = 3;
304	304	}
305	305	else
306	306	{
r245142	r245143
314	314	}
315	315	else if ((offset >= 0x30000 / 2) && (offset < 0x40000 / 2))
316	316	{
	317	if(m_spritesinit != 3)
	318	{
	319	printf("blitter bus write but blitter unselected? %08x %04x\n",offset*2,data);
	320	return;
	321	}
	322
	323	m_spritesinit = 0;
	324
317	325	// 0x30000-0x3ffff used, on Spider it's 0x20000-0x2ffff
318	326	offset &= 0x7fff;
319	327
320	328	UINT8 *src = m_rom8;
321	329
322		if (m_por~~t10 & 2) // NO, wr~~o~~ng for the portr~~a~~its~~
	330	if (m_rombank)
323	331	src += 0x100000;
324	332
325		// printf("%06x: spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", space.device().safe_pc(), offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
	333	// printf("%06x: spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", space.device().safe_pc(), offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
326	334	offset &= 0x7fff;
327	335
328	336	for (int i = 0; i < m_spriteswidth; i++)
r245142	r245143
337	345	UINT8 data;
338	346
339	347	data = (src[(m_spritesaddr * 2) + 1]);
	348	//data \|= vram[offset] >> 8;
340	349
341		if (data)
	350	/* bit 1 actually enables transparent pen */
	351	if (data \|\| (m_port10 & 2) == 0)
342	352	vram[offset] = (vram[offset] & 0x00ff) \| data << 8;
343	353
344
345	354	data = src[(m_spritesaddr * 2)];
	355	//data \|= vram[offset] & 0xff;
346	356
347		if (data)
	357	if (data \|\| (m_port10 & 2) == 0)
348	358	vram[offset] = (vram[offset] & 0xff00) \| data;
349	359
350	360
r245142	r245143
369	379	AM_RANGE(0x00000, 0xfffff) AM_READWRITE(ttchamp_mem_r, ttchamp_mem_w)
370	380	ADDRESS_MAP_END
371	381
	382	/* Re-use same parameters as before (one-shot) */
372	383	READ16_MEMBER(ttchamp_state::port1e_r)
373	384	{
	385	m_spritesinit = 3;
374	386	return 0xff;
375	387	}
376	388
r245142	r245143
384	396	{
385	397	UINT8 res;
386	398	COMBINE_DATA(&m_port10);
387
	399
388	400	res = m_port10 & 0xf0;
389	401	/* Assume that both bits clears layers. */
390	402	if(res == 0x30)
r245142	r245143
399	411	printf("Check me, i/o 0x10 used with %02x\n",res);
400	412	}
401	413
	414	/* selects upper bank for the blitter */
402	415	WRITE16_MEMBER(ttchamp_state::port20_w)
403	416	{
404	417	printf("%06x: port20_w %04x %04x\n", space.device().safe_pc(), data, mem_mask);
405		// seems to somehow be tied to layer clear
406		// might also depend on layer selected with 0x10 tho? written after it
407		/*for (int i = 0; i < 0x8000; i++)
408		{
409		// m_videoram0[i] = 0x0000;
410		m_videoram2[i] = 0x0000;
411		}*/
412
	418	m_rombank = 1;
413	419	}
414	420
	421	/* selects lower bank for the blitter */
415	422	WRITE16_MEMBER(ttchamp_state::port62_w)
416	423	{
417	424	printf("%06x: port62_w %04x %04x\n", space.device().safe_pc(), data, mem_mask);
	425	m_rombank = 0;
418	426	}
419	427
420	428	static ADDRESS_MAP_START( ttchamp_io, AS_IO, 16, ttchamp_state )
421		AM_RANGE(0x0000, 0x0001) AM_WRITENOP // startup only
	429	AM_RANGE(0x0000, 0x0001) AM_WRITENOP // startup only, nmi enable?
422	430
423	431	AM_RANGE(0x0002, 0x0003) AM_READ_PORT("SYSTEM")
424	432	AM_RANGE(0x0004, 0x0005) AM_READ_PORT("P1_P2")
r245142	r245143
435	443
436	444	AM_RANGE(0x0020, 0x0021) AM_WRITE(port20_w)
437	445
438		// AM_RANGE(0x0034, 0x0035) AM_READ(peno_rand) AM_WRITENOP // eeprom (PIC?) / settings?
	446	// AM_RANGE(0x0034, 0x0035) AM_READ(peno_rand) AM_WRITENOP // eeprom (PIC?) / settings?
439	447
440	448	AM_RANGE(0x0062, 0x0063) AM_WRITE(port62_w)
441	449
r245142	r245143
568	576
569	577	DRIVER_INIT_MEMBER(ttchamp_state,ttchamp)
570	578	{
571		// UINT8 *ROM1 = memregion("user1")->base();
572		// membank("bank1")->set_base(&ROM1[0x100000]);
573		// membank("bank2")->set_base(&ROM1[0x180000]);
	579	// UINT8 *ROM1 = memregion("user1")->base();
	580	// membank("bank1")->set_base(&ROM1[0x100000]);
	581	// membank("bank2")->set_base(&ROM1[0x180000]);
574	582	}
575	583
576	584	GAME( 1995, ttchamp, 0, ttchamp, ttchamp, ttchamp_state, ttchamp, ROT0, "Gamart", "Table Tennis Champions", GAME_NOT_WORKING ) // this has various advertising boards, including 'Electronic Devices' and 'Deniam'

trunk/src/mame/drivers/tugboat.c
r245142	r245143
49	49	required_device<gfxdecode_device> m_gfxdecode;
50	50	required_device<screen_device> m_screen;
51	51	required_device<palette_device> m_palette;
52
	52
53	53	required_shared_ptr<UINT8> m_ram;
54	54
55	55	UINT8 m_hd46505_0_reg[18];
r245142	r245143
58	58	int m_reg1;
59	59	int m_ctrl;
60	60	emu_timer *m_interrupt_timer;
61
	61
62	62	DECLARE_WRITE8_MEMBER(hd46505_0_w);
63	63	DECLARE_WRITE8_MEMBER(hd46505_1_w);
64	64	DECLARE_WRITE8_MEMBER(score_w);
65	65	DECLARE_READ8_MEMBER(input_r);
66	66	DECLARE_WRITE8_MEMBER(ctrl_w);
67
	67
68	68	virtual void machine_start();
69	69	virtual void video_start();
70	70	virtual void machine_reset();
71	71	DECLARE_PALETTE_INIT(tugboat);
72
	72
73	73	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
74	74	void draw_tilemap(bitmap_ind16 &bitmap,const rectangle &cliprect,
75	75	int addr,int gfx0,int gfx1,int transparency);
r245142	r245143
82	82	void tugboat_state::machine_start()
83	83	{
84	84	m_interrupt_timer = timer_alloc(TIMER_INTERRUPT);
85
	85
86	86	save_item(NAME(m_hd46505_0_reg));
87	87	save_item(NAME(m_hd46505_1_reg));
88	88	save_item(NAME(m_reg0));

trunk/src/mame/drivers/twins.c
r245142	r245143
123	123	READ16_MEMBER(twins_state::twins_port4_r)
124	124	{
125	125	// doesn't work??
126		// printf("%08x: twins_port4_r %04x\n", space.device().safe_pc(), mem_mask);
127		// return m_i2cmem->read_sda();// \| 0xfffe;
	126	// printf("%08x: twins_port4_r %04x\n", space.device().safe_pc(), mem_mask);
	127	// return m_i2cmem->read_sda();// \| 0xfffe;
128	128
129	129	return 0x0001;
130	130	}
131	131
132	132	WRITE16_MEMBER(twins_state::twins_port4_w)
133	133	{
134		// printf("%08x: twins_port4_w %04x %04x\n", space.device().safe_pc(), data, mem_mask);
	134	// printf("%08x: twins_port4_w %04x %04x\n", space.device().safe_pc(), data, mem_mask);
135	135	int i2c_clk = BIT(data, 1);
136	136	int i2c_mem = BIT(data, 0);
137	137	m_i2cmem->write_scl(i2c_clk);
r245142	r245143
165	165	/* ??? weird ..*/
166	166	WRITE16_MEMBER(twins_state::porte_paloff0_w)
167	167	{
168		// printf("porte_paloff0_w %04x\n", data);
	168	// printf("porte_paloff0_w %04x\n", data);
169	169	m_paloff = 0;
170	170	}
171	171
r245142	r245143
205	205
206	206	if (m_spritesinit == 1)
207	207	{
208		// printf("spider_blitter_w %08x %04x %04x (init?) (base?)\n", offset * 2, data, mem_mask);
	208	// printf("spider_blitter_w %08x %04x %04x (init?) (base?)\n", offset * 2, data, mem_mask);
209	209
210	210	m_spritesinit = 2;
211	211	m_spritesaddr = offset;
212	212	}
213	213	else if (m_spritesinit == 2)
214	214	{
215		// printf("spider_blitter_w %08x %04x %04x (init2) (width?)\n", offset * 2, data, mem_mask);
	215	// printf("spider_blitter_w %08x %04x %04x (init2) (width?)\n", offset * 2, data, mem_mask);
216	216	m_spriteswidth = offset & 0xff;
217	217	if (m_spriteswidth == 0)
218	218	m_spriteswidth = 80;
r245142	r245143
234	234	{
235	235	UINT8 *src = m_rom8;
236	236
237		// printf("spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
	237	// printf("spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
238	238	offset &= 0x7fff;
239	239
240	240	for (int i = 0; i < m_spriteswidth; i++)
241	241	{
242	242	UINT8 data;
243
	243
244	244	data = (src[(m_spritesaddr * 2) + 1]);
245
	245
246	246	if (data)
247	247	vram[offset] = (vram[offset] & 0x00ff) \| data << 8;
248	248
249	249
250	250	data = src[(m_spritesaddr*2)];
251
	251
252	252	if (data)
253	253	vram[offset] = (vram[offset] & 0xff00) \| data;
254	254
255	255
256		m_spritesaddr ++;
	256	m_spritesaddr ++;
257	257	offset++;
258	258
259	259	offset &= 0x7fff;
r245142	r245143
386	386	MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 200-1)
387	387	MCFG_SCREEN_UPDATE_DRIVER(twins_state, screen_update_twins)
388	388	MCFG_SCREEN_PALETTE("palette")
389
	389
390	390	MCFG_24C02_ADD("i2cmem")
391	391
392	392	MCFG_PALETTE_ADD("palette", 0x100)
r245142	r245143
447	447	MCFG_PALETTE_ADD("palette", 256)
448	448	MCFG_RAMDAC_ADD("ramdac", ramdac_map, "palette")
449	449	MCFG_RAMDAC_SPLIT_READ(0)
450
	450
451	451	MCFG_24C02_ADD("i2cmem")
452	452
453	453	MCFG_VIDEO_START_OVERRIDE(twins_state,twinsa)
r245142	r245143
477	477	}
478	478	else
479	479	{
480		// printf("first palette write %04x\n", data);
	480	// printf("first palette write %04x\n", data);
481	481	}
482
	482
483	483	m_paloff++;
484	484
485	485	if (m_paloff == 0x101)
r245142	r245143
503	503	{
504	504	// done before the 'sprite' read / writes
505	505	// might clear a buffer?
506
	506
507	507	// game is only animating sprites at 30fps, maybe there's some double buffering too?
508	508
509	509	UINT16* vram;
r245142	r245143
575	575	MCFG_PALETTE_ADD("palette", 0x100)
576	576
577	577	MCFG_VIDEO_START_OVERRIDE(twins_state,twins)
578
	578
579	579	MCFG_24C02_ADD("i2cmem")
580	580
581	581	/* sound hardware */

trunk/src/mame/drivers/usgames.c
r245142	r245143
32	32
33	33	void usgames_state::machine_start()
34	34	{
35		membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x4000);
	35	membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x4000);
36	36	}
37	37
38	38	WRITE8_MEMBER(usgames_state::usgames_rombank_w)
39	39	{
40		membank("bank1")->set_entry(data);
	40	membank("bank1")->set_entry(data);
41	41	}
42	42
43	43	WRITE8_MEMBER(usgames_state::lamps1_w)

trunk/src/mame/drivers/vamphalf.c
r245142	r245143
2754	2754	m_semicom_prot_data[0] = 2;
2755	2755	m_semicom_prot_data[1] = 1;
2756	2756
2757		// UINT8 romx = (UINT8 )memregion("user1")->base();
	2757	// UINT8 romx = (UINT8 )memregion("user1")->base();
2758	2758	// prevent code dying after a trap 33 by patching it out, why?
2759		// romx[BYTE4_XOR_BE(0x8ff0)] = 3;
2760		// romx[BYTE4_XOR_BE(0x8ff1)] = 0;
	2759	// romx[BYTE4_XOR_BE(0x8ff0)] = 3;
	2760	// romx[BYTE4_XOR_BE(0x8ff1)] = 0;
2761	2761
2762	2762	// Configure the QS1000 ROM banking. Care must be taken not to overlap the 256b internal RAM
2763	2763	machine().device("qs1000:cpu")->memory().space(AS_IO).install_read_bank(0x0100, 0xffff, "data");

trunk/src/mame/drivers/vigilant.c
r245142	r245143
24	24
25	25	void vigilant_state::machine_start()
26	26	{
27		membank("bank1")->configure_entries(0, 8, memregion("maincpu")->base() + 0x10000, 0x4000);
	27	membank("bank1")->configure_entries(0, 8, memregion("maincpu")->base() + 0x10000, 0x4000);
28	28	}
29	29
30	30	WRITE8_MEMBER(vigilant_state::vigilant_bank_select_w)
31	31	{
32		membank("bank1")->set_entry(data & 0x07);
	32	membank("bank1")->set_entry(data & 0x07);
33	33	}
34	34
35	35	/***************************************************************************

trunk/src/mame/drivers/wc90b.c
r245142	r245143
325	325	membank("mainbank")->configure_entries(0, 32, memregion("maincpu")->base() + 0x10000, 0x800);
326	326	membank("subbank")->configure_entries(0, 32, memregion("sub")->base() + 0x10000, 0x800);
327	327	membank("audiobank")->configure_entries(0, 2, memregion("audiocpu")->base() + 0x8000, 0x4000);
328
	328
329	329	save_item(NAME(m_msm5205next));
330	330	save_item(NAME(m_toggle));
331	331	}

trunk/src/mame/drivers/xain.c
r245142	r245143
555	555	membank("bank2")->configure_entries(0, 2, memregion("sub")->base() + 0x4000, 0xc000);
556	556	membank("bank1")->set_entry(0);
557	557	membank("bank2")->set_entry(0);
558
	558
559	559	save_item(NAME(m_vblank));
560
	560
561	561	if (m_mcu)
562	562	{
563	563	save_item(NAME(m_from_main));

trunk/src/mame/drivers/xtheball.c
r245142	r245143
30	30
31	31	required_device<cpu_device> m_maincpu;
32	32	required_device<tlc34076_device> m_tlc34076;
33
	33
34	34	required_shared_ptr<UINT16> m_vram_bg;
35	35	required_shared_ptr<UINT16> m_vram_fg;
36
	36
37	37	required_ioport m_analog_x;
38	38	required_ioport m_analog_y;
39
	39
40	40	UINT8 m_bitvals[32];
41
	41
42	42	DECLARE_WRITE16_MEMBER(bit_controls_w);
43	43	DECLARE_READ16_MEMBER(analogx_r);
44	44	DECLARE_READ16_MEMBER(analogy_watchdog_r);
45
	45
46	46	virtual void machine_start();
47
	47
48	48	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
49	49	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
50	50	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);

trunk/src/mame/includes/argus.h
r245142	r245143
42	42	UINT8 m_bg_status;
43	43	UINT8 m_flipscreen;
44	44	UINT16 m_palette_intensity;
45
	45
46	46	// argus specific
47	47	UINT8 *m_dummy_bg0ram;
48	48	int m_lowbitscroll;
49	49	int m_prvscrollx;
50
	50
51	51	// butasan specific
52	52	UINT8 *m_butasan_txram;
53	53	UINT8 *m_butasan_bg0ram;
r245142	r245143
57	57	UINT8 m_butasan_page_latch;
58	58	UINT8 m_butasan_bg1_status;
59	59	UINT8 m_butasan_unknown;
60
	60
61	61	// valtric specific
62	62	UINT8 m_valtric_mosaic;
63	63	bitmap_rgb32 m_mosaicbitmap;
64	64	UINT8 m_valtric_unknown;
65	65	int m_mosaic;
66
	66
67	67	tilemap_t *m_tx_tilemap;
68	68	tilemap_t *m_bg0_tilemap;
69	69	tilemap_t *m_bg1_tilemap;
70
	70
71	71	// common
72	72	DECLARE_WRITE8_MEMBER(bankselect_w);
73	73	DECLARE_WRITE8_MEMBER(valtric_mosaic_w);
r245142	r245143
94	94	DECLARE_WRITE8_MEMBER(valtric_bg_status_w);
95	95	DECLARE_WRITE8_MEMBER(valtric_paletteram_w);
96	96	DECLARE_WRITE8_MEMBER(valtric_unknown_w);
97
	97
98	98	TILE_GET_INFO_MEMBER(argus_get_tx_tile_info);
99	99	TILE_GET_INFO_MEMBER(argus_get_bg0_tile_info);
100	100	TILE_GET_INFO_MEMBER(argus_get_bg1_tile_info);
r245142	r245143
103	103	TILE_GET_INFO_MEMBER(butasan_get_tx_tile_info);
104	104	TILE_GET_INFO_MEMBER(butasan_get_bg0_tile_info);
105	105	TILE_GET_INFO_MEMBER(butasan_get_bg1_tile_info);
106
	106
107	107	virtual void machine_start();
108	108	DECLARE_VIDEO_START(argus);
109	109	DECLARE_VIDEO_RESET(argus);
r245142	r245143
111	111	DECLARE_VIDEO_RESET(valtric);
112	112	DECLARE_VIDEO_START(butasan);
113	113	DECLARE_VIDEO_RESET(butasan);
114
	114
115	115	UINT32 screen_update_argus(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
116	116	UINT32 screen_update_valtric(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
117	117	UINT32 screen_update_butasan(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
118
	118
119	119	TIMER_DEVICE_CALLBACK_MEMBER(scanline);
120	120	TIMER_DEVICE_CALLBACK_MEMBER(butasan_scanline);
121
	121
122	122	void reset_common();
123	123	void change_palette(int color, int lo_offs, int hi_offs);
124	124	void change_bg_palette(int color, int lo_offs, int hi_offs);
125	125	void bg_setting();
126
	126
127	127	// argus specific
128	128	void argus_bg0_scroll_handle();
129	129	void argus_write_dummy_rams(int dramoffs, int vromoffs);
130	130	void argus_draw_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, int priority);
131
	131
132	132	// butasan specific
133	133	void butasan_draw_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect);
134	134	void butasan_log_vram();
135
	135
136	136	// valtric specific
137	137	void valtric_draw_mosaic(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
138	138	void valtric_draw_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect);

trunk/src/mame/includes/bbusters.h
r245142	r245143
23	23	required_device<gfxdecode_device> m_gfxdecode;
24	24	required_device<buffered_spriteram16_device> m_spriteram;
25	25	optional_device<buffered_spriteram16_device> m_spriteram2;
26
	26
27	27	optional_shared_ptr<UINT16> m_eprom_data;
28	28	required_shared_ptr<UINT16> m_ram;
29	29	required_shared_ptr<UINT16> m_videoram;
r245142	r245143
53	53	DECLARE_WRITE16_MEMBER(video_w);
54	54	DECLARE_WRITE16_MEMBER(pf1_w);
55	55	DECLARE_WRITE16_MEMBER(pf2_w);
56
	56
57	57	TILE_GET_INFO_MEMBER(get_tile_info);
58	58	TILE_GET_INFO_MEMBER(get_pf1_tile_info);
59	59	TILE_GET_INFO_MEMBER(get_pf2_tile_info);
60
	60
61	61	virtual void machine_start();
62	62	DECLARE_VIDEO_START(bbuster);
63	63	DECLARE_VIDEO_START(mechatt);
64
	64
65	65	UINT32 screen_update_bbuster(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
66	66	UINT32 screen_update_mechatt(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
67	67	void screen_eof_bbuster(screen_device &screen, bool state);

trunk/src/mame/includes/cabal.h
r245142	r245143
38	38	int m_sound_command1;
39	39	int m_sound_command2;
40	40	int m_last[4];
41
	41
42	42	// common
43	43	DECLARE_WRITE16_MEMBER(flipscreen_w);
44	44	DECLARE_WRITE16_MEMBER(background_videoram_w);
r245142	r245143
57	57	DECLARE_WRITE8_MEMBER(cabalbl_coin_w);
58	58	DECLARE_WRITE8_MEMBER(cabalbl_1_adpcm_w);
59	59	DECLARE_WRITE8_MEMBER(cabalbl_2_adpcm_w);
60
	60
61	61	DECLARE_DRIVER_INIT(cabal);
62	62	DECLARE_DRIVER_INIT(cabalbl2);
63	63	DECLARE_MACHINE_START(cabal);
64	64	DECLARE_MACHINE_START(cabalbl);
65	65	DECLARE_MACHINE_RESET(cabalbl);
66	66	virtual void video_start();
67
	67
68	68	TILE_GET_INFO_MEMBER(get_back_tile_info);
69	69	TILE_GET_INFO_MEMBER(get_text_tile_info);
70
	70
71	71	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
72	72	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
73
	73
74	74	void seibu_sound_bootleg(const char *cpu,int length);
75	75	};

trunk/src/mame/includes/capbowl.h
r245142	r245143
37	37
38	38	/* input-related */
39	39	UINT8 m_last_trackball_val[2];
40
	40
41	41	emu_timer *m_update_timer;
42	42
43	43	// common
r245142	r245143
47	47	DECLARE_WRITE8_MEMBER(sndcmd_w);
48	48	DECLARE_WRITE8_MEMBER(tms34061_w);
49	49	DECLARE_READ8_MEMBER(tms34061_r);
50
	50
51	51	// capbowl specific
52	52	DECLARE_WRITE8_MEMBER(capbowl_rom_select_w);
53
	53
54	54	// bowlrama specific
55	55	DECLARE_WRITE8_MEMBER(bowlrama_blitter_w);
56	56	DECLARE_READ8_MEMBER(bowlrama_blitter_r);
57
	57
58	58	DECLARE_DRIVER_INIT(capbowl);
59	59	virtual void machine_start();
60	60	virtual void machine_reset();
61
	61
62	62	INTERRUPT_GEN_MEMBER(interrupt);
63	63	TIMER_CALLBACK_MEMBER(update);
64
	64
65	65	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
66	66	inline rgb_t pen_for_pixel( UINT8 *src, UINT8 pix );
67	67

trunk/src/mame/includes/fgoal.h
r245142	r245143
15	15	m_gfxdecode(*this, "gfxdecode"),
16	16	m_screen(*this, "screen"),
17	17	m_palette(*this, "palette"),
18		m_video_ram(*this, "video_ram") { }
	18	m_video_ram(*this, "video_ram") { }
19	19
20	20	/* devices */
21	21	required_device<cpu_device> m_maincpu;
r245142	r245143
58	58	DECLARE_WRITE8_MEMBER(xpos_w);
59	59
60	60	DECLARE_CUSTOM_INPUT_MEMBER(_80_r);
61
	61
62	62	TIMER_CALLBACK_MEMBER(interrupt_callback);
63	63
64	64	virtual void machine_start();

trunk/src/mame/includes/hng64.h
r245142	r245143
125	125	m_generic_paletteram_32(*this, "paletteram")
126	126
127	127	{ }
128
	128
129	129	required_device<mips3_device> m_maincpu;
130	130	required_device<v53a_device> m_audiocpu;
131	131	required_device<cpu_device> m_comm;
r245142	r245143
363	363	DECLARE_WRITE_LINE_MEMBER(tcu_tm2_cb);
364	364
365	365	UINT16 m_audiochannel;
366
	366
367	367	struct hng64_48bit_data {
368	368	UINT16 dat[3];
369	369	};
r245142	r245143
395	395
396	396	DECLARE_WRITE16_MEMBER(hng64_sound_bank_w);
397	397	};
398

trunk/src/mame/includes/ironhors.h
r245142	r245143
48	48	DECLARE_WRITE8_MEMBER(flipscreen_w);
49	49	DECLARE_WRITE8_MEMBER(filter_w);
50	50	DECLARE_READ8_MEMBER(farwest_soundlatch_r);
51
	51
52	52	TILE_GET_INFO_MEMBER(get_bg_tile_info);
53	53	TILE_GET_INFO_MEMBER(farwest_get_bg_tile_info);
54
	54
55	55	virtual void machine_start();
56	56	virtual void machine_reset();
57	57	virtual void video_start();
58	58	DECLARE_PALETTE_INIT(ironhors);
59	59	DECLARE_VIDEO_START(farwest);
60
	60
61	61	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
62	62	UINT32 screen_update_farwest(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
63	63	void draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect );
64	64	void farwest_draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect );
65
	65
66	66	TIMER_DEVICE_CALLBACK_MEMBER(irq);
67	67	TIMER_DEVICE_CALLBACK_MEMBER(farwest_irq);
68	68	};

trunk/src/mame/includes/mosaic.h
r245142	r245143
17	17	/* devices */
18	18	required_device<cpu_device> m_maincpu;
19	19	required_device<gfxdecode_device> m_gfxdecode;
20
	20
21	21	/* memory pointers */
22	22	required_shared_ptr<UINT8> m_fgvideoram;
23	23	required_shared_ptr<UINT8> m_bgvideoram;
r245142	r245143
28	28
29	29	/* misc */
30	30	int m_prot_val;
31
	31
32	32	DECLARE_WRITE8_MEMBER(protection_w);
33	33	DECLARE_READ8_MEMBER(protection_r);
34	34	DECLARE_WRITE8_MEMBER(gfire2_protection_w);
35	35	DECLARE_READ8_MEMBER(gfire2_protection_r);
36	36	DECLARE_WRITE8_MEMBER(fgvideoram_w);
37	37	DECLARE_WRITE8_MEMBER(bgvideoram_w);
38
	38
39	39	TILE_GET_INFO_MEMBER(get_fg_tile_info);
40	40	TILE_GET_INFO_MEMBER(get_bg_tile_info);
41
	41
42	42	virtual void machine_start();
43	43	virtual void machine_reset();
44	44	virtual void video_start();
45
	45
46	46	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
47	47	};

trunk/src/mame/includes/paradise.h
r245142	r245143
54	54	DECLARE_WRITE8_MEMBER(vram_2_w);
55	55	DECLARE_WRITE8_MEMBER(pixmap_w);
56	56	DECLARE_WRITE8_MEMBER(priority_w);
57
	57
58	58	// paradise specific
59	59	DECLARE_WRITE8_MEMBER(paradise_okibank_w);
60
	60
61	61	// torus specific
62	62	DECLARE_WRITE8_MEMBER(torus_coin_counter_w);
63	63

trunk/src/mame/includes/pooyan.h
r245142	r245143
32	32	DECLARE_WRITE8_MEMBER(videoram_w);
33	33	DECLARE_WRITE8_MEMBER(colorram_w);
34	34	DECLARE_WRITE8_MEMBER(flipscreen_w);
35
	35
36	36	TILE_GET_INFO_MEMBER(get_bg_tile_info);
37
	37
38	38	virtual void machine_start();
39	39	virtual void machine_reset();
40	40	virtual void video_start();
41	41	DECLARE_PALETTE_INIT(pooyan);
42
	42
43	43	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
44	44	void draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect );
45
	45
46	46	INTERRUPT_GEN_MEMBER(interrupt);
47	47	};

trunk/src/mame/includes/psychic5.h
r245142	r245143
21	21	m_ps5_palette_ram_tx(*this, "palette_ram_tx")
22	22
23	23	{ }
24
	24
25	25	required_device<cpu_device> m_maincpu;
26	26	required_device<cpu_device> m_audiocpu;
27	27	required_device<gfxdecode_device> m_gfxdecode;
28	28	required_device<palette_device> m_palette;
29	29	optional_device<address_map_bank_device> m_vrambank;
30	30	optional_device<jaleco_blend_device> m_blend;
31
	31
32	32	required_shared_ptr<UINT8> m_spriteram;
33	33	required_shared_ptr<UINT8> m_fg_videoram;
34	34	required_shared_ptr<UINT8> m_bg_videoram;
r245142	r245143
78	78	DECLARE_VIDEO_START(psychic5);
79	79	DECLARE_VIDEO_START(bombsa);
80	80	DECLARE_VIDEO_RESET(psychic5);
81
	81
82	82	TIMER_DEVICE_CALLBACK_MEMBER(scanline);
83	83
84	84	UINT32 screen_update_psychic5(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);

trunk/src/mame/includes/realbrk.h
r245142	r245143
71	71	UINT32 screen_update_dai2kaku(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
72	72	void draw_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect);
73	73	void dai2kaku_draw_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect, int layer);
74
	74
75	75	INTERRUPT_GEN_MEMBER(interrupt);
76	76	};

trunk/src/mame/includes/rltennis.h
r245142	r245143
18	18	required_device<cpu_device> m_maincpu;
19	19	required_device<dac_device> m_dac_1;
20	20	required_device<dac_device> m_dac_2;
21
	21
22	22	UINT16 m_blitter[RLT_NUM_BLITTER_REGS];
23	23	INT32 m_data760000;
24	24	INT32 m_data740000;
r245142	r245143
41	41	virtual void machine_start();
42	42	virtual void machine_reset();
43	43	virtual void video_start();
44
	44
45	45	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
46	46
47	47	INTERRUPT_GEN_MEMBER(interrupt);

trunk/src/mame/includes/seta2.h
r245142	r245143
28	28	required_device<gfxdecode_device> m_gfxdecode;
29	29	required_device<screen_device> m_screen;
30	30	required_device<palette_device> m_palette;
31
	31
32	32	optional_shared_ptr<UINT16> m_nvram;
33	33	optional_shared_ptr<UINT16> m_spriteram;
34	34	optional_shared_ptr<UINT16> m_vregs;
r245142	r245143
39	39	int m_yoffset;
40	40	int m_keyboard_row;
41	41	UINT16 *m_buffered_spriteram;
42
	42
43	43	UINT64 m_funcube_coin_start_cycles;
44	44	UINT8 m_funcube_hopper_motor;
45	45

trunk/src/mame/includes/shuuz.h
r245142	r245143
19	19	required_device<atari_vad_device> m_vad;
20	20
21	21	int m_cur[2];
22
	22
23	23	virtual void update_interrupts();
24
	24
25	25	DECLARE_WRITE16_MEMBER(latch_w);
26	26	DECLARE_READ16_MEMBER(leta_r);
27	27	DECLARE_READ16_MEMBER(special_port0_r);
28
	28
29	29	virtual void machine_start();
30
	30
31	31	TILE_GET_INFO_MEMBER(get_playfield_tile_info);
32
	32
33	33	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
34	34
35	35	static const atari_motion_objects_config s_mob_config;

trunk/src/mame/includes/sidearms.h
r245142	r245143
54	54	DECLARE_WRITE8_MEMBER(gfxctrl_w);
55	55	DECLARE_WRITE8_MEMBER(star_scrollx_w);
56	56	DECLARE_WRITE8_MEMBER(star_scrolly_w);
57
	57
58	58	DECLARE_READ8_MEMBER(turtship_ports_r);
59
	59
60	60	DECLARE_WRITE8_MEMBER(whizz_bankswitch_w);
61	61
62	62	DECLARE_DRIVER_INIT(dyger);
r245142	r245143
64	64	DECLARE_DRIVER_INIT(whizz);
65	65	DECLARE_DRIVER_INIT(turtship);
66	66	virtual void machine_start();
67		virtual void video_start();
	67	virtual void video_start();
68	68
69	69	TILE_GET_INFO_MEMBER(get_sidearms_bg_tile_info);
70	70	TILE_GET_INFO_MEMBER(get_philko_bg_tile_info);

trunk/src/mame/includes/simple_st0016.h
r245142	r245143
12	12	{ }
13	13
14	14	int mux_port;
15		// UINT32 m_st0016_rom_bank;
	15	// UINT32 m_st0016_rom_bank;
16	16
17	17	optional_device<st0016_cpu_device> m_maincpu;
18	18	DECLARE_READ8_MEMBER(mux_r);
r245142	r245143
27	27	DECLARE_DRIVER_INIT(mayjinsn);
28	28	DECLARE_DRIVER_INIT(mayjisn2);
29	29	DECLARE_DRIVER_INIT(renju);
30		virtual void machine_start();
	30	virtual void machine_start();
31	31	DECLARE_VIDEO_START(st0016);
32	32	void st0016_draw_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
33	33	UINT32 screen_update_st0016(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

trunk/src/mame/includes/speedbal.h
r245142	r245143
39	39
40	40	TILE_GET_INFO_MEMBER(get_tile_info_bg);
41	41	TILE_GET_INFO_MEMBER(get_tile_info_fg);
42
	42
43	43	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
44	44	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
45	45	};

trunk/src/mame/includes/srmp2.h
r245142	r245143
21	21	required_device<cpu_device> m_maincpu;
22	22	required_device<seta001_device> m_seta001;
23	23	required_device<msm5205_device> m_msm;
24
	24
25	25	int m_color_bank;
26	26	int m_gfx_bank;
27	27	int m_adpcm_bank;
r245142	r245143
43	43	DECLARE_WRITE16_MEMBER(mjyuugi_adpcm_bank_w);
44	44	DECLARE_READ8_MEMBER(mjyuugi_irq2_ack_r);
45	45	DECLARE_READ8_MEMBER(mjyuugi_irq4_ack_r);
46
	46
47	47	// rmgoldyh
48	48	DECLARE_WRITE8_MEMBER(rmgoldyh_rombank_w);
49	49

trunk/src/mame/includes/srumbler.h
r245142	r245143
29	29	DECLARE_WRITE8_MEMBER(background_w);
30	30	DECLARE_WRITE8_MEMBER(_4009_w);
31	31	DECLARE_WRITE8_MEMBER(scroll_w);
32
	32
33	33	TILE_GET_INFO_MEMBER(get_fg_tile_info);
34	34	TILE_GET_INFO_MEMBER(get_bg_tile_info);
35
	35
36	36	virtual void machine_start();
37	37	virtual void video_start();
38
	38
39	39	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
40	40	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
41
	41
42	42	TIMER_DEVICE_CALLBACK_MEMBER(interrupt);
43	43	};

trunk/src/mame/includes/ssozumo.h
r245142	r245143
29	29	tilemap_t *m_bg_tilemap;
30	30	tilemap_t *m_fg_tilemap;
31	31	UINT8 m_sound_nmi_mask;
32
	32
33	33	DECLARE_WRITE8_MEMBER(sh_command_w);
34	34	DECLARE_WRITE8_MEMBER(sound_nmi_mask_w);
35	35	DECLARE_WRITE8_MEMBER(videoram_w);
r245142	r245143
39	39	DECLARE_WRITE8_MEMBER(paletteram_w);
40	40	DECLARE_WRITE8_MEMBER(scroll_w);
41	41	DECLARE_WRITE8_MEMBER(flipscreen_w);
42
	42
43	43	DECLARE_INPUT_CHANGED_MEMBER(coin_inserted);
44
	44
45	45	INTERRUPT_GEN_MEMBER(sound_timer_irq);
46
	46
47	47	TILE_GET_INFO_MEMBER(get_bg_tile_info);
48	48	TILE_GET_INFO_MEMBER(get_fg_tile_info);
49
	49
50	50	virtual void machine_start();
51	51	virtual void video_start();
52	52	DECLARE_PALETTE_INIT(ssozumo);
53
	53
54	54	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
55	55	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
56	56	};

trunk/src/mame/includes/ssrj.h
r245142	r245143
27	27	tilemap_t *m_tilemap2;
28	28	tilemap_t *m_tilemap4;
29	29	UINT8 *m_buffer_spriteram;
30
	30
31	31	DECLARE_READ8_MEMBER(wheel_r);
32	32	DECLARE_WRITE8_MEMBER(vram1_w);
33	33	DECLARE_WRITE8_MEMBER(vram2_w);
34	34	DECLARE_WRITE8_MEMBER(vram4_w);
35
	35
36	36	TILE_GET_INFO_MEMBER(get_tile_info1);
37	37	TILE_GET_INFO_MEMBER(get_tile_info2);
38	38	TILE_GET_INFO_MEMBER(get_tile_info4);
39
	39
40	40	virtual void machine_start();
41	41	virtual void machine_reset();
42	42	virtual void video_start();
43	43	DECLARE_PALETTE_INIT(ssrj);
44
	44
45	45	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
46	46	void screen_eof(screen_device &screen, bool state);
47	47	void draw_objects(bitmap_ind16 &bitmap, const rectangle &cliprect );

trunk/src/mame/includes/ssv.h
r245142	r245143
106	106	DECLARE_WRITE16_MEMBER(scroll_w);
107	107	DECLARE_READ16_MEMBER(gdfs_eeprom_r);
108	108	DECLARE_WRITE16_MEMBER(gdfs_eeprom_w);
109
	109
110	110	TILE_GET_INFO_MEMBER(get_tile_info_0);
111
	111
112	112	DECLARE_DRIVER_INIT(gdfs);
113	113	DECLARE_DRIVER_INIT(sxyreac2);
114	114	DECLARE_DRIVER_INIT(hypreac2);
r245142	r245143
135	135	virtual void video_start();
136	136	DECLARE_VIDEO_START(gdfs);
137	137	DECLARE_VIDEO_START(eaglshot);
138
	138
139	139	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
140	140	UINT32 screen_update_gdfs(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
141	141	UINT32 screen_update_eaglshot(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
142
	142
143	143	TIMER_DEVICE_CALLBACK_MEMBER(interrupt);
144	144	TIMER_DEVICE_CALLBACK_MEMBER(gdfs_interrupt);
145	145	void update_irq_state();
146	146	IRQ_CALLBACK_MEMBER(irq_callback);
147
	147
148	148	void drawgfx(bitmap_ind16 &bitmap, const rectangle &cliprect, gfx_element *gfx,UINT32 code,UINT32 color,int flipx,int flipy,int x0,int y0,int shadow);
149	149	void draw_row(bitmap_ind16 &bitmap, const rectangle &cliprect, int sx, int sy, int scroll);
150	150	void draw_layer(bitmap_ind16 &bitmap, const rectangle &cliprect, int nr);

trunk/src/mame/includes/subs.h
r245142	r245143
42	42	int m_steering_val2;
43	43	int m_last_val_1;
44	44	int m_last_val_2;
45
	45
46	46	DECLARE_WRITE8_MEMBER(steer_reset_w);
47	47	DECLARE_READ8_MEMBER(control_r);
48	48	DECLARE_READ8_MEMBER(coin_r);
r245142	r245143
56	56	DECLARE_WRITE8_MEMBER(crash_w);
57	57	DECLARE_WRITE8_MEMBER(explode_w);
58	58	DECLARE_WRITE8_MEMBER(noise_reset_w);
59
	59
60	60	virtual void machine_start();
61	61	virtual void machine_reset();
62	62	DECLARE_PALETTE_INIT(subs);
63
	63
64	64	UINT32 screen_update_left(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
65	65	UINT32 screen_update_right(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
66
	66
67	67	INTERRUPT_GEN_MEMBER(interrupt);
68
	68
69	69	int steering_1();
70	70	int steering_2();
71	71	};

trunk/src/mame/includes/suna16.h
r245142	r245143
40	40	DECLARE_WRITE16_MEMBER(flipscreen_w);
41	41	DECLARE_WRITE8_MEMBER(DAC1_w);
42	42	DECLARE_WRITE8_MEMBER(DAC2_w);
43
	43
44	44	// bestbest specific
45	45	DECLARE_WRITE16_MEMBER(bestbest_flipscreen_w);
46	46	DECLARE_WRITE16_MEMBER(bestbest_coin_w);
r245142	r245143
54	54	DECLARE_WRITE8_MEMBER(bssoccer_pcm_2_bankswitch_w);
55	55	DECLARE_WRITE8_MEMBER(bssoccer_DAC3_w);
56	56	DECLARE_WRITE8_MEMBER(bssoccer_DAC4_w);
57
	57
58	58	// uballoon specific
59	59	DECLARE_WRITE16_MEMBER(uballoon_leds_w);
60	60	DECLARE_WRITE8_MEMBER(uballoon_pcm_1_bankswitch_w);
61	61	DECLARE_READ8_MEMBER(uballoon_prot_r);
62	62	DECLARE_WRITE8_MEMBER(uballoon_prot_w);
63
	63
64	64	TIMER_DEVICE_CALLBACK_MEMBER(bssoccer_interrupt);
65
	65
66	66	DECLARE_DRIVER_INIT(uballoon);
67	67	virtual void video_start();
68	68	DECLARE_MACHINE_START(bestbest);
69	69	DECLARE_MACHINE_START(bssoccer);
70		DECLARE_MACHINE_START(uballoon);
	70	DECLARE_MACHINE_START(uballoon);
71	71	DECLARE_MACHINE_RESET(uballoon);
72
	72
73	73	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
74	74	UINT32 screen_update_bestbest(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
75	75	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16 *sprites, int gfx);

trunk/src/mame/includes/suprloco.h
r245142	r245143
9	9	m_spriteram(*this, "spriteram"),
10	10	m_videoram(*this, "videoram"),
11	11	m_scrollram(*this, "scrollram") { }
12
	12
13	13	required_device<cpu_device> m_maincpu;
14	14	required_device<cpu_device> m_audiocpu;
15	15	required_device<gfxdecode_device> m_gfxdecode;
r245142	r245143
17	17	required_shared_ptr<UINT8> m_spriteram;
18	18	required_shared_ptr<UINT8> m_videoram;
19	19	required_shared_ptr<UINT8> m_scrollram;
20
	20
21	21	tilemap_t *m_bg_tilemap;
22	22	int m_control;
23	23
r245142	r245143
26	26	DECLARE_WRITE8_MEMBER(scrollram_w);
27	27	DECLARE_WRITE8_MEMBER(control_w);
28	28	DECLARE_READ8_MEMBER(control_r);
29
	29
30	30	TILE_GET_INFO_MEMBER(get_tile_info);
31
	31
32	32	virtual void video_start();
33	33	DECLARE_PALETTE_INIT(suprloco);
34	34	DECLARE_DRIVER_INIT(suprloco);
35
	35
36	36	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
37	37	inline void draw_pixel(bitmap_ind16 &bitmap,const rectangle &cliprect,int x,int y,int color,int flip);
38	38	void draw_sprite(bitmap_ind16 &bitmap,const rectangle &cliprect,int spr_number);

trunk/src/mame/includes/suprridr.h
r245142	r245143
35	35	tilemap_t *m_bg_tilemap_noscroll;
36	36	UINT8 m_flipx;
37	37	UINT8 m_flipy;
38
	38
39	39	DECLARE_WRITE8_MEMBER(nmi_enable_w);
40	40	DECLARE_WRITE8_MEMBER(sound_data_w);
41	41	DECLARE_WRITE8_MEMBER(sound_irq_ack_w);
r245142	r245143
48	48	DECLARE_WRITE8_MEMBER(bgram_w);
49	49	DECLARE_WRITE8_MEMBER(fgram_w);
50	50	DECLARE_READ8_MEMBER(sound_data_r);
51
	51
52	52	DECLARE_CUSTOM_INPUT_MEMBER(control_r);
53
	53
54	54	TILE_GET_INFO_MEMBER(get_tile_info);
55	55	TILE_GET_INFO_MEMBER(get_tile_info2);
56
	56
57	57	INTERRUPT_GEN_MEMBER(main_nmi_gen);
58	58	TIMER_CALLBACK_MEMBER(delayed_sound_w);
59
	59
60	60	virtual void machine_start();
61	61	virtual void video_start();
62	62	DECLARE_PALETTE_INIT(suprridr);
63
	63
64	64	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
65	65	int is_screen_flipped();
66	66	};

trunk/src/mame/includes/tankbatt.h
r245142	r245143
18	18
19	19	required_shared_ptr<UINT8> m_bulletsram;
20	20	required_shared_ptr<UINT8> m_videoram;
21
	21
22	22	int m_nmi_enable;
23	23	int m_sound_enable;
24	24	tilemap_t *m_bg_tilemap;
25
	25
26	26	DECLARE_WRITE8_MEMBER(led_w);
27	27	DECLARE_READ8_MEMBER(in0_r);
28	28	DECLARE_READ8_MEMBER(in1_r);
r245142	r245143
36	36	DECLARE_WRITE8_MEMBER(coincounter_w);
37	37	DECLARE_WRITE8_MEMBER(coinlockout_w);
38	38	DECLARE_WRITE8_MEMBER(videoram_w);
39
40
	39
	40
41	41	INTERRUPT_GEN_MEMBER(interrupt);
42	42	DECLARE_INPUT_CHANGED_MEMBER(coin_inserted);
43
	43
44	44	TILE_GET_INFO_MEMBER(get_bg_tile_info);
45
	45
46	46	virtual void machine_start();
47	47	virtual void video_start();
48	48	DECLARE_PALETTE_INIT(tankbatt);
49
	49
50	50	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
51	51	void draw_bullets(bitmap_ind16 &bitmap, const rectangle &cliprect);
52	52	};

trunk/src/mame/includes/tankbust.h
r245142	r245143
31	31	UINT8 m_xscroll[2];
32	32	UINT8 m_yscroll[2];
33	33	UINT8 m_irq_mask;
34
	34
35	35	DECLARE_WRITE8_MEMBER(soundlatch_w);
36	36	DECLARE_WRITE8_MEMBER(e0xx_w);
37	37	DECLARE_READ8_MEMBER(debug_output_area_r);
r245142	r245143
44	44	DECLARE_WRITE8_MEMBER(yscroll_w);
45	45	DECLARE_READ8_MEMBER(soundlatch_r);
46	46	DECLARE_READ8_MEMBER(soundtimer_r);
47
	47
48	48	TILE_GET_INFO_MEMBER(get_bg_tile_info);
49	49	TILE_GET_INFO_MEMBER(get_txt_tile_info);
50
51		virtual void machine_start();
52		virtual void machine_reset();
	50
	51	virtual void machine_start();
	52	virtual void machine_reset();
53	53	virtual void video_start();
54	54	DECLARE_PALETTE_INIT(tankbust);
55
	55
56	56	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
57	57	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
58
	58
59	59	INTERRUPT_GEN_MEMBER(vblank_irq);
60	60	TIMER_CALLBACK_MEMBER(soundlatch_callback);
61	61	TIMER_CALLBACK_MEMBER(soundirqline_callback);

trunk/src/mame/includes/taotaido.h
r245142	r245143
21	21	required_shared_ptr<UINT16> m_spriteram2;
22	22	required_shared_ptr<UINT16> m_scrollram;
23	23	required_shared_ptr<UINT16> m_bgram;
24
	24
25	25	int m_pending_command;
26	26	UINT16 m_sprite_character_bank_select[8];
27	27	UINT16 m_video_bank_select[8];
r245142	r245143
30	30	UINT16 *m_spriteram_older;
31	31	UINT16 *m_spriteram2_old;
32	32	UINT16 *m_spriteram2_older;
33
	33
34	34	DECLARE_READ16_MEMBER(pending_command_r);
35	35	DECLARE_WRITE16_MEMBER(sound_command_w);
36	36	DECLARE_WRITE8_MEMBER(pending_command_clear_w);
r245142	r245143
38	38	DECLARE_WRITE16_MEMBER(sprite_character_bank_select_w);
39	39	DECLARE_WRITE16_MEMBER(tileregs_w);
40	40	DECLARE_WRITE16_MEMBER(bgvideoram_w);
41
	41
42	42	TILE_GET_INFO_MEMBER(bg_tile_info);
43	43	TILEMAP_MAPPER_MEMBER(tilemap_scan_rows);
44
	44
45	45	virtual void machine_start();
46	46	virtual void video_start();
47
	47
48	48	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
49	49	void screen_eof(screen_device &screen, bool state);
50	50	UINT32 tile_callback( UINT32 code );

trunk/src/mame/includes/tbowl.h
r245142	r245143
62	62	DECLARE_WRITE8_MEMBER(bg2xscroll_hi);
63	63	DECLARE_WRITE8_MEMBER(bg2yscroll_lo);
64	64	DECLARE_WRITE8_MEMBER(bg2yscroll_hi);
65
	65
66	66	TILE_GET_INFO_MEMBER(get_tx_tile_info);
67	67	TILE_GET_INFO_MEMBER(get_bg_tile_info);
68	68	TILE_GET_INFO_MEMBER(get_bg2_tile_info);
69
	69
70	70	virtual void machine_start();
71	71	virtual void machine_reset();
72	72	virtual void video_start();
73
	73
74	74	UINT32 screen_update_left(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
75	75	UINT32 screen_update_right(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
76
	76
77	77	void adpcm_int(msm5205_device *device, int chip);
78	78	DECLARE_WRITE_LINE_MEMBER(adpcm_int_1);
79	79	DECLARE_WRITE_LINE_MEMBER(adpcm_int_2);

trunk/src/mame/includes/thunderx.h
r245142	r245143
62	62
63	63	virtual void machine_start();
64	64	virtual void machine_reset();
65		virtual void video_start();
	65	virtual void video_start();
66	66
67	67	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
68	68	INTERRUPT_GEN_MEMBER(vblank_interrupt);

trunk/src/mame/includes/timelimt.h
r245142	r245143
33	33	DECLARE_WRITE8_MEMBER(scroll_x_lsb_w);
34	34	DECLARE_WRITE8_MEMBER(scroll_x_msb_w);
35	35	DECLARE_WRITE8_MEMBER(scroll_y_w);
36
	36
37	37	TILE_GET_INFO_MEMBER(get_bg_tile_info);
38	38	TILE_GET_INFO_MEMBER(get_fg_tile_info);
39
	39
40	40	virtual void machine_start();
41	41	virtual void machine_reset();
42	42	virtual void video_start();
43	43	DECLARE_PALETTE_INIT(timelimt);
44
	44
45	45	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
46	46	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
47
	47
48	48	INTERRUPT_GEN_MEMBER(irq);
49	49	};

trunk/src/mame/includes/tryout.h
r245142	r245143
27	27	UINT8 m_vram_bank;
28	28	UINT8 *m_vram;
29	29	UINT8 *m_vram_gfx;
30
	30
31	31	DECLARE_WRITE8_MEMBER(nmi_ack_w);
32	32	DECLARE_WRITE8_MEMBER(sound_w);
33	33	DECLARE_WRITE8_MEMBER(sound_irq_ack_w);
r245142	r245143
45	45	TILEMAP_MAPPER_MEMBER(get_fg_memory_offset);
46	46	TILEMAP_MAPPER_MEMBER(get_bg_memory_offset);
47	47
48		virtual void machine_start();
49		virtual void video_start();
	48	virtual void machine_start();
	49	virtual void video_start();
50	50	DECLARE_PALETTE_INIT(tryout);
51	51
52	52	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

trunk/src/mame/includes/tsamurai.h
r245142	r245143
28	28
29	29	tilemap_t *m_background;
30	30	tilemap_t *m_foreground;
31
	31
32	32	//common
33	33	int m_flicker;
34	34	int m_textbank1;
35	35	int m_nmi_enabled;
36
	36
37	37	// tsamurai and m660 specific
38	38	int m_bgcolor;
39	39	int m_sound_command1;
40	40	int m_sound_command2;
41
	41
42	42	//m660 specific
43	43	int m_textbank2;
44	44	int m_sound_command3;
45
	45
46	46	//vsgongf specific
47	47	int m_vsgongf_sound_nmi_enabled;
48	48	int m_vsgongf_color;
49	49	int m_key_count; //debug only
50
	50
51	51	// common
52	52	DECLARE_WRITE8_MEMBER(nmi_enable_w);
53	53	DECLARE_WRITE8_MEMBER(coincounter_w);
r245142	r245143
68	68	DECLARE_WRITE8_MEMBER(sound_command2_w);
69	69	DECLARE_READ8_MEMBER(sound_command1_r);
70	70	DECLARE_READ8_MEMBER(sound_command2_r);
71
	71
72	72	// tsamurai specific
73	73	DECLARE_READ8_MEMBER(tsamurai_unknown_d803_r);
74
	74
75	75	// m660 specific
76	76	DECLARE_WRITE8_MEMBER(m660_textbank2_w);
77	77	DECLARE_READ8_MEMBER(m660_unknown_d803_r);
78	78	DECLARE_WRITE8_MEMBER(m660_sound_command3_w);
79	79	DECLARE_READ8_MEMBER(m660_sound_command3_r);
80
	80
81	81	// vsgongf specific
82	82	DECLARE_WRITE8_MEMBER(vsgongf_color_w);
83	83	DECLARE_WRITE8_MEMBER(vsgongf_sound_nmi_enable_w);
84	84	DECLARE_READ8_MEMBER(vsgongf_a006_r);
85	85	DECLARE_READ8_MEMBER(vsgongf_a100_r);
86	86	DECLARE_WRITE8_MEMBER(vsgongf_sound_command_w);
87
	87
88	88	TILE_GET_INFO_MEMBER(get_bg_tile_info);
89	89	TILE_GET_INFO_MEMBER(get_fg_tile_info);
90	90	TILE_GET_INFO_MEMBER(get_vsgongf_tile_info);
91
	91
92	92	virtual void machine_start();
93	93	DECLARE_MACHINE_START(m660);
94	94	DECLARE_MACHINE_START(tsamurai);
r245142	r245143
97	97	DECLARE_VIDEO_START(m660);
98	98	DECLARE_VIDEO_START(tsamurai);
99	99	DECLARE_VIDEO_START(vsgongf);
100
	100
101	101	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
102	102	UINT32 screen_update_vsgongf(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
103	103	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect );
104
	104
105	105	INTERRUPT_GEN_MEMBER(interrupt);
106	106	INTERRUPT_GEN_MEMBER(vsgongf_sound_interrupt);
107	107	};

trunk/src/mame/includes/usgames.h
r245142	r245143
17	17	DECLARE_WRITE8_MEMBER(usgames_videoram_w);
18	18	DECLARE_WRITE8_MEMBER(usgames_charram_w);
19	19	TILE_GET_INFO_MEMBER(get_usgames_tile_info);
20		virtual void machine_start();
21		virtual void video_start();
	20	virtual void machine_start();
	21	virtual void video_start();
22	22	DECLARE_PALETTE_INIT(usgames);
23	23	UINT32 screen_update_usgames(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
24	24	required_device<cpu_device> m_maincpu;

trunk/src/mame/includes/vigilant.h
r245142	r245143
38	38	DECLARE_WRITE8_MEMBER(vigilant_horiz_scroll_w);
39	39	DECLARE_WRITE8_MEMBER(vigilant_rear_horiz_scroll_w);
40	40	DECLARE_WRITE8_MEMBER(vigilant_rear_color_w);
41		virtual void machine_start();
42		virtual void video_start();
	41	virtual void machine_start();
	42	virtual void video_start();
43	43	virtual void video_reset();
44	44	UINT32 screen_update_vigilant(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
45	45	UINT32 screen_update_kikcubic(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

trunk/src/mame/includes/vulgus.h
r245142	r245143
48	48
49	49	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
50	50	void draw_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect);
51
	51
52	52	INTERRUPT_GEN_MEMBER(vblank_irq);
53	53	};

trunk/src/mame/includes/wc90b.h
r245142	r245143
51	51	DECLARE_WRITE8_MEMBER(txvideoram_w);
52	52	DECLARE_WRITE8_MEMBER(adpcm_control_w);
53	53	DECLARE_WRITE_LINE_MEMBER(adpcm_int);
54
	54
55	55	TILE_GET_INFO_MEMBER(get_bg_tile_info);
56	56	TILE_GET_INFO_MEMBER(get_fg_tile_info);
57	57	TILE_GET_INFO_MEMBER(get_tx_tile_info);
58
	58
59	59	virtual void machine_start();
60	60	virtual void video_start();
61
	61
62	62	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
63	63	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, int priority );
64	64	};

trunk/src/mame/machine/hng64_net.c
r245142	r245143
141	141	MCFG_CPU_ADD("network", KL5C80A12, HNG64_MASTER_CLOCK / 4) /* KL5C80A12CFP - binary compatible with Z80. */
142	142	MCFG_CPU_PROGRAM_MAP(hng_comm_map)
143	143	MCFG_CPU_IO_MAP(hng_comm_io_map)
144		MACHINE_CONFIG_END
		No newline at end of file
	144	MACHINE_CONFIG_END

trunk/src/mame/machine/iteagle_fpga.c
r245142	r245143
35	35
36	36	add_map(sizeof(m_ctrl_regs), M_IO, FUNC(iteagle_fpga_device::ctrl_map));
37	37	// ctrl defaults to base address 0x00000000
38		bank_infos[0].adr = 0x00000000 & (~(bank_infos[0].size - 1));
	38	bank_infos[0].adr = 0x00000000 & (~(bank_infos[0].size - 1));
39	39
40	40	add_map(sizeof(m_fpga_regs), M_IO, FUNC(iteagle_fpga_device::fpga_map));
41	41	// fpga defaults to base address 0x00000300
42		bank_infos[1].adr = 0x00000300 & (~(bank_infos[1].size - 1));
	42	bank_infos[1].adr = 0x00000300 & (~(bank_infos[1].size - 1));
43	43
44	44	add_map(sizeof(m_rtc_regs), M_MEM, FUNC(iteagle_fpga_device::rtc_map));
45	45	// RTC defaults to base address 0x000c0000
46		bank_infos[2].adr = 0x000c0000 & (~(bank_infos[2].size - 1));
	46	bank_infos[2].adr = 0x000c0000 & (~(bank_infos[2].size - 1));
47	47	}
48	48
49	49	void iteagle_fpga_device::device_reset()
r245142	r245143
106	106	if (LOG_FPGA && (m_prev_reg != offset && m_prev_reg != (0x08/4)))
107	107	logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
108	108	break;
109		case 0x04/4:
	109	case 0x04/4:
110	110	result = (result & 0xFF0FFFFF) \| (machine().root_device().ioport("SW5")->read()<<20); // Resolution
111	111	if (LOG_FPGA)
112	112	logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
r245142	r245143
183	183
184	184	COMBINE_DATA(&m_rtc_regs[offset]);
185	185	switch (offset) {
186		case 0x7F8/4: // M48T02 time
	186	case 0x7F8/4: // M48T02 time
187	187	if (data & mem_mask & 0x40) {
188	188	// get the current date/time from the core
189	189	machine().current_datetime(systime);
r245142	r245143
191	191	raw[1] = dec_2_bcd(systime.local_time.second);
192	192	raw[2] = dec_2_bcd(systime.local_time.minute);
193	193	raw[3] = dec_2_bcd(systime.local_time.hour);
194
	194
195	195	raw[4] = dec_2_bcd((systime.local_time.weekday != 0) ? systime.local_time.weekday : 7);
196	196	raw[5] = dec_2_bcd(systime.local_time.mday);
197	197	raw[6] = dec_2_bcd(systime.local_time.month + 1);
r245142	r245143
199	199	m_rtc_regs[0x7F8/4] = (raw[3]<<24) \| (raw[2]<<16) \| (raw[1]<<8) \| (raw[0] <<0);
200	200	//m_rtc_regs[0x7FC/4] = (raw[7]<<24) \| (raw[6]<<16) \| (raw[5]<<8) \| (raw[4] <<0);
201	201	m_rtc_regs[0x7FC/4] = (0x95<<24) \| (raw[6]<<16) \| (raw[5]<<8) \| (raw[4] <<0);
202		}
	202	}
203	203	if (LOG_RTC)
204	204	logerror("%s:RTC write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
205
	205
206	206	break;
207	207	default:
208	208	if (LOG_RTC)
r245142	r245143
249	249	pci_device::device_reset();
250	250	}
251	251
252		READ32_MEMBER( iteagle_eeprom_device::eeprom_r )
	252	READ32_MEMBER( iteagle_eeprom_device::eeprom_r )
253	253	{
254	254	UINT32 result = 0;
255	255
r245142	r245143
257	257	case 0xC/4: // I2C Handler
258	258	if (ACCESSING_BITS_16_23) {
259	259	result = m_eeprom->do_read()<<(16+3);
260		} else {
	260	} else {
261	261	if (LOG_EEPROM)
262	262	logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
263	263	}
r245142	r245143
270	270	return result;
271	271	}
272	272
273		WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w )
	273	WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w )
274	274	{
275	275	switch (offset) {
276	276	case 0xC/4: // I2C Handler
r245142	r245143
278	278	m_eeprom->di_write((data & 0x040000) >> (16+2));
279	279	m_eeprom->cs_write((data & 0x020000) ? ASSERT_LINE : CLEAR_LINE);
280	280	m_eeprom->clk_write((data & 0x010000) ? ASSERT_LINE : CLEAR_LINE);
281		} else {
	281	} else {
282	282	if (LOG_EEPROM)
283	283	logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
284	284	}

trunk/src/mame/machine/iteagle_fpga.h
r245142	r245143
31	31	UINT32 m_fpga_regs[0x20];
32	32	UINT32 m_rtc_regs[0x800];
33	33	UINT32 m_prev_reg;
34
	34
35	35	DECLARE_ADDRESS_MAP(rtc_map, 32);
36	36	DECLARE_ADDRESS_MAP(fpga_map, 32);
37	37	DECLARE_ADDRESS_MAP(ctrl_map, 32);

trunk/src/mame/mame.lst
r245142	r245143
336	336	frogf // bootleg
337	337	quaak // bootleg
338	338	froggeram // bootleg
339		froggerv // bootleg
	339	froggerv // bootleg
340	340	amidars // GX337 (c) 1982 Konami
341	341	triplep // (c) 1982 KKI / made by Sanritsu?
342	342	triplepa // (c) 1982 KKI / made by Sanritsu?
r245142	r245143
6350	6350	combatsct // GX611 (c) 1987
6351	6351	combatscj // GX611 (c) 1987 (Japan)
6352	6352	bootcamp // GX611 (c) 1987
6353		bootcampa // GX611 (c) 1987
	6353	bootcampa // GX611 (c) 1987
6354	6354	combatscb // bootleg
6355	6355	rockrage // GX620 (c) 1986 (World?)
6356	6356	rockragea // GX620 (c) 1986 (Prototype?)
r245142	r245143
7713	7713	kof2000n // 0257 (c) 2000 SNK
7714	7714	// 0258 SNK vs. Capcom?
7715	7715	bangbead // 0259 (c) 2000 Visco
7716		b2b // 0071 (c) 2000 Visco (released by NCI in 2010)
	7716	b2b // 0071 (c) 2000 Visco (released by NCI in 2010)
7717	7717	nitd // 0260 (c) 2000 Eleven / Gavaking
7718	7718	nitdbl // bootleg
7719	7719	sengoku3 // 0261 (c) 2001 Noise Factory / SNK
r245142	r245143
7910	7910	tstrikea // Game Room
7911	7911	ctribe // TA-0028 (c) 1990 (US)
7912	7912	ctribe1 // TA-0028 (c) 1990 (US)
7913		ctribeo // TA-0028 (c) 1990 (US)
	7913	ctribeo // TA-0028 (c) 1990 (US)
7914	7914	ctribej // TA-0028 (c) 1990 (Japan)
7915	7915	ctribeb // bootleg
7916	7916	ctribeb2 // bootleg
r245142	r245143
8453	8453	raiden2eu // (c) 1993 Seibu Kaihatsu + Fabtek license
8454	8454	raiden2eua // (c) 1993 Seibu Kaihatsu + Fabtek license
8455	8455	raiden2nl // (c) 1993 Seibu Kaihatsu
8456		raiden2f // (c) 1993 Seibu Kaihatsu
	8456	raiden2f // (c) 1993 Seibu Kaihatsu
8457	8457	raiden2g // (c) 1993 Seibu Kaihatsu + Tuning license
8458	8458	raiden2dx // (c) 1993 Seibu Kaihatsu
8459	8459
r245142	r245143
8777	8777	gunbirdk // (c) 1994
8778	8778	gunbirdj // (c) 1994
8779	8779	btlkroad // (c) 1994
8780		btlkroadk // (c) 1994
	8780	btlkroadk // (c) 1994
8781	8781	s1945 // (c) 1995
8782	8782	s1945a // (c) 1995
8783	8783	s1945j // (c) 1995

trunk/src/mame/video/bbusters.c
r245142	r245143
76	76
77	77	m_pf1_tilemap->set_transparent_pen(15);
78	78	m_fix_tilemap->set_transparent_pen(15);
79
	79
80	80	save_item(NAME(m_scale_line_count));
81	81	}
82	82
r245142	r245143
88	88
89	89	m_pf1_tilemap->set_transparent_pen(15);
90	90	m_fix_tilemap->set_transparent_pen(15);
91
	91
92	92	save_item(NAME(m_scale_line_count));
93	93	}
94	94

trunk/src/mame/video/deadang.c
r245142	r245143
77	77	m_pf2_layer->set_transparent_pen(15);
78	78	m_pf1_layer->set_transparent_pen(15);
79	79	m_text_layer->set_transparent_pen(15);
80
	80
81	81	save_item(NAME(m_tilebank));
82	82	save_item(NAME(m_oldtilebank));
83	83	}

trunk/src/mame/video/decmxc06.c
r245142	r245143
110	110	else
111	111	mult = -16;
112	112
113
	113
114	114	// thedeep strongly suggests that this check goes here, otherwise the radar breaks
115	115	if (!(spriteram[offs] & 0x8000))
116	116	{
117	117	offs += 4;
118	118	continue;
119	119	}
120
121	120
	121
122	122	for (x = 0; x < w; x++)
123	123	{
124	124	// maybe, birdie try appears to specify the base code for each part..
r245142	r245143
173	173	offs += 4;
174	174	if (offs >= m_ramsize / 2)
175	175	return;
176
177	176
	177
178	178	}
179	179	}
180	180	}

trunk/src/mame/video/dynax.c
r245142	r245143
122	122	}
123	123
124	124	/*
125		mjelctrn: 7 d e -> 1 - 4 8
126		mjembase: b d e -> - 2 4 8
	125	mjelctrn: 7 d e -> 1 - 4 8
	126	mjembase: b d e -> - 2 4 8
127	127	*/
128	128	WRITE8_MEMBER(dynax_state::mjembase_blit_dest_w)
129	129	{
r245142	r245143
381	381	}
382	382
383	383	/*
384		Flags:
	384	Flags:
385	385
386	386	7654 ---- -
387	387	---- 3--- Rotation = SWAPXY + FLIPY
r245142	r245143
1223	1223	}
1224	1224
1225	1225	/*
1226		mjembase: priority: 00 08 10 18 20 28; enable: 1,2,4
	1226	mjembase: priority: 00 08 10 18 20 28; enable: 1,2,4
1227	1227	Convert to:
1228		mjelctrn: priority: 00 20 10 40 30 50; enable: 1,2,8
	1228	mjelctrn: priority: 00 20 10 40 30 50; enable: 1,2,8
1229	1229	*/
1230	1230	WRITE8_MEMBER(dynax_state::mjembase_priority_w)
1231	1231	{

trunk/src/mame/video/hng64.c
r245142	r245143
660	660
661	661	// xrally's pink tilemaps make me think this is a tilemap enable bit.
662	662	// fatfurwa makes me think otherwise.
663		// if (!(tileregs & 0x0040)) return;
	663	// if (!(tileregs & 0x0040)) return;
664	664
665	665	// set the transmask so our manual copy is correct
666	666	if (tileregs & 0x0400)
r245142	r245143
1251	1251	m_vertsrom = (UINT16*)memregion("verts")->base();
1252	1252	m_vertsrom_size = memregion("verts")->bytes();
1253	1253	}
1254

trunk/src/mame/video/hng64_3d.c
r245142	r245143
68	68	/* Note: Samurai Shodown games never calls bit 1, so it can't be framebuffer clear. It also calls bit 3 at start-up, meaning unknown */
69	69	WRITE32_MEMBER(hng64_state::dl_control_w) // This handles framebuffers
70	70	{
71		// printf("dl_control_w %08x %08x\n", data, mem_mask);
	71	// printf("dl_control_w %08x %08x\n", data, mem_mask);
72	72
73	73	//if(data & 2) // swap buffers
74	74	//{
r245142	r245143
540	540	#if 0
541	541	if (((chunkOffset[2] & 0xc000) == 0x4000) && (m_screen->frame_number() & 1))
542	542	{
543		// if (chunkOffset[2] == 0xd870)
	543	// if (chunkOffset[2] == 0xd870)
544	544	{
545	545	polys[*numPolys].debugColor = 0xffff0000;
546	546	printf("%d (%08x) : %04x %04x %04x\n", k, address[k] * 3 * 2, chunkOffset[0], chunkOffset[1], chunkOffset[2]);
r245142	r245143
863	863
864	864	void hng64_state::hng64_command3d(const UINT16* packet)
865	865	{
866
867	866	/* A temporary place to put some polygons. This will optimize away if the compiler's any good. */
868	867	int numPolys = 0;
869	868	dynamic_array<polygon> polys(1024*5);
870	869
871	870	//printf("packet type : %04x %04x\|%04x %04x\|%04x %04x\|%04x %04x \| %04x %04x %04x %04x %04x %04x %04x %04x\n", packet[0],packet[1],packet[2],packet[3],packet[4],packet[5],packet[6],packet[7], packet[8], packet[9], packet[10], packet[11], packet[12], packet[13], packet[14], packet[15]);
872
	871
873	872	switch (packet[0])
874	873	{
875	874	case 0x0000: // Appears to be a NOP.
r245142	r245143
1239	1238
1240	1239	UINT8 paletteEntry = 0;
1241	1240	float t_coord, s_coord;
1242		const UINT8 *gfx = m_texturerom;
	1241	const UINT8 *gfx = m_texturerom;
1243	1242	const UINT8 textureOffset = &gfx[prOptions.texIndex 1024 * 1024];
1244	1243
1245	1244	for (; x_start <= x_end; x_start++)
r245142	r245143
1702	1701	prOptions);
1703	1702	}
1704	1703	}
1705

trunk/src/mame/video/hng64_sprite.c
r245142	r245143
222	222	if (!chaini) source +=8;
223	223	}
224	224	}
225

trunk/src/mame/video/jalblend.c
r245142	r245143
35	35	void jaleco_blend_device::device_start()
36	36	{
37	37	m_table = auto_alloc_array_clear(machine(), UINT8, 0xc00);
38
	38
39	39	save_pointer(NAME(m_table), 0xc00);
40	40	}
41	41

trunk/src/mame/video/jalblend.h
r245142	r245143
3	3	public:
4	4	jaleco_blend_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
5	5	~jaleco_blend_device() {}
6
	6
7	7	void set(int color, UINT8 val);
8	8	rgb_t func(rgb_t dest, rgb_t addMe, UINT8 alpha);
9	9	void drawgfx(palette_device &palette,bitmap_ind16 &dest_bmp,const rectangle &clip,gfx_element *gfx,
r245142	r245143
18	18	virtual void device_start();
19	19	virtual void device_reset();
20	20
21		private:
	21	private:
22	22	/* each palette entry contains a fourth 'alpha' value */
23	23	UINT8 *m_table;
24
	24
25	25	template<class _BitmapClass>
26	26	void drawgfx_common(palette_device &palette,_BitmapClass &dest_bmp,const rectangle &clip,gfx_element *gfx,
27	27	UINT32 code,UINT32 color,int flipx,int flipy,int offsx,int offsy,
28	28	int transparent_color);
29	29	};
30	30
31		extern const device_type JALECO_BLEND;
		No newline at end of file
	31	extern const device_type JALECO_BLEND;

trunk/src/mame/video/pc080sn.c
r245142	r245143
62	62	{
63	63	for (int i = 0; i < 8; i++)
64	64	m_ctrl[i] = 0;
65
	65
66	66	for (int i = 0; i < 2; i++)
67	67	{
68	68	m_bg_ram[i] = NULL;

trunk/src/mame/video/psychic5.c
r245142	r245143
24	24	UINT8 hi = palram[(offset) \| 1];
25	25
26	26	int color = offset >> 1;
27
	27
28	28	if (m_blend)
29	29	m_blend->set(palbase + color, hi & 0x0f);
30
	30
31	31	m_palette->set_pen_color(palbase + color, pal4bit(lo >> 4), pal4bit(lo), pal4bit(hi >> 4));
32	32	}
33	33
r245142	r245143
188	188	VIDEO_START_MEMBER(psychic5_state,psychic5)
189	189	{
190	190	video_start();
191
	191
192	192	m_bg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(psychic5_state::get_bg_tile_info),this), TILEMAP_SCAN_COLS, 16, 16, 64, 32);
193	193	m_fg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(psychic5_state::get_fg_tile_info),this), TILEMAP_SCAN_COLS, 8, 8, 32, 32);
194	194	m_fg_tilemap->set_transparent_pen(15);
195
	195
196	196	save_item(NAME(m_title_screen));
197	197
198	198	}
r245142	r245143
200	200	VIDEO_START_MEMBER(psychic5_state,bombsa)
201	201	{
202	202	video_start();
203
	203
204	204	m_bg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(psychic5_state::get_bg_tile_info),this), TILEMAP_SCAN_COLS, 16, 16, 128, 32);
205	205	m_fg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(psychic5_state::get_fg_tile_info),this), TILEMAP_SCAN_COLS, 8, 8, 32, 32);
206	206	m_fg_tilemap->set_transparent_pen(15);
207
	207
208	208	save_item(NAME(m_bombsa_unknown));
209	209	}
210	210

trunk/src/mame/video/realbrk.c
r245142	r245143
154	154
155	155	m_tmpbitmap0 = auto_bitmap_ind16_alloc(machine(),32,32);
156	156	m_tmpbitmap1 = auto_bitmap_ind16_alloc(machine(),32,32);
157
	157
158	158	save_item(NAME(m_disable_video));
159	159	}
160	160

trunk/src/mame/video/rltennis.c
r245142	r245143
224	224	m_tmp_bitmap[BITMAP_FG_1] = auto_bitmap_ind16_alloc(machine(), 512, 256);
225	225	m_tmp_bitmap[BITMAP_FG_2] = auto_bitmap_ind16_alloc(machine(), 512, 256);
226	226	m_tmp_bitmap[BITMAP_FG_DISPLAY] = auto_bitmap_ind16_alloc(machine(), 512, 256);
227
	227
228	228	save_item(NAME(m_blitter));
229	229	}
230	230

trunk/src/mame/video/seta001.c
r245142	r245143
84	84	m_spritelimit = 0x1ff;
85	85
86	86	m_bgflag = 0x00;
87
	87
88	88	m_gfxbank_cb.bind_relative_to(*owner());
89	89
90	90	save_item(NAME(m_bgflag));

trunk/src/mame/video/seta2.c
r245142	r245143
457	457	VIDEO_START_MEMBER(seta2_state,xoffset)
458	458	{
459	459	video_start();
460
	460
461	461	m_xoffset = 0x200;
462	462	}
463	463
464	464	VIDEO_START_MEMBER(seta2_state,yoffset)
465	465	{
466	466	video_start();
467
	467
468	468	m_yoffset = 0x10;
469	469	}
470	470

trunk/src/mame/video/sidearms.c
r245142	r245143
159	159	m_latch_374 = m_vcount_191 = m_hcount_191 = 0;
160	160
161	161	m_flipon = m_charon = m_staron = m_objon = m_bgon = 0;
162
	162
163	163	save_item(NAME(m_bgon));
164	164	save_item(NAME(m_objon));
165	165	save_item(NAME(m_staron));

trunk/src/mame/video/srumbler.c
r245142	r245143
52	52
53	53	m_bg_tilemap->set_transmask(0,0xffff,0x0000); /* split type 0 is totally transparent in front half */
54	54	m_bg_tilemap->set_transmask(1,0x07ff,0xf800); /* split type 1 has pens 0-10 transparent in front half */
55
	55
56	56	save_item(NAME(m_scroll));
57	57	}
58	58

trunk/src/mame/video/ssv.c
r245142	r245143
194	194	void ssv_state::video_start()
195	195	{
196	196	m_gfxdecode->gfx(0)->set_granularity(64); /* 256 colour sprites with palette selectable on 64 colour boundaries */
197
	197
198	198	save_item(NAME(m_enable_video));
199	199	save_item(NAME(m_shadow_pen_mask));
200	200	save_item(NAME(m_shadow_pen_shift));
r245142	r245143
208	208
209	209	m_gfxdecode->gfx(0)->set_source((UINT8 *)m_eaglshot_gfxram);
210	210	m_gfxdecode->gfx(1)->set_source((UINT8 *)m_eaglshot_gfxram);
211
	211
212	212	save_pointer(NAME(m_eaglshot_gfxram), 16 * 0x40000 / 2);
213	213	}
214	214

trunk/src/mame/video/suna16.c
r245142	r245143
92	92	void suna16_state::video_start()
93	93	{
94	94	m_paletteram = auto_alloc_array(machine(), UINT16, m_palette->entries());
95
	95
96	96	save_item(NAME(m_color_bank));
97	97	}
98	98

trunk/src/mame/video/suprloco.c
r245142	r245143
98	98	m_bg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(suprloco_state::get_tile_info),this),TILEMAP_SCAN_ROWS,8,8,32,32);
99	99
100	100	m_bg_tilemap->set_scroll_rows(32);
101
	101
102	102	save_item(NAME(m_control));
103	103	}
104	104

trunk/src/mame/video/suprridr.c
r245142	r245143
44	44	m_bg_tilemap_noscroll = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(suprridr_state::get_tile_info),this), TILEMAP_SCAN_ROWS, 8,8, 32,32);
45	45
46	46	m_fg_tilemap->set_transparent_pen(0);
47
	47
48	48	save_item(NAME(m_flipx));
49	49	save_item(NAME(m_flipy));
50	50	}

trunk/src/mame/video/tankbust.c
r245142	r245143
83	83	m_bg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(tankbust_state::get_bg_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 64, 32);
84	84
85	85	m_txt_tilemap->set_transparent_pen(0);
86
	86
87	87	save_item(NAME(m_xscroll));
88	88	save_item(NAME(m_yscroll));
89	89	}

trunk/src/mame/video/tbowl.c
r245142	r245143
116	116	m_tx_tilemap->set_transparent_pen(0);
117	117	m_bg_tilemap->set_transparent_pen(0);
118	118	m_bg2_tilemap->set_transparent_pen(0);
119
	119
120	120	save_item(NAME(m_xscroll));
121	121	save_item(NAME(m_yscroll));
122	122	save_item(NAME(m_bg2xscroll));

trunk/src/mame/video/thedeep.c
r245142	r245143
134	134	m_tilemap_1->draw(screen, bitmap, cliprect, 0,0);
135	135	return 0;
136	136	}
137

trunk/src/mame/video/timelimt.c
r245142	r245143
73	73	8, 8, 32, 32);
74	74
75	75	m_fg_tilemap->set_transparent_pen(0);
76
	76
77	77	save_item(NAME(m_scrollx));
78	78	save_item(NAME(m_scrolly));
79	79	}

trunk/src/mame/video/tryout.c
r245142	r245143
12	12	PALETTE_INIT_MEMBER(tryout_state, tryout)
13	13	{
14	14	const UINT8 *color_prom = memregion("proms")->base();
15
	15
16	16	for (int i = 0;i < palette.entries();i++)
17	17	{
18	18	int bit0,bit1,bit2,r,g,b;

trunk/src/mame/video/tsamurai.c
r245142	r245143
55	55
56	56	m_background->set_transparent_pen(0);
57	57	m_foreground->set_transparent_pen(0);
58
	58
59	59	save_item(NAME(m_bgcolor));
60	60	video_start();
61	61	}
r245142	r245143
63	63	VIDEO_START_MEMBER(tsamurai_state, m660)
64	64	{
65	65	VIDEO_START_CALL_MEMBER(tsamurai);
66
	66
67	67	save_item(NAME(m_textbank2));
68	68	}
69	69
r245142	r245143
256	256	VIDEO_START_MEMBER(tsamurai_state,vsgongf)
257	257	{
258	258	m_foreground = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(tsamurai_state::get_vsgongf_tile_info),this),TILEMAP_SCAN_ROWS,8,8,32,32);
259
	259
260	260	save_item(NAME(m_vsgongf_color));
261	261	video_start();
262	262	}

trunk/src/mame/video/vulgus.c
r245142	r245143
113	113	m_bg_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(vulgus_state::get_bg_tile_info),this),TILEMAP_SCAN_COLS,16,16,32,32);
114	114
115	115	m_fg_tilemap->configure_groups(*m_gfxdecode->gfx(0), 47);
116
	116
117	117	save_item(NAME(m_palette_bank));
118	118	}
119	119

trunk/src/mame/video/xain.c
r245142	r245143
89	89	m_bgram0_tilemap->set_transparent_pen(0);
90	90	m_bgram1_tilemap->set_transparent_pen(0);
91	91	m_char_tilemap->set_transparent_pen(0);
92
	92
93	93	save_item(NAME(m_pri));
94	94	save_item(NAME(m_scrollxP0));
95	95	save_item(NAME(m_scrollyP0));

trunk/src/mess/audio/gamate.c
r245142	r245143
38	38	void gamate_sound_device::device_start()
39	39	{
40	40	// bind callbacks
41		// m_irq_cb.bind_relative_to(*owner());
	41	// m_irq_cb.bind_relative_to(*owner());
42	42
43	43	memset(m_channels, 0, sizeof(m_channels));
44	44	memset(reg, 0, sizeof(reg));
r245142	r245143
56	56	stream_sample_t left=outputs[0], right=outputs[1];
57	57	int i, j;
58	58	Tone *channel;
59
	59
60	60	for (i = 0; i < samples; i++, left++, right++)
61	61	{
62	62	noise.pos += noise.step;
r245142	r245143
77	77	{
78	78	case 0: case 1: case 2: case 3:
79	79	case 4: case 5: case 6: case 7:
80		case 8: case 9: case 0xb:
	80	case 8: case 9: case 0xb:
81	81	case 0xd: case 0xf:
82	82	if (envelope.index>=ARRAY_LENGTH(EnvelopeVolumes)/2)
83	83	{

trunk/src/mess/drivers/a7800.c
r245142	r245143
286	286	AM_RANGE(0x0480, 0x04ff) AM_RAM AM_SHARE("riot_ram") AM_MIRROR(0x100)
287	287	AM_RANGE(0x1800, 0x1fff) AM_RAM AM_SHARE("6116_1")
288	288	AM_RANGE(0x2000, 0x27ff) AM_RAM AM_SHARE("6116_2") AM_MIRROR(0x0800)
289		// According to the official Software Guide, the RAM at 0x2000 is
290		// repeatedly mirrored up to 0x3fff, but this is evidently incorrect
291		// because the High Score Cartridge maps ROM at 0x3000-0x3fff
292		// Hardware tests show that only the mirror at 0x2800-0x2fff actually
293		// exists, and only on some hardware (MARIA? motherboard?) revisions
	289	// According to the official Software Guide, the RAM at 0x2000 is
	290	// repeatedly mirrored up to 0x3fff, but this is evidently incorrect
	291	// because the High Score Cartridge maps ROM at 0x3000-0x3fff
	292	// Hardware tests show that only the mirror at 0x2800-0x2fff actually
	293	// exists, and only on some hardware (MARIA? motherboard?) revisions
294	294	AM_RANGE(0x4000, 0xffff) AM_DEVWRITE("cartslot", a78_cart_slot_device, write_40xx)
295	295	AM_RANGE(0x4000, 0xbfff) AM_DEVREAD("cartslot", a78_cart_slot_device, read_40xx)
296	296	AM_RANGE(0xc000, 0xffff) AM_READ(bios_or_cart_r) // here also the BIOS can be accessed

trunk/src/mess/drivers/apple2.c
r245142	r245143
1229	1229	SLOT_INTERFACE("dx1", A2BUS_DX1) /* Decillonix DX-1 sampler card */
1230	1230	SLOT_INTERFACE("tm2ho", A2BUS_TIMEMASTERHO) /* Applied Engineering TimeMaster II H.O. */
1231	1231	SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */
1232		SLOT_INTERFACE("ezcgi", A2BUS_EZCGI) /* E-Z Color Graphics Interface */
1233		SLOT_INTERFACE("ezcgi9938", A2BUS_EZCGI_9938) /* E-Z Color Graphics Interface (TMS9938) */
1234		SLOT_INTERFACE("ezcgi9958", A2BUS_EZCGI_9958) /* E-Z Color Graphics Interface (TMS9958) */
	1232	SLOT_INTERFACE("ezcgi", A2BUS_EZCGI) /* E-Z Color Graphics Interface */
	1233	SLOT_INTERFACE("ezcgi9938", A2BUS_EZCGI_9938) /* E-Z Color Graphics Interface (TMS9938) */
	1234	SLOT_INTERFACE("ezcgi9958", A2BUS_EZCGI_9958) /* E-Z Color Graphics Interface (TMS9958) */
1235	1235	// SLOT_INTERFACE("magicmusician", A2BUS_MAGICMUSICIAN) /* Magic Musician Card */
1236	1236	SLOT_INTERFACE_END
1237	1237

trunk/src/mess/drivers/apple2e.c
r245142	r245143
3036	3036	SLOT_INTERFACE("dx1", A2BUS_DX1) /* Decillonix DX-1 sampler card */
3037	3037	SLOT_INTERFACE("tm2ho", A2BUS_TIMEMASTERHO) /* Applied Engineering TimeMaster II H.O. */
3038	3038	SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */
3039		SLOT_INTERFACE("ezcgi", A2BUS_EZCGI) /* E-Z Color Graphics Interface */
3040		SLOT_INTERFACE("ezcgi9938", A2BUS_EZCGI_9938) /* E-Z Color Graphics Interface (TMS9938) */
3041		SLOT_INTERFACE("ezcgi9958", A2BUS_EZCGI_9958) /* E-Z Color Graphics Interface (TMS9958) */
	3039	SLOT_INTERFACE("ezcgi", A2BUS_EZCGI) /* E-Z Color Graphics Interface */
	3040	SLOT_INTERFACE("ezcgi9938", A2BUS_EZCGI_9938) /* E-Z Color Graphics Interface (TMS9938) */
	3041	SLOT_INTERFACE("ezcgi9958", A2BUS_EZCGI_9958) /* E-Z Color Graphics Interface (TMS9958) */
3042	3042	// SLOT_INTERFACE("magicmusician", A2BUS_MAGICMUSICIAN) /* Magic Musician Card */
3043	3043	SLOT_INTERFACE_END
3044	3044

trunk/src/mess/drivers/gamate.c
r245142	r245143
4	4	Morten Shearman Kirkegaard morten+gamate@afdelingp.dk
5	5	Juan F??lix Mateos vectrex@hackermesh.org
6	6
7		nmi unknown
	7	nmi unknown
8	8	bomb blast top status line missing
9	9	******************************************************************************/
10	10
r245142	r245143
84	84	WRITE8_MEMBER( gamate_state::gamate_cart_protection_w )
85	85	{
86	86	logerror("%.6f protection write %x %x address:%x data:%x shift:%d\n",machine().time().as_double(), offset, data, card_protection.address, card_protection.cartridge_byte, card_protection.bit_shifter);
87
	87
88	88	switch (offset)
89	89	{
90	90	case 0:
r245142	r245143
118	118	ret=(card_protection.cartridge_byte&0x80) ? 2 : 0;
119	119	if (card_protection.bit_shifter==7 && !card_protection.failed)
120	120	{ // now protection chip on cartridge activates cartridge chip select on cpu accesses
121		// m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r)); // next time I will try to get this working
	121	// m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r)); // next time I will try to get this working
122	122	}
123	123	card_protection.cartridge_byte<<=1;
124	124	}
r245142	r245143
318	318	m_cart_ptr = memregion("maincpu")->base() + 0x6000;
319	319	if (m_cart->exists())
320	320	{
321		// m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r));
	321	// m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r));
322	322	m_cart_ptr = m_cart->get_rom_base();
323	323	membank("bankmulti")->set_base(m_cart->get_rom_base()+1);
324	324	membank("bank")->set_base(m_cart->get_rom_base()+0x4000); // bankswitched games in reality no offset
325	325	}
326		// m_bios[0xdf1]=0xea; m_bios[0xdf2]=0xea; // default bios: $47 protection readback
	326	// m_bios[0xdf1]=0xea; m_bios[0xdf2]=0xea; // default bios: $47 protection readback
327	327	card_protection.set=false;
328	328	bank_multi=0;
329	329	card_protection.unprotected=false;
r245142	r245143
400	400
401	401	/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */
402	402	CONS( 19??, gamate, 0, 0, gamate, gamate, gamate_state, gamate, "Bit Corp", "Gamate", 0)
403

trunk/src/mess/drivers/hh_hmcs40.c
r245142	r245143
66	66	required_device<cpu_device> m_maincpu;
67	67	optional_ioport_array<7> m_inp_matrix; // max 7
68	68	optional_device<speaker_sound_device> m_speaker;
69
	69
70	70	// misc common
71	71	UINT16 m_inp_mux; // multiplexed inputs mask
72	72
r245142	r245143
78	78	int m_display_wait; // led/lamp off-delay in microseconds (default 33ms)
79	79	int m_display_maxy; // display matrix number of rows
80	80	int m_display_maxx; // display matrix number of columns
81
	81
82	82	UINT32 m_grid; // VFD current row data
83	83	UINT64 m_plate; // VFD current column data
84
85		UINT64 m_display_state[0x20]; // display matrix rows data
	84
	85	UINT64 m_display_state[0x20]; // display matrix rows data
86	86	UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
87	87	UINT64 m_display_cache[0x20]; // (internal use)
88	88	UINT8 m_display_decay[0x20][0x40]; // (internal use)
r245142	r245143
95	95	DECLARE_WRITE8_MEMBER(alnattck_plate_w);
96	96	DECLARE_WRITE16_MEMBER(alnattck_d_w);
97	97	DECLARE_READ16_MEMBER(alnattck_d_r);
98
	98
99	99	void egalaxn2_display();
100	100	DECLARE_WRITE8_MEMBER(egalaxn2_plate_w);
101	101	DECLARE_WRITE16_MEMBER(egalaxn2_grid_w);
r245142	r245143
110	110	memset(m_display_cache, ~0, sizeof(m_display_cache));
111	111	memset(m_display_decay, 0, sizeof(m_display_decay));
112	112	memset(m_display_segmask, 0, sizeof(m_display_segmask));
113
	113
114	114	m_inp_mux = 0;
115	115	m_grid = 0;
116	116	m_plate = 0;
r245142	r245143
191	191	for (int x = 0; x < m_display_maxx; x++)
192	192	if (m_display_decay[y][x] != 0)
193	193	m_display_decay[y][x]--;
194
	194
195	195	display_update();
196	196	}
197	197
r245142	r245143
204	204	UINT64 mask = (1 << maxx) - 1;
205	205	for (int y = 0; y < maxy; y++)
206	206	m_display_state[y] = (sety >> y & 1) ? (setx & mask) : 0;
207
	207
208	208	display_update();
209	209	}
210	210
r245142	r245143
249	249	/* basic machine hardware */
250	250	MCFG_CPU_ADD("maincpu", HD38750, 400000) // approximation - RC osc.
251	251
252		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	252	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
253	253	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
254	254
255	255	/* no video! */
r245142	r245143
284	284	/* basic machine hardware */
285	285	MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc.
286	286
287		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	287	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
288	288	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
289	289
290	290	/* no video! */
r245142	r245143
318	318	/* basic machine hardware */
319	319	MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
320	320
321		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	321	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
322	322	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
323	323
324	324	/* no video! */
r245142	r245143
351	351
352	352	// update display
353	353	UINT32 plate = BITSWAP16(m_plate,11,9,8,10,7,2,0,1,3,4,5,6,12,13,14,15) \| (m_plate & 0xf0000);
354
	354
355	355	display_matrix(20, 10, plate, m_grid);
356	356	}
357	357
r245142	r245143
359	359	{
360	360	// D4: speaker out
361	361	m_speaker->level_w(data >> 4 & 1);
362
	362
363	363	// D7-D13: input mux
364	364	m_inp_mux = data >> 7 & 0x7f;
365	365
366	366	// D6-D15: vfd matrix grid
367	367	m_grid = data >> 6 & 0x3ff;
368
	368
369	369	// D0-D3: plate 16-19 (update display there)
370	370	alnattck_plate_w(space, 4, data & 0xf);
371	371	}
r245142	r245143
449	449	/* basic machine hardware */
450	450	MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
451	451
452		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	452	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
453	453	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
454	454
455	455	/* no video! */
r245142	r245143
484	484	/* basic machine hardware */
485	485	MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc.
486	486
487		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	487	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
488	488	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
489	489
490	490	/* no video! */
r245142	r245143
519	519	/* basic machine hardware */
520	520	MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
521	521
522		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	522	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
523	523	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
524	524
525	525	/* no video! */
r245142	r245143
554	554	/* basic machine hardware */
555	555	MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
556	556
557		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	557	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
558	558	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
559	559
560	560	/* no video! */
r245142	r245143
583	583	{
584	584	UINT32 grid = BITSWAP16(m_grid,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14);
585	585	UINT32 plate = BITSWAP24(m_plate,23,22,21,20,15,14,13,12,7,6,5,4,3,2,1,0,19,18,17,16,11,10,9,8);
586
	586
587	587	display_matrix(24, 15, plate, grid);
588	588	}
589	589
r245142	r245143
591	591	{
592	592	// D0: speaker out
593	593	m_speaker->level_w(data & 1);
594
	594
595	595	// D1-D4: input mux
596	596	m_inp_mux = data >> 1 & 0xf;
597
	597
598	598	// D1-D15: vfd matrix grid
599	599	m_grid = data >> 1;
600	600	egalaxn2_display();
r245142	r245143
766	766	/* basic machine hardware */
767	767	MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
768	768
769		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	769	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
770	770	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
771	771
772	772	/* no video! */
r245142	r245143
787	787	* boards are labeled THF-01II 2E138E01/2E128E02
788	788	* Hitachi HD38800B23 MCU
789	789	* cyan/red/blue VFD display Futaba DM-65ZK 3A
790
	790
791	791	NOTE!: MESS external artwork is recommended
792	792
793	793	***************************************************************************/
r245142	r245143
801	801	/* basic machine hardware */
802	802	MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc.
803	803
804		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	804	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
805	805	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
806	806
807	807	/* no video! */
r245142	r245143
836	836	/* basic machine hardware */
837	837	MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc.
838	838
839		// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
	839	// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
840	840	MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
841	841
842	842	/* no video! */

trunk/src/mess/drivers/hh_pic16.c
r245142	r245143
57	57	int m_display_wait; // led/lamp off-delay in microseconds (default 33ms)
58	58	int m_display_maxy; // display matrix number of rows
59	59	int m_display_maxx; // display matrix number of columns
60
61		UINT32 m_display_state[0x20]; // display matrix rows data
	60
	61	UINT32 m_display_state[0x20]; // display matrix rows data
62	62	UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
63	63	UINT32 m_display_cache[0x20]; // (internal use)
64	64	UINT8 m_display_decay[0x20][0x20]; // (internal use)
r245142	r245143
79	79	memset(m_display_cache, ~0, sizeof(m_display_cache));
80	80	memset(m_display_decay, 0, sizeof(m_display_decay));
81	81	memset(m_display_segmask, 0, sizeof(m_display_segmask));
82
	82
83	83	m_b = 0;
84	84	m_c = 0;
85	85
r245142	r245143
158	158	for (int x = 0; x < m_display_maxx; x++)
159	159	if (m_display_decay[y][x] != 0)
160	160	m_display_decay[y][x]--;
161
	161
162	162	display_update();
163	163	}
164	164
r245142	r245143
171	171	UINT32 mask = (1 << maxx) - 1;
172	172	for (int y = 0; y < maxy; y++)
173	173	m_display_state[y] = (sety >> y & 1) ? (setx & mask) : 0;
174
	174
175	175	display_update();
176	176	}
177	177
r245142	r245143
199	199	m_c = data;
200	200	else
201	201	m_b = data;
202
	202
203	203	// d7: speaker out
204	204	m_speaker->level_w((m_b >> 7 & 1) \| (m_c >> 6 & 2));
205	205
206	206	// d0-d6: 7seg
207	207	m_display_maxx = 7;
208	208	m_display_maxy = 2;
209
	209
210	210	m_display_segmask[offset] = 0x7f;
211	211	m_display_state[offset] = ~data & 0x7f;
212	212	display_update();

trunk/src/mess/drivers/hh_tms1k.c
r245142	r245143
5	5	This driver is a collection of simple dedicated handheld and tabletop
6	6	toys based around the TMS1000 MCU series. Anything more complex or clearly
7	7	part of a series is (or will be) in its own driver.
8
	8
9	9	Let's use this driver for a list of known devices and their serials,
10	10	excluding TI's own products (see for example ticalc1x.c, tispeak.c)
11	11
r245142	r245143
53	53	@MP7334 TMS1400 1981, Coleco Total Control 4
54	54
55	55	inconsistent:
56
	56
57	57	@CD7282SL TMS1100 1981, Tandy/RadioShack Tandy-12 (serial is similar to TI Speak & Spell series?)
58	58
59	59	(* denotes not yet emulated by MESS, @ denotes it's in this driver)
r245142	r245143
102	102	memset(m_display_cache, ~0, sizeof(m_display_cache));
103	103	memset(m_display_decay, 0, sizeof(m_display_decay));
104	104	memset(m_display_segmask, 0, sizeof(m_display_segmask));
105
	105
106	106	m_o = 0;
107	107	m_r = 0;
108	108	m_inp_mux = 0;
r245142	r245143
190	190	for (int x = 0; x < m_display_maxx; x++)
191	191	if (m_display_decay[y][x] != 0)
192	192	m_display_decay[y][x]--;
193
	193
194	194	display_update();
195	195	}
196	196
r245142	r245143
203	203	UINT32 mask = (1 << maxx) - 1;
204	204	for (int y = 0; y < maxy; y++)
205	205	m_display_state[y] = (sety >> y & 1) ? (setx & mask) : 0;
206
	206
207	207	display_update();
208	208	}
209	209
r245142	r245143
293	293	{
294	294	// R3,R5-R7,R9,R10: input mux
295	295	m_inp_mux = (data >> 3 & 1) \| (data >> 4 & 0xe) \| (data >> 5 & 0x30);
296
	296
297	297	// +others:
298	298	m_r = data;
299	299	mathmagi_display();
r245142	r245143
442	442	m_display_segmask[y] = 0x7f;
443	443	m_display_state[y] = (m_r >> (y + 8) & 1) ? m_o : 0;
444	444	}
445
	445
446	446	// R6,R7: lamps (-> lamp20,21)
447	447	m_display_state[2] = m_r >> 6 & 3;
448
	448
449	449	display_update();
450	450	}
451	451
r245142	r245143
453	453	{
454	454	// R0-R5: input mux
455	455	m_inp_mux = data & 0x3f;
456
	456
457	457	// R10: speaker out
458	458	m_speaker->level_w(data >> 10 & 1);
459	459
r245142	r245143
582	582	void hh_tms1k_state::tc4_display()
583	583	{
584	584	m_display_wait = 50;
585
	585
586	586	// R5,7,8,9 are 7segs
587	587	for (int y = 0; y < 10; y++)
588	588	if (y >= 5 && y <= 9 && y != 6)
589	589	m_display_segmask[y] = 0x7f;
590
	590
591	591	// update current state (note: R6 as extra column!)
592	592	display_matrix(9, 10, (m_o \| (m_r << 2 & 0x100)), m_r);
593	593	}
r245142	r245143
600	600	// R0-R5: input mux
601	601	// R9: to cartridge slot
602	602	m_inp_mux = data & 0x23f;
603
	603
604	604	// R6: led column 8
605	605	// +other columns
606	606	m_r = data;
r245142	r245143
699	699
700	700	Entex Electronic Baseball (1)
701	701	* TMS1000NLP MP0914 (die labeled MP0914A)
702
	702
703	703	This is a handheld LED baseball game. One player controls the batter, the CPU
704	704	or other player controls the pitcher. Pitcher throw buttons are on a 'joypad'
705	705	obtained from a compartment in the back. Player scores are supposed to be
706	706	written down manually, the game doesn't save scores or innings (this annoyance
707	707	was resolved in the sequel). For more information, refer to the official manual.
708
	708
709	709	The overlay graphic is known to have 2 versions: one where the field players
710	710	are denoted by words ("left", "center", "short", etc), and an alternate one
711	711	with little guys drawn next to the LEDs.
r245142	r245143
730	730	{
731	731	// R8 is a 7seg
732	732	m_display_segmask[8] = 0x7f;
733
	733
734	734	display_matrix(7, 9, ~m_o, m_r);
735	735	}
736	736
r245142	r245143
738	738	{
739	739	// R1-R5: input mux
740	740	m_inp_mux = data >> 1 & 0x1f;
741
	741
742	742	// R9: speaker out
743	743	m_speaker->level_w(data >> 9 & 1);
744
	744
745	745	// R0-R8: led columns
746	746	m_r = data;
747	747	ebball_display();
r245142	r245143
821	821	Entex Electronic Baseball 2
822	822	* boards are labeled: ZENY
823	823	* TMS1000 MCU, MP0923 (die labeled MP0923)
824
	824
825	825	The Japanese version was published by Gakken, black casing instead of white.
826
	826
827	827	The sequel to Entex Baseball, this version keeps up with score and innings.
828	828	As its predecessor, the pitcher controls are on a separate joypad.
829	829
830	830
831	831	lamp translation table: led zz from game PCB = MESS lampyx:
832
	832
833	833	00 = - 10 = lamp94 20 = lamp74 30 = lamp50
834	834	01 = lamp53 11 = lamp93 21 = lamp75 31 = lamp51
835	835	02 = lamp7 12 = lamp92 22 = lamp80 32 = lamp52
r245142	r245143
848	848	// the first 3 are 7segs
849	849	for (int y = 0; y < 3; y++)
850	850	m_display_segmask[y] = 0x7f;
851
	851
852	852	display_matrix(8, 10, ~m_o, m_r ^ 0x7f);
853	853	}
854	854
r245142	r245143
856	856	{
857	857	// R3-R6: input mux
858	858	m_inp_mux = data >> 3 & 0xf;
859
	859
860	860	// R10: speaker out
861	861	m_speaker->level_w(data >> 10 & 1);
862
	862
863	863	// R0-R9: led columns
864	864	m_r = data;
865	865	ebball2_display();
r245142	r245143
932	932	* boards are labeled: ZENY
933	933	* TMS1100NLL 6007 MP1204 (die labeled MP1204)
934	934	* 2*SN75492N LED display driver
935
	935
936	936	This is another improvement over Entex Baseball, where gameplay is a bit more
937	937	varied. Like the others, the pitcher controls are on a separate joypad.
938	938
939	939
940	940	lamp translation table: led zz from game PCB = MESS lampyx:
941	941	note: unlabeled panel leds are listed here as Sz, Bz, Oz, Iz, z left-to-right
942
	942
943	943	00 = - 10 = lamp75 20 = lamp72
944	944	01 = lamp60 11 = lamp65 21 = lamp84
945	945	02 = lamp61 12 = lamp55 22 = lamp85
r245142	r245143
969	969
970	970	// R0,R1 are normal 7segs
971	971	m_display_segmask[0] = m_display_segmask[1] = 0x7f;
972
	972
973	973	// R4,R7 contain segments(only F and B) for the two other digits
974	974	m_display_state[10] = (m_display_state[4] & 0x20) \| (m_display_state[7] & 0x02);
975	975	m_display_state[11] = ((m_display_state[4] & 0x10) \| (m_display_state[7] & 0x01)) << 1;
976	976	m_display_segmask[10] = m_display_segmask[11] = 0x22;
977
	977
978	978	display_update();
979	979	}
980	980
r245142	r245143
982	982	{
983	983	// R0-R2: input mux
984	984	m_inp_mux = data & 7;
985
	985
986	986	// R10: speaker out
987	987	m_speaker->level_w(data >> 10 & 1);
988
	988
989	989	// R0-R9: led columns
990	990	m_r = data;
991	991	ebball3_display();
r245142	r245143
1118	1118	{
1119	1119	// O0,O1,O4,O6: input mux
1120	1120	m_inp_mux = (data & 3) \| (data >> 2 & 4) \| (data >> 3 & 8);
1121
	1121
1122	1122	// O0-O6: led segments A-G
1123	1123	// O7: speaker out
1124	1124	m_o = data;
r245142	r245143
1218	1218	{
1219	1219	// R6,R8 are 7segs
1220	1220	m_display_segmask[6] = m_display_segmask[8] = 0x7f;
1221
	1221
1222	1222	display_matrix(8, 10, m_o, m_r);
1223	1223	}
1224	1224
r245142	r245143
1569	1569
1570	1570	// R6-R9: direction leds (-> lamp60-63)
1571	1571	m_display_state[6] = data >> 6 & 0xf;
1572
	1572
1573	1573	display_update();
1574	1574	}
1575	1575
r245142	r245143
1577	1577	{
1578	1578	// O0-O4: input mux
1579	1579	m_inp_mux = data & 0x1f;
1580
	1580
1581	1581	// O0-O7: digit segments
1582	1582	m_o = data;
1583	1583	}
r245142	r245143
1646	1646	Parker Bros Merlin handheld game, by Bob Doyle
1647	1647	* TMS1100NLL MP3404A-N2
1648	1648	* red LEDs and 1-bit sound
1649
	1649
1650	1650	Also published in Japan by Tomy as "Dr. Smith", white case instead of red.
1651	1651	The one with dark-blue case is the rare sequel Master Merlin. More sequels
1652	1652	followed too, but on other hardware.
r245142	r245143
1780	1780	{
1781	1781	// O0,O6: input mux
1782	1782	m_inp_mux = (data & 1) \| (data >> 5 & 2);
1783
	1783
1784	1784	// O3: speaker out
1785	1785	// O0-O2,O4-O7: led segments A-G
1786	1786	m_o = data;

trunk/src/mess/drivers/hh_ucom4.c
r245142	r245143
6	6
7	7
8	8	known chips:
9
	9
10	10	serial device etc.
11	11	----------------------------------------------------------------
12	12	@031 uPD553C 1979, Bambino Superstar Football (ET-03)
r245142	r245143
52	52	required_device<cpu_device> m_maincpu;
53	53	optional_ioport_array<5> m_inp_matrix; // max 5
54	54	optional_device<speaker_sound_device> m_speaker;
55
	55
56	56	// misc common
57	57	UINT8 m_port[9]; // MCU port A-I write data
58	58	UINT16 m_inp_mux; // multiplexed inputs mask
r245142	r245143
65	65	int m_display_wait; // led/lamp off-delay in microseconds (default 33ms)
66	66	int m_display_maxy; // display matrix number of rows
67	67	int m_display_maxx; // display matrix number of columns
68
	68
69	69	UINT32 m_grid; // VFD current row data
70	70	UINT32 m_plate; // VFD current column data
71
72		UINT32 m_display_state[0x20]; // display matrix rows data
	71
	72	UINT32 m_display_state[0x20]; // display matrix rows data
73	73	UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
74	74	UINT32 m_display_cache[0x20]; // (internal use)
75	75	UINT8 m_display_decay[0x20][0x20]; // (internal use)
r245142	r245143
95	95
96	96	DECLARE_WRITE8_MEMBER(edracula_grid_w);
97	97	DECLARE_WRITE8_MEMBER(edracula_plate_w);
98
	98
99	99	DECLARE_WRITE8_MEMBER(tmtennis_grid_w);
100	100	DECLARE_WRITE8_MEMBER(tmtennis_plate_w);
101	101	DECLARE_WRITE8_MEMBER(tmtennis_port_e_w);
r245142	r245143
107	107	void tmpacman_display();
108	108	DECLARE_WRITE8_MEMBER(tmpacman_grid_w);
109	109	DECLARE_WRITE8_MEMBER(tmpacman_plate_w);
110
	110
111	111	DECLARE_WRITE8_MEMBER(alnchase_output_w);
112	112	DECLARE_READ8_MEMBER(alnchase_input_r);
113	113	};
r245142	r245143
120	120	memset(m_display_cache, ~0, sizeof(m_display_cache));
121	121	memset(m_display_decay, 0, sizeof(m_display_decay));
122	122	memset(m_display_segmask, 0, sizeof(m_display_segmask));
123
	123
124	124	memset(m_port, 0, sizeof(m_port));
125	125	m_inp_mux = 0;
126	126	m_grid = 0;
r245142	r245143
203	203	for (int x = 0; x < m_display_maxx; x++)
204	204	if (m_display_decay[y][x] != 0)
205	205	m_display_decay[y][x]--;
206
	206
207	207	display_update();
208	208	}
209	209
r245142	r245143
216	216	UINT32 mask = (1 << maxx) - 1;
217	217	for (int y = 0; y < maxy; y++)
218	218	m_display_state[y] = (sety >> y & 1) ? (setx & mask) : 0;
219
	219
220	220	display_update();
221	221	}
222	222
r245142	r245143
247	247	* PCB label Emix Corp. ET-03
248	248	* NEC uCOM-43 MCU, labeled D553C 031
249	249	* green VFD display Emix-102
250
	250
251	251	Press the Kick button to start the game, an automatic sequence follows.
252	252	Then choose a formation(A,B,C) and either pass the ball, and/or start
253	253	running. For more information, refer to the official manual.
r245142	r245143
274	274	WRITE8_MEMBER(hh_ucom4_state::ssfball_plate_w)
275	275	{
276	276	m_port[offset] = data;
277
	277
278	278	// E,F,G,H,I(not all!): vfd matrix plate
279	279	int shift = (offset - NEC_UCOM4_PORTE) * 4;
280	280	m_plate = (m_plate & ~(0xf << shift)) \| (data << shift);
281
	281
282	282	// F3,G3: input mux + speaker
283	283	m_inp_mux = (m_port[NEC_UCOM4_PORTF] >> 3 & 1) \| (m_port[NEC_UCOM4_PORTG] >> 2 & 2);
284	284	m_speaker->level_w(m_inp_mux);
285
	285
286	286	// E3: vfd matrix grid 8
287	287	if (offset == NEC_UCOM4_PORTE)
288	288	ssfball_grid_w(space, offset, data >> 3 & 1);
r245142	r245143
376	376	// G,H,I0: vfd matrix grid
377	377	int shift = (offset - NEC_UCOM4_PORTG) * 4;
378	378	m_grid = (m_grid & ~(0xf << shift)) \| (data << shift);
379
	379
380	380	// G(grid 0-3): input mux
381	381	m_inp_mux = m_grid & 0xf;
382
	382
383	383	// I2: vfd matrix plate 6
384	384	if (offset == NEC_UCOM4_PORTI)
385	385	m_plate = (m_plate & 0xffff) \| (data << 14 & 0x10000);
r245142	r245143
392	392	// C,D,E,F23: vfd matrix plate
393	393	int shift = (offset - NEC_UCOM4_PORTC) * 4;
394	394	m_plate = (m_plate & ~(0xf << shift)) \| (data << shift);
395
	395
396	396	// F01: speaker out
397	397	if (offset == NEC_UCOM4_PORTF)
398	398	m_speaker->level_w(data & 3);
399
	399
400	400	ssfball_display();
401	401	}
402	402
r245142	r245143
408	408
409	409
410	410	/* physical button layout and labels is like this:
411
	411
412	412	* left = P1 side * * right = P2 side * (note: in 1P mode, switch sides between turns)
413	413
414	414	[ JUMP ] [ HIGH ] (players sw) [ HIGH ] [ JUMP ]
r245142	r245143
530	530	{
531	531	// E2: speaker out
532	532	m_speaker->level_w(data >> 2 & 1);
533
	533
534	534	// E3: vfd matrix grid 8
535	535	astrocmd_grid_w(space, offset, data >> 3 & 1);
536	536	}
r245142	r245143
719	719
720	720
721	721	/* Pro-Tennis physical button layout and labels is like this:
722
	722
723	723	* left = P2/CPU side * * right = P1 side *
724	724
725	725	[SERVE] [1] [2] [3] [3] [2] [1] [SERVE]
r245142	r245143
818	818	- USA: Pac Man
819	819	- UK: Puckman (Tomy), and also published by Grandstand as Munchman
820	820	- Australia: Pac Man-1, published by Futuretronics
821
	821
822	822	The game will start automatically after turning it on. This Pac Man refuses
823	823	to eat dots with his butt, you can only eat them going right-to-left.
824	824
r245142	r245143
830	830	{
831	831	UINT32 grid = BITSWAP8(m_grid,0,1,2,3,4,5,6,7);
832	832	UINT32 plate = BITSWAP24(m_plate,23,22,21,20,19,16,17,18,11,10,9,8,0,2,3,1,4,5,6,7,12,13,14,15);
833
	833
834	834	display_matrix(19, 8, plate \| 0x100, grid); // plate 8 (maze) is always on
835	835	}
836	836
r245142	r245143
930	930	// C0(grid 0): input enable PL1
931	931	// D0(grid 4): input enable PL2
932	932	m_inp_mux = (m_grid & 1) \| (m_grid >> 3 & 2);
933
	933
934	934	// E1: speaker out
935	935	if (offset == NEC_UCOM4_PORTE)
936	936	m_speaker->level_w(data >> 1 & 1);

trunk/src/mess/drivers/imds2.c
r245142	r245143
89	89	#define IOC_BEEP_FREQ 3300
90	90
91	91	static ADDRESS_MAP_START(ipc_mem_map , AS_PROGRAM , 8 , imds2_state)
92		AM_RANGE(0x0000 , 0xffff) AM_READWRITE(ipc_mem_read, ipc_mem_write)
	92	AM_RANGE(0x0000 , 0xffff) AM_READWRITE(ipc_mem_read, ipc_mem_write)
93	93	ADDRESS_MAP_END
94	94
95	95	static ADDRESS_MAP_START(ipc_io_map , AS_IO , 8 , imds2_state)
96		ADDRESS_MAP_UNMAP_LOW
97		AM_RANGE(0xc0 , 0xc0) AM_READWRITE(imds2_ipc_dbbout_r , imds2_ipc_dbbin_data_w)
98		AM_RANGE(0xc1 , 0xc1) AM_READWRITE(imds2_ipc_status_r , imds2_ipc_dbbin_cmd_w)
99		AM_RANGE(0xfa , 0xfb) AM_READWRITE(imds2_ipclocpic_r , imds2_ipclocpic_w)
100		AM_RANGE(0xfc , 0xfd) AM_READWRITE(imds2_ipcsyspic_r , imds2_ipcsyspic_w)
101		AM_RANGE(0xff , 0xff) AM_WRITE(imds2_ipc_control_w)
	96	ADDRESS_MAP_UNMAP_LOW
	97	AM_RANGE(0xc0 , 0xc0) AM_READWRITE(imds2_ipc_dbbout_r , imds2_ipc_dbbin_data_w)
	98	AM_RANGE(0xc1 , 0xc1) AM_READWRITE(imds2_ipc_status_r , imds2_ipc_dbbin_cmd_w)
	99	AM_RANGE(0xfa , 0xfb) AM_READWRITE(imds2_ipclocpic_r , imds2_ipclocpic_w)
	100	AM_RANGE(0xfc , 0xfd) AM_READWRITE(imds2_ipcsyspic_r , imds2_ipcsyspic_w)
	101	AM_RANGE(0xff , 0xff) AM_WRITE(imds2_ipc_control_w)
102	102	ADDRESS_MAP_END
103	103
104		static ADDRESS_MAP_START(ioc_mem_map , AS_PROGRAM , 8 , imds2_state)
105		ADDRESS_MAP_UNMAP_HIGH
106		AM_RANGE(0x0000 , 0x1fff) AM_ROM
107		AM_RANGE(0x4000 , 0x5fff) AM_RAM
	104	static ADDRESS_MAP_START(ioc_mem_map , AS_PROGRAM , 8 , imds2_state)
	105	ADDRESS_MAP_UNMAP_HIGH
	106	AM_RANGE(0x0000 , 0x1fff) AM_ROM
	107	AM_RANGE(0x4000 , 0x5fff) AM_RAM
108	108	ADDRESS_MAP_END
109	109
110	110	static ADDRESS_MAP_START(ioc_io_map , AS_IO , 8 , imds2_state)
111		ADDRESS_MAP_UNMAP_HIGH
112		AM_RANGE(0x00 , 0x0f) AM_WRITE(imds2_ioc_dbbout_w)
113		AM_RANGE(0x20 , 0x2f) AM_WRITE(imds2_ioc_f0_w)
114		AM_RANGE(0x30 , 0x3f) AM_WRITE(imds2_ioc_set_f1_w)
115		AM_RANGE(0x40 , 0x4f) AM_WRITE(imds2_ioc_reset_f1_w)
116		AM_RANGE(0x50 , 0x5f) AM_WRITE(imds2_start_timer_w)
117		AM_RANGE(0x60 , 0x6f) AM_WRITE(imds2_miscout_w)
118		AM_RANGE(0x80 , 0x8f) AM_READ(imds2_miscin_r)
119		AM_RANGE(0x90 , 0x9f) AM_READ(imds2_kb_read)
120		AM_RANGE(0xa0 , 0xaf) AM_READ(imds2_ioc_status_r)
121		AM_RANGE(0xb0 , 0xbf) AM_READ(imds2_ioc_dbbin_r)
122		AM_RANGE(0xc0 , 0xcf) AM_DEVREADWRITE("iocfdc" , i8271_device , read , write)
123		AM_RANGE(0xd0 , 0xdf) AM_DEVREADWRITE("ioccrtc" , i8275_device , read , write)
124		AM_RANGE(0xe0 , 0xef) AM_DEVREADWRITE("ioctimer" , pit8253_device , read , write);
	111	ADDRESS_MAP_UNMAP_HIGH
	112	AM_RANGE(0x00 , 0x0f) AM_WRITE(imds2_ioc_dbbout_w)
	113	AM_RANGE(0x20 , 0x2f) AM_WRITE(imds2_ioc_f0_w)
	114	AM_RANGE(0x30 , 0x3f) AM_WRITE(imds2_ioc_set_f1_w)
	115	AM_RANGE(0x40 , 0x4f) AM_WRITE(imds2_ioc_reset_f1_w)
	116	AM_RANGE(0x50 , 0x5f) AM_WRITE(imds2_start_timer_w)
	117	AM_RANGE(0x60 , 0x6f) AM_WRITE(imds2_miscout_w)
	118	AM_RANGE(0x80 , 0x8f) AM_READ(imds2_miscin_r)
	119	AM_RANGE(0x90 , 0x9f) AM_READ(imds2_kb_read)
	120	AM_RANGE(0xa0 , 0xaf) AM_READ(imds2_ioc_status_r)
	121	AM_RANGE(0xb0 , 0xbf) AM_READ(imds2_ioc_dbbin_r)
	122	AM_RANGE(0xc0 , 0xcf) AM_DEVREADWRITE("iocfdc" , i8271_device , read , write)
	123	AM_RANGE(0xd0 , 0xdf) AM_DEVREADWRITE("ioccrtc" , i8275_device , read , write)
	124	AM_RANGE(0xe0 , 0xef) AM_DEVREADWRITE("ioctimer" , pit8253_device , read , write);
125	125	// DMA controller range doesn't extend to 0xff because register 0xfd needs to be read as 0xff
126	126	// This register is used by IOC firmware to detect DMA controller model (either 8237 or 8257)
127		AM_RANGE(0xf0 , 0xf8) AM_DEVREADWRITE("iocdma" , i8257_device , read , write)
	127	AM_RANGE(0xf0 , 0xf8) AM_DEVREADWRITE("iocdma" , i8257_device , read , write)
128	128	ADDRESS_MAP_END
129
	129
130	130	static ADDRESS_MAP_START(kb_io_map , AS_IO , 8 , imds2_state)
131		AM_RANGE(MCS48_PORT_P1 , MCS48_PORT_P1) AM_WRITE(imds2_kb_port_p1_w)
132		AM_RANGE(MCS48_PORT_P2 , MCS48_PORT_P2) AM_READ(imds2_kb_port_p2_r)
133		AM_RANGE(MCS48_PORT_T0 , MCS48_PORT_T0) AM_READ(imds2_kb_port_t0_r)
134		AM_RANGE(MCS48_PORT_T1 , MCS48_PORT_T1) AM_READ(imds2_kb_port_t1_r)
	131	AM_RANGE(MCS48_PORT_P1 , MCS48_PORT_P1) AM_WRITE(imds2_kb_port_p1_w)
	132	AM_RANGE(MCS48_PORT_P2 , MCS48_PORT_P2) AM_READ(imds2_kb_port_p2_r)
	133	AM_RANGE(MCS48_PORT_T0 , MCS48_PORT_T0) AM_READ(imds2_kb_port_t0_r)
	134	AM_RANGE(MCS48_PORT_T1 , MCS48_PORT_T1) AM_READ(imds2_kb_port_t1_r)
135	135	ADDRESS_MAP_END
136
	136
137	137	imds2_state::imds2_state(const machine_config &mconfig, device_type type, const char *tag)
138		: driver_device(mconfig , type , tag),
139		m_ipccpu(*this , "ipccpu"),
140		m_ipcsyspic(*this , "ipcsyspic"),
141		m_ipclocpic(*this , "ipclocpic"),
142		m_ioccpu(*this , "ioccpu"),
143		m_iocdma(*this , "iocdma"),
144		m_ioccrtc(*this , "ioccrtc"),
145		m_iocbeep(*this , "iocbeep"),
146		m_ioctimer(*this , "ioctimer"),
147		m_iocfdc(*this , "iocfdc"),
148		m_kbcpu(*this , "kbcpu"),
149		m_palette(*this , "palette"),
150		m_gfxdecode(*this, "gfxdecode"),
151		m_floppy0(*this , FLOPPY_0),
152		m_io_key0(*this , "KEY0"),
153		m_io_key1(*this , "KEY1"),
154		m_io_key2(*this , "KEY2"),
155		m_io_key3(*this , "KEY3"),
156		m_io_key4(*this , "KEY4"),
157		m_io_key5(*this , "KEY5"),
158		m_io_key6(*this , "KEY6"),
159		m_io_key7(*this , "KEY7"),
160		m_ioc_options(*this , "IOC_OPTS")
	138	: driver_device(mconfig , type , tag),
	139	m_ipccpu(*this , "ipccpu"),
	140	m_ipcsyspic(*this , "ipcsyspic"),
	141	m_ipclocpic(*this , "ipclocpic"),
	142	m_ioccpu(*this , "ioccpu"),
	143	m_iocdma(*this , "iocdma"),
	144	m_ioccrtc(*this , "ioccrtc"),
	145	m_iocbeep(*this , "iocbeep"),
	146	m_ioctimer(*this , "ioctimer"),
	147	m_iocfdc(*this , "iocfdc"),
	148	m_kbcpu(*this , "kbcpu"),
	149	m_palette(*this , "palette"),
	150	m_gfxdecode(*this, "gfxdecode"),
	151	m_floppy0(*this , FLOPPY_0),
	152	m_io_key0(*this , "KEY0"),
	153	m_io_key1(*this , "KEY1"),
	154	m_io_key2(*this , "KEY2"),
	155	m_io_key3(*this , "KEY3"),
	156	m_io_key4(*this , "KEY4"),
	157	m_io_key5(*this , "KEY5"),
	158	m_io_key6(*this , "KEY6"),
	159	m_io_key7(*this , "KEY7"),
	160	m_ioc_options(*this , "IOC_OPTS")
161	161	{
162	162	}
163	163
164	164	READ8_MEMBER(imds2_state::ipc_mem_read)
165	165	{
166		if (imds2_in_ipc_rom(offset)) {
167		return m_ipc_rom[ (offset & 0x07ff) \| ((offset & 0x1000) >> 1) ];
168		} else {
169		return m_ipc_ram[ offset ];
170		}
	166	if (imds2_in_ipc_rom(offset)) {
	167	return m_ipc_rom[ (offset & 0x07ff) \| ((offset & 0x1000) >> 1) ];
	168	} else {
	169	return m_ipc_ram[ offset ];
	170	}
171	171	}
172	172
173	173	WRITE8_MEMBER(imds2_state::ipc_mem_write)
174	174	{
175		if (!imds2_in_ipc_rom(offset)) {
176		m_ipc_ram[ offset ] = data;
177		}
	175	if (!imds2_in_ipc_rom(offset)) {
	176	m_ipc_ram[ offset ] = data;
	177	}
178	178	}
179	179
180	180	WRITE8_MEMBER(imds2_state::imds2_ipc_control_w)
181	181	{
182		// See A84, pg 28 of [1]
183		// b3 is ~(bit to be written)
184		// b2-b0 is ~(no. of bit to be written)
185		UINT8 mask = (1U << (~data & 0x07));
	182	// See A84, pg 28 of [1]
	183	// b3 is ~(bit to be written)
	184	// b2-b0 is ~(no. of bit to be written)
	185	UINT8 mask = (1U << (~data & 0x07));
186	186
187		if (BIT(data , 3)) {
188		m_ipc_control &= ~mask;
189		} else {
190		m_ipc_control \|= mask;
191		}
	187	if (BIT(data , 3)) {
	188	m_ipc_control &= ~mask;
	189	} else {
	190	m_ipc_control \|= mask;
	191	}
192	192	}
193	193
194	194	WRITE_LINE_MEMBER(imds2_state::imds2_ipc_intr)
195	195	{
196		m_ipccpu->set_input_line(I8085_INTR_LINE , (state != 0) && BIT(m_ipc_control , 2));
	196	m_ipccpu->set_input_line(I8085_INTR_LINE , (state != 0) && BIT(m_ipc_control , 2));
197	197	}
198	198
199	199	READ8_MEMBER(imds2_state::imds2_ipcsyspic_r)
200	200	{
201		return m_ipcsyspic->read(space , offset == 0);
	201	return m_ipcsyspic->read(space , offset == 0);
202	202	}
203	203
204	204	READ8_MEMBER(imds2_state::imds2_ipclocpic_r)
205	205	{
206		return m_ipclocpic->read(space , offset == 0);
	206	return m_ipclocpic->read(space , offset == 0);
207	207	}
208	208
209	209	WRITE8_MEMBER(imds2_state::imds2_ipcsyspic_w)
210	210	{
211		m_ipcsyspic->write(space , offset == 0 , data);
	211	m_ipcsyspic->write(space , offset == 0 , data);
212	212	}
213	213
214	214	WRITE8_MEMBER(imds2_state::imds2_ipclocpic_w)
215	215	{
216		m_ipclocpic->write(space , offset == 0 , data);
	216	m_ipclocpic->write(space , offset == 0 , data);
217	217	}
218	218
219	219	WRITE8_MEMBER(imds2_state::imds2_miscout_w)
220	220	{
221		m_miscout = data;
222		imds2_update_beeper();
223		// Send INTR to IPC
224		m_ipclocpic->ir6_w(BIT(m_miscout , 1));
	221	m_miscout = data;
	222	imds2_update_beeper();
	223	// Send INTR to IPC
	224	m_ipclocpic->ir6_w(BIT(m_miscout , 1));
225	225	}
226	226
227	227	READ8_MEMBER(imds2_state::imds2_miscin_r)
228	228	{
229		UINT8 res = m_ioc_options->read();
230		return res \| ((m_beeper_timer == 0) << 2);
	229	UINT8 res = m_ioc_options->read();
	230	return res \| ((m_beeper_timer == 0) << 2);
231	231	}
232	232
233	233	WRITE_LINE_MEMBER(imds2_state::imds2_beep_timer_w)
234	234	{
235		m_beeper_timer = state;
236		imds2_update_beeper();
	235	m_beeper_timer = state;
	236	imds2_update_beeper();
237	237	}
238	238
239	239	WRITE8_MEMBER(imds2_state::imds2_start_timer_w)
240	240	{
241		// Trigger timer 2 of ioctimer
242		m_ioctimer->write_gate2(0);
243		m_ioctimer->write_gate2(1);
	241	// Trigger timer 2 of ioctimer
	242	m_ioctimer->write_gate2(0);
	243	m_ioctimer->write_gate2(1);
244	244	}
245	245
246	246	READ8_MEMBER(imds2_state::imds2_kb_read)
247	247	{
248		return m_kbcpu->upi41_master_r(space , (offset & 2) >> 1);
	248	return m_kbcpu->upi41_master_r(space , (offset & 2) >> 1);
249	249	}
250	250
251	251	READ8_MEMBER(imds2_state::imds2_kb_port_p2_r)
252	252	{
253		if ((m_kb_p1 & 3) == 0) {
254		// Row selected
255		// Row number is encoded on bits P15..P12, they are "backwards" (P15 is LSB) and keyboard rows are encoded starting with value 2 on these bits (see A4, pg 56 of [1])
256		unsigned row = (m_kb_p1 >> 2) & 0x0f;
257		ioport_value data;
258
259		switch (row) {
260		case 4:
261		// Row 0
262		data = m_io_key0->read();
263		break;
	253	if ((m_kb_p1 & 3) == 0) {
	254	// Row selected
	255	// Row number is encoded on bits P15..P12, they are "backwards" (P15 is LSB) and keyboard rows are encoded starting with value 2 on these bits (see A4, pg 56 of [1])
	256	unsigned row = (m_kb_p1 >> 2) & 0x0f;
	257	ioport_value data;
264	258
265		case 12:
266		// Row 1
267		data = m_io_key1->read();
268		break;
	259	switch (row) {
	260	case 4:
	261	// Row 0
	262	data = m_io_key0->read();
	263	break;
269	264
270		case 2:
271		// Row 2
272		data = m_io_key2->read();
273		break;
	265	case 12:
	266	// Row 1
	267	data = m_io_key1->read();
	268	break;
274	269
275		case 10:
276		// Row 3
277		data = m_io_key3->read();
278		break;
	270	case 2:
	271	// Row 2
	272	data = m_io_key2->read();
	273	break;
279	274
280		case 6:
281		// Row 4
282		data = m_io_key4->read();
283		break;
	275	case 10:
	276	// Row 3
	277	data = m_io_key3->read();
	278	break;
284	279
285		case 14:
286		// Row 5
287		data = m_io_key5->read();
288		break;
	280	case 6:
	281	// Row 4
	282	data = m_io_key4->read();
	283	break;
289	284
290		case 1:
291		// Row 6
292		data = m_io_key6->read();
293		break;
	285	case 14:
	286	// Row 5
	287	data = m_io_key5->read();
	288	break;
294	289
295		case 9:
296		// Row 7
297		data = m_io_key7->read();
298		break;
	290	case 1:
	291	// Row 6
	292	data = m_io_key6->read();
	293	break;
299	294
300		default:
301		data = 0xff;
302		break;
303		}
304		return data & 0xff;
305		} else {
306		// No row selected
307		return 0xff;
308		}
	295	case 9:
	296	// Row 7
	297	data = m_io_key7->read();
	298	break;
	299
	300	default:
	301	data = 0xff;
	302	break;
	303	}
	304	return data & 0xff;
	305	} else {
	306	// No row selected
	307	return 0xff;
	308	}
309	309	}
310	310
311	311	WRITE8_MEMBER(imds2_state::imds2_kb_port_p1_w)
312	312	{
313		m_kb_p1 = data;
	313	m_kb_p1 = data;
314	314	}
315	315
316	316	READ8_MEMBER(imds2_state::imds2_kb_port_t0_r)
317	317	{
318		// T0 tied low
319		// It appears to be some kind of strapping option on kb hw
320		return 0;
	318	// T0 tied low
	319	// It appears to be some kind of strapping option on kb hw
	320	return 0;
321	321	}
322	322
323	323	READ8_MEMBER(imds2_state::imds2_kb_port_t1_r)
324	324	{
325		// T1 tied low
326		// It appears to be some kind of strapping option on kb hw
327		return 0;
	325	// T1 tied low
	326	// It appears to be some kind of strapping option on kb hw
	327	return 0;
328	328	}
329	329
330	330	WRITE8_MEMBER(imds2_state::imds2_ioc_dbbout_w)
331	331	{
332		m_ioc_obf = ~data;
333		// Set/reset OBF flag (b0)
334		m_ipc_ioc_status = ((offset & 1) == 0) \| (m_ipc_ioc_status & ~0x01);
	332	m_ioc_obf = ~data;
	333	// Set/reset OBF flag (b0)
	334	m_ipc_ioc_status = ((offset & 1) == 0) \| (m_ipc_ioc_status & ~0x01);
335	335	}
336	336
337	337	WRITE8_MEMBER(imds2_state::imds2_ioc_f0_w)
338	338	{
339		// Set/reset F0 flag (b2)
340		m_ipc_ioc_status = ((offset & 1) << 2) \| (m_ipc_ioc_status & ~0x04);
	339	// Set/reset F0 flag (b2)
	340	m_ipc_ioc_status = ((offset & 1) << 2) \| (m_ipc_ioc_status & ~0x04);
341	341	}
342	342
343	343	WRITE8_MEMBER(imds2_state::imds2_ioc_set_f1_w)
344	344	{
345		// Set F1 flag (b3)
346		m_ipc_ioc_status \|= 0x08;
	345	// Set F1 flag (b3)
	346	m_ipc_ioc_status \|= 0x08;
347	347	}
348	348
349	349	WRITE8_MEMBER(imds2_state::imds2_ioc_reset_f1_w)
350	350	{
351		// Reset F1 flag (b3)
352		m_ipc_ioc_status &= ~0x08;
	351	// Reset F1 flag (b3)
	352	m_ipc_ioc_status &= ~0x08;
353	353	}
354	354
355	355	READ8_MEMBER(imds2_state::imds2_ioc_status_r)
356	356	{
357		return (~m_ipc_ioc_status & 0x0f) \| 0xf0;
	357	return (~m_ipc_ioc_status & 0x0f) \| 0xf0;
358	358	}
359	359
360	360	READ8_MEMBER(imds2_state::imds2_ioc_dbbin_r)
361	361	{
362		// Reset IBF flag (b1)
363		m_ipc_ioc_status &= ~0x02;
364		return ~m_ioc_ibf;
	362	// Reset IBF flag (b1)
	363	m_ipc_ioc_status &= ~0x02;
	364	return ~m_ioc_ibf;
365	365	}
366	366
367	367	READ8_MEMBER(imds2_state::imds2_ipc_dbbout_r)
368	368	{
369		// Reset OBF flag (b0)
370		m_ipc_ioc_status &= ~0x01;
371		return m_ioc_obf;
	369	// Reset OBF flag (b0)
	370	m_ipc_ioc_status &= ~0x01;
	371	return m_ioc_obf;
372	372	}
373	373
374	374	READ8_MEMBER(imds2_state::imds2_ipc_status_r)
375	375	{
376		return m_ipc_ioc_status;
	376	return m_ipc_ioc_status;
377	377	}
378	378
379	379	WRITE8_MEMBER(imds2_state::imds2_ipc_dbbin_data_w)
380	380	{
381		// Set IBF flag (b1)
382		m_ipc_ioc_status \|= 0x02;
383		// Reset F1 flag (b3)
384		m_ipc_ioc_status &= ~0x08;
385		m_ioc_ibf = data;
	381	// Set IBF flag (b1)
	382	m_ipc_ioc_status \|= 0x02;
	383	// Reset F1 flag (b3)
	384	m_ipc_ioc_status &= ~0x08;
	385	m_ioc_ibf = data;
386	386	}
387	387
388	388	WRITE8_MEMBER(imds2_state::imds2_ipc_dbbin_cmd_w)
389	389	{
390		// Set IBF flag (b1)
391		m_ipc_ioc_status \|= 0x02;
392		// Set F1 flag (b3)
393		m_ipc_ioc_status \|= 0x08;
394		m_ioc_ibf = data;
	390	// Set IBF flag (b1)
	391	m_ipc_ioc_status \|= 0x02;
	392	// Set F1 flag (b3)
	393	m_ipc_ioc_status \|= 0x08;
	394	m_ioc_ibf = data;
395	395	}
396	396
397	397	WRITE_LINE_MEMBER(imds2_state::imds2_hrq_w)
398	398	{
399		// Should be propagated to HOLD input of IOC CPU
400		m_iocdma->hlda_w(state);
	399	// Should be propagated to HOLD input of IOC CPU
	400	m_iocdma->hlda_w(state);
401	401	}
402	402
403	403	READ8_MEMBER(imds2_state::imds2_ioc_mem_r)
404	404	{
405		address_space& prog_space = m_ioccpu->space(AS_PROGRAM);
406		return prog_space.read_byte(offset);
	405	address_space& prog_space = m_ioccpu->space(AS_PROGRAM);
	406	return prog_space.read_byte(offset);
407	407	}
408	408
409	409	WRITE8_MEMBER(imds2_state::imds2_ioc_mem_w)
410	410	{
411		address_space& prog_space = m_ioccpu->space(AS_PROGRAM);
412		return prog_space.write_byte(offset , data);
	411	address_space& prog_space = m_ioccpu->space(AS_PROGRAM);
	412	return prog_space.write_byte(offset , data);
413	413	}
414	414
415	415	I8275_DRAW_CHARACTER_MEMBER(imds2_state::crtc_display_pixels)
416	416	{
417		unsigned i;
418		const rgb_t *palette = m_palette->palette()->entry_list_raw();
419		UINT8 chargen_byte = m_chargen[ (linecount & 7) \| ((unsigned)charcode << 3) ];
420		UINT16 pixels;
	417	unsigned i;
	418	const rgb_t *palette = m_palette->palette()->entry_list_raw();
	419	UINT8 chargen_byte = m_chargen[ (linecount & 7) \| ((unsigned)charcode << 3) ];
	420	UINT16 pixels;
421	421
422		if (lten) {
423		pixels = ~0;
424		} else if (vsp != 0 \|\| (linecount & 8) != 0) {
425		pixels = 0;
426		} else {
427		// See [2], pg 58 for the very peculiar way of generating character images
428		// Here each half-pixel is translated into a full pixel
429		UINT16 exp_pix_l;
430		UINT16 exp_pix_r;
	422	if (lten) {
	423	pixels = ~0;
	424	} else if (vsp != 0 \|\| (linecount & 8) != 0) {
	425	pixels = 0;
	426	} else {
	427	// See [2], pg 58 for the very peculiar way of generating character images
	428	// Here each half-pixel is translated into a full pixel
	429	UINT16 exp_pix_l;
	430	UINT16 exp_pix_r;
431	431
432		exp_pix_l = (UINT16)chargen_byte;
433		exp_pix_l = ((exp_pix_l & 0x80) << 5) \|
434		((exp_pix_l & 0x40) << 4) \|
435		((exp_pix_l & 0x20) << 3) \|
436		((exp_pix_l & 0x10) << 2) \|
437		((exp_pix_l & 0x08) << 1) \|
438		(exp_pix_l & 0x04);
439		exp_pix_l \|= (exp_pix_l << 1);
440		exp_pix_r = exp_pix_l;
	432	exp_pix_l = (UINT16)chargen_byte;
	433	exp_pix_l = ((exp_pix_l & 0x80) << 5) \|
	434	((exp_pix_l & 0x40) << 4) \|
	435	((exp_pix_l & 0x20) << 3) \|
	436	((exp_pix_l & 0x10) << 2) \|
	437	((exp_pix_l & 0x08) << 1) \|
	438	(exp_pix_l & 0x04);
	439	exp_pix_l \|= (exp_pix_l << 1);
	440	exp_pix_r = exp_pix_l;
441	441
442		// Layout of exp_pix_l/r:
443		// Bit # : F E D C B A 9 8 7 6 5 4 3 2 1 0
444		// Bit of chargen_byte: 0 0 b7 b7 b6 b6 b5 b5 b4 b4 b3 b3 b2 b2 0 0
445		if ((chargen_byte & 2) == 0) {
446		exp_pix_l >>= 1;
447		}
448		exp_pix_l &= 0x3fc0;
	442	// Layout of exp_pix_l/r:
	443	// Bit # : F E D C B A 9 8 7 6 5 4 3 2 1 0
	444	// Bit of chargen_byte: 0 0 b7 b7 b6 b6 b5 b5 b4 b4 b3 b3 b2 b2 0 0
	445	if ((chargen_byte & 2) == 0) {
	446	exp_pix_l >>= 1;
	447	}
	448	exp_pix_l &= 0x3fc0;
449	449
450		if ((chargen_byte & 1) == 0) {
451		exp_pix_r >>= 1;
452		}
453		exp_pix_r &= 0x003e;
454
455		pixels = exp_pix_l \| exp_pix_r;
456		}
	450	if ((chargen_byte & 1) == 0) {
	451	exp_pix_r >>= 1;
	452	}
	453	exp_pix_r &= 0x003e;
457	454
458		if (rvv) {
459		pixels = ~pixels;
460		}
	455	pixels = exp_pix_l \| exp_pix_r;
	456	}
461	457
462		for (i = 0; i < 14; i++) {
463		bitmap.pix32(y, x + i) = palette[ (pixels & (1U << (13 - i))) != 0 ];
464		}
	458	if (rvv) {
	459	pixels = ~pixels;
	460	}
	461
	462	for (i = 0; i < 14; i++) {
	463	bitmap.pix32(y, x + i) = palette[ (pixels & (1U << (13 - i))) != 0 ];
	464	}
465	465	}
466	466
467	467	void imds2_state::driver_start()
468	468	{
469		// Allocate 64k for IPC RAM
470		m_ipc_ram.resize(0x10000);
	469	// Allocate 64k for IPC RAM
	470	m_ipc_ram.resize(0x10000);
471	471
472		memory_region *ipcrom = memregion("ipcrom");
473		if (ipcrom == NULL) {
474		fatalerror("Unable to find IPC ROM region\n");
475		} else {
476		m_ipc_rom = ipcrom->base();
477		}
	472	memory_region *ipcrom = memregion("ipcrom");
	473	if (ipcrom == NULL) {
	474	fatalerror("Unable to find IPC ROM region\n");
	475	} else {
	476	m_ipc_rom = ipcrom->base();
	477	}
478	478	}
479	479
480	480	void imds2_state::machine_start()
481	481	{
482		m_floppy0->floppy_mon_w(0);
483		m_floppy0->floppy_drive_set_ready_state(1 , 0);
	482	m_floppy0->floppy_mon_w(0);
	483	m_floppy0->floppy_drive_set_ready_state(1 , 0);
484	484	}
485	485
486	486	void imds2_state::video_start()
487	487	{
488		m_chargen = memregion("gfx1")->base();
	488	m_chargen = memregion("gfx1")->base();
489	489	}
490	490
491	491	void imds2_state::machine_reset()
492	492	{
493		m_iocbeep->set_frequency(IOC_BEEP_FREQ);
494		m_ipc_control = 0x00;
495		m_ipc_ioc_status = 0x0f;
	493	m_iocbeep->set_frequency(IOC_BEEP_FREQ);
	494	m_ipc_control = 0x00;
	495	m_ipc_ioc_status = 0x0f;
496	496	}
497	497
498	498	bool imds2_state::imds2_in_ipc_rom(offs_t offset) const
499	499	{
500		offs_t masked_offset = offset & 0xf800;
	500	offs_t masked_offset = offset & 0xf800;
501	501
502		// Region 0000-07ff is in ROM when START_UP/ == 0 && SEL_BOOT/ == 0
503		if (masked_offset == 0x0000 && (m_ipc_control & 0x28) == 0) {
504		return true;
505		}
	502	// Region 0000-07ff is in ROM when START_UP/ == 0 && SEL_BOOT/ == 0
	503	if (masked_offset == 0x0000 && (m_ipc_control & 0x28) == 0) {
	504	return true;
	505	}
506	506
507		// Region e800-efff is in ROM when SEL_BOOT/ == 0
508		if (masked_offset == 0xe800 && (m_ipc_control & 0x08) == 0) {
509		return true;
510		}
	507	// Region e800-efff is in ROM when SEL_BOOT/ == 0
	508	if (masked_offset == 0xe800 && (m_ipc_control & 0x08) == 0) {
	509	return true;
	510	}
511	511
512		// Region f800-ffff is always in ROM
513		if (masked_offset == 0xf800) {
514		return true;
515		}
	512	// Region f800-ffff is always in ROM
	513	if (masked_offset == 0xf800) {
	514	return true;
	515	}
516	516
517		return false;
	517	return false;
518	518	}
519
	519
520	520	void imds2_state::imds2_update_beeper(void)
521	521	{
522		m_iocbeep->set_state(m_beeper_timer == 0 && BIT(m_miscout , 0) == 0);
	522	m_iocbeep->set_state(m_beeper_timer == 0 && BIT(m_miscout , 0) == 0);
523	523	}
524	524
525	525	static INPUT_PORTS_START(imds2)
526		// See [1], pg 56 for key matrix layout
527		// See [1], pg 57 for keyboard layout
528		PORT_START("KEY0")
529		PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t') // OK
530		PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`')
531		PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') // OK
532		PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13) // OK
533		PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
534		PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*') // '
535		PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>') // .
536		PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
	526	// See [1], pg 56 for key matrix layout
	527	// See [1], pg 57 for keyboard layout
	528	PORT_START("KEY0")
	529	PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t') // OK
	530	PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`')
	531	PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') // OK
	532	PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13) // OK
	533	PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
	534	PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*') // '
	535	PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>') // .
	536	PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
537	537
538		PORT_START("KEY1")
539		PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z') // OK
540		PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X') // OK
541		PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M') // OK
542		PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V') // OK
543		PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_UNUSED)
544		PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C') // OK
545		PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N') // OK
546		PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B') // OK
	538	PORT_START("KEY1")
	539	PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z') // OK
	540	PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X') // OK
	541	PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M') // OK
	542	PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V') // OK
	543	PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_UNUSED)
	544	PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C') // OK
	545	PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N') // OK
	546	PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B') // OK
547	547
548		PORT_START("KEY2")
549		PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('~') // OK
550		PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
551		PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O') // OK
552		PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L') // OK
553		PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') // OK
554		PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=') // OK
555		PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P') // OK
556		PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
	548	PORT_START("KEY2")
	549	PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('~') // OK
	550	PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')
	551	PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O') // OK
	552	PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L') // OK
	553	PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') // OK
	554	PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=') // OK
	555	PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P') // OK
	556	PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
557	557
558		PORT_START("KEY3")
559		PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') // OK
560		PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') // OK
561		PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') // OK
562		PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G') // OK
563		PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') // OK
564		PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F') // OK
565		PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J') // OK
566		PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') // OK
	558	PORT_START("KEY3")
	559	PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') // OK
	560	PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') // OK
	561	PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') // OK
	562	PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G') // OK
	563	PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') // OK
	564	PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F') // OK
	565	PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J') // OK
	566	PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') // OK
567	567
568		PORT_START("KEY4")
569		PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W') // OK
570		PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E') // OK
571		PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') // OK
572		PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T') // OK
573		PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q') // OK
574		PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') // OK
575		PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U') // OK
576		PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') // OK
	568	PORT_START("KEY4")
	569	PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W') // OK
	570	PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E') // OK
	571	PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') // OK
	572	PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T') // OK
	573	PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q') // OK
	574	PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') // OK
	575	PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U') // OK
	576	PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') // OK
577	577
578		PORT_START("KEY5")
579		PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"') // OK
580		PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#') // OK
581		PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(') // OK
582		PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') // OK
583		PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') // OK
584		PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$') // OK
585		PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'') // OK
586		PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') // OK
	578	PORT_START("KEY5")
	579	PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"') // OK
	580	PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#') // OK
	581	PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(') // OK
	582	PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') // OK
	583	PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') // OK
	584	PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$') // OK
	585	PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'') // OK
	586	PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') // OK
587	587
588		PORT_START("KEY6")
589		PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) // BS
590		PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_HOME) PORT_CHAR(UCHAR_MAMEKEY(HOME)) // OK
591		PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('\|') // OK
592		PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) // OK
593		PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2) // OK
594		PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT)) // OK
595		PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}')
596		PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP)) // OK
	588	PORT_START("KEY6")
	589	PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) // BS
	590	PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_HOME) PORT_CHAR(UCHAR_MAMEKEY(HOME)) // OK
	591	PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('\|') // OK
	592	PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) // OK
	593	PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2) // OK
	594	PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT)) // OK
	595	PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}')
	596	PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP)) // OK
597	597
598		PORT_START("KEY7")
599		PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC)) // OK
600		PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) // OK
601		PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('_') PORT_CHAR('^')
602		PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1) // OK
603		PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_LALT) PORT_CHAR(UCHAR_MAMEKEY(LALT)) // OK
604		PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
605		PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_UNUSED)
606		PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_UNUSED)
	598	PORT_START("KEY7")
	599	PORT_BIT(0x01 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC)) // OK
	600	PORT_BIT(0x02 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) // OK
	601	PORT_BIT(0x04 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('_') PORT_CHAR('^')
	602	PORT_BIT(0x08 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1) // OK
	603	PORT_BIT(0x10 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_LALT) PORT_CHAR(UCHAR_MAMEKEY(LALT)) // OK
	604	PORT_BIT(0x20 , IP_ACTIVE_LOW , IPT_KEYBOARD) PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
	605	PORT_BIT(0x40 , IP_ACTIVE_LOW , IPT_UNUSED)
	606	PORT_BIT(0x80 , IP_ACTIVE_LOW , IPT_UNUSED)
607	607
608		// Options on IOC: see [1], pg 40
609		PORT_START("IOC_OPTS")
610		PORT_DIPNAME(0x80 , 0x80 , "Keyboard present")
611		PORT_DIPSETTING(0x80 , DEF_STR(Yes))
612		PORT_DIPSETTING(0x00 , DEF_STR(No))
613		PORT_DIPNAME(0x28 , 0x00 , "IOC mode")
614		PORT_DIPSETTING(0x00 , "On line")
615		PORT_DIPSETTING(0x08 , "Local")
616		PORT_DIPSETTING(0x20 , "Diagnostic")
617		PORT_DIPNAME(0x02 , 0x00 , "Floppy present")
618		PORT_DIPSETTING(0x02 , DEF_STR(Yes))
619		PORT_DIPSETTING(0x00 , DEF_STR(No))
620		PORT_DIPNAME(0x01 , 0x01 , "CRT frame frequency")
621		PORT_DIPSETTING(0x01 , "50 Hz")
622		PORT_DIPSETTING(0x00 , "60 Hz")
	608	// Options on IOC: see [1], pg 40
	609	PORT_START("IOC_OPTS")
	610	PORT_DIPNAME(0x80 , 0x80 , "Keyboard present")
	611	PORT_DIPSETTING(0x80 , DEF_STR(Yes))
	612	PORT_DIPSETTING(0x00 , DEF_STR(No))
	613	PORT_DIPNAME(0x28 , 0x00 , "IOC mode")
	614	PORT_DIPSETTING(0x00 , "On line")
	615	PORT_DIPSETTING(0x08 , "Local")
	616	PORT_DIPSETTING(0x20 , "Diagnostic")
	617	PORT_DIPNAME(0x02 , 0x00 , "Floppy present")
	618	PORT_DIPSETTING(0x02 , DEF_STR(Yes))
	619	PORT_DIPSETTING(0x00 , DEF_STR(No))
	620	PORT_DIPNAME(0x01 , 0x01 , "CRT frame frequency")
	621	PORT_DIPSETTING(0x01 , "50 Hz")
	622	PORT_DIPSETTING(0x00 , "60 Hz")
623	623	INPUT_PORTS_END
624	624
625	625	static GFXLAYOUT_RAW(imds2_charlayout , 8 , 8 , 8 , 64)
626	626
627	627	static GFXDECODE_START(imds2)
628		GFXDECODE_ENTRY("gfx1" , 0x0000 , imds2_charlayout , 0 , 1)
	628	GFXDECODE_ENTRY("gfx1" , 0x0000 , imds2_charlayout , 0 , 1)
629	629	GFXDECODE_END
630	630
631	631	static LEGACY_FLOPPY_OPTIONS_START(imds2)
r245142	r245143
633	633
634	634	static const floppy_interface imds2_floppy_interface =
635	635	{
636		FLOPPY_STANDARD_8_SSSD,
637		LEGACY_FLOPPY_OPTIONS_NAME(imds2),
638		"floppy_8"
	636	FLOPPY_STANDARD_8_SSSD,
	637	LEGACY_FLOPPY_OPTIONS_NAME(imds2),
	638	"floppy_8"
639	639	};
640	640
641	641	static MACHINE_CONFIG_START(imds2 , imds2_state)
642		MCFG_CPU_ADD("ipccpu" , I8085A , IPC_XTAL_Y2 / 2) // 4 MHz
643		MCFG_CPU_PROGRAM_MAP(ipc_mem_map)
644		MCFG_CPU_IO_MAP(ipc_io_map)
645		MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("ipcsyspic" , pic8259_device , inta_cb)
646		MCFG_QUANTUM_TIME(attotime::from_hz(100))
	642	MCFG_CPU_ADD("ipccpu" , I8085A , IPC_XTAL_Y2 / 2) // 4 MHz
	643	MCFG_CPU_PROGRAM_MAP(ipc_mem_map)
	644	MCFG_CPU_IO_MAP(ipc_io_map)
	645	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("ipcsyspic" , pic8259_device , inta_cb)
	646	MCFG_QUANTUM_TIME(attotime::from_hz(100))
647	647
648		MCFG_PIC8259_ADD("ipcsyspic" , WRITELINE(imds2_state , imds2_ipc_intr) , VCC , NULL)
649		MCFG_PIC8259_ADD("ipclocpic" , DEVWRITELINE("ipcsyspic" , pic8259_device , ir7_w) , VCC , NULL)
650
651		MCFG_CPU_ADD("ioccpu" , I8080A , IOC_XTAL_Y2 / 9) // 2.448 MHz
652		MCFG_CPU_PROGRAM_MAP(ioc_mem_map)
653		MCFG_CPU_IO_MAP(ioc_io_map)
654		MCFG_QUANTUM_TIME(attotime::from_hz(100))
	648	MCFG_PIC8259_ADD("ipcsyspic" , WRITELINE(imds2_state , imds2_ipc_intr) , VCC , NULL)
	649	MCFG_PIC8259_ADD("ipclocpic" , DEVWRITELINE("ipcsyspic" , pic8259_device , ir7_w) , VCC , NULL)
655	650
656		// The IOC CRT hw is a bit complex, as the character clock (CCLK) to i8275
657		// is varied according to the part of the video frame being scanned and according to
658		// the 50/60 Hz option jumper (W8).
659		// The basic clock (BCLK) runs at 22.032 MHz.
660		// CCLK = BCLK / 14 when in the active region of video
661		// CCLK = BCLK / 12 when in horizontal retrace (HRTC=1)
662		// CCLK = BCLK / 10 when in horizontal retrace of "short scan lines" (50 Hz only)
663		//
664		// *** 50 Hz timings ***
665		// 80 chars/row, 26 chars/h. retrace, 11 scan lines/row, 25 active rows, 3 vertical retrace rows
666		// Scan line: 80 chars * 14 BCLK + 26 chars * 12 BCLK = 1432 BCLK (64.996 usec)
667		// Scan row: 11 * scan lines = 15752 BCLK (714.960 usec)
668		// "Short" scan line: 80 chars * 14 BCLK + 26 chars * 10 BCLK = 1380 BCLK (62.636 usec)
669		// Frame: 28 scan rows (8 scan lines of 27th row are short): 27 * scan row + 3 * scan line + 8 * short scan line: 440640 BCLK (20 msec)
670		//
671		// *** 60 Hz timings ***
672		// 80 chars/row, 20 chars/h. retrace, 10 scan lines/row, 25 active rows, 2 vertical retrace rows
673		// Scan line: 80 chars * 14 BCLK + 20 chars * 12 BCLK = 1360 BCLK (61.728 usec)
674		// Scan row: 10 * scan lines = 13600 BCLK (617.284 usec)
675		// Frame: 27 scan rows : 367200 BCLK (16.667 msec)
676		//
677		// Clock here is semi-bogus: it gives the correct frame frequency at 50 Hz (with the incorrect
678		// assumption that CCLK is fixed at BCLK / 14)
679		MCFG_DEVICE_ADD("ioccrtc" , I8275 , 22853600 / 14)
680		MCFG_I8275_CHARACTER_WIDTH(14)
681		MCFG_I8275_DRAW_CHARACTER_CALLBACK_OWNER(imds2_state , crtc_display_pixels)
682		MCFG_I8275_DRQ_CALLBACK(DEVWRITELINE("iocdma" , i8257_device , dreq2_w))
683		MCFG_I8275_IRQ_CALLBACK(INPUTLINE("ioccpu" , I8085_INTR_LINE))
	651	MCFG_CPU_ADD("ioccpu" , I8080A , IOC_XTAL_Y2 / 9) // 2.448 MHz
	652	MCFG_CPU_PROGRAM_MAP(ioc_mem_map)
	653	MCFG_CPU_IO_MAP(ioc_io_map)
	654	MCFG_QUANTUM_TIME(attotime::from_hz(100))
684	655
685		MCFG_SCREEN_ADD("screen" , RASTER)
686		MCFG_SCREEN_UPDATE_DEVICE("ioccrtc" , i8275_device , screen_update)
687		MCFG_SCREEN_REFRESH_RATE(50)
688		MCFG_GFXDECODE_ADD("gfxdecode" , "palette" , imds2)
689		MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
	656	// The IOC CRT hw is a bit complex, as the character clock (CCLK) to i8275
	657	// is varied according to the part of the video frame being scanned and according to
	658	// the 50/60 Hz option jumper (W8).
	659	// The basic clock (BCLK) runs at 22.032 MHz.
	660	// CCLK = BCLK / 14 when in the active region of video
	661	// CCLK = BCLK / 12 when in horizontal retrace (HRTC=1)
	662	// CCLK = BCLK / 10 when in horizontal retrace of "short scan lines" (50 Hz only)
	663	//
	664	// *** 50 Hz timings ***
	665	// 80 chars/row, 26 chars/h. retrace, 11 scan lines/row, 25 active rows, 3 vertical retrace rows
	666	// Scan line: 80 chars * 14 BCLK + 26 chars * 12 BCLK = 1432 BCLK (64.996 usec)
	667	// Scan row: 11 * scan lines = 15752 BCLK (714.960 usec)
	668	// "Short" scan line: 80 chars * 14 BCLK + 26 chars * 10 BCLK = 1380 BCLK (62.636 usec)
	669	// Frame: 28 scan rows (8 scan lines of 27th row are short): 27 * scan row + 3 * scan line + 8 * short scan line: 440640 BCLK (20 msec)
	670	//
	671	// *** 60 Hz timings ***
	672	// 80 chars/row, 20 chars/h. retrace, 10 scan lines/row, 25 active rows, 2 vertical retrace rows
	673	// Scan line: 80 chars * 14 BCLK + 20 chars * 12 BCLK = 1360 BCLK (61.728 usec)
	674	// Scan row: 10 * scan lines = 13600 BCLK (617.284 usec)
	675	// Frame: 27 scan rows : 367200 BCLK (16.667 msec)
	676	//
	677	// Clock here is semi-bogus: it gives the correct frame frequency at 50 Hz (with the incorrect
	678	// assumption that CCLK is fixed at BCLK / 14)
	679	MCFG_DEVICE_ADD("ioccrtc" , I8275 , 22853600 / 14)
	680	MCFG_I8275_CHARACTER_WIDTH(14)
	681	MCFG_I8275_DRAW_CHARACTER_CALLBACK_OWNER(imds2_state , crtc_display_pixels)
	682	MCFG_I8275_DRQ_CALLBACK(DEVWRITELINE("iocdma" , i8257_device , dreq2_w))
	683	MCFG_I8275_IRQ_CALLBACK(INPUTLINE("ioccpu" , I8085_INTR_LINE))
690	684
691		MCFG_SPEAKER_STANDARD_MONO("mono")
692		MCFG_SOUND_ADD("iocbeep" , BEEP , 0)
693		MCFG_SOUND_ROUTE(ALL_OUTPUTS , "mono" , 1.00)
694
695		MCFG_DEVICE_ADD("iocdma" , I8257 , IOC_XTAL_Y2 / 9)
696		MCFG_I8257_OUT_HRQ_CB(WRITELINE(imds2_state, imds2_hrq_w))
697		MCFG_I8257_IN_MEMR_CB(READ8(imds2_state , imds2_ioc_mem_r))
698		MCFG_I8257_OUT_MEMW_CB(WRITE8(imds2_state , imds2_ioc_mem_w))
699		MCFG_I8257_IN_IOR_1_CB(DEVREAD8("iocfdc" , i8271_device , dack_r))
700		MCFG_I8257_OUT_IOW_1_CB(DEVWRITE8("iocfdc" , i8271_device , dack_w))
701		MCFG_I8257_OUT_IOW_2_CB(DEVWRITE8("ioccrtc" , i8275_device , dack_w))
	685	MCFG_SCREEN_ADD("screen" , RASTER)
	686	MCFG_SCREEN_UPDATE_DEVICE("ioccrtc" , i8275_device , screen_update)
	687	MCFG_SCREEN_REFRESH_RATE(50)
	688	MCFG_GFXDECODE_ADD("gfxdecode" , "palette" , imds2)
	689	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
702	690
703		MCFG_DEVICE_ADD("ioctimer" , PIT8253 , 0)
704		MCFG_PIT8253_CLK0(IOC_XTAL_Y1 / 4)
705		MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("ioctimer" , pit8253_device , write_clk2));
706		MCFG_PIT8253_OUT2_HANDLER(WRITELINE(imds2_state , imds2_beep_timer_w));
	691	MCFG_SPEAKER_STANDARD_MONO("mono")
	692	MCFG_SOUND_ADD("iocbeep" , BEEP , 0)
	693	MCFG_SOUND_ROUTE(ALL_OUTPUTS , "mono" , 1.00)
707	694
708		MCFG_DEVICE_ADD("iocfdc" , I8271 , IOC_XTAL_Y1 / 2)
709		MCFG_I8271_DRQ_CALLBACK(DEVWRITELINE("iocdma" , i8257_device , dreq1_w))
710		MCFG_I8271_FLOPPIES(FLOPPY_0 , FLOPPY_1)
711
712		MCFG_LEGACY_FLOPPY_DRIVE_ADD(FLOPPY_0, imds2_floppy_interface)
713
714		MCFG_CPU_ADD("kbcpu", I8741, XTAL_3_579545MHz) /* 3.579545 MHz */
715		MCFG_CPU_IO_MAP(kb_io_map)
716		MCFG_QUANTUM_TIME(attotime::from_hz(100))
	695	MCFG_DEVICE_ADD("iocdma" , I8257 , IOC_XTAL_Y2 / 9)
	696	MCFG_I8257_OUT_HRQ_CB(WRITELINE(imds2_state, imds2_hrq_w))
	697	MCFG_I8257_IN_MEMR_CB(READ8(imds2_state , imds2_ioc_mem_r))
	698	MCFG_I8257_OUT_MEMW_CB(WRITE8(imds2_state , imds2_ioc_mem_w))
	699	MCFG_I8257_IN_IOR_1_CB(DEVREAD8("iocfdc" , i8271_device , dack_r))
	700	MCFG_I8257_OUT_IOW_1_CB(DEVWRITE8("iocfdc" , i8271_device , dack_w))
	701	MCFG_I8257_OUT_IOW_2_CB(DEVWRITE8("ioccrtc" , i8275_device , dack_w))
	702
	703	MCFG_DEVICE_ADD("ioctimer" , PIT8253 , 0)
	704	MCFG_PIT8253_CLK0(IOC_XTAL_Y1 / 4)
	705	MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("ioctimer" , pit8253_device , write_clk2));
	706	MCFG_PIT8253_OUT2_HANDLER(WRITELINE(imds2_state , imds2_beep_timer_w));
	707
	708	MCFG_DEVICE_ADD("iocfdc" , I8271 , IOC_XTAL_Y1 / 2)
	709	MCFG_I8271_DRQ_CALLBACK(DEVWRITELINE("iocdma" , i8257_device , dreq1_w))
	710	MCFG_I8271_FLOPPIES(FLOPPY_0 , FLOPPY_1)
	711
	712	MCFG_LEGACY_FLOPPY_DRIVE_ADD(FLOPPY_0, imds2_floppy_interface)
	713
	714	MCFG_CPU_ADD("kbcpu", I8741, XTAL_3_579545MHz) /* 3.579545 MHz */
	715	MCFG_CPU_IO_MAP(kb_io_map)
	716	MCFG_QUANTUM_TIME(attotime::from_hz(100))
717	717	MACHINE_CONFIG_END
718	718
719	719	ROM_START(imds2)
720		// ROM definition of IPC cpu (8085A)
721		ROM_REGION(0x1000 , "ipcrom" , 0)
722		ROM_LOAD("ipc_a82.bin" , 0x0000 , 0x1000 , CRC(0889394f) SHA1(b7525baf1884a7d67402dea4b5566016a9861ef2))
723
724		// ROM definition of IOC cpu (8080A)
725		ROM_REGION(0x2000 , "ioccpu" , 0)
726		ROM_LOAD("ioc_a50.bin" , 0x0000 , 0x0800 , CRC(d9f926a1) SHA1(bd9d0f7458acc2806120a6dbaab9c48be315b060))
727		ROM_LOAD("ioc_a51.bin" , 0x0800 , 0x0800 , CRC(6aa2f86c) SHA1(d3a5314d86e3366545b4c97b29e323dfab383d5f))
728		ROM_LOAD("ioc_a52.bin" , 0x1000 , 0x0800 , CRC(b88a38d5) SHA1(934716a1daec852f4d1f846510f42408df0c9584))
729		ROM_LOAD("ioc_a53.bin" , 0x1800 , 0x0800 , CRC(c8df4bb9) SHA1(2dfb921e94ae7033a7182457b2f00657674d1b77))
730		// ROM definition of keyboard controller (8741)
731		ROM_REGION(0x400 , "kbcpu" , 0)
732		ROM_LOAD("kbd511.bin" , 0 , 0x400 , CRC(ba7c4303) SHA1(19899af732d0ae1247bfc79979b1ee5f339ee5cf))
733		// ROM definition of character generator (2708, A19 on IOC)
734		ROM_REGION(0x400 , "gfx1" , 0)
735		ROM_LOAD ("ioc_a19.bin" , 0x0000 , 0x0400 , CRC(47487d0f) SHA1(0ed98f9f06622949ee3cc2ffc572fb9702db0f81))
	720	// ROM definition of IPC cpu (8085A)
	721	ROM_REGION(0x1000 , "ipcrom" , 0)
	722	ROM_LOAD("ipc_a82.bin" , 0x0000 , 0x1000 , CRC(0889394f) SHA1(b7525baf1884a7d67402dea4b5566016a9861ef2))
	723
	724	// ROM definition of IOC cpu (8080A)
	725	ROM_REGION(0x2000 , "ioccpu" , 0)
	726	ROM_LOAD("ioc_a50.bin" , 0x0000 , 0x0800 , CRC(d9f926a1) SHA1(bd9d0f7458acc2806120a6dbaab9c48be315b060))
	727	ROM_LOAD("ioc_a51.bin" , 0x0800 , 0x0800 , CRC(6aa2f86c) SHA1(d3a5314d86e3366545b4c97b29e323dfab383d5f))
	728	ROM_LOAD("ioc_a52.bin" , 0x1000 , 0x0800 , CRC(b88a38d5) SHA1(934716a1daec852f4d1f846510f42408df0c9584))
	729	ROM_LOAD("ioc_a53.bin" , 0x1800 , 0x0800 , CRC(c8df4bb9) SHA1(2dfb921e94ae7033a7182457b2f00657674d1b77))
	730	// ROM definition of keyboard controller (8741)
	731	ROM_REGION(0x400 , "kbcpu" , 0)
	732	ROM_LOAD("kbd511.bin" , 0 , 0x400 , CRC(ba7c4303) SHA1(19899af732d0ae1247bfc79979b1ee5f339ee5cf))
	733	// ROM definition of character generator (2708, A19 on IOC)
	734	ROM_REGION(0x400 , "gfx1" , 0)
	735	ROM_LOAD ("ioc_a19.bin" , 0x0000 , 0x0400 , CRC(47487d0f) SHA1(0ed98f9f06622949ee3cc2ffc572fb9702db0f81))
736	736	ROM_END
737	737
738	738	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */

trunk/src/mess/drivers/mbdtower.c
r245142	r245143
14	14	The emulated part is the centerpiece, a black tower with a rotating card
15	15	panel and LED digits for displaying health, amount of gold, etc. As far
16	16	as MESS is concerned, the game works fine.
17
	17
18	18	To start up the game, first press [MOVE], the machine now does a self-test.
19	19	Then select level and number of players and the game will start. Read the
20	20	official manual on how to play the game.
r245142	r245143
64	64	m_display_maxx = 7;
65	65	m_display_maxy = 3;
66	66	m_display_segmask[1] = m_display_segmask[2] = 0x7f;
67
	67
68	68	// update current state
69	69	if (~m_r & 0x10)
70	70	{
r245142	r245143
89	89	if (m_motor_on)
90	90	{
91	91	m_motor_pos = (m_motor_pos - 1) & 0x7f;
92
	92
93	93	// give it some time to spin out when it's turned off
94	94	if (m_r & 0x200)
95		m_motor_decay += (m_motor_decay < 6);
	95	m_motor_decay += (m_motor_decay < 4);
96	96	else if (m_motor_decay > 0)
97	97	m_motor_decay--;
98	98	else
r245142	r245143
105	105	m_sensor_blind = false;
106	106	else
107	107	m_sensor_blind = true;
108
	108
109	109	// on change, output info
110	110	if (m_motor_pos != m_motor_pos_prev)
111	111	output_set_value("motor_pos", 100 * (m_motor_pos / (float)0x80));
112
	112
113	113	/* 3 display cards per hole, like this:
114
115		(0) <---- display increments this way <---- (7)
116	114
117		VICTORY WIZARD DRAGON GOLD KEY SCOUT WARRIOR (void) CURSED
118		WARRIORS BAZAAR CLOSED SWORD SILVER KEY HEALER FOOD (void) LOST
119		BRIGANDS KEY MISSING PEGASUS BRASS KEY GOLD BEAST (void) PLAGUE
	115	(0) <---- display increments this way <---- (7)
	116
	117	CURSED VICTORY WIZARD DRAGON GOLD KEY SCOUT WARRIOR (void)
	118	LOST WARRIORS BAZAAR CLOSED SWORD SILVER KEY HEALER FOOD (void)
	119	PLAGUE BRIGANDS KEY MISSING PEGASUS BRASS KEY GOLD BEAST (void)
120	120	*/
121	121	int card_pos = m_motor_pos >> 4 & 7;
122	122	if (card_pos != (m_motor_pos_prev >> 4 & 7))
123	123	output_set_value("card_pos", card_pos);
124
	124
125	125	m_motor_pos_prev = m_motor_pos;
126	126	}
127	127
r245142	r245143
137	137	{
138	138	// R0-R2: input mux
139	139	m_inp_mux = data & 7;
140
	140
141	141	// R9: motor on
142	142	if ((m_r ^ data) & 0x200)
143	143	output_set_value("motor_on", data >> 9 & 1);
r245142	r245143
150	150	// R8: rotation sensor led
151	151	m_r = data;
152	152	mbdtower_display();
153
	153
154	154	// R10: speaker out
155	155	m_speaker->level_w(~data >> 4 & data >> 10 & 1);
156	156	}
r245142	r245143
182	182	(green) (l.blue) (red)
183	183	[YES/ [REPEAT] [NO/
184	184	BUY] END]
185
	185
186	186	(yellow) (blue) (white)
187	187	[HAGGLE] [BAZAAR] [CLEAR]
188
	188
189	189	(blue) (blue) (blue)
190	190	[TOMB/ [MOVE] [SANCTUARY/
191	191	RUIN] CITADEL]
192
	192
193	193	(orange) (blue) (d.yellow)
194	194	[DARK [FRONTIER] [INVENTORY]
195	195	TOWER]
r245142	r245143
233	233	m_motor_decay = 0;
234	234	m_motor_on = false;
235	235	m_sensor_blind = false;
236
	236
237	237	save_item(NAME(m_motor_pos));
238	238	/* save_item(NAME(m_motor_pos_prev)); */ // don't save!
239	239	save_item(NAME(m_motor_decay));
r245142	r245143
281	281	ROM_END
282	282
283	283
284		CONS( 1981, mbdtower, 0, 0, mbdtower, mbdtower, driver_device, 0, "Milton Bradley", "Dark Tower (Milton Bradley)", GAME_SUPPORTS_SAVE \| GAME_MECHANICAL ~~\| GAME_NOT_WORKING~~ )
	284	CONS( 1981, mbdtower, 0, 0, mbdtower, mbdtower, driver_device, 0, "Milton Bradley", "Dark Tower (Milton Bradley)", GAME_SUPPORTS_SAVE \| GAME_MECHANICAL )

trunk/src/mess/drivers/snes.c
r245142	r245143
1005	1005	*************************************/
1006	1006
1007	1007	static ADDRESS_MAP_START( snes_map, AS_PROGRAM, 8, snes_console_state )
1008		// AM_RANGE(0x000000, 0x7dffff) AM_READWRITE(snes20_lo_r, snes20_lo_w)
	1008	// AM_RANGE(0x000000, 0x7dffff) AM_READWRITE(snes20_lo_r, snes20_lo_w)
1009	1009	AM_RANGE(0x7e0000, 0x7fffff) AM_RAM /* 8KB Low RAM, 24KB High RAM, 96KB Expanded RAM */
1010		// AM_RANGE(0x800000, 0xffffff) AM_READWRITE(snes20_hi_r, snes20_hi_w)
	1010	// AM_RANGE(0x800000, 0xffffff) AM_READWRITE(snes20_hi_r, snes20_hi_w)
1011	1011	ADDRESS_MAP_END
1012	1012
1013	1013	static ADDRESS_MAP_START( spc_map, AS_PROGRAM, 8, snes_console_state )
r245142	r245143
1196	1196	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x000000, 0x7dffff, read8_delegate(FUNC(snes_console_state::snes20_lo_r),this), write8_delegate(FUNC(snes_console_state::snes20_lo_w),this));
1197	1197	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x800000, 0xffffff, read8_delegate(FUNC(snes_console_state::snes20_hi_r),this), write8_delegate(FUNC(snes_console_state::snes20_hi_w),this));
1198	1198	m_maincpu->set_5a22_map();
1199
	1199
1200	1200	m_type = m_cartslot->get_type();
1201	1201
1202	1202	switch (m_type)

trunk/src/mess/drivers/ticalc1x.c
r245142	r245143
59	59	int m_display_wait; // led/lamp off-delay in microseconds (default 33ms)
60	60	int m_display_maxy; // display matrix number of rows
61	61	int m_display_maxx; // display matrix number of columns
62
63		UINT32 m_display_state[0x20]; // display matrix rows data
	62
	63	UINT32 m_display_state[0x20]; // display matrix rows data
64	64	UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
65	65	UINT32 m_display_cache[0x20]; // (internal use)
66	66	UINT8 m_display_decay[0x20][0x20]; // (internal use)
r245142	r245143
68	68	TIMER_DEVICE_CALLBACK_MEMBER(display_decay_tick);
69	69	void display_update();
70	70	void display_matrix_seg(int maxx, int maxy, UINT32 setx, UINT32 sety, UINT16 segmask);
71
	71
72	72	// calculator-specific handlers
73	73	void tisr16_display();
74	74	DECLARE_WRITE16_MEMBER(tisr16_write_o);
r245142	r245143
105	105	memset(m_display_cache, ~0, sizeof(m_display_cache));
106	106	memset(m_display_decay, 0, sizeof(m_display_decay));
107	107	memset(m_display_segmask, ~0, sizeof(m_display_segmask)); // !
108
	108
109	109	m_o = 0;
110	110	m_r = 0;
111	111	m_inp_mux = 0;
r245142	r245143
193	193	for (int x = 0; x < m_display_maxx; x++)
194	194	if (m_display_decay[y][x] != 0)
195	195	m_display_decay[y][x]--;
196
	196
197	197	display_update();
198	198	}
199	199
r245142	r245143
209	209	m_display_segmask[y] &= segmask;
210	210	m_display_state[y] = (sety >> y & 1) ? (setx & colmask) : 0;
211	211	}
212
	212
213	213	display_update();
214	214	}
215	215
r245142	r245143
482	482	// \./ GAB
483	483	// --- F
484	484	// /.\ EDC
485
	485
486	486	// 3rd digit only has A and G for =, though some newer hardware revisions
487	487	// (goes for both wizatron and lilprof) use a custom equals-sign digit here
488	488	m_display_segmask[3] = 0x41;
489
	489
490	490	// R0-R8: select digit (right-to-left)
491	491	display_matrix_seg(7, 9, m_o, data, 0x7f);
492	492	}
r245142	r245143
557	557
558	558	TI Little Professor (1976 version)
559	559	* TMS0970 MCU labeled TMS0975NL ZA0356, GP0975CS. die labeled 0970D-75C
560
	560
561	561	The hardware is nearly identical to Wiz-A-Tron (or vice versa, since this
562	562	one is older).
563	563
r245142	r245143
631	631
632	632	// 3rd digit A/G(equals sign) is from O7
633	633	m_display_state[3] = (m_o & 0x80) ? 0x41 : 0;
634
	634
635	635	// 6th digit is a custom 7seg for math symbols (see wizatron_write_r)
636	636	m_display_state[6] = BITSWAP8(m_display_state[6],7,6,1,4,2,3,5,0);
637	637
r245142	r245143
996	996	ROM_LOAD( "za0356", 0x0000, 0x0400, CRC(fef9dd39) SHA1(5c9614c9c5092d55dabeee2d6e0387d50d6ad4d5) )
997	997
998	998	ROM_REGION( 782, "maincpu:ipla", 0 )
999		ROM_LOAD( "tms0970_lilprof_ipla.pla", 0, 782, ~~BAD_DUMP~~ CRC(05306ef8) SHA1(60a0a3c49ce330bce0c27f15f81d61461d0432ce) ) ~~// not verified~~
	999	ROM_LOAD( "tms0970_lilprof_ipla.pla", 0, 782, CRC(05306ef8) SHA1(60a0a3c49ce330bce0c27f15f81d61461d0432ce) )
1000	1000	ROM_REGION( 860, "maincpu:mpla", 0 )
1001		ROM_LOAD( "tms0970_lilprof_mpla.pla", 0, 860, ~~BAD_DUMP~~ CRC(6ff5d51d) SHA1(59d3e5de290ba57694068ddba78d21a0c1edf427) ) ~~// not verified~~
	1001	ROM_LOAD( "tms0970_lilprof_mpla.pla", 0, 860, CRC(6ff5d51d) SHA1(59d3e5de290ba57694068ddba78d21a0c1edf427) )
1002	1002	ROM_REGION( 352, "maincpu:opla", 0 )
1003		ROM_LOAD( "tms0970_lilprof_opla.pla", 0, 352, ~~BAD_DUMP~~ CRC(c74daf97) SHA1(c4948000196171b34d4fe9cdd2962a945da9883d) ) ~~// not verified~~
	1003	ROM_LOAD( "tms0970_lilprof_opla.pla", 0, 352, CRC(c74daf97) SHA1(c4948000196171b34d4fe9cdd2962a945da9883d) )
1004	1004	ROM_REGION( 157, "maincpu:spla", 0 )
1005	1005	ROM_LOAD( "tms0970_lilprof_spla.pla", 0, 157, CRC(56c37a4f) SHA1(18ecc20d2666e89673739056483aed5a261ae927) )
1006	1006	ROM_END

trunk/src/mess/drivers/tispeak.c
r245142	r245143
326	326	int m_display_wait; // led/lamp off-delay in microseconds (default 33ms)
327	327	int m_display_maxy; // display matrix number of rows
328	328	int m_display_maxx; // display matrix number of columns
329
330		UINT32 m_display_state[0x20]; // display matrix rows data
	329
	330	UINT32 m_display_state[0x20]; // display matrix rows data
331	331	UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
332	332	UINT32 m_display_cache[0x20]; // (internal use)
333	333	UINT8 m_display_decay[0x20][0x20]; // (internal use)
r245142	r245143
454	454	for (int x = 0; x < m_display_maxx; x++)
455	455	if (m_display_decay[y][x] != 0)
456	456	m_display_decay[y][x]--;
457
	457
458	458	display_update();
459	459	}
460	460
r245142	r245143
470	470	m_display_segmask[y] &= segmask;
471	471	m_display_state[y] = (sety >> y & 1) ? (setx & colmask) : 0;
472	472	}
473
	473
474	474	display_update();
475	475	}
476	476
r245142	r245143
501	501	{
502	502	// R15: filament on
503	503	m_filament_on = data & 0x8000;
504
	504
505	505	// R13: power-off request, on falling edge
506	506	if ((m_r >> 13 & 1) && !(data >> 13 & 1))
507	507	power_off();

trunk/src/mess/includes/hh_tms1k.h
r245142	r245143
32	32	required_device<cpu_device> m_maincpu;
33	33	optional_ioport_array<7> m_inp_matrix; // max 7
34	34	optional_device<speaker_sound_device> m_speaker;
35
	35
36	36	// misc common
37	37	UINT16 m_r; // MCU R-pins data
38	38	UINT16 m_o; // MCU O-pins data
r245142	r245143
47	47	int m_display_wait; // led/lamp off-delay in microseconds (default 33ms)
48	48	int m_display_maxy; // display matrix number of rows
49	49	int m_display_maxx; // display matrix number of columns
50
51		UINT32 m_display_state[0x20]; // display matrix rows data
	50
	51	UINT32 m_display_state[0x20]; // display matrix rows data
52	52	UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
53	53	UINT32 m_display_cache[0x20]; // (internal use)
54	54	UINT8 m_display_decay[0x20][0x20]; // (internal use)

trunk/src/mess/includes/imds2.h
r245142	r245143
18	18
19	19	class imds2_state : public driver_device
20	20	{
21		public:
22		imds2_state(const machine_config &mconfig, device_type type, const char *tag);
	21	public:
	22	imds2_state(const machine_config &mconfig, device_type type, const char *tag);
23	23
24		DECLARE_READ8_MEMBER(ipc_mem_read);
25		DECLARE_WRITE8_MEMBER(ipc_mem_write);
26		DECLARE_WRITE8_MEMBER(imds2_ipc_control_w);
27		DECLARE_WRITE_LINE_MEMBER(imds2_ipc_intr);
28		DECLARE_READ8_MEMBER(imds2_ipcsyspic_r);
29		DECLARE_READ8_MEMBER(imds2_ipclocpic_r);
30		DECLARE_WRITE8_MEMBER(imds2_ipcsyspic_w);
31		DECLARE_WRITE8_MEMBER(imds2_ipclocpic_w);
32
33		DECLARE_WRITE8_MEMBER(imds2_miscout_w);
34		DECLARE_READ8_MEMBER(imds2_miscin_r);
35		DECLARE_WRITE_LINE_MEMBER(imds2_beep_timer_w);
36		DECLARE_WRITE8_MEMBER(imds2_start_timer_w);
37		DECLARE_READ8_MEMBER(imds2_kb_read);
38		DECLARE_READ8_MEMBER(imds2_kb_port_p2_r);
39		DECLARE_WRITE8_MEMBER(imds2_kb_port_p1_w);
40		DECLARE_READ8_MEMBER(imds2_kb_port_t0_r);
41		DECLARE_READ8_MEMBER(imds2_kb_port_t1_r);
42		DECLARE_WRITE8_MEMBER(imds2_ioc_dbbout_w);
43		DECLARE_WRITE8_MEMBER(imds2_ioc_f0_w);
44		DECLARE_WRITE8_MEMBER(imds2_ioc_set_f1_w);
45		DECLARE_WRITE8_MEMBER(imds2_ioc_reset_f1_w);
46		DECLARE_READ8_MEMBER(imds2_ioc_status_r);
47		DECLARE_READ8_MEMBER(imds2_ioc_dbbin_r);
48		DECLARE_READ8_MEMBER(imds2_ipc_dbbout_r);
49		DECLARE_READ8_MEMBER(imds2_ipc_status_r);
50		DECLARE_WRITE8_MEMBER(imds2_ipc_dbbin_data_w);
51		DECLARE_WRITE8_MEMBER(imds2_ipc_dbbin_cmd_w);
52		DECLARE_WRITE_LINE_MEMBER(imds2_hrq_w);
53
54		DECLARE_READ8_MEMBER(imds2_ioc_mem_r);
55		DECLARE_WRITE8_MEMBER(imds2_ioc_mem_w);
56
57		I8275_DRAW_CHARACTER_MEMBER(crtc_display_pixels);
58
59		virtual void driver_start();
60		virtual void machine_start();
61		virtual void video_start();
62		virtual void machine_reset();
63
64		private:
65		required_device<i8085a_cpu_device> m_ipccpu;
66		required_device<pic8259_device> m_ipcsyspic;
67		required_device<pic8259_device> m_ipclocpic;
68		required_device<i8080a_cpu_device> m_ioccpu;
69		required_device<i8257_device> m_iocdma;
70		required_device<i8275_device> m_ioccrtc;
71		required_device<beep_device> m_iocbeep;
72		required_device<pit8253_device> m_ioctimer;
73		required_device<i8271_device> m_iocfdc;
74		required_device<i8741_device> m_kbcpu;
75		required_device<palette_device> m_palette;
76		required_device<gfxdecode_device> m_gfxdecode;
77		required_device<legacy_floppy_image_device> m_floppy0;
78		required_ioport m_io_key0;
79		required_ioport m_io_key1;
80		required_ioport m_io_key2;
81		required_ioport m_io_key3;
82		required_ioport m_io_key4;
83		required_ioport m_io_key5;
84		required_ioport m_io_key6;
85		required_ioport m_io_key7;
86		required_ioport m_ioc_options;
87
88		dynamic_array<UINT8> m_ipc_ram;
	24	DECLARE_READ8_MEMBER(ipc_mem_read);
	25	DECLARE_WRITE8_MEMBER(ipc_mem_write);
	26	DECLARE_WRITE8_MEMBER(imds2_ipc_control_w);
	27	DECLARE_WRITE_LINE_MEMBER(imds2_ipc_intr);
	28	DECLARE_READ8_MEMBER(imds2_ipcsyspic_r);
	29	DECLARE_READ8_MEMBER(imds2_ipclocpic_r);
	30	DECLARE_WRITE8_MEMBER(imds2_ipcsyspic_w);
	31	DECLARE_WRITE8_MEMBER(imds2_ipclocpic_w);
89	32
90		bool imds2_in_ipc_rom(offs_t offset) const;
91
92		void imds2_update_beeper(void);
	33	DECLARE_WRITE8_MEMBER(imds2_miscout_w);
	34	DECLARE_READ8_MEMBER(imds2_miscin_r);
	35	DECLARE_WRITE_LINE_MEMBER(imds2_beep_timer_w);
	36	DECLARE_WRITE8_MEMBER(imds2_start_timer_w);
	37	DECLARE_READ8_MEMBER(imds2_kb_read);
	38	DECLARE_READ8_MEMBER(imds2_kb_port_p2_r);
	39	DECLARE_WRITE8_MEMBER(imds2_kb_port_p1_w);
	40	DECLARE_READ8_MEMBER(imds2_kb_port_t0_r);
	41	DECLARE_READ8_MEMBER(imds2_kb_port_t1_r);
	42	DECLARE_WRITE8_MEMBER(imds2_ioc_dbbout_w);
	43	DECLARE_WRITE8_MEMBER(imds2_ioc_f0_w);
	44	DECLARE_WRITE8_MEMBER(imds2_ioc_set_f1_w);
	45	DECLARE_WRITE8_MEMBER(imds2_ioc_reset_f1_w);
	46	DECLARE_READ8_MEMBER(imds2_ioc_status_r);
	47	DECLARE_READ8_MEMBER(imds2_ioc_dbbin_r);
	48	DECLARE_READ8_MEMBER(imds2_ipc_dbbout_r);
	49	DECLARE_READ8_MEMBER(imds2_ipc_status_r);
	50	DECLARE_WRITE8_MEMBER(imds2_ipc_dbbin_data_w);
	51	DECLARE_WRITE8_MEMBER(imds2_ipc_dbbin_cmd_w);
	52	DECLARE_WRITE_LINE_MEMBER(imds2_hrq_w);
93	53
94		// IPC control port
95		UINT8 m_ipc_control;
	54	DECLARE_READ8_MEMBER(imds2_ioc_mem_r);
	55	DECLARE_WRITE8_MEMBER(imds2_ioc_mem_w);
96	56
97		// IPC ROM content
98		const UINT8 *m_ipc_rom;
99
100		// Character generator
101		const UINT8 *m_chargen;
102
103		// MISCOUT state
104		UINT8 m_miscout;
	57	I8275_DRAW_CHARACTER_MEMBER(crtc_display_pixels);
105	58
106		// Beeper timer line
107		int m_beeper_timer;
108
109		// Keyboard state
110		UINT8 m_kb_p1;
	59	virtual void driver_start();
	60	virtual void machine_start();
	61	virtual void video_start();
	62	virtual void machine_reset();
111	63
112		// IPC to IOC buffer
113		UINT8 m_ioc_ibf;
	64	private:
	65	required_device<i8085a_cpu_device> m_ipccpu;
	66	required_device<pic8259_device> m_ipcsyspic;
	67	required_device<pic8259_device> m_ipclocpic;
	68	required_device<i8080a_cpu_device> m_ioccpu;
	69	required_device<i8257_device> m_iocdma;
	70	required_device<i8275_device> m_ioccrtc;
	71	required_device<beep_device> m_iocbeep;
	72	required_device<pit8253_device> m_ioctimer;
	73	required_device<i8271_device> m_iocfdc;
	74	required_device<i8741_device> m_kbcpu;
	75	required_device<palette_device> m_palette;
	76	required_device<gfxdecode_device> m_gfxdecode;
	77	required_device<legacy_floppy_image_device> m_floppy0;
	78	required_ioport m_io_key0;
	79	required_ioport m_io_key1;
	80	required_ioport m_io_key2;
	81	required_ioport m_io_key3;
	82	required_ioport m_io_key4;
	83	required_ioport m_io_key5;
	84	required_ioport m_io_key6;
	85	required_ioport m_io_key7;
	86	required_ioport m_ioc_options;
114	87
115		// IOC to IPC buffer
116		UINT8 m_ioc_obf;
	88	dynamic_array<UINT8> m_ipc_ram;
117	89
118		// IPC/IOC status
119		UINT8 m_ipc_ioc_status;
	90	bool imds2_in_ipc_rom(offs_t offset) const;
	91
	92	void imds2_update_beeper(void);
	93
	94	// IPC control port
	95	UINT8 m_ipc_control;
	96
	97	// IPC ROM content
	98	const UINT8 *m_ipc_rom;
	99
	100	// Character generator
	101	const UINT8 *m_chargen;
	102
	103	// MISCOUT state
	104	UINT8 m_miscout;
	105
	106	// Beeper timer line
	107	int m_beeper_timer;
	108
	109	// Keyboard state
	110	UINT8 m_kb_p1;
	111
	112	// IPC to IOC buffer
	113	UINT8 m_ioc_ibf;
	114
	115	// IOC to IPC buffer
	116	UINT8 m_ioc_obf;
	117
	118	// IPC/IOC status
	119	UINT8 m_ipc_ioc_status;
120	120	};
121	121
122	122	#endif /* _IMDS2_H_ */

trunk/src/mess/layout/mbdtower.lay
r245142	r245143
4	4	<!-- define elements -->
5	5
6	6	<element name="static_black"><rect><color red="0.0" green="0.0" blue="0.0" /></rect></element>
	7	<element name="static_white"><rect><color red="1.0" green="1.0" blue="1.0" /></rect></element>
7	8
	9	<element name="mask" defstate="0">
	10	<text string=" "><color red="0.0" green="0.0" blue="0.0" /></text>
	11	<rect state="0"><color red="0.0" green="0.0" blue="0.0" /></rect>
	12	</element>
	13
	14	<element name="card1" defstate="0">
	15	<rect><color red="1.0" green="1.0" blue="1.0" /></rect>
	16	<text state="0" string="CURSED"><color red="0.0" green="0.0" blue="0.0" /></text>
	17	<text state="1" string="VICTORY"><color red="0.0" green="0.0" blue="0.0" /></text>
	18	<text state="2" string="WIZARD"><color red="0.0" green="0.0" blue="0.0" /></text>
	19	<text state="3" string="DRAGON"><color red="0.0" green="0.0" blue="0.0" /></text>
	20	<text state="4" string="GOLD KEY"><color red="0.0" green="0.0" blue="0.0" /></text>
	21	<text state="5" string="SCOUT"><color red="0.0" green="0.0" blue="0.0" /></text>
	22	<text state="6" string="WARRIOR"><color red="0.0" green="0.0" blue="0.0" /></text>
	23	<text state="7" string=" "><color red="0.0" green="0.0" blue="0.0" /></text>
	24	</element>
	25
	26	<element name="card2" defstate="0">
	27	<rect><color red="1.0" green="1.0" blue="1.0" /></rect>
	28	<text state="0" string="LOST"><color red="0.0" green="0.0" blue="0.0" /></text>
	29	<text state="1" string="WARRIORS"><color red="0.0" green="0.0" blue="0.0" /></text>
	30	<text state="2" string="BAZAAR CLOSED"><color red="0.0" green="0.0" blue="0.0" /></text>
	31	<text state="3" string="SWORD"><color red="0.0" green="0.0" blue="0.0" /></text>
	32	<text state="4" string="SILVER KEY"><color red="0.0" green="0.0" blue="0.0" /></text>
	33	<text state="5" string="HEALER"><color red="0.0" green="0.0" blue="0.0" /></text>
	34	<text state="6" string="FOOD"><color red="0.0" green="0.0" blue="0.0" /></text>
	35	<text state="7" string=" "><color red="0.0" green="0.0" blue="0.0" /></text>
	36	</element>
	37
	38	<element name="card3" defstate="0">
	39	<rect><color red="1.0" green="1.0" blue="1.0" /></rect>
	40	<text state="0" string="PLAGUE"><color red="0.0" green="0.0" blue="0.0" /></text>
	41	<text state="1" string="BRIGANDS"><color red="0.0" green="0.0" blue="0.0" /></text>
	42	<text state="2" string="KEY MISSING"><color red="0.0" green="0.0" blue="0.0" /></text>
	43	<text state="3" string="PEGASUS"><color red="0.0" green="0.0" blue="0.0" /></text>
	44	<text state="4" string="BRASS KEY"><color red="0.0" green="0.0" blue="0.0" /></text>
	45	<text state="5" string="GOLD"><color red="0.0" green="0.0" blue="0.0" /></text>
	46	<text state="6" string="BEAST"><color red="0.0" green="0.0" blue="0.0" /></text>
	47	<text state="7" string=" "><color red="0.0" green="0.0" blue="0.0" /></text>
	48	</element>
	49
	50	<element name="text_m1"><text string="(motor pos: 0." align="1"><color red="0.95" green="0.95" blue="0.95" /></text></element>
	51	<element name="text_m2"><text string=")" align="1"><color red="0.95" green="0.95" blue="0.95" /></text></element>
	52	<element name="counter" defstate="0">
	53	<simplecounter maxstate="99" digits="2" align="1">
	54	<color red="0.95" green="0.95" blue="0.95" />
	55	</simplecounter>
	56	</element>
	57
8	58	<element name="digit" defstate="0">
9	59	<led7seg><color red="1.0" green="0.20" blue="0.22" /></led7seg>
10	60	</element>
11	61
	62	<element name="led" defstate="0">
	63	<disk state="0"><color red="0.2" green="0.04" blue="0.05" /></disk>
	64	<disk state="1"><color red="1.0" green="0.20" blue="0.22" /></disk>
	65	</element>
12	66
	67
	68
13	69	<!-- build screen -->
14	70
15	71	<view name="Internal Layout">
16		<bounds left="0" right="64" top="0" bottom="64" />
	72	<bounds left="0" right="40" top="0" bottom="118" />
17	73	<bezel element="static_black">
18		<bounds left="0" right="64" top="0" bottom="64" />
	74	<bounds left="0" right="40" top="0" bottom="118" />
19	75	</bezel>
20	76
21		<bezel name="digit1" element="digit"><bounds x="0" y="0" width="10" height="15" /></bezel>
22		<bezel name="digit2" element="digit"><bounds x="10" y="0" width="10" height="15" /></bezel>
	77	<bezel name="digit1" element="digit"><bounds x="10" y="3" width="10" height="15" /></bezel>
	78	<bezel name="digit2" element="digit"><bounds x="20" y="3" width="10" height="15" /></bezel>
23	79
	80	<!-- card lamps -->
24	81
	82	<bezel element="static_white"><bounds x="1" y="28" width="38" height="25" /></bezel>
	83	<bezel name="card_pos" element="card1"><bounds x="1" y="38" width="38" height="5" /></bezel>
	84	<bezel name="lamp3" element="mask">
	85	<bounds x="1" y="28" width="38" height="25" />
	86	<color alpha="0.8" />
	87	</bezel>
	88
	89	<bezel element="static_white"><bounds x="1" y="56" width="38" height="25" /></bezel>
	90	<bezel name="card_pos" element="card2"><bounds x="1" y="66" width="38" height="5" /></bezel>
	91	<bezel name="lamp2" element="mask">
	92	<bounds x="1" y="56" width="38" height="25" />
	93	<color alpha="0.8" />
	94	</bezel>
	95
	96	<bezel element="static_white"><bounds x="1" y="84" width="38" height="25" /></bezel>
	97	<bezel name="card_pos" element="card3"><bounds x="1" y="94" width="38" height="5" /></bezel>
	98	<bezel name="lamp1" element="mask">
	99	<bounds x="1" y="84" width="38" height="25" />
	100	<color alpha="0.8" />
	101	</bezel>
	102
	103	<!-- motor status info -->
	104
	105	<bezel element="text_m1"><bounds x="7" y="112" width="22" height="4" /></bezel>
	106	<bezel name="motor_pos" element="counter"><bounds x="27.6" y="112" width="10" height="4" /></bezel>
	107	<bezel element="text_m2"><bounds x="31.4" y="112" width="5" height="4" /></bezel>
	108	<bezel name="motor_on" element="mask">
	109	<bounds x="1" y="111" width="38" height="6" />
	110	<color alpha="0.75" />
	111	</bezel>
	112
	113
25	114	</view>
26	115	</mamelayout>

trunk/src/mess/mess.lst
r245142	r245143
2206	2206	starwbcp // Kenner (prototype)
2207	2207	comp4 // Milton Bradley
2208	2208	simon // Milton Bradley
2209		//ssimon // Milton Bradley
	2209	ssimon // Milton Bradley
2210	2210	cnsector // Parker Bros
2211	2211	merlin // Parker Bros
2212	2212	stopthie // Parker Bros

trunk/src/mess/mess.mak
r245142	r245143
1335	1335	$(MESS_DRIVERS)/rex6000.o \
1336	1336	$(MESS_DRIVERS)/sdk85.o \
1337	1337	$(MESS_DRIVERS)/sdk86.o \
1338		$(MESS_DRIVERS)/imds2.o \
	1338	$(MESS_DRIVERS)/imds2.o \
1339	1339
1340	1340	$(MESSOBJ)/imp.a: \
1341	1341	$(MESS_DRIVERS)/tim011.o \
r245142	r245143
2137	2137	$(MESS_DRIVERS)/hh_hmcs40.o:$(MESS_LAYOUT)/hh_hmcs40_test.lh
2138	2138	$(MESS_DRIVERS)/hh_pic16.o: $(MESS_LAYOUT)/maniac.lh
2139	2139	$(MESS_DRIVERS)/hh_tms1k.o: $(MESS_LAYOUT)/amaztron.lh \
2140		$(MESS_LAYOUT)/bankshot.lh \
2141		$(MESS_LAYOUT)/cnsector.lh \
2142		$(MESS_LAYOUT)/comp4.lh \
2143		$(MESS_LAYOUT)/ebball.lh \
2144		$(MESS_LAYOUT)/ebball2.lh \
2145		$(MESS_LAYOUT)/ebball3.lh \
2146		$(MESS_LAYOUT)/elecdet.lh \
2147		$(MESS_LAYOUT)/mathmagi.lh \
2148		$(MESS_LAYOUT)/merlin.lh \
2149		$(MESS_LAYOUT)/simon.lh \
2150		$(MESS_LAYOUT)/ssimon.lh \
2151		$(MESS_LAYOUT)/splitsec.lh \
2152		$(MESS_LAYOUT)/starwbc.lh \
2153		$(MESS_LAYOUT)/stopthie.lh \
2154		$(MESS_LAYOUT)/tandy12.lh \
2155		$(MESS_LAYOUT)/tc4.lh
	2140	$(MESS_LAYOUT)/bankshot.lh \
	2141	$(MESS_LAYOUT)/cnsector.lh \
	2142	$(MESS_LAYOUT)/comp4.lh \
	2143	$(MESS_LAYOUT)/ebball.lh \
	2144	$(MESS_LAYOUT)/ebball2.lh \
	2145	$(MESS_LAYOUT)/ebball3.lh \
	2146	$(MESS_LAYOUT)/elecdet.lh \
	2147	$(MESS_LAYOUT)/mathmagi.lh \
	2148	$(MESS_LAYOUT)/merlin.lh \
	2149	$(MESS_LAYOUT)/simon.lh \
	2150	$(MESS_LAYOUT)/ssimon.lh \
	2151	$(MESS_LAYOUT)/splitsec.lh \
	2152	$(MESS_LAYOUT)/starwbc.lh \
	2153	$(MESS_LAYOUT)/stopthie.lh \
	2154	$(MESS_LAYOUT)/tandy12.lh \
	2155	$(MESS_LAYOUT)/tc4.lh
2156	2156	$(MESS_DRIVERS)/hh_ucom4.o: $(MESS_LAYOUT)/hh_ucom4_test.lh
2157	2157	$(MESS_DRIVERS)/ie15.o: $(MESS_LAYOUT)/ie15.lh
2158	2158	$(MESS_DRIVERS)/instruct.o: $(MESS_LAYOUT)/instruct.lh

trunk/src/osd/modules/opengl/osd_opengl.h
r245142	r245143
61	61	virtual const char *LastErrorMsg() = 0;
62	62	virtual void getProcAddress(const char proc) = 0;
63	63	/*
64		* 0 for immediate updates,
65		* 1 for updates synchronized with the vertical retrace,
66		* -1 for late swap tearing
	64	* 0 for immediate updates,
	65	* 1 for updates synchronized with the vertical retrace,
	66	* -1 for late swap tearing
67	67	*
68		* returns -1 if swap interval is not supported
	68	* returns -1 if swap interval is not supported
69	69	*
70	70	*/
71	71	virtual int SetSwapInterval(const int swap) = 0;
r245142	r245143
99	99	#undef GET_GLFUNC
100	100	};
101	101	#ifdef _MSC_VER
102		}
	102	}
103	103	#endif
104	104
105	105	#undef OSD_GL

trunk/src/osd/modules/osdwindow.h
r245142	r245143
78	78	#endif
79	79
80	80	render_primitive_list *m_primlist;
81		osd_window_config m_win_config;
	81	osd_window_config m_win_config;
82	82	protected:
83		int m_prescale;
	83	int m_prescale;
84	84	};
85	85
86	86	class osd_renderer
r245142	r245143
131	131	private:
132	132
133	133	osd_window *m_window;
134		int m_flags;
	134	int m_flags;
135	135	};
136	136
137	137

trunk/src/osd/modules/render/draw13.c
r245142	r245143
118	118
119	119	private:
120	120	Uint32 m_sdl_access;
121		sdl_info13 * m_renderer;
	121	sdl_info13 * m_renderer;
122	122	render_texinfo m_texinfo; // copy of the texture info
123	123	HashT m_hash; // hash value for the texture (must be >= pointer size)
124	124	UINT32 m_flags; // rendering flags

trunk/src/osd/modules/render/drawogl.c
r245142	r245143
281	281
282	282	int setupPixelFormat(HDC hDC)
283	283	{
284		PIXELFORMATDESCRIPTOR pfd = {
285		sizeof(PIXELFORMATDESCRIPTOR), /* size */
286		1, /* version */
287		PFD_SUPPORT_OPENGL \|
288		PFD_DRAW_TO_WINDOW \|
289		PFD_DOUBLEBUFFER, /* support double-buffering */
290		PFD_TYPE_RGBA, /* color type */
291		32, /* prefered color depth */
292		0, 0, 0, 0, 0, 0, /* color bits (ignored) */
293		0, /* no alpha buffer */
294		0, /* alpha bits (ignored) */
295		0, /* no accumulation buffer */
296		0, 0, 0, 0, /* accum bits (ignored) */
297		16, /* depth buffer */
298		0, /* no stencil buffer */
299		0, /* no auxiliary buffers */
300		PFD_MAIN_PLANE, /* main layer */
301		0, /* reserved */
302		0, 0, 0, /* no layer, visible, damage masks */
303		};
304		int pixelFormat;
	284	PIXELFORMATDESCRIPTOR pfd = {
	285	sizeof(PIXELFORMATDESCRIPTOR), /* size */
	286	1, /* version */
	287	PFD_SUPPORT_OPENGL \|
	288	PFD_DRAW_TO_WINDOW \|
	289	PFD_DOUBLEBUFFER, /* support double-buffering */
	290	PFD_TYPE_RGBA, /* color type */
	291	32, /* prefered color depth */
	292	0, 0, 0, 0, 0, 0, /* color bits (ignored) */
	293	0, /* no alpha buffer */
	294	0, /* alpha bits (ignored) */
	295	0, /* no accumulation buffer */
	296	0, 0, 0, 0, /* accum bits (ignored) */
	297	16, /* depth buffer */
	298	0, /* no stencil buffer */
	299	0, /* no auxiliary buffers */
	300	PFD_MAIN_PLANE, /* main layer */
	301	0, /* reserved */
	302	0, 0, 0, /* no layer, visible, damage masks */
	303	};
	304	int pixelFormat;
305	305
306		pixelFormat = ChoosePixelFormat(hDC, &pfd);
307		if (pixelFormat == 0) {
308		strcpy(m_error, "ChoosePixelFormat failed");
309		return 1;
310		}
	306	pixelFormat = ChoosePixelFormat(hDC, &pfd);
	307	if (pixelFormat == 0) {
	308	strcpy(m_error, "ChoosePixelFormat failed");
	309	return 1;
	310	}
311	311
312		if (SetPixelFormat(hDC, pixelFormat, &pfd) != TRUE) {
313		strcpy(m_error, "SetPixelFormat failed.");
314		return 1;
315		}
316		return 0;
	312	if (SetPixelFormat(hDC, pixelFormat, &pfd) != TRUE) {
	313	strcpy(m_error, "SetPixelFormat failed.");
	314	return 1;
	315	}
	316	return 0;
317	317	}
318	318
319	319	bool WGLExtensionSupported(const char *extension_name)
320	320	{
321		//if (pfn_wglGetExtensionsStringEXT != NULL)
322		// printf("%s\n", this->pfn_wglGetExtensionsStringEXT());
	321	//if (pfn_wglGetExtensionsStringEXT != NULL)
	322	// printf("%s\n", this->pfn_wglGetExtensionsStringEXT());
323	323
324		if (pfn_wglGetExtensionsStringEXT != NULL && strstr(pfn_wglGetExtensionsStringEXT(), extension_name) != NULL)
325		return true;
326		else
327		return false;
	324	if (pfn_wglGetExtensionsStringEXT != NULL && strstr(pfn_wglGetExtensionsStringEXT(), extension_name) != NULL)
	325	return true;
	326	else
	327	return false;
328	328	}
329	329
330	330	HGLRC m_context;
r245142	r245143
589	589	int m_height;
590	590	osd_dim m_blit_dim;
591	591
592		osd_gl_context *m_gl_context;
	592	osd_gl_context *m_gl_context;
593	593
594	594	int m_initialized; // is everything well initialized, i.e. all GL stuff etc.
595	595	// 3D info (GL mode only)

trunk/src/osd/sdl/sdl.mak
r245142	r245143
429	429	$(OSDOBJ)/modules/netdev \
430	430	$(OSDOBJ)/modules/opengl \
431	431	$(OSDOBJ)/modules/render
432
	432
433	433	#-------------------------------------------------
434	434	# OSD core library
435	435	#-------------------------------------------------
r245142	r245143
827	827	$(OSDOBJ)/modules/render/drawogl.o \
828	828	$(OSDOBJ)/modules/opengl/gl_shader_tool.o \
829	829	$(OSDOBJ)/modules/opengl/gl_shader_mgr.o
830
	830
831	831	DEFS += -DUSE_OPENGL=1
832	832	ifeq ($(USE_DISPATCH_GL),1)
833	833	DEFS += -DUSE_DISPATCH_GL=1

trunk/src/osd/sdl/video.h
r245142	r245143
131	131	osd_monitor_info *m_next; // pointer to next monitor in list
132	132	protected:
133	133	virtual void refresh() = 0;
134		osd_rect m_pos_size;
135		osd_rect m_usuable_pos_size;
136		bool m_is_primary;
	134	osd_rect m_pos_size;
	135	osd_rect m_usuable_pos_size;
	136	bool m_is_primary;
137	137	char m_name[64];
138	138	private:
139	139
r245142	r245143
185	185	int syncrefresh; // sync only to refresh rate
186	186	int switchres; // switch resolutions
187	187
188		int fullstretch; // FXIME: implement in windows!
	188	int fullstretch; // FXIME: implement in windows!
189	189
190	190	// ddraw options
191	191	int hwstretch; // stretch using the hardware

trunk/src/osd/sdl/window.c
r245142	r245143
1153	1153
1154	1154	#ifdef SDLMAME_MACOSX
1155	1155	/* FIMXE: On OSX, SDL_WINDOW_FULLSCREEN_DESKTOP seems to be more reliable.
1156		* It however creates issues with white borders, i.e. the screen clear
1157		* does not work. This happens both with opengl and accel.
	1156	* It however creates issues with white borders, i.e. the screen clear
	1157	* does not work. This happens both with opengl and accel.
1158	1158	*/
1159	1159	#endif
1160	1160

trunk/src/osd/windows/video.h
r245142	r245143
131	131	osd_monitor_info *m_next; // pointer to next monitor in list
132	132	protected:
133	133	virtual void refresh() = 0;
134		osd_rect m_pos_size;
135		osd_rect m_usuable_pos_size;
136		bool m_is_primary;
	134	osd_rect m_pos_size;
	135	osd_rect m_usuable_pos_size;
	136	bool m_is_primary;
137	137	char m_name[64];
138	138	private:
139	139
r245142	r245143
175	175	int syncrefresh; // sync only to refresh rate
176	176	int switchres; // switch resolutions
177	177
178		int fullstretch; // FXIME: implement in windows!
	178	int fullstretch; // FXIME: implement in windows!
179	179
180	180	// ddraw options
181	181	int hwstretch; // stretch using the hardware

trunk/src/osd/windows/windows.mak
r245142	r245143
406	406	$(OSDOBJ)/modules/render/drawogl.o \
407	407	$(OSDOBJ)/modules/opengl/gl_shader_tool.o \
408	408	$(OSDOBJ)/modules/opengl/gl_shader_mgr.o
409
	409
410	410	OBJDIRS += \
411		$(OSDOBJ)/modules/opengl
	411	$(OSDOBJ)/modules/opengl
412	412
413	413	DEFS += -DUSE_OPENGL=1
414	414

trunk/src/version.c
r245142	r245143
8	8
9	9	***************************************************************************/
10	10
11		#define BARE_BUILD_VERSION "0.159"
	11	#define BARE_BUILD_VERSION "0.160"
12	12
13	13	extern const char bare_build_version[];
14	14	extern const char build_version[];

https://github.com/mamedev/mame/commit/09ee79273f2849cb211855e7b26dfe24951e5662

199869 Revisions