trunk/src/emu/cpu/nec/v53.c
| r244922 | r244923 | |
|---|
| 215 | 215 | m_out_dack_1_cb.resolve_safe(); |
| 216 | 216 | m_out_dack_2_cb.resolve_safe(); |
| 217 | 217 | m_out_dack_3_cb.resolve_safe(); |
| 218 | |
| 219 | static_set_irq_acknowledge_callback(*this, device_irq_acknowledge_delegate(FUNC(pic8259_device::inta_cb), (pic8259_device*)m_v53icu)); |
| 218 | 220 | } |
| 219 | 221 | |
| 220 | 222 | void v53_base_device::install_peripheral_io() |
| r244922 | r244923 | |
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| 484 | 486 | MCFG_PIT8253_OUT0_HANDLER(WRITELINE( v53_base_device, tcu_out0_trampoline_cb )) |
| 485 | 487 | MCFG_PIT8253_OUT1_HANDLER(WRITELINE( v53_base_device, tcu_out1_trampoline_cb )) |
| 486 | 488 | MCFG_PIT8253_OUT2_HANDLER(WRITELINE( v53_base_device, tcu_out2_trampoline_cb )) |
| 489 | |
| 487 | 490 | |
| 488 | 491 | MCFG_DEVICE_ADD("upd71071dma", V53_DMAU, 4000000) |
| 489 | 492 | MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(v53_base_device, hreq_trampoline_cb)) |
| r244922 | r244923 | |
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| 506 | 509 | |
| 507 | 510 | MCFG_PIC8259_ADD( "upd71059pic", WRITELINE(v53_base_device, internal_irq_w), VCC, READ8(v53_base_device,get_pic_ack)) |
| 508 | 511 | |
| 512 | |
| 513 | |
| 509 | 514 | MCFG_DEVICE_ADD("v53scu", V53_SCU, 0) |
| 510 | 515 | MCFG_I8251_TXD_HANDLER(WRITELINE(v53_base_device, scu_txd_trampoline_cb)) |
| 511 | 516 | MCFG_I8251_DTR_HANDLER(WRITELINE(v53_base_device, scu_dtr_trampoline_cb)) |
trunk/src/mame/audio/hng64.c
| r244922 | r244923 | |
|---|
| 14 | 14 | |
| 15 | 15 | The earlier revisions appear to have 2 banks of code (there are vectors at the end of the 0x1e0000 block and the 0x1f0000 block) |
| 16 | 16 | |
| 17 | | Those first two revisions also spam the entire range of I/O ports with values several times on startup causing some unexpected |
| 18 | | writes to the V53 internal registers. The important ones are reinitialized after this however, I'm guessing this is harmless |
| 19 | | on real hardware, as the code flow seems to be correct. |
| 17 | If the banking setup is wrong then those first two revisions also spam the entire range of I/O ports with values several times |
| 18 | on startup causing some unexpected writes to the V53 internal registers. |
| 20 | 19 | |
| 21 | 20 | data structures look very similar between all of them |
| 22 | 21 | |
| 22 | IRQ mask register on the internal interrupt controller is set to 0xd8 |
| 23 | |
| 24 | so levels 0,1,2,5 are unmasked |
| 25 | |
| 23 | 26 | */ |
| 24 | 27 | |
| 25 | 28 | |
| r244922 | r244923 | |
|---|
| 298 | 301 | { |
| 299 | 302 | // these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1 |
| 300 | 303 | // printf("tcu_tm1_cb %02x\n", state); |
| 304 | m_audiocpu->set_input_line(0, state? ASSERT_LINE:CLEAR_LINE); |
| 301 | 305 | } |
| 302 | 306 | |
| 303 | 307 | WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb) |