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r36359 Tuesday 10th March, 2015 at 11:40:07 UTC by David Haywood
the V53 SCU is a i8251 clone, but with the command / mode registers separated, and only Asynchronous transfer mode available, this splits the function into something we can use for that purpose (nw)
[src/emu/cpu/nec]v53.c v53.h
[src/emu/machine]am9517a.c am9517a.h i8251.c i8251.h

trunk/src/emu/cpu/nec/v53.c
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33// V33 / V33A cores with onboard peripherals
44
55// Interrupt Controller is uPD71059 equivalent (a PIC8259 clone?)
6// DMA Controller can operate in modes providing a subset of the uPD71071 or uPD71037 functionality (some modes unavailable / settings ignored) (uPD71071 mode is an extended am9517a, uPD71037 mode is ??)
6// DMA Controller can operate in modes providing a subset of the uPD71071 or uPD71037 functionality (some modes unavailable / settings ignored) (uPD71071 mode is an extended 8237A, uPD71037 mode is plain 8237A)
77// Serial Controller is based on the uPD71051 but with some changes (i8251 clone?)
88// Timer Unit is functionally identical to uPD71054 (which in turn is said to be the same as a pit8253)
99
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216216      }
217217      else // uPD71071 mode
218218      {
219         space(AS_IO).install_readwrite_handler(base+0x00, base+0x0f, read8_delegate(FUNC(upd71071_v53_device::read), (upd71071_v53_device*)m_dma_71071mode), write8_delegate(FUNC(upd71071_v53_device::write),  (upd71071_v53_device*)m_dma_71071mode), 0xffff);
219         space(AS_IO).install_readwrite_handler(base+0x00, base+0x0f, read8_delegate(FUNC(upd71071_v53_device::read), (upd71071_v53_device*)m_v53dmau), write8_delegate(FUNC(upd71071_v53_device::write),  (upd71071_v53_device*)m_v53dmau), 0xffff);
220220      }
221221   }
222222
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231231      }
232232      else
233233      {
234         space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::icu_0_r), this), write8_delegate(FUNC(v53_base_device::icu_0_w), this), 0x00ff);
235         space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::icu_1_r), this), write8_delegate(FUNC(v53_base_device::icu_1_w), this), 0x00ff);
236
234         space(AS_IO).install_readwrite_handler(base+0x00, base+0x03, read8_delegate(FUNC(pic8259_device::read), (pic8259_device*)m_v53icu), write8_delegate(FUNC(pic8259_device::write), (pic8259_device*)m_v53icu), 0x00ff);
237235      }
238236   }
239237
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277275
278276}
279277
280/*** ICU ***/
281278
282279
283
284READ8_MEMBER(v53_base_device::icu_0_r)
285{
286   printf("v53: icu_0_r\n");
287   return 0;
288}
289
290WRITE8_MEMBER(v53_base_device::icu_0_w)
291{
292   printf("v53: icu_0_w %02x\n", data);
293}
294
295READ8_MEMBER(v53_base_device::icu_1_r)
296{
297   printf("v53: icu_1_r\n");
298   return 0;
299}
300
301WRITE8_MEMBER(v53_base_device::icu_1_w)
302{
303   printf("v53: icu_1_w %02x\n", data);
304}
305
306280/*** SCU ***/
307281
308282READ8_MEMBER(v53_base_device::scu_srb_r)
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346320
347321/*** TCU ***/
348322
349WRITE8_MEMBER(v53_base_device::tmu_tct0_w) { m_pit->write(space, 0, data); }
350WRITE8_MEMBER(v53_base_device::tmu_tct1_w) { m_pit->write(space, 1, data); }
351WRITE8_MEMBER(v53_base_device::tmu_tct2_w) { m_pit->write(space, 2, data); }
352WRITE8_MEMBER(v53_base_device::tmu_tmd_w)  { m_pit->write(space, 3, data); }
323WRITE8_MEMBER(v53_base_device::tmu_tct0_w) { m_v53tcu->write(space, 0, data); }
324WRITE8_MEMBER(v53_base_device::tmu_tct1_w) { m_v53tcu->write(space, 1, data); }
325WRITE8_MEMBER(v53_base_device::tmu_tct2_w) { m_v53tcu->write(space, 2, data); }
326WRITE8_MEMBER(v53_base_device::tmu_tmd_w)  { m_v53tcu->write(space, 3, data); }
353327
354328
355READ8_MEMBER(v53_base_device::tmu_tst0_r) {   return m_pit->read(space, 0); }
356READ8_MEMBER(v53_base_device::tmu_tst1_r) {   return m_pit->read(space, 1); }
357READ8_MEMBER(v53_base_device::tmu_tst2_r) {   return m_pit->read(space, 2); }
329READ8_MEMBER(v53_base_device::tmu_tst0_r) {   return m_v53tcu->read(space, 0); }
330READ8_MEMBER(v53_base_device::tmu_tst1_r) {   return m_v53tcu->read(space, 1); }
331READ8_MEMBER(v53_base_device::tmu_tst2_r) {   return m_v53tcu->read(space, 2); }
358332
359333/*** DMA ***/
360334
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363337{
364338   if (!(m_SCTL & 0x02))
365339   {
366      m_dma_71071mode->dreq0_w(state);
340      m_v53dmau->dreq0_w(state);
367341   }
368342   else
369343   {
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375349{
376350   if (!(m_SCTL & 0x02))
377351   {
378      m_dma_71071mode->dreq1_w(state);
352      m_v53dmau->dreq1_w(state);
379353   }
380354   else
381355   {
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387361{
388362   if (!(m_SCTL & 0x02))
389363   {
390      m_dma_71071mode->dreq2_w(state);
364      m_v53dmau->dreq2_w(state);
391365   }
392366   else
393367   {
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399373{
400374   if (!(m_SCTL & 0x02))
401375   {
402      m_dma_71071mode->dreq3_w(state);
376      m_v53dmau->dreq3_w(state);
403377   }
404378   else
405379   {
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411385{
412386   if (!(m_SCTL & 0x02))
413387   {
414      m_dma_71071mode->hack_w(state);
388      m_v53dmau->hack_w(state);
415389   }
416390   else
417391   {
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459433WRITE_LINE_MEMBER(v53_base_device::dma_hrq_changed)
460434{
461435   // pass this back to the driver? / expose externally?
462   m_dma_71071mode->hack_w(state);
436   m_v53dmau->hack_w(state);
463437}
464438
465439WRITE8_MEMBER(v53_base_device::dma_io_3_w)
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481455
482456WRITE_LINE_MEMBER( v53_base_device::upd71059_irq_w)
483457{
484   printf("upd71059_irq_w %d", state);
458   printf("upd71059_irq_w %d\n", state);
485459}
486460
487461static MACHINE_CONFIG_FRAGMENT( v53 )
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489463   MCFG_PIT8253_CLK0(16000000/2/8)
490464   //MCFG_PIT8253_OUT0_HANDLER(WRITELINE(v53_base_device, pit_out0))
491465
492   MCFG_DEVICE_ADD("upd71071dma", UPD71071_V53, 4000000)
466   MCFG_DEVICE_ADD("upd71071dma", V53_DMAU, 4000000)
493467   MCFG_I8237_OUT_HREQ_CB(WRITELINE(v53_base_device, dma_hrq_changed))
494468   MCFG_I8237_OUT_IOW_3_CB(WRITE8(v53_base_device, dma_io_3_w))
495469   MCFG_I8237_IN_MEMR_CB(READ8(v53_base_device, dma_memin_r))
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497471   
498472   MCFG_PIC8259_ADD( "upd71059pic", WRITELINE(v53_base_device, upd71059_irq_w), VCC, READ8(v53_base_device,get_pic_ack))
499473
500   MCFG_DEVICE_ADD("upd71051", I8251, 0)
474   MCFG_DEVICE_ADD("v53scu", V53_SCU, 0)
501475
502476MACHINE_CONFIG_END
503477
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510484v53_base_device::v53_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, offs_t fetch_xor, UINT8 prefetch_size, UINT8 prefetch_cycles, UINT32 chip_type)
511485   : nec_common_device(mconfig, type, name, tag, owner, clock, shortname, true, fetch_xor, prefetch_size, prefetch_cycles, chip_type),
512486   m_io_space_config( "io", ENDIANNESS_LITTLE, 16, 16, 0, ADDRESS_MAP_NAME( v53_internal_port_map ) ),
513   m_pit(*this, "pit"),
514   m_dma_71071mode(*this, "upd71071dma"),
515   m_upd71059(*this, "upd71059pic"),
516   m_upd71051(*this, "upd71051")
487   m_v53tcu(*this, "pit"),
488   m_v53dmau(*this, "upd71071dma"),
489   m_v53icu(*this, "upd71059pic"),
490   m_v53scu(*this, "v53scu")
517491{
518492}
519493
trunk/src/emu/cpu/nec/v53.h
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6262   DECLARE_READ8_MEMBER(scu_simk_r);
6363   DECLARE_WRITE8_MEMBER(scu_simk_w);
6464
65   // ICU
66   DECLARE_READ8_MEMBER(icu_0_r);
67   DECLARE_WRITE8_MEMBER(icu_0_w);
68   DECLARE_READ8_MEMBER(icu_1_r);
69   DECLARE_WRITE8_MEMBER(icu_1_w);
7065
7166   void install_peripheral_io();
7267
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8176      }
8277   }
8378
84   required_device<pit8253_device> m_pit;
85   required_device<upd71071_v53_device> m_dma_71071mode;
86   required_device<pic8259_device> m_upd71059;
87   required_device<i8251_device> m_upd71051;
79   required_device<pit8253_device> m_v53tcu;
80   required_device<upd71071_v53_device> m_v53dmau;
81   required_device<pic8259_device> m_v53icu;
82   required_device<v53_scu_device> m_v53scu;
8883
8984   DECLARE_WRITE_LINE_MEMBER(dreq0_trampoline_w);
9085   DECLARE_WRITE_LINE_MEMBER(dreq1_trampoline_w);
trunk/src/emu/machine/am9517a.c
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44
55    AMD AM9517A
66   Intel 8237A
7   NEC UPD71071
7   NEC uPD71037
8
9   NEC uPD71071 (extended version of above)
10
11   a variant is used in the V53 CPU which offers subsets of both the
12   uPD71071 and uPD71037 functionality depending on a mode bit.
813   
914   Multimode DMA Controller emulation
1015
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1722
1823    TODO:
1924
20    - memory-to-memory transfer
2125    - external EOP
2226
2327*/
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4751//**************************************************************************
4852
4953const device_type AM9517A = &device_creator<am9517a_device>;
50const device_type UPD71071_V53 = &device_creator<upd71071_v53_device>;
54const device_type V53_DMAU = &device_creator<upd71071_v53_device>;
5155
5256
5357//**************************************************************************
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471475
472476
473477am9517a_device::am9517a_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname)
474   : device_t(mconfig, AM9517A, name, tag, owner, clock, shortname, __FILE__),
478   : device_t(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
475479      device_execute_interface(mconfig, *this),
476480      m_icount(0),
477481      m_hack(0),
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525529}
526530
527531upd71071_v53_device::upd71071_v53_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
528   : am9517a_device(mconfig, UPD71071_V53, "UPD71071 (V53)", tag, owner, clock, "upd71071_v53")
532   : am9517a_device(mconfig, V53_DMAU, "V53 DMAU", tag, owner, clock, "v53_dmau")
529533{
530534}
531535
trunk/src/emu/machine/am9517a.h
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183183
184184// device type definition
185185extern const device_type AM9517A;
186extern const device_type UPD71071_V53;
186extern const device_type V53_DMAU;
187187
188188
189189/***************************************************************************
trunk/src/emu/machine/i8251.c
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33    i8251.c
44
55    Intel 8251 Universal Synchronous/Asynchronous Receiver Transmitter code
6   NEC uPD71051 is a clone
67
8   The V53/V53A use a customized version with only the Asynchronous mode
9   and a split command / mode register
10
11
12
713*********************************************************************/
814
915#include "emu.h"
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2329//**************************************************************************
2430
2531const device_type I8251 = &device_creator<i8251_device>;
32const device_type V53_SCU = &device_creator<v53_scu_device>;
2633
2734//-------------------------------------------------
2835//  i8251_device - constructor
2936//-------------------------------------------------
3037
38i8251_device::i8251_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname)
39   : device_t(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
40   device_serial_interface(mconfig, *this),
41   m_txd_handler(*this),
42   m_dtr_handler(*this),
43   m_rts_handler(*this),
44   m_rxrdy_handler(*this),
45   m_txrdy_handler(*this),
46   m_txempty_handler(*this),
47   m_syndet_handler(*this),
48   m_cts(1),
49   m_dsr(1),
50   m_rxd(0),
51   m_rxc(0),
52   m_txc(0)
53{
54}
55
3156i8251_device::i8251_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
3257   : device_t(mconfig, I8251, "8251 USART", tag, owner, clock, "i8251", __FILE__),
3358   device_serial_interface(mconfig, *this),
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4671{
4772}
4873
74v53_scu_device::v53_scu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
75   : i8251_device(mconfig, V53_SCU, "V53 SCU", tag, owner, clock, "v53_scu")
76{
77}
78
79
4980//-------------------------------------------------
5081//  device_start - device-specific startup
5182//-------------------------------------------------
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325356    control_w
326357-------------------------------------------------*/
327358
328WRITE8_MEMBER(i8251_device::control_w)
359WRITE8_MEMBER(i8251_device::command_w)
329360{
330   if (m_flags & I8251_EXPECTING_MODE)
361   /* command */
362   LOG(("I8251: Command byte\n"));
363
364   m_command = data;
365
366   LOG(("Command byte: %02x\n", data));
367
368   if (data & (1<<7))
331369   {
332      if (m_flags & I8251_EXPECTING_SYNC_BYTE)
333      {
334         LOG(("I8251: Sync byte\n"));
370      LOG(("hunt mode\n"));
371   }
335372
336         LOG(("Sync byte: %02x\n", data));
337         /* store sync byte written */
338         m_sync_bytes[m_sync_byte_offset] = data;
339         m_sync_byte_offset++;
373   if (data & (1<<5))
374   {
375      LOG(("/rts set to 0\n"));
376   }
377   else
378   {
379      LOG(("/rts set to 1\n"));
380   }
340381
341         if (m_sync_byte_offset == m_sync_byte_count)
382   if (data & (1<<2))
383   {
384      LOG(("receive enable\n"));
385   }
386   else
387   {
388      LOG(("receive disable\n"));
389   }
390
391   if (data & (1<<1))
392   {
393      LOG(("/dtr set to 0\n"));
394   }
395   else
396   {
397      LOG(("/dtr set to 1\n"));
398   }
399
400   if (data & (1<<0))
401   {
402      LOG(("transmit enable\n"));
403
404      /* if we get a tx enable with a disable pending, cancel the disable */
405      m_disable_tx_pending = false;
406   }
407   else
408   {
409      if (m_tx_busy)
410      {
411         if (!m_disable_tx_pending)
342412         {
343            /* finished transfering sync bytes, now expecting command */
344            m_flags &= ~(I8251_EXPECTING_MODE | I8251_EXPECTING_SYNC_BYTE);
345            m_sync_byte_offset = 0;
346         //  m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY;
413            LOG(("Tx busy, set pending disable\n"));
347414         }
415         m_disable_tx_pending = true;
416         m_command |= (1<<0);
348417      }
349418      else
350419      {
351         LOG(("I8251: Mode byte\n"));
352
353         m_mode_byte = data;
354
355         /* Synchronous or Asynchronous? */
356         if ((data & 0x03)!=0)
420         LOG(("transmit disable\n"));
421         if ((data & (1<<0))==0)
357422         {
358            /*  Asynchronous
423            /* held in high state when transmit disable */
424            m_txd_handler(1);
425         }
426      }
427   }
359428
360                bit 7,6: stop bit length
361                    0 = inhibit
362                    1 = 1 bit
363                    2 = 1.5 bits
364                    3 = 2 bits
365                bit 5: parity type
366                    0 = parity odd
367                    1 = parity even
368                bit 4: parity test enable
369                    0 = disable
370                    1 = enable
371                bit 3,2: character length
372                    0 = 5 bits
373                    1 = 6 bits
374                    2 = 7 bits
375                    3 = 8 bits
376                bit 1,0: baud rate factor
377                    0 = defines command byte for synchronous or asynchronous
378                    1 = x1
379                    2 = x16
380                    3 = x64
381            */
382429
383            LOG(("I8251: Asynchronous operation\n"));
430   /*  bit 7:
431          0 = normal operation
432          1 = hunt mode
433      bit 6:
434          0 = normal operation
435          1 = internal reset
436      bit 5:
437          0 = /RTS set to 1
438          1 = /RTS set to 0
439      bit 4:
440          0 = normal operation
441          1 = reset error flag
442      bit 3:
443          0 = normal operation
444          1 = send break character
445      bit 2:
446          0 = receive disable
447          1 = receive enable
448      bit 1:
449          0 = /DTR set to 1
450          1 = /DTR set to 0
451      bit 0:
452          0 = transmit disable
453          1 = transmit enable
454   */
384455
385            LOG(("Character length: %d\n", (((data>>2) & 0x03)+5)));
456   m_rts_handler(!BIT(data, 5));
457   m_dtr_handler(!BIT(data, 1));
386458
387            parity_t parity;
459   if (data & (1<<4))
460   {
461      m_status &= ~(I8251_STATUS_PARITY_ERROR | I8251_STATUS_OVERRUN_ERROR | I8251_STATUS_FRAMING_ERROR);
462   }
388463
389            if (data & (1<<4))
390            {
391               LOG(("enable parity checking\n"));
464   if (data & (1<<6))
465   {
466      // datasheet says "returns to mode format", not
467      // completely resets the chip.  behavior of DEC Rainbow
468      // backs this up.
469      m_flags |= I8251_EXPECTING_MODE;
470   }
392471
393               if (data & (1<<5))
394               {
395                  LOG(("even parity\n"));
396                  parity = PARITY_EVEN;
397               }
398               else
399               {
400                  LOG(("odd parity\n"));
401                  parity = PARITY_ODD;
402               }
403            }
404            else
405            {
406               LOG(("parity check disabled\n"));
407               parity = PARITY_NONE;
408            }
472   update_rx_ready();
473   update_tx_ready();
474}
409475
410            stop_bits_t stop_bits;
476WRITE8_MEMBER(i8251_device::mode_w)
477{
478   LOG(("I8251: Mode byte\n"));
411479
412            switch ((data>>6) & 0x03)
413            {
414            case 0:
415            default:
416               stop_bits = STOP_BITS_0;
417               LOG(("stop bit: inhibit\n"));
418               break;
480   m_mode_byte = data;
419481
420            case 1:
421               stop_bits = STOP_BITS_1;
422               LOG(("stop bit: 1 bit\n"));
423               break;
482   /* Synchronous or Asynchronous? */
483   if ((data & 0x03) != 0)
484   {
485      /*  Asynchronous
424486
425            case 2:
426               stop_bits = STOP_BITS_1_5;
427               LOG(("stop bit: 1.5 bits\n"));
428               break;
487         bit 7,6: stop bit length
488         0 = inhibit
489         1 = 1 bit
490         2 = 1.5 bits
491         3 = 2 bits
492         bit 5: parity type
493         0 = parity odd
494         1 = parity even
495         bit 4: parity test enable
496         0 = disable
497         1 = enable
498         bit 3,2: character length
499         0 = 5 bits
500         1 = 6 bits
501         2 = 7 bits
502         3 = 8 bits
503         bit 1,0: baud rate factor
504         0 = defines command byte for synchronous or asynchronous
505         1 = x1
506         2 = x16
507         3 = x64
508         */
429509
430            case 3:
431               stop_bits = STOP_BITS_2;
432               LOG(("stop bit: 2 bits\n"));
433               break;
434            }
510      LOG(("I8251: Asynchronous operation\n"));
435511
436            int data_bits_count = ((data>>2) & 0x03)+5;
512      LOG(("Character length: %d\n", (((data >> 2) & 0x03) + 5)));
437513
438            set_data_frame(1, data_bits_count, parity, stop_bits);
439            receive_register_reset();
514      parity_t parity;
440515
441            switch (data & 0x03)
442            {
443            case 1: m_br_factor = 1; break;
444            case 2: m_br_factor = 16; break;
445            case 3: m_br_factor = 64; break;
446            }
516      if (data & (1 << 4))
517      {
518         LOG(("enable parity checking\n"));
447519
448            m_rxc_count = m_txc_count = 0;
449
450#if 0
451            /* data bits */
452            m_receive_char_length = (((data>>2) & 0x03)+5);
453
454            if (data & (1<<4))
455            {
456               /* parity */
457               m_receive_char_length++;
458            }
459
460            /* stop bits */
461            m_receive_char_length++;
462
463            m_receive_flags &=~I8251_TRANSFER_RECEIVE_SYNCHRONISED;
464            m_receive_flags |= I8251_TRANSFER_RECEIVE_WAITING_FOR_START_BIT;
465#endif
466            /* not expecting mode byte now */
467            m_flags &= ~I8251_EXPECTING_MODE;
468//              m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY;
520         if (data & (1 << 5))
521         {
522            LOG(("even parity\n"));
523            parity = PARITY_EVEN;
469524         }
470525         else
471526         {
472            /*  bit 7: Number of sync characters
473                    0 = 1 character
474                    1 = 2 character
475                bit 6: Synchronous mode
476                    0 = Internal synchronisation
477                    1 = External synchronisation
478                bit 5: parity type
479                    0 = parity odd
480                    1 = parity even
481                bit 4: parity test enable
482                    0 = disable
483                    1 = enable
484                bit 3,2: character length
485                    0 = 5 bits
486                    1 = 6 bits
487                    2 = 7 bits
488                    3 = 8 bits
489                bit 1,0 = 0
490            */
491            LOG(("I8251: Synchronous operation\n"));
492
493            /* setup for sync byte(s) */
494            m_flags |= I8251_EXPECTING_SYNC_BYTE;
495            m_sync_byte_offset = 0;
496            if (data & 0x07)
497            {
498               m_sync_byte_count = 1;
499            }
500            else
501            {
502               m_sync_byte_count = 2;
503            }
504
527            LOG(("odd parity\n"));
528            parity = PARITY_ODD;
505529         }
506530      }
507   }
508   else
509   {
510      /* command */
511      LOG(("I8251: Command byte\n"));
531      else
532      {
533         LOG(("parity check disabled\n"));
534         parity = PARITY_NONE;
535      }
512536
513      m_command = data;
537      stop_bits_t stop_bits;
514538
515      LOG(("Command byte: %02x\n", data));
539      switch ((data >> 6) & 0x03)
540      {
541      case 0:
542      default:
543         stop_bits = STOP_BITS_0;
544         LOG(("stop bit: inhibit\n"));
545         break;
516546
517      if (data & (1<<7))
518      {
519         LOG(("hunt mode\n"));
547      case 1:
548         stop_bits = STOP_BITS_1;
549         LOG(("stop bit: 1 bit\n"));
550         break;
551
552      case 2:
553         stop_bits = STOP_BITS_1_5;
554         LOG(("stop bit: 1.5 bits\n"));
555         break;
556
557      case 3:
558         stop_bits = STOP_BITS_2;
559         LOG(("stop bit: 2 bits\n"));
560         break;
520561      }
521562
522      if (data & (1<<5))
563      int data_bits_count = ((data >> 2) & 0x03) + 5;
564
565      set_data_frame(1, data_bits_count, parity, stop_bits);
566      receive_register_reset();
567
568      switch (data & 0x03)
523569      {
524         LOG(("/rts set to 0\n"));
570      case 1: m_br_factor = 1; break;
571      case 2: m_br_factor = 16; break;
572      case 3: m_br_factor = 64; break;
525573      }
526      else
527      {
528         LOG(("/rts set to 1\n"));
529      }
530574
531      if (data & (1<<2))
575      m_rxc_count = m_txc_count = 0;
576
577#if 0
578      /* data bits */
579      m_receive_char_length = (((data >> 2) & 0x03) + 5);
580
581      if (data & (1 << 4))
532582      {
533         LOG(("receive enable\n"));
583         /* parity */
584         m_receive_char_length++;
534585      }
535      else
536      {
537         LOG(("receive disable\n"));
538      }
539586
540      if (data & (1<<1))
587      /* stop bits */
588      m_receive_char_length++;
589
590      m_receive_flags &= ~I8251_TRANSFER_RECEIVE_SYNCHRONISED;
591      m_receive_flags |= I8251_TRANSFER_RECEIVE_WAITING_FOR_START_BIT;
592#endif
593      /* not expecting mode byte now */
594      m_flags &= ~I8251_EXPECTING_MODE;
595      //              m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY;
596   }
597   else
598   {
599      /*  bit 7: Number of sync characters
600            0 = 1 character
601            1 = 2 character
602            bit 6: Synchronous mode
603            0 = Internal synchronisation
604            1 = External synchronisation
605            bit 5: parity type
606            0 = parity odd
607            1 = parity even
608            bit 4: parity test enable
609            0 = disable
610            1 = enable
611            bit 3,2: character length
612            0 = 5 bits
613            1 = 6 bits
614            2 = 7 bits
615            3 = 8 bits
616            bit 1,0 = 0
617            */
618      LOG(("I8251: Synchronous operation\n"));
619
620      /* setup for sync byte(s) */
621      m_flags |= I8251_EXPECTING_SYNC_BYTE;
622      m_sync_byte_offset = 0;
623      if (data & 0x07)
541624      {
542         LOG(("/dtr set to 0\n"));
625         m_sync_byte_count = 1;
543626      }
544627      else
545628      {
546         LOG(("/dtr set to 1\n"));
629         m_sync_byte_count = 2;
547630      }
548631
549      if (data & (1<<0))
632   }
633}
634
635WRITE8_MEMBER(i8251_device::control_w)
636{
637   if (m_flags & I8251_EXPECTING_MODE)
638   {
639      if (m_flags & I8251_EXPECTING_SYNC_BYTE)
550640      {
551         LOG(("transmit enable\n"));
641         LOG(("I8251: Sync byte\n"));
552642
553         /* if we get a tx enable with a disable pending, cancel the disable */
554         m_disable_tx_pending = false;
555      }
556      else
557      {
558         if (m_tx_busy)
643         LOG(("Sync byte: %02x\n", data));
644         /* store sync byte written */
645         m_sync_bytes[m_sync_byte_offset] = data;
646         m_sync_byte_offset++;
647
648         if (m_sync_byte_offset == m_sync_byte_count)
559649         {
560            if (!m_disable_tx_pending)
561            {
562               LOG(("Tx busy, set pending disable\n"));
563            }
564            m_disable_tx_pending = true;
565            m_command |= (1<<0);
650            /* finished transfering sync bytes, now expecting command */
651            m_flags &= ~(I8251_EXPECTING_MODE | I8251_EXPECTING_SYNC_BYTE);
652            m_sync_byte_offset = 0;
653         //  m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY;
566654         }
567         else
568         {
569            LOG(("transmit disable\n"));
570            if ((data & (1<<0))==0)
571            {
572               /* held in high state when transmit disable */
573               m_txd_handler(1);
574            }
575         }
576655      }
577
578
579      /*  bit 7:
580              0 = normal operation
581              1 = hunt mode
582          bit 6:
583              0 = normal operation
584              1 = internal reset
585          bit 5:
586              0 = /RTS set to 1
587              1 = /RTS set to 0
588          bit 4:
589              0 = normal operation
590              1 = reset error flag
591          bit 3:
592              0 = normal operation
593              1 = send break character
594          bit 2:
595              0 = receive disable
596              1 = receive enable
597          bit 1:
598              0 = /DTR set to 1
599              1 = /DTR set to 0
600          bit 0:
601              0 = transmit disable
602              1 = transmit enable
603      */
604
605      m_rts_handler(!BIT(data, 5));
606      m_dtr_handler(!BIT(data, 1));
607
608      if (data & (1<<4))
656      else
609657      {
610         m_status &= ~(I8251_STATUS_PARITY_ERROR | I8251_STATUS_OVERRUN_ERROR | I8251_STATUS_FRAMING_ERROR);
658         mode_w(space, offset, data);
611659      }
612
613      if (data & (1<<6))
614      {
615         // datasheet says "returns to mode format", not
616         // completely resets the chip.  behavior of DEC Rainbow
617         // backs this up.
618         m_flags |= I8251_EXPECTING_MODE;
619      }
620
621      update_rx_ready();
622      update_tx_ready();
623
624660   }
661   else
662   {
663      command_w(space, offset, data);
664   }
625665}
626666
627667
trunk/src/emu/machine/i8251.h
r244870r244871
4040{
4141public:
4242   // construction/destruction
43   i8251_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname);
4344   i8251_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
4445
4546   // static configuration helpers
r244870r244871
5556   DECLARE_WRITE8_MEMBER(data_w);
5657   DECLARE_READ8_MEMBER(status_r);
5758   DECLARE_WRITE8_MEMBER(control_w);
59   DECLARE_WRITE8_MEMBER(command_w);
60   DECLARE_WRITE8_MEMBER(mode_w);
5861
5962   DECLARE_WRITE_LINE_MEMBER( write_rxd );
6063   DECLARE_WRITE_LINE_MEMBER( write_cts );
r244870r244871
132135   bool m_disable_tx_pending;
133136};
134137
138class v53_scu_device :  public i8251_device
139{
140public:
141   // construction/destruction
142   v53_scu_device(const machine_config &mconfig,  const char *tag, device_t *owner, UINT32 clock);
143};
144
145
146
135147// device type definition
136148extern const device_type I8251;
149extern const device_type V53_SCU;
137150
151
138152#endif /* __I8251_H__ */

https://github.com/mamedev/mame/commit/5ac1220284792c6bb76e22c91082078bbfbbc504

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