trunk/src/emu/machine/am9517a.c
| r244838 | r244839 | |
| 474 | 474 | : device_t(mconfig, AM9517A, name, tag, owner, clock, shortname, __FILE__), |
| 475 | 475 | device_execute_interface(mconfig, *this), |
| 476 | 476 | m_icount(0), |
| 477 | m_hack(0), |
| 478 | m_ready(1), |
| 479 | m_command(0), |
| 477 | 480 | m_out_hreq_cb(*this), |
| 478 | 481 | m_out_eop_cb(*this), |
| 479 | 482 | m_in_memr_cb(*this), |
| r244838 | r244839 | |
| 489 | 492 | m_out_dack_0_cb(*this), |
| 490 | 493 | m_out_dack_1_cb(*this), |
| 491 | 494 | m_out_dack_2_cb(*this), |
| 492 | | m_out_dack_3_cb(*this), |
| 493 | | m_hack(0), |
| 494 | | m_ready(1), |
| 495 | | m_command(0) |
| 495 | m_out_dack_3_cb(*this) |
| 496 | 496 | { |
| 497 | 497 | } |
| 498 | 498 | |
| r244838 | r244839 | |
| 501 | 501 | : device_t(mconfig, AM9517A, "AM9517A", tag, owner, clock, "am9517a", __FILE__), |
| 502 | 502 | device_execute_interface(mconfig, *this), |
| 503 | 503 | m_icount(0), |
| 504 | m_hack(0), |
| 505 | m_ready(1), |
| 506 | m_command(0), |
| 504 | 507 | m_out_hreq_cb(*this), |
| 505 | 508 | m_out_eop_cb(*this), |
| 506 | 509 | m_in_memr_cb(*this), |
| r244838 | r244839 | |
| 516 | 519 | m_out_dack_0_cb(*this), |
| 517 | 520 | m_out_dack_1_cb(*this), |
| 518 | 521 | m_out_dack_2_cb(*this), |
| 519 | | m_out_dack_3_cb(*this), |
| 520 | | m_hack(0), |
| 521 | | m_ready(1), |
| 522 | | m_command(0) |
| 522 | m_out_dack_3_cb(*this) |
| 523 | |
| 523 | 524 | { |
| 524 | 525 | } |
| 525 | 526 | |
| r244838 | r244839 | |
| 592 | 593 | |
| 593 | 594 | } |
| 594 | 595 | |
| 595 | | void upd71071_v53_device::device_start() |
| 596 | | { |
| 597 | | am9517a_device::device_start(); |
| 598 | | m_address_mask = 0x00ffffff; |
| 599 | | } |
| 600 | 596 | |
| 601 | 597 | //------------------------------------------------- |
| 602 | 598 | // device_reset - device-specific reset |
| r244838 | r244839 | |
| 1079 | 1075 | // upd71071 register layouts |
| 1080 | 1076 | //------------------------------------------------- |
| 1081 | 1077 | |
| 1078 | void upd71071_v53_device::device_start() |
| 1079 | { |
| 1080 | am9517a_device::device_start(); |
| 1081 | m_address_mask = 0x00ffffff; |
| 1082 | |
| 1083 | m_selected_channel = 0; |
| 1084 | m_base = 0; |
| 1085 | |
| 1086 | save_item(NAME(m_selected_channel)); |
| 1087 | save_item(NAME(m_base)); |
| 1088 | } |
| 1089 | |
| 1090 | void upd71071_v53_device::device_reset() |
| 1091 | { |
| 1092 | am9517a_device::device_reset(); |
| 1093 | |
| 1094 | m_selected_channel = 0; |
| 1095 | m_base = 0; |
| 1096 | } |
| 1097 | |
| 1098 | |
| 1082 | 1099 | READ8_MEMBER(upd71071_v53_device::read) |
| 1083 | 1100 | { |
| 1084 | | // printf("upd71071_v53_device read %02x\n", offset); |
| 1085 | | return 0x00; |
| 1101 | UINT8 ret = 0; |
| 1102 | int channel = m_selected_channel; |
| 1103 | |
| 1104 | logerror("DMA: read from register %02x\n",offset); |
| 1105 | switch (offset) |
| 1106 | { |
| 1107 | case 0x01: // Channel |
| 1108 | ret = (1 << m_selected_channel); |
| 1109 | if (m_base != 0) |
| 1110 | ret |= 0x10; |
| 1111 | break; |
| 1112 | case 0x02: // Count (low) |
| 1113 | if (m_base != 0) |
| 1114 | ret = m_channel[channel].m_base_count & 0xff; |
| 1115 | else |
| 1116 | ret = m_channel[channel].m_count & 0xff; |
| 1117 | break; |
| 1118 | case 0x03: // Count (high) |
| 1119 | if (m_base != 0) |
| 1120 | ret = (m_channel[channel].m_base_count >> 8) & 0xff; |
| 1121 | else |
| 1122 | ret = (m_channel[channel].m_count >> 8) & 0xff; |
| 1123 | break; |
| 1124 | case 0x04: // Address (low) |
| 1125 | if (m_base != 0) |
| 1126 | ret = m_channel[channel].m_base_address & 0xff; |
| 1127 | else |
| 1128 | ret = m_channel[channel].m_address & 0xff; |
| 1129 | break; |
| 1130 | case 0x05: // Address (mid) |
| 1131 | if (m_base != 0) |
| 1132 | ret = (m_channel[channel].m_base_address >> 8) & 0xff; |
| 1133 | else |
| 1134 | ret = (m_channel[channel].m_address >> 8) & 0xff; |
| 1135 | break; |
| 1136 | case 0x06: // Address (high) |
| 1137 | if (m_base != 0) |
| 1138 | ret = (m_channel[channel].m_base_address >> 16) & 0xff; |
| 1139 | else |
| 1140 | ret = (m_channel[channel].m_address >> 16) & 0xff; |
| 1141 | break; |
| 1142 | case 0x07: // Address (highest) |
| 1143 | if (m_base != 0) |
| 1144 | ret = (m_channel[channel].m_base_address >> 24) & 0xff; |
| 1145 | else |
| 1146 | ret = (m_channel[channel].m_address >> 24) & 0xff; |
| 1147 | break; |
| 1148 | case 0x0a: // Mode control |
| 1149 | ret = (m_channel[channel].m_mode); |
| 1150 | break; |
| 1151 | |
| 1152 | case 0x08: // Device control (low) |
| 1153 | ret = m_command & 0xff; |
| 1154 | break; |
| 1155 | case 0x09: // Device control (high) // UPD71071 only? |
| 1156 | ret = m_command_high & 0xff; |
| 1157 | break; |
| 1158 | case 0x0b: // Status |
| 1159 | ret = m_status; |
| 1160 | // clear TC bits |
| 1161 | m_status &= 0xf0; |
| 1162 | break; |
| 1163 | case 0x0c: // Temporary (low) |
| 1164 | ret = m_temp & 0xff; |
| 1165 | break; |
| 1166 | case 0x0d: // Temporary (high) // UPD71071 only? (other doesn't do 16-bit?) |
| 1167 | ret = (m_temp >> 8 ) & 0xff; |
| 1168 | break; |
| 1169 | case 0x0e: // Request |
| 1170 | //ret = m_reg.request; |
| 1171 | ret = 0; // invalid? |
| 1172 | break; |
| 1173 | case 0x0f: // Mask |
| 1174 | ret = m_mask; |
| 1175 | break; |
| 1176 | |
| 1177 | } |
| 1178 | |
| 1179 | return ret; |
| 1086 | 1180 | } |
| 1087 | 1181 | |
| 1088 | 1182 | WRITE8_MEMBER(upd71071_v53_device::write) |
| 1089 | 1183 | { |
| 1090 | | // printf("upd71071_v53_device write %02x %02x\n", offset, data); |
| 1184 | int channel = m_selected_channel; |
| 1185 | |
| 1186 | switch (offset) |
| 1187 | { |
| 1188 | case 0x00: // Initialise |
| 1189 | // TODO: reset (bit 0) |
| 1190 | //m_buswidth = data & 0x02; |
| 1191 | //if (data & 0x01) |
| 1192 | // soft_reset(); |
| 1193 | logerror("DMA: Initialise [%02x]\n", data); |
| 1194 | break; |
| 1195 | case 0x01: // Channel |
| 1196 | m_selected_channel = data & 0x03; |
| 1197 | m_base = data & 0x04; |
| 1198 | logerror("DMA: Channel selected [%02x]\n", data); |
| 1199 | break; |
| 1200 | case 0x02: // Count (low) |
| 1201 | m_channel[channel].m_base_count = |
| 1202 | (m_channel[channel].m_base_count & 0xff00) | data; |
| 1203 | if (m_base == 0) |
| 1204 | m_channel[channel].m_count = |
| 1205 | (m_channel[channel].m_count & 0xff00) | data; |
| 1206 | logerror("DMA: Channel %i Counter set [%04x]\n", m_selected_channel, m_channel[channel].m_base_count); |
| 1207 | break; |
| 1208 | case 0x03: // Count (high) |
| 1209 | m_channel[channel].m_base_count = |
| 1210 | (m_channel[channel].m_base_count & 0x00ff) | (data << 8); |
| 1211 | if (m_base == 0) |
| 1212 | m_channel[channel].m_count = |
| 1213 | (m_channel[channel].m_count & 0x00ff) | (data << 8); |
| 1214 | logerror("DMA: Channel %i Counter set [%04x]\n", m_selected_channel, m_channel[channel].m_base_count); |
| 1215 | break; |
| 1216 | case 0x04: // Address (low) |
| 1217 | m_channel[channel].m_base_address = |
| 1218 | (m_channel[channel].m_base_address & 0xffffff00) | data; |
| 1219 | if (m_base == 0) |
| 1220 | m_channel[channel].m_address = |
| 1221 | (m_channel[channel].m_address & 0xffffff00) | data; |
| 1222 | logerror("DMA: Channel %i Address set [%08x]\n", m_selected_channel, m_channel[channel].m_base_address); |
| 1223 | break; |
| 1224 | case 0x05: // Address (mid) |
| 1225 | m_channel[channel].m_base_address = |
| 1226 | (m_channel[channel].m_base_address & 0xffff00ff) | (data << 8); |
| 1227 | if (m_base == 0) |
| 1228 | m_channel[channel].m_address = |
| 1229 | (m_channel[channel].m_address & 0xffff00ff) | (data << 8); |
| 1230 | logerror("DMA: Channel %i Address set [%08x]\n", m_selected_channel, m_channel[channel].m_base_address); |
| 1231 | break; |
| 1232 | case 0x06: // Address (high) |
| 1233 | m_channel[channel].m_base_address = |
| 1234 | (m_channel[channel].m_base_address & 0xff00ffff) | (data << 16); |
| 1235 | if (m_base == 0) |
| 1236 | m_channel[channel].m_address = |
| 1237 | (m_channel[channel].m_address & 0xff00ffff) | (data << 16); |
| 1238 | logerror("DMA: Channel %i Address set [%08x]\n", m_selected_channel, m_channel[channel].m_base_address); |
| 1239 | break; |
| 1240 | case 0x07: // Address (highest) |
| 1241 | m_channel[channel].m_base_address = |
| 1242 | (m_channel[channel].m_base_address & 0x00ffffff) | (data << 24); |
| 1243 | if (m_base == 0) |
| 1244 | m_channel[channel].m_address = |
| 1245 | (m_channel[channel].m_address & 0x00ffffff) | (data << 24); |
| 1246 | logerror("DMA: Channel %i Address set [%08x]\n", m_selected_channel, m_channel[channel].m_base_address); |
| 1247 | break; |
| 1248 | case 0x0a: // Mode control |
| 1249 | m_channel[channel].m_mode = data; |
| 1250 | // clear terminal count |
| 1251 | m_status &= ~(1 << channel); |
| 1252 | |
| 1253 | logerror("DMA: Channel %i Mode control set [%02x]\n",m_selected_channel,m_channel[channel].m_mode); |
| 1254 | break; |
| 1255 | |
| 1256 | case 0x08: // Device control (low) |
| 1257 | m_command = data; |
| 1258 | logerror("DMA: Device control low set [%02x]\n",data); |
| 1259 | break; |
| 1260 | case 0x09: // Device control (high) |
| 1261 | m_command_high = data; |
| 1262 | logerror("DMA: Device control high set [%02x]\n",data); |
| 1263 | break; |
| 1264 | case 0x0e: // Request |
| 1265 | //m_reg.request = data; |
| 1266 | logerror("(invalid) DMA: Request set [%02x]\n",data); // no software requests on the v53 integrated version |
| 1267 | break; |
| 1268 | case 0x0f: // Mask |
| 1269 | m_mask = data & 0x0f; |
| 1270 | logerror("DMA: Mask set [%02x]\n",data); |
| 1271 | break; |
| 1272 | |
| 1273 | |
| 1274 | } |
| 1275 | |
| 1091 | 1276 | } |
| | No newline at end of file |