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r36311 Saturday 7th March, 2015 at 22:42:15 UTC by David Haywood
shuffle more HNG64 stuff around, add stub CPU classes for the different CPU types it uses so that we can start implementing the peripherals properly rather than hacking them into the driver (nw)
[src/emu/cpu]cpu.mak
[src/emu/cpu/nec]nec.c nec.h
[src/emu/cpu/z80]kl5c80a12.c* kl5c80a12.h*
[src/mame]mame.mak
[src/mame/audio]hng64.c*
[src/mame/drivers]hng64.c
[src/mame/includes]hng64.h
[src/mame/machine]hng64_net.c*

trunk/src/emu/cpu/cpu.mak
r244822r244823
23712371CPUOBJS += $(CPUOBJ)/z80/z80.o \
23722372   $(CPUOBJ)/z80/z80daisy.o \
23732373   $(CPUOBJ)/z80/tmpz84c011.o \
2374   $(CPUOBJ)/z80/tmpz84c015.o
2374   $(CPUOBJ)/z80/tmpz84c015.o \
2375   $(CPUOBJ)/z80/kl5c80a12.o
23752376
23762377DASMOBJS += $(CPUOBJ)/z80/z80dasm.o
23772378endif
trunk/src/emu/cpu/nec/nec.c
r244822r244823
5151
5252
5353
54    V33A = uPD70136A
55
54    V33A = uPD70136A (interrupt vector #s compatible with x86)
5655    V53A = uPD70236A
5756
5857
r244822r244823
6160        V20, V30, V40, V50 have dedicated emulation instructions
6261            (BRKEM, RETEM, CALLN)
6362
64        V33A, V53A has dedicated address mode instructions
63        V33 / V33A has dedicated address mode instructions (V53 / V53A are based on those cores with extra peripherals)
6564            (BRKXA, RETXA)
6665
6766
r244822r244823
117116const device_type V20 = &device_creator<v20_device>;
118117const device_type V30 = &device_creator<v30_device>;
119118const device_type V33 = &device_creator<v33_device>;
119const device_type V33A =&device_creator<v33a_device>;
120const device_type V53 = &device_creator<v53_device>;
121const device_type V53A =&device_creator<v53a_device>;
120122
121123
122124nec_common_device::nec_common_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, bool is_16bit, offs_t fetch_xor, UINT8 prefetch_size, UINT8 prefetch_cycles, UINT32 chip_type)
r244822r244823
152154}
153155
154156
157v33a_device::v33a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
158   : nec_common_device(mconfig, V33A, "V33A", tag, owner, clock, "v33A", true, BYTE_XOR_LE(0), 6, 1, V33_TYPE)
159{
160}
161
162v53_device::v53_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
163   : nec_common_device(mconfig, V53, "V53", tag, owner, clock, "v53", true, BYTE_XOR_LE(0), 6, 1, V33_TYPE)
164{
165}
166
167v53a_device::v53a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
168   : nec_common_device(mconfig, V53A, "V53A", tag, owner, clock, "v53a", true, BYTE_XOR_LE(0), 6, 1, V33_TYPE)
169{
170}
171
155172offs_t nec_common_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
156173{
157174   extern CPU_DISASSEMBLE( nec );
trunk/src/emu/cpu/nec/nec.h
r244822r244823
414414   v33_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
415415};
416416
417class v33a_device : public nec_common_device
418{
419public:
420   v33a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
421};
417422
423class v53_device : public nec_common_device
424{
425public:
426   v53_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
427};
428
429class v53a_device : public nec_common_device
430{
431public:
432   v53a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
433};
434
435
418436extern const device_type V20;
419437extern const device_type V30;
420438extern const device_type V33;
439extern const device_type V33A;
440extern const device_type V53;
441extern const device_type V53A;
421442
422443
423444#endif
trunk/src/emu/cpu/z80/kl5c80a12.c
r0r244823
1/***************************************************************************
2
3   Kawasaki LSI
4   KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
5
6   Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
7   Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
8
9   (is this different enough to need it's own core?)
10   (todo: everything, some code currently lives in machine/hng64_net.c but not much)
11
12***************************************************************************/
13
14#include "KL5C80A12.h"
15
16const device_type KL5C80A12 = &device_creator<kl5c80a12_device>;
17
18
19kl5c80a12_device::kl5c80a12_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
20   : z80_device(mconfig, KL5C80A12, "KL5C80A12", tag, owner, clock, "KL5C80A12", __FILE__)
21{
22}
23
24
25//-------------------------------------------------
26//  device_start - device-specific startup
27//-------------------------------------------------
28
29void kl5c80a12_device::device_start()
30{
31   z80_device::device_start();
32}
33
34
35//-------------------------------------------------
36//  device_reset - device-specific reset
37//-------------------------------------------------
38
39void kl5c80a12_device::device_reset()
40{
41   z80_device::device_reset();
42}
43
44
45/* CPU interface */
46static MACHINE_CONFIG_FRAGMENT( kl5c80a12 )
47MACHINE_CONFIG_END
48
49machine_config_constructor kl5c80a12_device::device_mconfig_additions() const
50{
51   return MACHINE_CONFIG_NAME( kl5c80a12 );
52}
trunk/src/emu/cpu/z80/kl5c80a12.h
r0r244823
1/***************************************************************************
2
3   Kawasaki LSI
4   KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
5
6   Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
7   Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
8
9   (is this different enough to need it's own core?)
10   (todo: everything, some code currently lives in machine/hng64_net.c but not much)
11
12***************************************************************************/
13
14#pragma once
15
16#ifndef __KL5C80A12__
17#define __KL5C80A12__
18
19#include "emu.h"
20#include "z80.h"
21#include "machine/z80ctc.h"
22
23
24/***************************************************************************
25    DEVICE CONFIGURATION MACROS
26***************************************************************************/
27
28
29/***************************************************************************
30    TYPE DEFINITIONS
31***************************************************************************/
32
33class kl5c80a12_device : public z80_device
34{
35public:
36   kl5c80a12_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
37
38   // static configuration helpers
39
40protected:
41   // device-level overrides
42   virtual machine_config_constructor device_mconfig_additions() const;
43   virtual void device_start();
44   virtual void device_reset();
45
46
47private:
48   // devices/pointers
49
50   // internal state
51
52   // callbacks
53};
54
55
56// device type definition
57extern const device_type KL5C80A12;
58
59
60#endif /// __KL5C80A12__
trunk/src/mame/audio/hng64.c
r0r244823
1/* Hyper NeoGeo 64 Audio */
2
3// uses a V53A ( == V33A with extra peripherals eg. DMA, Timers, MMU giving virtual 24-bit address space etc.)
4
5/* The uploaded code shows that several different sound program revisions were used
6
7sams64    (#)SNK R&D Center (R) NEO-GEO64 Sound Driver Ver 1.00a.     (#)Copyright (C) SNK Corp. 1996-1997 All rights reserved
8roadedge  (#)SNK R&D Center (R) NEO-GEO64 Sound Driver Ver 1.10.      (#)Copyright (C) SNK Corp. 1996-1997 All rights reserved
9xrally    (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.10. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved
10bbust2    (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.11. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved
11sams64_2  (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.14. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved
12fatfurwa  (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.14. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved
13buriki    (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.15. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved
14
15the earlier revisions appear to have 2 banks of code (there are vectors at the end of the 0x1e0000 block and the 0x1f0000 block)
16
17data structures look very similar between all of them
18
19*/
20
21
22#include "includes/hng64.h"
23
24// save the sound program?
25#define DUMP_SOUNDPRG  0
26
27// ----------------------------------------------
28// MIPS side
29// ----------------------------------------------
30
31// if you actually map RAM here on the MIPS side then xrally will upload the actual sound program here and blank out the area where
32// the program would usually be uploaded (and where all other games upload it) this seems to suggest that the area is unmapped on
33// real hardware.
34WRITE32_MEMBER(hng64_state::hng64_soundram2_w)
35{
36}
37
38READ32_MEMBER(hng64_state::hng64_soundram2_r)
39{
40   return 0x0000;
41}
42
43
44WRITE32_MEMBER(hng64_state::hng64_soundram_w)
45{
46   //logerror("hng64_soundram_w %08x: %08x %08x\n", offset, data, mem_mask);
47
48   UINT32 mem_mask32 = mem_mask;
49   UINT32 data32 = data;
50
51   /* swap data around.. keep the v55 happy */
52   data = data32 >> 16;
53   data = FLIPENDIAN_INT16(data);
54   mem_mask = mem_mask32 >> 16;
55   mem_mask = FLIPENDIAN_INT16(mem_mask);
56   COMBINE_DATA(&m_soundram[offset * 2 + 0]);
57
58   data = data32 & 0xffff;
59   data = FLIPENDIAN_INT16(data);
60   mem_mask = mem_mask32 & 0xffff;
61   mem_mask = FLIPENDIAN_INT16(mem_mask);
62   COMBINE_DATA(&m_soundram[offset * 2 + 1]);
63
64   if (DUMP_SOUNDPRG)
65   {
66      if (offset==0x7ffff)
67      {
68         logerror("dumping sound program in m_soundram\n");
69         FILE *fp;
70         char filename[256];
71         sprintf(filename,"soundram_%s", space.machine().system().name);
72         fp=fopen(filename, "w+b");
73         if (fp)
74         {
75            fwrite((UINT8*)m_soundram, 0x80000*4, 1, fp);
76            fclose(fp);
77         }
78      }
79   }
80}
81
82
83READ32_MEMBER(hng64_state::hng64_soundram_r)
84{
85   UINT16 datalo = m_soundram[offset * 2 + 0];
86   UINT16 datahi = m_soundram[offset * 2 + 1];
87
88   return FLIPENDIAN_INT16(datahi) | (FLIPENDIAN_INT16(datalo) << 16);
89}
90
91WRITE32_MEMBER( hng64_state::hng64_soundcpu_enable_w )
92{
93   if (mem_mask&0xffff0000)
94   {
95      int cmd = data >> 16;
96      // I guess it's only one of the bits, the commands are inverse of each other
97      if (cmd==0x55AA)
98      {
99         printf("soundcpu ON\n");
100         m_audiocpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
101         m_audiocpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
102      }
103      else if (cmd==0xAA55)
104      {
105         printf("soundcpu OFF\n");
106         m_audiocpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
107         m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
108      }
109      else
110      {
111         printf("unknown hng64_soundcpu_enable_w cmd %04x\n", cmd);
112      }
113   }
114
115   if (mem_mask&0x0000ffff)
116   {
117         printf("unknown hng64_soundcpu_enable_w %08x %08x\n", data, mem_mask);
118   }
119}
120
121// ----------------------------------------------
122// General
123// ----------------------------------------------
124
125
126void hng64_state::reset_sound()
127{
128   UINT8 *RAM = (UINT8*)m_soundram;
129   membank("bank1")->set_base(&RAM[0x1f0000]); // allows us to boot
130   membank("bank2")->set_base(&RAM[0x1f0000]); // seems to be the right default for most games (initial area jumps to a DI here)
131   m_audiocpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
132   m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
133}
134
135// ----------------------------------------------
136// V53A side
137// ----------------------------------------------
138
139
140static ADDRESS_MAP_START( hng_sound_map, AS_PROGRAM, 16, hng64_state )
141   AM_RANGE(0x00000, 0x0ffff) AM_RAMBANK("bank2")
142   AM_RANGE(0x10000, 0x1ffff) AM_RAM // tmp, roadedge
143   AM_RANGE(0xf0000, 0xfffff) AM_RAMBANK("bank1")
144ADDRESS_MAP_END
145
146static ADDRESS_MAP_START( hng_sound_io, AS_IO, 16, hng64_state )
147   AM_RANGE(0xc002, 0xc003) AM_NOP // buriki one fills the log, wants 0xffff
148ADDRESS_MAP_END
149
150MACHINE_CONFIG_FRAGMENT( hng64_audio )
151   MCFG_CPU_ADD("audiocpu", V53A, 16000000)              // V53A, 16? mhz!
152   MCFG_CPU_PROGRAM_MAP(hng_sound_map)
153   MCFG_CPU_IO_MAP(hng_sound_io)
154MACHINE_CONFIG_END
155
156   
trunk/src/mame/drivers/hng64.c
r244822r244823
224224
225225Games that use the LVS-DG2 cart: Fatal Fury: Wild Ambition, Buriki One, SS 64 II
226226
227Other games not dumped yet     : Samurai Spirits 64 / Samurai Shodown 64
228                                 Samurai Spirits II: Asura Zanmaden / Samurai Shodown: Warrior's Rage
229                                 Off Beat Racer / Xtreme Rally
230                                 Beast Busters: Second Nightmare
231                                 Garou Densetsu 64: Wild Ambition (=Fatal Fury Wild Ambition)*
232                                 Round Trip RV (=Road's Edge)*
227There might be Rev.A boards for Buriki and Round Trip, we have Rev. B
233228
234                               * Different regions might use the same roms, not known yet
235
236                               There might be Rev.A boards for Buriki and Round Trip
237
238229pr = program
239230sc = scroll characters?
240231sd = sound
r244822r244823
444435or Fatal Fury for example).
445436*/
446437
447#define DUMP_SOUNDPRG  0
448438
449#define MASTER_CLOCK 50000000
439
450440#include "emu.h"
451441#include "cpu/z80/z80.h"
452#include "cpu/nec/nec.h"
453442#include "cpu/mips/mips3.h"
454443#include "machine/nvram.h"
455444#include "includes/hng64.h"
456445
457446/* TODO: NOT measured! */
458#define PIXEL_CLOCK         ((MASTER_CLOCK*2)/4) // x 2 is due of the interlaced screen ...
447#define PIXEL_CLOCK         ((HNG64_MASTER_CLOCK*2)/4) // x 2 is due of the interlaced screen ...
459448
460449#define HTOTAL              (0x200+0x100)
461450#define HBEND               (0)
r244822r244823
866855//  return ++m_unk_vreg_toggle;
867856}
868857
869/***** I don't think there is a soundram2, having it NOT hooked up causes xrally to copy the sound program to the expected location, see memory map note *****/
870858
871WRITE32_MEMBER(hng64_state::hng64_soundram2_w)
872{
873   // xrally uploads the sound program here, and 00 in the usual hng64_soundram_w straight after it??
874   logerror("hng64_soundram2_w %08x: %08x %08x\n", offset, data, mem_mask);
875859
876   UINT32 mem_mask32 = mem_mask;
877   UINT32 data32 = data;
878
879   /* swap data around.. keep the v55 happy */
880   data = data32 >> 16;
881   data = FLIPENDIAN_INT16(data);
882   mem_mask = mem_mask32 >> 16;
883   mem_mask = FLIPENDIAN_INT16(mem_mask);
884   COMBINE_DATA(&m_soundram2[offset * 2 + 0]);
885
886   data = data32 & 0xffff;
887   data = FLIPENDIAN_INT16(data);
888   mem_mask = mem_mask32 & 0xffff;
889   mem_mask = FLIPENDIAN_INT16(mem_mask);
890   COMBINE_DATA(&m_soundram2[offset * 2 + 1]);
891
892   if (DUMP_SOUNDPRG)
893   {
894      if (offset==0x7ffff)
895      {
896         logerror("dumping sound program in m_soundram2\n");
897         FILE *fp;
898         char filename[256];
899         sprintf(filename,"soundram2_%s", space.machine().system().name);
900         fp=fopen(filename, "w+b");
901         if (fp)
902         {
903            fwrite((UINT8*)m_soundram2, 0x80000*4, 1, fp);
904            fclose(fp);
905         }
906      }
907   }
908}
909
910READ32_MEMBER(hng64_state::hng64_soundram2_r)
911{
912   UINT16 datalo = m_soundram2[offset * 2 + 0];
913   UINT16 datahi = m_soundram2[offset * 2 + 1];
914
915   return FLIPENDIAN_INT16(datahi) | (FLIPENDIAN_INT16(datalo) << 16);
916}
917
918860/************************************************************************************************************/
919861
920WRITE32_MEMBER(hng64_state::hng64_soundram_w)
921{
922   //logerror("hng64_soundram_w %08x: %08x %08x\n", offset, data, mem_mask);
923
924   UINT32 mem_mask32 = mem_mask;
925   UINT32 data32 = data;
926
927   /* swap data around.. keep the v55 happy */
928   data = data32 >> 16;
929   data = FLIPENDIAN_INT16(data);
930   mem_mask = mem_mask32 >> 16;
931   mem_mask = FLIPENDIAN_INT16(mem_mask);
932   COMBINE_DATA(&m_soundram[offset * 2 + 0]);
933
934   data = data32 & 0xffff;
935   data = FLIPENDIAN_INT16(data);
936   mem_mask = mem_mask32 & 0xffff;
937   mem_mask = FLIPENDIAN_INT16(mem_mask);
938   COMBINE_DATA(&m_soundram[offset * 2 + 1]);
939
940   if (DUMP_SOUNDPRG)
941   {
942      if (offset==0x7ffff)
943      {
944         logerror("dumping sound program in m_soundram\n");
945         FILE *fp;
946         char filename[256];
947         sprintf(filename,"soundram_%s", space.machine().system().name);
948         fp=fopen(filename, "w+b");
949         if (fp)
950         {
951            fwrite((UINT8*)m_soundram, 0x80000*4, 1, fp);
952            fclose(fp);
953         }
954      }
955   }
956}
957
958
959READ32_MEMBER(hng64_state::hng64_soundram_r)
960{
961   UINT16 datalo = m_soundram[offset * 2 + 0];
962   UINT16 datahi = m_soundram[offset * 2 + 1];
963
964   return FLIPENDIAN_INT16(datahi) | (FLIPENDIAN_INT16(datalo) << 16);
965}
966
967WRITE32_MEMBER( hng64_state::hng64_soundcpu_enable_w )
968{
969   if (mem_mask&0xffff0000)
970   {
971      int cmd = data >> 16;
972      // I guess it's only one of the bits, the commands are inverse of each other
973      if (cmd==0x55AA)
974      {
975         printf("soundcpu ON\n");
976         m_audiocpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
977         m_audiocpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
978      }
979      else if (cmd==0xAA55)
980      {
981         printf("soundcpu OFF\n");
982         m_audiocpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
983         m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
984      }
985      else
986      {
987         printf("unknown hng64_soundcpu_enable_w cmd %04x\n", cmd);
988      }
989   }
990
991   if (mem_mask&0x0000ffff)
992   {
993         printf("unknown hng64_soundcpu_enable_w %08x %08x\n", data, mem_mask);
994   }
995}
996
997862/* The following is guesswork, needs confirmation with a test on the real board. */
998863WRITE32_MEMBER(hng64_state::hng64_sprite_clear_even_w)
999864{
r244822r244823
1060925static ADDRESS_MAP_START( hng_map, AS_PROGRAM, 32, hng64_state )
1061926
1062927   AM_RANGE(0x00000000, 0x00ffffff) AM_RAM AM_SHARE("mainram")
1063   AM_RANGE(0x04000000, 0x05ffffff) AM_WRITENOP AM_ROM AM_REGION("user3", 0) AM_SHARE("cart")
928   AM_RANGE(0x04000000, 0x05ffffff) AM_WRITENOP AM_ROM AM_REGION("gameprg", 0) AM_SHARE("cart")
1064929
1065930   // Ports
1066931   AM_RANGE(0x1f700000, 0x1f702fff) AM_READWRITE(hng64_sysregs_r, hng64_sysregs_w) AM_SHARE("sysregs")
r244822r244823
1094959   AM_RANGE(0x30200000, 0x3025ffff) AM_READWRITE(hng64_3d_2_r, hng64_3d_2_w) AM_SHARE("3d_2")  // 3D Display Buffer B
1095960
1096961   // Sound
1097//  AM_RANGE(0x60000000, 0x601fffff) AM_READWRITE(hng64_soundram2_r, hng64_soundram2_w) // if this area acts as RAM then xrally will copy the sound program here and blank out the usual area below.  None of the other games test this as sound ram (usually just write to the first byte) -- maybe it's actually unmapped?
1098   AM_RANGE(0x60200000, 0x603fffff) AM_READWRITE(hng64_soundram_r, hng64_soundram_w)   // uploads the v53 sound program here, elsewhere on ss64-2
962   AM_RANGE(0x60000000, 0x601fffff) AM_READWRITE(hng64_soundram2_r, hng64_soundram2_w) // actually seems unmapped, see note in audio/hng64.c
963   AM_RANGE(0x60200000, 0x603fffff) AM_READWRITE(hng64_soundram_r, hng64_soundram_w)   // program + data for V53A gets uploaded here
1099964
1100965   // These are sound ports of some sort
1101966//  AM_RANGE(0x68000000, 0x68000003) AM_WRITENOP    // ??
r244822r244823
1115980   /* a0000000-a3ffffff */
1116981ADDRESS_MAP_END
1117982
1118/*
11190x6010: tests RAM at [3]8000
1120983
1121*/
1122
1123UINT8 hng64_state::read_comm_data(UINT32 offset)
1124{
1125   if((offset & 0x10000) == 0)
1126      return m_comm_rom[offset & 0xffff];
1127
1128   if(offset & 0x10000)
1129      return m_comm_ram[(offset & 0xffff)];
1130
1131   printf("%08x\n",offset);
1132   return 0xff;
1133}
1134
1135void hng64_state::write_comm_data(UINT32 offset,UINT8 data)
1136{
1137   if((offset & 0x10000) == 0)
1138   {
1139      //m_comm_rom[offset];
1140      return;
1141   }
1142   if(offset & 0x10000)
1143   {
1144      m_comm_ram[offset & 0xffff] = data;
1145      return;
1146   }
1147
1148
1149   printf("%08x %02x\n",offset,data);
1150
1151}
1152
1153READ8_MEMBER(hng64_state::hng64_comm_space_r)
1154{
1155   if((offset & 0xfc00) == 0) // B0 is fixed at 0-0x3ff
1156      return m_comm_rom[offset];
1157
1158   for(int i=0;i<5;i++)
1159   {
1160      if(offset >= m_mmub[i] && offset <= m_mmub[i+1]-1)
1161         return read_comm_data(m_mmua[i]|offset);
1162   }
1163
1164   return 0xff;
1165}
1166
1167WRITE8_MEMBER(hng64_state::hng64_comm_space_w)
1168{
1169   if((offset & 0xfc00) == 0) // B0 is fixed at 0-0x3ff
1170      return;// m_comm_rom[offset];
1171
1172   for(int i=0;i<5;i++)
1173   {
1174      if(offset >= m_mmub[i] && offset <= m_mmub[i+1]-1)
1175      {
1176         write_comm_data(m_mmua[i]|offset,data);
1177         return;
1178      }
1179   }
1180}
1181
1182READ8_MEMBER(hng64_state::hng64_comm_mmu_r)
1183{
1184   return m_mmu_regs[offset];
1185}
1186
1187#define MMUA (m_mmu_regs[(offset&~1)+0]>>6)|(m_mmu_regs[(offset&~1)+1]<<2)
1188#define MMUB (m_mmu_regs[(offset&~1)+0]&0x3f)
1189
1190WRITE8_MEMBER(hng64_state::hng64_comm_mmu_w)
1191{
1192   m_mmu_regs[offset] = data;
1193
1194   /* cheap: avoid to overwrite read only params*/
1195   if((offset & 6) == 6)
1196   {
1197      m_mmu_regs[6] = m_mmu_regs[6] & 0x3f;
1198      m_mmu_regs[7] = 0xf0;
1199
1200   }
1201
1202   {
1203      m_mmua[offset/2+1] = (m_mmu_regs[(offset&~1)+0]>>6)|(m_mmu_regs[(offset&~1)+1]<<2);
1204      m_mmua[offset/2+1]*= 0x400;
1205      m_mmub[offset/2+1] = (m_mmu_regs[(offset&~1)+0]&0x3f);
1206      m_mmub[offset/2+1]++;
1207      m_mmub[offset/2+1]*= 0x400;
1208      //printf("%d A %08x B %04x\n",offset/2,m_mmua[offset/2],m_mmub[offset/2]);
1209      //printf("A %04x B %02x\n",MMUA,MMUB);
1210   }
1211}
1212
1213static ADDRESS_MAP_START( hng_comm_map, AS_PROGRAM, 8, hng64_state )
1214   AM_RANGE(0x0000,0xffff) AM_READWRITE(hng64_comm_space_r, hng64_comm_space_w )
1215ADDRESS_MAP_END
1216
1217static ADDRESS_MAP_START( hng_comm_io_map, AS_IO, 8, hng64_state )
1218   ADDRESS_MAP_GLOBAL_MASK(0xff)
1219   /* Reserved for the KL5C80 internal hardware */
1220   AM_RANGE(0x00, 0x07) AM_READWRITE(hng64_comm_mmu_r,hng64_comm_mmu_w )
1221//  AM_RANGE(0x08,0x1f) AM_NOP              /* Reserved */
1222//  AM_RANGE(0x20,0x25) AM_READWRITE        /* Timer/Counter B */           /* hng64 writes here */
1223//  AM_RANGE(0x27,0x27) AM_NOP              /* Reserved */
1224//  AM_RANGE(0x28,0x2b) AM_READWRITE        /* Timer/Counter A */           /* hng64 writes here */
1225//  AM_RANGE(0x2c,0x2f) AM_READWRITE        /* Parallel port A */
1226//  AM_RANGE(0x30,0x33) AM_READWRITE        /* Parallel port B */
1227//  AM_RANGE(0x34,0x37) AM_READWRITE        /* Interrupt controller */      /* hng64 writes here */
1228//  AM_RANGE(0x38,0x39) AM_READWRITE        /* Serial port */               /* hng64 writes here */
1229//  AM_RANGE(0x3a,0x3b) AM_READWRITE        /* System control register */   /* hng64 writes here */
1230//  AM_RANGE(0x3c,0x3f) AM_NOP              /* Reserved */
1231
1232   /* General IO */
1233   AM_RANGE(0x50,0x57) AM_READWRITE(hng64_com_share_r, hng64_com_share_w)
1234//  AM_RANGE(0x72,0x72) AM_WRITE            /* dunno yet */
1235ADDRESS_MAP_END
1236
1237
1238static ADDRESS_MAP_START( hng_sound_map, AS_PROGRAM, 16, hng64_state )
1239   AM_RANGE(0x00000, 0x0ffff) AM_RAMBANK("bank2")
1240   AM_RANGE(0x10000, 0x1ffff) AM_RAM // tmp, roadedge
1241   AM_RANGE(0xf0000, 0xfffff) AM_RAMBANK("bank1")
1242ADDRESS_MAP_END
1243
1244static ADDRESS_MAP_START( hng_sound_io, AS_IO, 16, hng64_state )
1245   AM_RANGE(0xc002, 0xc003) AM_NOP // buriki one fills the log, wants 0xffff
1246ADDRESS_MAP_END
1247
1248984static INPUT_PORTS_START( hng64 )
1249985   PORT_START("VBLANK")
1250986   PORT_BIT( 0xffffffff, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen")
r244822r244823
16371373   hng64_reorder(memregion("scrtile")->base(), memregion("scrtile")->bytes());
16381374}
16391375
1640#define HACK_REGION
1641#ifdef HACK_REGION
1642void hng64_state::hng64_patch_bios_region(int region)
1643{
1644   UINT8 *rom = memregion("user1")->base();
16451376
1646   if ((rom[0x4000]==0xff) && (rom[0x4001] == 0xff))
1647   {
1648      // both?
1649      rom[0x4002] = region;
1650      rom[0x4003] = region;
1651
1652   }
1653}
1654#endif
1655
16561377DRIVER_INIT_MEMBER(hng64_state,hng64)
16571378{
1658   // region hacking, english error messages are more useful to us, but no english bios is dumped...
1659#ifdef HACK_REGION
1660// versions according to fatal fury test mode
1661//  hng64_patch_bios_region( 0); // 'Others Ver' (invalid?)
1662   hng64_patch_bios_region( 1); // Japan
1663//  hng64_patch_bios_region( 2); // USA
1664//  hng64_patch_bios_region( 3); // Korea
1665//  hng64_patch_bios_region( 4); // 'Others'
1666#endif
1667
16681379   /* 1 meg of virtual address space for the com cpu */
16691380   m_com_virtual_mem = auto_alloc_array(machine(), UINT8, 0x100000);
16701381   m_com_op_base     = auto_alloc_array(machine(), UINT8, 0x10000);
r244822r244823
17981509
17991510void hng64_state::machine_reset()
18001511{
1801   /* Sound CPU */
1802   UINT8 *RAM = (UINT8*)m_soundram;
1803   membank("bank1")->set_base(&RAM[0x1f0000]); // allows us to boot
1804   membank("bank2")->set_base(&RAM[0x1f0000]); // seems to be the right default for most games (initial area jumps to a DI here)
1805   m_audiocpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
1806   m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1807
1808//  m_comm->set_input_line(INPUT_LINE_RESET, PULSE_LINE);     // reset the CPU and let 'er rip
1809//  m_comm->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);     // hold on there pardner...
1810
18111512   // "Display List" init - ugly
18121513//  m_activeBuffer = 0;
18131514
r244822r244823
18151516   m_mcu_fake_time = 0;
18161517   m_mcu_en = 0;
18171518
1818   m_mmub[0] = 0;
1819   m_mmub[5] = 0; // rolls back to 0xffff
1519   reset_net();
1520   reset_sound();
18201521}
18211522
1523MACHINE_CONFIG_EXTERN(hng64_audio);
1524MACHINE_CONFIG_EXTERN(hng64_network);
18221525
1823static MACHINE_CONFIG_START( hng64, hng64_state )
1824
1526static MACHINE_CONFIG_START(hng64, hng64_state)
18251527   /* basic machine hardware */
1826   MCFG_CPU_ADD("maincpu", VR4300BE, MASTER_CLOCK)     // actually R4300
1528   MCFG_CPU_ADD("maincpu", VR4300BE, HNG64_MASTER_CLOCK)     // actually R4300
18271529   MCFG_MIPS3_ICACHE_SIZE(16384)
18281530   MCFG_MIPS3_DCACHE_SIZE(16384)
18291531   MCFG_CPU_PROGRAM_MAP(hng_map)
18301532   MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", hng64_state, hng64_irq, "screen", 0, 1)
18311533
1832   MCFG_CPU_ADD("audiocpu", V33, 8000000)              // v53, 16? mhz!
1833   MCFG_CPU_PROGRAM_MAP(hng_sound_map)
1834   MCFG_CPU_IO_MAP(hng_sound_io)
18351534
1836   MCFG_CPU_ADD("comm", Z80,MASTER_CLOCK/4)        /* KL5C80A12CFP - binary compatible with Z80. */
1837   MCFG_CPU_PROGRAM_MAP(hng_comm_map)
1838   MCFG_CPU_IO_MAP(hng_comm_io_map)
18391535
1536
18401537   MCFG_NVRAM_ADD_0FILL("nvram")
18411538
18421539   MCFG_DEVICE_ADD("rtc", MSM6242, XTAL_32_768kHz)
r244822r244823
18491546   MCFG_SCREEN_VBLANK_DRIVER(hng64_state, screen_eof_hng64)
18501547
18511548   MCFG_PALETTE_ADD("palette", 0x1000)
1549
1550   MCFG_FRAGMENT_ADD( hng64_audio )
1551   MCFG_FRAGMENT_ADD( hng64_network )
1552
18521553MACHINE_CONFIG_END
18531554
1555#define ROM_LOAD_HNG64_BIOS(bios,name,offset,length,hash) \
1556      ROMX_LOAD(name, offset, length, hash,  ROM_BIOS(bios+1)) /* Note '+1' */
18541557
1558// all BIOS roms are said to be from 'fighting' type PCB, it is unknown if the actual MIPS BIOS differs on the others, or only the MCU internal ROM
1559#define HNG64_BIOS \
1560   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */ \
1561   ROM_SYSTEM_BIOS( 0, "japan", "Japan" ) \
1562   ROM_LOAD_HNG64_BIOS( 0, "brom1.bin",         0x00000, 0x080000, CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) ) \
1563   ROM_SYSTEM_BIOS( 1, "us", "USA" ) \
1564   ROM_LOAD_HNG64_BIOS( 1, "bios_us.bin",        0x00000, 0x080000,  CRC(ab5948d6) SHA1(f8b940c1ae5ce2d3b2cd0c9bfaf6e5b063cec06e) ) \
1565   ROM_SYSTEM_BIOS( 2, "export", "Export" ) \
1566   ROM_LOAD_HNG64_BIOS( 2, "bios_export.bin",        0x00000, 0x080000, CRC(bbf07ec6) SHA1(5656aa077f6a6d43953f15b5123eea102a9d5313) ) \
1567   ROM_SYSTEM_BIOS( 3, "korea", "Korea" ) \
1568   ROM_LOAD_HNG64_BIOS( 3, "bios_korea.bin",        0x00000, 0x080000, CRC(ac953e2e) SHA1(f502188ef252b7c9d04934c4b525730a116de48b) ) \
1569   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS */ \
1570   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) ) \
1571   ROM_REGION( 0x0100000, "fpga", 0 ) /* FPGA data  */ \
1572   ROM_LOAD ( "rom1.bin",  0x000000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) ) \
1573
1574
18551575ROM_START( hng64 )
18561576   /* BIOS */
1857   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */
1858   ROM_LOAD ( "brom1.bin", 0x000000, 0x080000,  CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) )
1859   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS and unknown ROM */
1860   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) )
1861   ROM_LOAD ( "rom1.bin",  0x080000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
1577   HNG64_BIOS
18621578
18631579   /* To placate MAME */
1864   ROM_REGION32_LE( 0x2000000, "user3", ROMREGION_ERASEFF )
1580   ROM_REGION32_LE( 0x2000000, "gameprg", ROMREGION_ERASEFF )
18651581   ROM_REGION( 0x4000, "scrtile", ROMREGION_ERASEFF )
18661582   ROM_REGION( 0x4000, "sprtile", ROMREGION_ERASEFF )
18671583   ROM_REGION( 0x1000000, "textures", ROMREGION_ERASEFF )
r244822r244823
18711587
18721588
18731589ROM_START( roadedge )
1874   /* BIOS */
1875   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */
1876   ROM_LOAD ( "brom1.bin", 0x000000, 0x080000,  CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) )
1877   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS and unknown ROM */
1878   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) )
1879   ROM_LOAD ( "rom1.bin",  0x080000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
1880   /* END BIOS */
1590   HNG64_BIOS
18811591
1882   ROM_REGION32_LE( 0x2000000, "user3", 0 )
1592   ROM_REGION32_LE( 0x2000000, "gameprg", 0 )
18831593   ROM_LOAD32_WORD( "001pr01b.81", 0x0000000, 0x400000, CRC(effbac30) SHA1(c1bddf3e511a8950f65ac7e452f81dbc4b7fd977) )
18841594   ROM_LOAD32_WORD( "001pr02b.82", 0x0000002, 0x400000, CRC(b9aa4ad3) SHA1(9ab3c896dbdc45560b7127486e2db6ca3b15a057) )
18851595
r244822r244823
19301640
19311641
19321642ROM_START( sams64 )
1933   /* BIOS */
1934   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */
1935   ROM_LOAD ( "brom1.bin", 0x000000, 0x080000,  CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) )
1936   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS and unknown ROM */
1937   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) )
1938   ROM_LOAD ( "rom1.bin",  0x080000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
1939   /* END BIOS */
1643   HNG64_BIOS
19401644
1941   ROM_REGION32_LE( 0x2000000, "user3", 0 )
1645   ROM_REGION32_LE( 0x2000000, "gameprg", 0 )
19421646   ROM_LOAD32_WORD( "002-pro1a.81", 0x0000000, 0x400000, CRC(e5b907c5) SHA1(83637ffaa9031d41a5bed3397a519d1dfa8052cb) )
19431647   ROM_LOAD32_WORD( "002-pro2a.82", 0x0000002, 0x400000, CRC(803ed2eb) SHA1(666db47886a316e68b911311e5db3bc0f5b8a34d) )
19441648   ROM_LOAD32_WORD( "002-pro3a.83", 0x0800000, 0x400000, CRC(582156a7) SHA1(a7bbbd472a53072cbfaed5d41d4265123c9e3f3d) )
r244822r244823
19911695
19921696
19931697ROM_START( xrally )
1994   /* BIOS */
1995   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */
1996   ROM_LOAD ( "brom1.bin", 0x000000, 0x080000,  CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) )
1997   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS and unknown ROM */
1998   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) )
1999   ROM_LOAD ( "rom1.bin",  0x080000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
2000   /* END BIOS */
1698   HNG64_BIOS
20011699
2002   ROM_REGION32_LE( 0x2000000, "user3", 0 )
1700   ROM_REGION32_LE( 0x2000000, "gameprg", 0 )
20031701   ROM_LOAD32_WORD( "003-pr01a.81", 0x0000000, 0x400000, CRC(4e160388) SHA1(08fba66d0f0dab47f7db5bc7d411f4fc0e8219c8) )
20041702   ROM_LOAD32_WORD( "003-pr02a.82", 0x0000002, 0x400000, CRC(c4dd4f18) SHA1(4db0e6d5cabd9e4f82d5905556174b9eff8ad4d9) )
20051703
r244822r244823
20391737
20401738
20411739ROM_START( bbust2 )
2042   /* BIOS */
2043   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */
2044   ROM_LOAD ( "brom1.bin", 0x000000, 0x080000,  CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) )
2045   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS and unknown ROM */
2046   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) )
2047   ROM_LOAD ( "rom1.bin",  0x080000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
2048   /* END BIOS */
1740   HNG64_BIOS
20491741
2050   ROM_REGION32_LE( 0x2000000, "user3", 0 )
1742   ROM_REGION32_LE( 0x2000000, "gameprg", 0 )
20511743   ROM_LOAD32_WORD( "004-pr01a.81", 0x0000000, 0x400000, CRC(7b836ece) SHA1(7a4a08251f1dd66c368ac203f5a006266e77f73d) )
20521744   ROM_LOAD32_WORD( "004-pr02a.82", 0x0000002, 0x400000, CRC(8c55a988) SHA1(d9a61ac3d8550ce0ee6aab374c9f024912163180) )
20531745   ROM_LOAD32_WORD( "004-pr03a.83", 0x0800000, 0x400000, CRC(f25a82dd) SHA1(74c0a03021ef424e0b9c3c818be297d2967b3012) )
r244822r244823
20931785
20941786
20951787ROM_START( sams64_2 )
2096   /* BIOS */
2097   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */
2098   ROM_LOAD ( "brom1.bin", 0x000000, 0x080000,  CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) )
2099   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS and unknown ROM */
2100   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) )
2101   ROM_LOAD ( "rom1.bin",  0x080000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
2102   /* END BIOS */
1788   HNG64_BIOS
21031789
2104   ROM_REGION32_LE( 0x2000000, "user3", 0 )
1790   ROM_REGION32_LE( 0x2000000, "gameprg", 0 )
21051791   ROM_LOAD32_WORD( "005pr01a.81", 0x0000000, 0x400000, CRC(a69d7700) SHA1(a580783a109bc3e24248d70bcd67f62dd7d8a5dd) )
21061792   ROM_LOAD32_WORD( "005pr02a.82", 0x0000002, 0x400000, CRC(38b9e6b3) SHA1(d1dad8247d920cc66854a0096e1c7845842d2e1c) )
21071793   ROM_LOAD32_WORD( "005pr03a.83", 0x0800000, 0x400000, CRC(0bc738a8) SHA1(79893b0e1c4a31e02ab385c4382684245975ae8f) )
r244822r244823
21711857
21721858
21731859ROM_START( fatfurwa )
2174   /* BIOS */
2175   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */
2176   ROM_LOAD ( "brom1.bin", 0x000000, 0x080000,  CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) )
2177   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS and unknown ROM */
2178   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) )
2179   ROM_LOAD ( "rom1.bin",  0x080000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
2180   /* END BIOS */
1860   HNG64_BIOS
21811861
2182   ROM_REGION32_LE( 0x2000000, "user3", 0 )
1862   ROM_REGION32_LE( 0x2000000, "gameprg", 0 )
21831863   ROM_LOAD32_WORD( "006pr01a.81", 0x0000000, 0x400000, CRC(3830efa1) SHA1(9d8c941ccb6cbe8d138499cf9d335db4ac7a9ec0) )
21841864   ROM_LOAD32_WORD( "006pr02a.82", 0x0000002, 0x400000, CRC(8d5de84e) SHA1(e3ae014263f370c2836f62ab323f1560cb3a9cf0) )
21851865   ROM_LOAD32_WORD( "006pr03a.83", 0x0800000, 0x400000, CRC(c811b458) SHA1(7d94e0df501fb086b2e5cf08905d7a3adc2c6472) )
r244822r244823
22421922
22431923
22441924ROM_START( buriki )
2245   /* BIOS */
2246   ROM_REGION32_BE( 0x0100000, "user1", 0 ) /* 512k for R4300 BIOS code */
2247   ROM_LOAD ( "brom1.bin", 0x000000, 0x080000,  CRC(a30dd3de) SHA1(3e2fd0a56214e6f5dcb93687e409af13d065ea30) )
2248   ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS and unknown ROM */
2249   ROM_LOAD ( "from1.bin", 0x000000, 0x080000,  CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) )
2250   ROM_LOAD ( "rom1.bin",  0x080000, 0x01ff32,  CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
2251   /* END BIOS */
1925   HNG64_BIOS
22521926
2253   ROM_REGION32_LE( 0x2000000, "user3", 0 )
1927   ROM_REGION32_LE( 0x2000000, "gameprg", 0 )
22541928   ROM_LOAD32_WORD( "007pr01b.81", 0x0000000, 0x400000, CRC(a31202f5) SHA1(c657729b292d394ced021a0201a1c5608a7118ba) )
22551929   ROM_LOAD32_WORD( "007pr02b.82", 0x0000002, 0x400000, CRC(a563fed6) SHA1(9af9a021beb814e35df968abe5a99225a124b5eb) )
22561930   ROM_LOAD32_WORD( "007pr03a.83", 0x0800000, 0x400000, CRC(da5f6105) SHA1(5424cf5289cef66e301e968b4394e551918fe99b) )
trunk/src/mame/includes/hng64.h
r244822r244823
11#include "machine/msm6242.h"
22#include "cpu/mips/mips3.h"
3#include "cpu/nec/nec.h"
34
45enum
56{
r244822r244823
2930   hng64trans_t        drawformat;
3031};
3132
33#define HNG64_MASTER_CLOCK 50000000
3234
3335///////////////
3436// 3d Engine //
r244822r244823
101103      : driver_device(mconfig, type, tag),
102104      m_maincpu(*this, "maincpu"),
103105      m_audiocpu(*this, "audiocpu"),
104      m_comm(*this, "comm"),
106      m_comm(*this, "network"),
105107      m_rtc(*this, "rtc"),
106108      m_mainram(*this, "mainram"),
107109      m_cart(*this, "cart"),
r244822r244823
337339
338340   void drawShaded( struct polygon *p);
339341
340   void hng64_patch_bios_region(int region);
341
342342   void printPacket(const UINT16* packet, int hex);
343343   void matmul4(float *product, const float *a, const float *b);
344344   void vecmatmul4(float *product, const float *a, const float *b);
r244822r244823
352352   UINT8 *m_texturerom;
353353   UINT16* m_vertsrom;
354354   int m_vertsrom_size;
355
355   void reset_sound();
356   void reset_net();
356357};
357358
trunk/src/mame/machine/hng64_net.c
r0r244823
1/* HNG64 Communication / Network CPU */
2
3// this is driven by a KL5C80A12CFP which is basically a super-charged Z80
4// most of this MMU handling etc. should be moved to the core.
5
6// I believe this CPU is used for network only (the racing games) and not related to the I/O MCU
7
8/*
90x6010: tests RAM at [3]8000
10
11*/
12
13#include "includes/hng64.h"
14#include "cpu/z80/kl5c80a12.h"
15
16UINT8 hng64_state::read_comm_data(UINT32 offset)
17{
18   if((offset & 0x10000) == 0)
19      return m_comm_rom[offset & 0xffff];
20
21   if(offset & 0x10000)
22      return m_comm_ram[(offset & 0xffff)];
23
24   printf("%08x\n",offset);
25   return 0xff;
26}
27
28void hng64_state::write_comm_data(UINT32 offset,UINT8 data)
29{
30   if((offset & 0x10000) == 0)
31   {
32      //m_comm_rom[offset];
33      return;
34   }
35   if(offset & 0x10000)
36   {
37      m_comm_ram[offset & 0xffff] = data;
38      return;
39   }
40
41
42   printf("%08x %02x\n",offset,data);
43
44}
45
46READ8_MEMBER(hng64_state::hng64_comm_space_r)
47{
48   if((offset & 0xfc00) == 0) // B0 is fixed at 0-0x3ff
49      return m_comm_rom[offset];
50
51   for(int i=0;i<5;i++)
52   {
53      if(offset >= m_mmub[i] && offset <= m_mmub[i+1]-1)
54         return read_comm_data(m_mmua[i]|offset);
55   }
56
57   return 0xff;
58}
59
60WRITE8_MEMBER(hng64_state::hng64_comm_space_w)
61{
62   if((offset & 0xfc00) == 0) // B0 is fixed at 0-0x3ff
63      return;// m_comm_rom[offset];
64
65   for(int i=0;i<5;i++)
66   {
67      if(offset >= m_mmub[i] && offset <= m_mmub[i+1]-1)
68      {
69         write_comm_data(m_mmua[i]|offset,data);
70         return;
71      }
72   }
73}
74
75READ8_MEMBER(hng64_state::hng64_comm_mmu_r)
76{
77   return m_mmu_regs[offset];
78}
79
80#define MMUA (m_mmu_regs[(offset&~1)+0]>>6)|(m_mmu_regs[(offset&~1)+1]<<2)
81#define MMUB (m_mmu_regs[(offset&~1)+0]&0x3f)
82
83WRITE8_MEMBER(hng64_state::hng64_comm_mmu_w)
84{
85   m_mmu_regs[offset] = data;
86
87   /* cheap: avoid to overwrite read only params*/
88   if((offset & 6) == 6)
89   {
90      m_mmu_regs[6] = m_mmu_regs[6] & 0x3f;
91      m_mmu_regs[7] = 0xf0;
92
93   }
94
95   {
96      m_mmua[offset/2+1] = (m_mmu_regs[(offset&~1)+0]>>6)|(m_mmu_regs[(offset&~1)+1]<<2);
97      m_mmua[offset/2+1]*= 0x400;
98      m_mmub[offset/2+1] = (m_mmu_regs[(offset&~1)+0]&0x3f);
99      m_mmub[offset/2+1]++;
100      m_mmub[offset/2+1]*= 0x400;
101      //printf("%d A %08x B %04x\n",offset/2,m_mmua[offset/2],m_mmub[offset/2]);
102      //printf("A %04x B %02x\n",MMUA,MMUB);
103   }
104}
105
106static ADDRESS_MAP_START( hng_comm_map, AS_PROGRAM, 8, hng64_state )
107   AM_RANGE(0x0000,0xffff) AM_READWRITE(hng64_comm_space_r, hng64_comm_space_w )
108ADDRESS_MAP_END
109
110static ADDRESS_MAP_START( hng_comm_io_map, AS_IO, 8, hng64_state )
111   ADDRESS_MAP_GLOBAL_MASK(0xff)
112   /* Reserved for the KL5C80 internal hardware */
113   AM_RANGE(0x00, 0x07) AM_READWRITE(hng64_comm_mmu_r,hng64_comm_mmu_w )
114//  AM_RANGE(0x08,0x1f) AM_NOP              /* Reserved */
115//  AM_RANGE(0x20,0x25) AM_READWRITE        /* Timer/Counter B */           /* hng64 writes here */
116//  AM_RANGE(0x27,0x27) AM_NOP              /* Reserved */
117//  AM_RANGE(0x28,0x2b) AM_READWRITE        /* Timer/Counter A */           /* hng64 writes here */
118//  AM_RANGE(0x2c,0x2f) AM_READWRITE        /* Parallel port A */
119//  AM_RANGE(0x30,0x33) AM_READWRITE        /* Parallel port B */
120//  AM_RANGE(0x34,0x37) AM_READWRITE        /* Interrupt controller */      /* hng64 writes here */
121//  AM_RANGE(0x38,0x39) AM_READWRITE        /* Serial port */               /* hng64 writes here */
122//  AM_RANGE(0x3a,0x3b) AM_READWRITE        /* System control register */   /* hng64 writes here */
123//  AM_RANGE(0x3c,0x3f) AM_NOP              /* Reserved */
124
125   /* General IO */
126   AM_RANGE(0x50,0x57) AM_READWRITE(hng64_com_share_r, hng64_com_share_w)
127//  AM_RANGE(0x72,0x72) AM_WRITE            /* dunno yet */
128ADDRESS_MAP_END
129
130
131void hng64_state::reset_net()
132{
133//  m_comm->set_input_line(INPUT_LINE_RESET, PULSE_LINE);     // reset the CPU and let 'er rip
134//  m_comm->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);     // hold on there pardner...
135
136   m_mmub[0] = 0;
137   m_mmub[5] = 0; // rolls back to 0xffff
138}
139
140MACHINE_CONFIG_FRAGMENT( hng64_network )
141   MCFG_CPU_ADD("network", KL5C80A12, HNG64_MASTER_CLOCK / 4)        /* KL5C80A12CFP - binary compatible with Z80. */
142   MCFG_CPU_PROGRAM_MAP(hng_comm_map)
143   MCFG_CPU_IO_MAP(hng_comm_io_map)
144MACHINE_CONFIG_END
No newline at end of file
trunk/src/mame/mame.mak
r244822r244823
18281828$(MAMEOBJ)/snk.a: \
18291829   $(DRIVERS)/bbusters.o $(VIDEO)/bbusters.o \
18301830   $(DRIVERS)/dmndrby.o \
1831   $(DRIVERS)/hng64.o $(VIDEO)/hng64.o $(VIDEO)/hng64_3d.o $(VIDEO)/hng64_sprite.o \
1831   $(DRIVERS)/hng64.o $(VIDEO)/hng64.o $(AUDIO)/hng64.o $(MACHINE)/hng64_net.o $(VIDEO)/hng64_3d.o $(VIDEO)/hng64_sprite.o \
18321832   $(DRIVERS)/lasso.o $(VIDEO)/lasso.o \
18331833   $(DRIVERS)/mainsnk.o $(VIDEO)/mainsnk.o \
18341834   $(DRIVERS)/munchmo.o $(VIDEO)/munchmo.o \

https://github.com/mamedev/mame/commit/04e15f745fd09a7ccc79265580c2f887211d6863

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