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r36309 Saturday 7th March, 2015 at 19:59:59 UTC by hap
moved i/o handling to the c file
[src/emu/cpu/hmcs40]hmcs40.c hmcs40op.inc

trunk/src/emu/cpu/hmcs40/hmcs40.c
r244820r244821
281281
282282
283283//-------------------------------------------------
284//  i/o handling
285//-------------------------------------------------
286
287UINT8 hmcs40_cpu_device::read_r(int index)
288{
289   index &= 7;
290   UINT8 inp = 0xf;
291   
292   switch (index)
293   {
294      case 0: inp = m_read_r0(index, 0xff); break;
295      case 1: inp = m_read_r1(index, 0xff); break;
296      case 2: inp = m_read_r2(index, 0xff); break;
297      case 3: inp = m_read_r3(index, 0xff); break;
298      case 4: inp = m_read_r4(index, 0xff); break;
299      case 5: inp = m_read_r5(index, 0xff); break;
300      case 6: inp = m_read_r6(index, 0xff); break;
301      case 7: inp = m_read_r7(index, 0xff); break;
302   }
303   
304   if (m_is_cmos)
305      return (inp & m_r[index]) & 0xf;
306   else
307      return (inp | m_r[index]) & 0xf;
308}
309
310void hmcs40_cpu_device::write_r(int index, UINT8 data)
311{
312   index &= 7;
313   data &= 0xf;
314   m_r[index] = data;
315   
316   switch (index)
317   {
318      case 0: m_write_r0(index, m_r[index], 0xff); break;
319      case 1: m_write_r1(index, m_r[index], 0xff); break;
320      case 2: m_write_r2(index, m_r[index], 0xff); break;
321      case 3: m_write_r3(index, m_r[index], 0xff); break;
322      case 4: m_write_r4(index, m_r[index], 0xff); break;
323      case 5: m_write_r5(index, m_r[index], 0xff); break;
324      case 6: m_write_r6(index, m_r[index], 0xff); break;
325      case 7: m_write_r7(index, m_r[index], 0xff); break;
326   }
327}
328
329int hmcs40_cpu_device::read_d(int index)
330{
331   index &= 15;
332   
333   if (m_is_cmos)
334      return (m_read_d(index, 0xffff) & m_d) >> index & 1;
335   else
336      return (m_read_d(index, 0xffff) | m_d) >> index & 1;
337}
338
339void hmcs40_cpu_device::write_d(int index, int state)
340{
341   index &= 15;
342   
343   m_d = (m_d & ~(1 << index)) | (((state) ? 1 : 0) << index);
344   m_write_d(index, m_d, 0xffff);
345}
346
347// HMCS43:
348// R0 is input-only, R1 is i/o, R2,R3 are output-only, no R4-R7
349// D0-D3 are i/o, D4-D15 are output-only
350
351UINT8 hmcs43_cpu_device::read_r(int index)
352{
353   index &= 7;
354   
355   if (index >= 2)
356      logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc << 1);
357
358   return hmcs40_cpu_device::read_r(index);
359}
360
361void hmcs43_cpu_device::write_r(int index, UINT8 data)
362{
363   index &= 7;
364
365   if (index != 0 && index < 4)
366      hmcs40_cpu_device::write_r(index, data);
367   else
368      logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
369}
370
371int hmcs43_cpu_device::read_d(int index)
372{
373   index &= 15;
374   
375   if (index >= 4)
376   {
377      logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc << 1);
378      return m_d >> index & 1;
379   }
380   else
381      return hmcs40_cpu_device::read_d(index);
382}
383
384// HMCS44:
385// R0-R3 are i/o, R4,R5 are extra registers, no R6,R7
386// D0-D15 are i/o
387
388UINT8 hmcs44_cpu_device::read_r(int index)
389{
390   index &= 7;
391   
392   if (index >= 6)
393      logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc << 1);
394   
395   return hmcs40_cpu_device::read_r(index);
396}
397
398void hmcs44_cpu_device::write_r(int index, UINT8 data)
399{
400   index &= 7;
401
402   if (index < 6)
403      hmcs40_cpu_device::write_r(index, data);
404   else
405      logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
406}
407
408// HMCS45:
409// R0-R5 are i/o, R6 is output-only, no R7
410// D0-D15 are i/o
411
412UINT8 hmcs45_cpu_device::read_r(int index)
413{
414   index &= 7;
415   
416   if (index >= 6)
417      logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc << 1);
418   
419   return hmcs40_cpu_device::read_r(index);
420}
421
422void hmcs45_cpu_device::write_r(int index, UINT8 data)
423{
424   index &= 7;
425
426   if (index != 7)
427      hmcs40_cpu_device::write_r(index, data);
428   else
429      logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
430}
431
432
433
434//-------------------------------------------------
284435//  execute
285436//-------------------------------------------------
286437
trunk/src/emu/cpu/hmcs40/hmcs40op.inc
r244820r244821
2929}
3030
3131
32// i/o
3332
34UINT8 hmcs40_cpu_device::read_r(int index)
35{
36   index &= 7;
37   UINT8 inp = 0xf;
38   
39   switch (index)
40   {
41      case 0: inp = m_read_r0(index, 0xff); break;
42      case 1: inp = m_read_r1(index, 0xff); break;
43      case 2: inp = m_read_r2(index, 0xff); break;
44      case 3: inp = m_read_r3(index, 0xff); break;
45      case 4: inp = m_read_r4(index, 0xff); break;
46      case 5: inp = m_read_r5(index, 0xff); break;
47      case 6: inp = m_read_r6(index, 0xff); break;
48      case 7: inp = m_read_r7(index, 0xff); break;
49   }
50   
51   if (m_is_cmos)
52      return (inp & m_r[index]) & 0xf;
53   else
54      return (inp | m_r[index]) & 0xf;
55}
56
57void hmcs40_cpu_device::write_r(int index, UINT8 data)
58{
59   index &= 7;
60   data &= 0xf;
61   m_r[index] = data;
62   
63   switch (index)
64   {
65      case 0: m_write_r0(index, m_r[index], 0xff); break;
66      case 1: m_write_r1(index, m_r[index], 0xff); break;
67      case 2: m_write_r2(index, m_r[index], 0xff); break;
68      case 3: m_write_r3(index, m_r[index], 0xff); break;
69      case 4: m_write_r4(index, m_r[index], 0xff); break;
70      case 5: m_write_r5(index, m_r[index], 0xff); break;
71      case 6: m_write_r6(index, m_r[index], 0xff); break;
72      case 7: m_write_r7(index, m_r[index], 0xff); break;
73   }
74}
75
76int hmcs40_cpu_device::read_d(int index)
77{
78   index &= 15;
79   
80   if (m_is_cmos)
81      return (m_read_d(index, 0xffff) & m_d) >> index & 1;
82   else
83      return (m_read_d(index, 0xffff) | m_d) >> index & 1;
84}
85
86void hmcs40_cpu_device::write_d(int index, int state)
87{
88   index &= 15;
89   
90   m_d = (m_d & ~(1 << index)) | (((state) ? 1 : 0) << index);
91   m_write_d(index, m_d, 0xffff);
92}
93
94// HMCS43:
95// R0 is input-only, R1 is i/o, R2,R3 are output-only, no R4-R7
96// D0-D3 are i/o, D4-D15 are output-only
97
98UINT8 hmcs43_cpu_device::read_r(int index)
99{
100   index &= 7;
101   
102   if (index >= 2)
103      logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc << 1);
104
105   return hmcs40_cpu_device::read_r(index);
106}
107
108void hmcs43_cpu_device::write_r(int index, UINT8 data)
109{
110   index &= 7;
111
112   if (index != 0 && index < 4)
113      hmcs40_cpu_device::write_r(index, data);
114   else
115      logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
116}
117
118int hmcs43_cpu_device::read_d(int index)
119{
120   index &= 15;
121   
122   if (index >= 4)
123   {
124      logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc << 1);
125      return m_d >> index & 1;
126   }
127   else
128      return hmcs40_cpu_device::read_d(index);
129}
130
131// HMCS44:
132// R0-R3 are i/o, R4,R5 are extra registers, no R6,R7
133// D0-D15 are i/o
134
135UINT8 hmcs44_cpu_device::read_r(int index)
136{
137   index &= 7;
138   
139   if (index >= 6)
140      logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc << 1);
141   
142   return hmcs40_cpu_device::read_r(index);
143}
144
145void hmcs44_cpu_device::write_r(int index, UINT8 data)
146{
147   index &= 7;
148
149   if (index < 6)
150      hmcs40_cpu_device::write_r(index, data);
151   else
152      logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
153}
154
155// HMCS45:
156// R0-R5 are i/o, R6 is output-only, no R7
157// D0-D15 are i/o
158
159UINT8 hmcs45_cpu_device::read_r(int index)
160{
161   index &= 7;
162   
163   if (index >= 6)
164      logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc << 1);
165   
166   return hmcs40_cpu_device::read_r(index);
167}
168
169void hmcs45_cpu_device::write_r(int index, UINT8 data)
170{
171   index &= 7;
172
173   if (index != 7)
174      hmcs40_cpu_device::write_r(index, data);
175   else
176      logerror("%s ineffective write to port R%d = $%X at $%04X\n", tag(), index, data & 0xf, m_prev_pc << 1);
177}
178
179
180
181
182
18333// instruction set
18434
18535void hmcs40_cpu_device::op_illegal()

https://github.com/mamedev/mame/commit/a36a9bef31fa70ead2f7f4ac6e67b265d98b7704

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