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r36248 Wednesday 4th March, 2015 at 19:58:17 UTC by hap
added Hitachi HMCS40 series MCU core skeleton
[src/emu/cpu]cpu.mak
[src/emu/cpu/hmcs40]hmcs40.c* hmcs40.h* hmcs40d.c* hmcs40op.inc*
[src/mame]mame.mak
[src/mess]mess.mak
[src/tools]unidasm.c

trunk/src/emu/cpu/cpu.mak
r244759r244760
741741   @echo Generating H8S/2600 source file...
742742   $(PYTHON) $(CPUSRC)/h8/h8make.py $(CPUSRC)/h8/h8.lst s26 $@
743743
744
745
744746#-------------------------------------------------
745747# Hitachi HCD62121
746748#@src/emu/cpu/hcd62121/hcd62121.h,CPUS += HCD62121
r244759r244760
757759                     $(CPUSRC)/hcd62121/hcd62121_ops.h
758760
759761
762
760763#-------------------------------------------------
764# Hitachi HMCS40 series
765#@src/emu/cpu/hmcs40/hmcs40.h,CPUS += HMCS40
766#-------------------------------------------------
767
768ifneq ($(filter HMCS40,$(CPUS)),)
769OBJDIRS += $(CPUOBJ)/hmcs40
770CPUOBJS += $(CPUOBJ)/hmcs40/hmcs40.o
771DASMOBJS += $(CPUOBJ)/hmcs40/hmcs40d.o
772endif
773
774$(CPUOBJ)/hmcs40/hmcs40.o:      $(CPUSRC)/hmcs40/hmcs40.h \
775                        $(CPUSRC)/hmcs40/hmcs40.c \
776                        $(CPUSRC)/hmcs40/hmcs40op.inc
777
778$(CPUOBJ)/hmcs40/hmcs40d.o:     $(CPUSRC)/hmcs40/hmcs40.h \
779                        $(CPUSRC)/hmcs40/hmcs40d.c
780
781
782
783#-------------------------------------------------
761784# Hitachi SH1/SH2
762785#@src/emu/cpu/sh2/sh2.h,CPUS += SH2
763786#-------------------------------------------------
r244759r244760
779802         $(CPUSRC)/sh2/sh2.h \
780803         $(CPUSRC)/sh2/sh2comn.h
781804
805
806
782807#-------------------------------------------------
783808# Hitachi SH4
784809#@src/emu/cpu/sh4/sh4.h,CPUS += SH4
r244759r244760
824849         $(CPUSRC)/sh4/sh4comn.h \
825850         $(CPUSRC)/sh4/sh3comn.h
826851
852
853
827854#-------------------------------------------------
828855# Hudsonsoft 6280
829856#@src/emu/cpu/h6280/h6280.h,CPUS += H6280
trunk/src/emu/cpu/hmcs40/hmcs40.c
r0r244760
1// license:BSD-3-Clause
2// copyright-holders:hap
3/*
4
5  Hitachi HMCS40 MCU family cores
6
7*/
8
9#include "hmcs40.h"
10#include "debugger.h"
11
12#include "hmcs40op.inc"
13
14// MCU types
15
16// HMCS42/C/CL
17//const device_type HD38702 = &device_creator<hd38702_device>; // PMOS, 28 pins, 22 I/O lines, (512+32)x10 ROM, 32x4 RAM
18//const device_type HD44700 = &device_creator<hd44700_device>; // CMOS version
19//const device_type HD44708 = &device_creator<hd44708_device>; // CMOS version, low-power
20
21// HMCS43/C/CL
22const device_type HD38750 = &device_creator<hd38750_device>; // PMOS, 42 pins, 32 I/O lines, (1024+64)x10 ROM, 80x4 RAM
23//const device_type HD38755 = &device_creator<hd38755_device>; // ceramic filter oscillator type
24//const device_type HD44750 = &device_creator<hd44750_device>; // CMOS version
25//const device_type HD44758 = &device_creator<hd44758_device>; // CMOS version, low-power
26
27// HMCS44A/C/CL
28const device_type HD38800 = &device_creator<hd38800_device>; // PMOS, 42 pins, 32 I/O lines, (2048+128)x10 ROM, 160x4 RAM
29//const device_type HD38805 = &device_creator<hd38805_device>; // ceramic filter oscillator type
30//const device_type HD44801 = &device_creator<hd44801_device>; // CMOS version
31//const device_type HD44808 = &device_creator<hd44808_device>; // CMOS version, low-power
32
33// HMCS45A/C/CL
34const device_type HD38820 = &device_creator<hd38820_device>; // PMOS, 54 pins(QFP) or 64 pins(DIP), 44 I/O lines, (2048+128)x10 ROM, 160x4 RAM
35//const device_type HD38825 = &device_creator<hd38825_device>; // ceramic filter oscillator type
36//const device_type HD44820 = &device_creator<hd44820_device>; // CMOS version
37//const device_type HD44828 = &device_creator<hd44828_device>; // CMOS version, low-power
38
39// HMCS46C/CL (no PMOS version exists)
40//const device_type HD44840 = &device_creator<hd44840_device>; // CMOS, 42 pins, 32 I/O lines, 4096x10 ROM, 256x4 RAM
41//const device_type HD44848 = &device_creator<hd44848_device>; // CMOS, low-power
42
43// HMCS47A/C/CL
44//const device_type HD38870 = &device_creator<hd38870_device>; // PMOS, 54 pins(QFP) or 64 pins(DIP), 44 I/O lines, 4096x10 ROM, 256x4 RAM
45//const device_type HD44860 = &device_creator<hd44860_device>; // CMOS version
46//const device_type HD44868 = &device_creator<hd44868_device>; // CMOS version, low-power
47
48
49// internal memory maps
50static ADDRESS_MAP_START(program_1k, AS_PROGRAM, 16, hmcs40_cpu_device)
51   AM_RANGE(0x0000, 0x07ff) AM_ROM
52   AM_RANGE(0x0800, 0x007f) AM_ROM
53ADDRESS_MAP_END
54
55static ADDRESS_MAP_START(program_2k, AS_PROGRAM, 16, hmcs40_cpu_device)
56   AM_RANGE(0x0000, 0x0fff) AM_ROM
57   AM_RANGE(0x1000, 0x10ff) AM_ROM
58ADDRESS_MAP_END
59
60
61static ADDRESS_MAP_START(data_80x4, AS_DATA, 8, hmcs40_cpu_device)
62   AM_RANGE(0x00, 0x3f) AM_RAM
63   AM_RANGE(0x40, 0x4f) AM_RAM AM_MIRROR(0x30)
64ADDRESS_MAP_END
65
66static ADDRESS_MAP_START(data_160x4, AS_DATA, 8, hmcs40_cpu_device)
67   AM_RANGE(0x00, 0x7f) AM_RAM
68   AM_RANGE(0x80, 0x9f) AM_RAM AM_MIRROR(0x70)
69ADDRESS_MAP_END
70
71
72// device definitions
73hd38750_device::hd38750_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
74   : hmcs40_cpu_device(mconfig, HD38750, "HD38750", tag, owner, clock, 3, 12, ADDRESS_MAP_NAME(program_1k), 7, ADDRESS_MAP_NAME(data_80x4), "hd38750", __FILE__)
75{ }
76
77hd38800_device::hd38800_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
78   : hmcs40_cpu_device(mconfig, HD38800, "HD38800", tag, owner, clock, 4, 13, ADDRESS_MAP_NAME(program_2k), 8, ADDRESS_MAP_NAME(data_160x4), "hd38800", __FILE__)
79{ }
80
81hd38820_device::hd38820_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
82   : hmcs40_cpu_device(mconfig, HD38820, "HD38820", tag, owner, clock, 4, 13, ADDRESS_MAP_NAME(program_2k), 8, ADDRESS_MAP_NAME(data_160x4), "hd38820", __FILE__)
83{ }
84
85
86// disasm
87void hmcs40_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
88{
89   switch (entry.index())
90   {
91      case STATE_GENFLAGS:
92         string.printf("%c%c",
93            m_c ? 'C':'c',
94            m_s ? 'S':'s'
95         );
96         break;
97
98      default: break;
99   }
100}
101
102offs_t hmcs40_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
103{
104   extern CPU_DISASSEMBLE(hmcs40);
105   return CPU_DISASSEMBLE_NAME(hmcs40)(this, buffer, pc, oprom, opram, options);
106}
107
108
109
110//-------------------------------------------------
111//  device_start - device-specific startup
112//-------------------------------------------------
113
114enum
115{
116   HMCS40_PC=1, HMCS40_A, HMCS40_B,
117   HMCS40_X, HMCS40_SPX, HMCS40_Y, HMCS40_SPY
118};
119
120void hmcs40_cpu_device::device_start()
121{
122   m_program = &space(AS_PROGRAM);
123   m_data = &space(AS_DATA);
124   m_prgmask = (1 << m_prgwidth) - 1;
125   m_datamask = (1 << m_datawidth) - 1;
126
127   m_read_d.resolve_safe(0);
128   m_write_d.resolve_safe();
129
130   // zerofill
131   memset(m_stack, 0, sizeof(m_stack));
132   m_op = 0;
133   m_pc = 0;
134   m_a = 0;
135   m_b = 0;
136   m_x = 0;
137   m_spx = 0;
138   m_y = 0;
139   m_spy = 0;
140   m_s = 0;
141   m_c = 0;
142
143   // register for savestates
144   save_item(NAME(m_stack));
145   save_item(NAME(m_op));
146   save_item(NAME(m_pc));
147   save_item(NAME(m_a));
148   save_item(NAME(m_b));
149   save_item(NAME(m_x));
150   save_item(NAME(m_spx));
151   save_item(NAME(m_y));
152   save_item(NAME(m_spy));
153   save_item(NAME(m_s));
154   save_item(NAME(m_c));
155
156   // register state for debugger
157   state_add(HMCS40_PC,  "PC",  m_pc).formatstr("%04X");
158   state_add(HMCS40_A,   "A",   m_a).formatstr("%01X");
159   state_add(HMCS40_B,   "B",   m_b).formatstr("%01X");
160   state_add(HMCS40_X,   "X",   m_x).formatstr("%01X");
161   state_add(HMCS40_SPX, "SPX", m_spx).formatstr("%01X");
162   state_add(HMCS40_Y,   "Y",   m_y).formatstr("%01X");
163   state_add(HMCS40_SPY, "SPY", m_spy).formatstr("%01X");
164
165   state_add(STATE_GENPC, "curpc", m_pc).formatstr("%04X").noshow();
166   state_add(STATE_GENFLAGS, "GENFLAGS", m_s).formatstr("%2s").noshow();
167
168   m_icountptr = &m_icount;
169}
170
171
172
173//-------------------------------------------------
174//  device_reset - device-specific reset
175//-------------------------------------------------
176
177void hmcs40_cpu_device::device_reset()
178{
179   m_pc = 0;
180   m_op = 0;
181}
182
183
184
185//-------------------------------------------------
186//  execute
187//-------------------------------------------------
188
189void hmcs40_cpu_device::execute_run()
190{
191   while (m_icount > 0)
192   {
193      m_icount--;
194     
195      debugger_instruction_hook(this, m_pc);
196      m_op = m_program->read_byte(m_pc);
197      m_pc = (m_pc + 1) & m_prgmask;
198   }
199}
trunk/src/emu/cpu/hmcs40/hmcs40.h
r0r244760
1// license:BSD-3-Clause
2// copyright-holders:hap
3/*
4
5  Hitachi HMCS40 MCU family cores
6
7*/
8
9#ifndef _HMCS40_H_
10#define _HMCS40_H_
11
12#include "emu.h"
13
14
15// I/O ports setup
16#define MCFG_HMCS40_READ_A_CB(_devcb) \
17   hmcs40_cpu_device::set_read_d_callback(*device, DEVCB_##_devcb);
18#define MCFG_HMCS40_WRITE_D_CB(_devcb) \
19   hmcs40_cpu_device::set_write_d_callback(*device, DEVCB_##_devcb);
20
21
22
23class hmcs40_cpu_device : public cpu_device
24{
25public:
26   // construction/destruction
27   hmcs40_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, int stack_levels, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source)
28      : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
29      , m_program_config("program", ENDIANNESS_BIG, 16, prgwidth, 0, program)
30      , m_data_config("data", ENDIANNESS_BIG, 8, datawidth, 0, data)
31      , m_prgwidth(prgwidth-1)
32      , m_datawidth(datawidth)
33      , m_stack_levels(stack_levels)
34      , m_read_d(*this)
35      , m_write_d(*this)
36   { }
37
38   // static configuration helpers
39   template<class _Object> static devcb_base &set_read_d_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_read_d.set_callback(object); }
40   template<class _Object> static devcb_base &set_write_d_callback(device_t &device, _Object object) { return downcast<hmcs40_cpu_device &>(device).m_write_d.set_callback(object); }
41
42protected:
43   // device-level overrides
44   virtual void device_start();
45   virtual void device_reset();
46
47   // device_execute_interface overrides
48   virtual UINT32 execute_min_cycles() const { return 1; }
49   virtual UINT32 execute_max_cycles() const { return 2; }
50   virtual UINT32 execute_input_lines() const { return 1; }
51   virtual void execute_run();
52
53   // device_memory_interface overrides
54   virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return(spacenum == AS_PROGRAM) ? &m_program_config :((spacenum == AS_DATA) ? &m_data_config : NULL); }
55
56   // device_disasm_interface overrides
57   virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
58   virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
59   virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
60   void state_string_export(const device_state_entry &entry, astring &string);
61
62   address_space_config m_program_config;
63   address_space_config m_data_config;
64   address_space *m_program;
65   address_space *m_data;
66
67   int m_prgwidth;
68   int m_datawidth;
69   int m_prgmask;
70   int m_datamask;
71   int m_stack_levels; // number of callstack levels
72   UINT16 m_stack[4];  // max 4
73   UINT16 m_op;
74   int m_icount;
75   
76   UINT16 m_pc;        // Program Counter
77   UINT8 m_a;          // 4-bit Accumulator
78   UINT8 m_b;          // 4-bit B register
79   UINT8 m_x;          // 1/3/4-bit X register
80   UINT8 m_spx;        // 1/3/4-bit SPX register
81   UINT8 m_y;          // 4-bit Y register
82   UINT8 m_spy;        // 4-bit SPY register
83   UINT8 m_s;          // Status F/F
84   UINT8 m_c;          // Carry F/F
85
86   // i/o handlers
87   devcb_read16 m_read_d;
88   devcb_write16 m_write_d;
89
90   // opcode handlers
91   void op_lab();
92   void op_lba();
93   void op_lay();
94   void op_laspx();
95   void op_laspy();
96   void op_xamr();
97
98   void op_lxa();
99   void op_lya();
100   void op_lxi();
101   void op_lyi();
102   void op_iy();
103   void op_dy();
104   void op_ayy();
105   void op_syy();
106   void op_xspx();
107   void op_sxpy();
108   void op_xspxy();
109
110   void op_lam();
111   void op_lbm();
112   void op_xma();
113   void op_xmb();
114   void op_lmaiy();
115   void op_lmady();
116
117   void op_lmiiy();
118   void op_lai();
119   void op_lbi();
120
121   void op_ai();
122   void op_ib();
123   void op_db();
124   void op_amc();
125   void op_smc();
126   void op_am();
127   void op_daa();
128   void op_das();
129   void op_nega();
130   void op_comb();
131   void op_sec();
132   void op_rec();
133   void op_tc();
134   void op_rotl();
135   void op_rotr();
136   void op_or();
137
138   void op_mnei();
139   void op_ynei();
140   void op_anem();
141   void op_bnem();
142   void op_alei();
143   void op_alem();
144   void op_blem();
145
146   void op_sem();
147   void op_rem();
148   void op_tm();
149
150   void op_br();
151   void op_cal();
152   void op_lpu();
153   void op_tbr();
154   void op_rtn();
155
156   void op_seie();
157   void op_seif0();
158   void op_seif1();
159   void op_setf();
160   void op_secf();
161   void op_reie();
162   void op_reif0();
163   void op_reif1();
164   void op_retf();
165   void op_recf();
166   void op_ti0();
167   void op_ti1();
168   void op_tif0();
169   void op_tif1();
170   void op_ttf();
171   void op_lti();
172   void op_lta();
173   void op_lat();
174   void op_rtni();
175
176   void op_sed();
177   void op_red();
178   void op_td();
179   void op_sedd();
180   void op_redd();
181   void op_lar();
182   void op_lbr();
183   void op_lra();
184   void op_lrb();
185   void op_p();
186
187   void op_nop();
188   void op_illegal();
189};
190
191
192class hd38750_device : public hmcs40_cpu_device
193{
194public:
195   hd38750_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
196};
197
198
199class hd38800_device : public hmcs40_cpu_device
200{
201public:
202   hd38800_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
203};
204
205
206class hd38820_device : public hmcs40_cpu_device
207{
208public:
209   hd38820_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
210};
211
212
213
214extern const device_type HD38750;
215extern const device_type HD38800;
216extern const device_type HD38820;
217
218
219#endif /* _HMCS40_H_ */
trunk/src/emu/cpu/hmcs40/hmcs40d.c
r0r244760
1// license:BSD-3-Clause
2// copyright-holders:hap
3/*
4
5  Hitachi HMCS40 MCU family disassembler
6
7*/
8
9#include "emu.h"
10#include "debugger.h"
11#include "hmcs40.h"
12
13
14CPU_DISASSEMBLE(hmcs40)
15{
16   int pos = 2;//0;
17//   UINT16 op = ((oprom[pos] << 8) | oprom[pos + 1]) & 0x3ff;
18//   pos += 2;
19//   UINT8 instr = hmcs40_mnemonic[op];
20
21   char *dst = buffer;
22   dst += sprintf(dst, "ABC");
23
24   return pos | 0 | DASMFLAG_SUPPORTED;
25}
trunk/src/emu/cpu/hmcs40/hmcs40op.inc
r0r244760
1// HMCS40 opcode handlers
2
3// internal helpers
4
5void hmcs40_cpu_device::op_illegal()
6{
7   logerror("%s unknown opcode $%03X at $%04X\n", tag(), m_op, m_pc);
8}
9
10
11
12// instruction set
13
14// Register-to-Register Instruction
15
16void hmcs40_cpu_device::op_lab()
17{
18   // LAB: Load A from B
19   op_illegal();
20}
21
22void hmcs40_cpu_device::op_lba()
23{
24   // LBA: Load B from A
25   op_illegal();
26}
27
28void hmcs40_cpu_device::op_lay()
29{
30   // LAY: Load A from Y
31   op_illegal();
32}
33
34void hmcs40_cpu_device::op_laspx()
35{
36   // LASPX: Load A from SPX
37   op_illegal();
38}
39
40void hmcs40_cpu_device::op_laspy()
41{
42   // LASPY: Load A from SPY
43   op_illegal();
44}
45
46void hmcs40_cpu_device::op_xamr()
47{
48   // XAMR m: Exchange A and MR(m)
49   op_illegal();
50}
51
52
53// RAM Address Instruction
54
55void hmcs40_cpu_device::op_lxa()
56{
57   // LXA: Load X from A
58   op_illegal();
59}
60
61void hmcs40_cpu_device::op_lya()
62{
63   // LYA: Load Y from A
64   op_illegal();
65}
66
67void hmcs40_cpu_device::op_lxi()
68{
69   // LXI i: Load X from Immediate
70   op_illegal();
71}
72
73void hmcs40_cpu_device::op_lyi()
74{
75   // LYI i: Load Y from Immediate
76   op_illegal();
77}
78
79void hmcs40_cpu_device::op_iy()
80{
81   // IY: Increment Y
82   op_illegal();
83}
84
85void hmcs40_cpu_device::op_dy()
86{
87   // DY: Decrement Y
88   op_illegal();
89}
90
91void hmcs40_cpu_device::op_ayy()
92{
93   // AYY: Add A to Y
94   op_illegal();
95}
96
97void hmcs40_cpu_device::op_syy()
98{
99   // SYY: Subtract A from Y
100   op_illegal();
101}
102
103void hmcs40_cpu_device::op_xspx()
104{
105   // XSPX: Exchange X and SPX
106   op_illegal();
107}
108
109void hmcs40_cpu_device::op_sxpy()
110{
111   // SXPY: Exchange Y and SPY
112   op_illegal();
113}
114
115void hmcs40_cpu_device::op_xspxy()
116{
117   // XSPXY: Exchange X and SPX, Y and SPY
118   op_illegal();
119}
120
121
122// Ram Register Instruction
123
124void hmcs40_cpu_device::op_lam()
125{
126   // LAM (XY): Load A from Memory
127   op_illegal();
128}
129
130void hmcs40_cpu_device::op_lbm()
131{
132   // LBM (XY): Load B from Memory
133   op_illegal();
134}
135
136void hmcs40_cpu_device::op_xma()
137{
138   // XMA (XY): Exchange Memory and A
139   op_illegal();
140}
141
142void hmcs40_cpu_device::op_xmb()
143{
144   // XMB (XY): Exchange Memory and B
145   op_illegal();
146}
147
148void hmcs40_cpu_device::op_lmaiy()
149{
150   // LMAIY (X): Load Memory from A, Increment Y
151   op_illegal();
152}
153
154void hmcs40_cpu_device::op_lmady()
155{
156   // LMADY (X): Load Memory from A, Decrement Y
157   op_illegal();
158}
159
160
161// Immediate Instruction
162
163void hmcs40_cpu_device::op_lmiiy()
164{
165   // LMIIY i: Load Memory from Immediate, Increment Y
166   op_illegal();
167}
168
169void hmcs40_cpu_device::op_lai()
170{
171   // LAI i: Load A from Immediate
172   op_illegal();
173}
174
175void hmcs40_cpu_device::op_lbi()
176{
177   // LBI i: Load B from Immediate
178   op_illegal();
179}
180
181
182// Arithmetic Instruction
183
184void hmcs40_cpu_device::op_ai()
185{
186   // AI i: Add Immediate to A
187   op_illegal();
188}
189
190void hmcs40_cpu_device::op_ib()
191{
192   // IB: Increment B
193   op_illegal();
194}
195
196void hmcs40_cpu_device::op_db()
197{
198   // DB: Decrement B
199   op_illegal();
200}
201
202void hmcs40_cpu_device::op_amc()
203{
204   // AMC: Add A to Memory with Carry
205   op_illegal();
206}
207
208void hmcs40_cpu_device::op_smc()
209{
210   // SMC: Subtract A from Memory with Carry
211   op_illegal();
212}
213
214void hmcs40_cpu_device::op_am()
215{
216   // AM: Add A to Memory
217   op_illegal();
218}
219
220void hmcs40_cpu_device::op_daa()
221{
222   // DAA: Decimal Adjust for Addition
223   op_illegal();
224}
225
226void hmcs40_cpu_device::op_das()
227{
228   // DAS: Decimal Adjust for Subtraction
229   op_illegal();
230}
231
232void hmcs40_cpu_device::op_nega()
233{
234   // NEGA: Negate A
235   op_illegal();
236}
237
238void hmcs40_cpu_device::op_comb()
239{
240   // COMB: Complement B
241   op_illegal();
242}
243
244void hmcs40_cpu_device::op_sec()
245{
246   // SEC: Set Carry
247   op_illegal();
248}
249
250void hmcs40_cpu_device::op_rec()
251{
252   // REC: Reset Carry
253   op_illegal();
254}
255
256void hmcs40_cpu_device::op_tc()
257{
258   // TC: Test Carry
259   op_illegal();
260}
261
262void hmcs40_cpu_device::op_rotl()
263{
264   // ROTL: Rotate Left A with Carry
265   op_illegal();
266}
267
268void hmcs40_cpu_device::op_rotr()
269{
270   // ROTR: Rotate Right A with Carry
271   op_illegal();
272}
273
274void hmcs40_cpu_device::op_or()
275{
276   // OR: OR A and B
277   op_illegal();
278}
279
280
281// Compare Instruction
282
283void hmcs40_cpu_device::op_mnei()
284{
285   // MNEI i: Memory Not Equal to Immediate
286   op_illegal();
287}
288
289void hmcs40_cpu_device::op_ynei()
290{
291   // YNEI i: Y Not Equal to Immediate
292   op_illegal();
293}
294
295void hmcs40_cpu_device::op_anem()
296{
297   // ANEM: A Not Equal to Memory
298   op_illegal();
299}
300
301void hmcs40_cpu_device::op_bnem()
302{
303   // BNEM: B Not Equal to Memory
304   op_illegal();
305}
306
307void hmcs40_cpu_device::op_alei()
308{
309   // ALEI i: A Less or Equal to Immediate
310   op_illegal();
311}
312
313void hmcs40_cpu_device::op_alem()
314{
315   // ALEM: A Less or Equal to Memory
316   op_illegal();
317}
318
319void hmcs40_cpu_device::op_blem()
320{
321   // BLEM: B Less or Equal to Memory
322   op_illegal();
323}
324
325
326// RAM Bit Manipulation Instruction
327
328void hmcs40_cpu_device::op_sem()
329{
330   // SEM n: Set Memory Bit
331   op_illegal();
332}
333
334void hmcs40_cpu_device::op_rem()
335{
336   // REM n: Reset Memory Bit
337   op_illegal();
338}
339
340void hmcs40_cpu_device::op_tm()
341{
342   // TM n: Test Memory Bit
343   op_illegal();
344}
345
346
347// ROM Address Instruction
348
349void hmcs40_cpu_device::op_br()
350{
351   // BR a: Branch on Status 1
352   op_illegal();
353}
354
355void hmcs40_cpu_device::op_cal()
356{
357   // CAL a: Subroutine Jump on Status 1
358   op_illegal();
359}
360
361void hmcs40_cpu_device::op_lpu()
362{
363   // LPU u: Load Program Counter Upper on Status 1
364   op_illegal();
365}
366
367void hmcs40_cpu_device::op_tbr()
368{
369   // TBR p: Table Branch
370   op_illegal();
371}
372
373void hmcs40_cpu_device::op_rtn()
374{
375   // RTN: Return from Subroutine
376   op_illegal();
377}
378
379
380// Interrupt Instruction
381
382void hmcs40_cpu_device::op_seie()
383{
384   // SEIE: Set I/E
385   op_illegal();
386}
387
388void hmcs40_cpu_device::op_seif0()
389{
390   // SEIF0: Set IF0
391   op_illegal();
392}
393
394void hmcs40_cpu_device::op_seif1()
395{
396   // SEIF1: Set IF1
397   op_illegal();
398}
399
400void hmcs40_cpu_device::op_setf()
401{
402   // SETF: Set TF
403   op_illegal();
404}
405
406void hmcs40_cpu_device::op_secf()
407{
408   // SECF: Set CF
409   op_illegal();
410}
411
412void hmcs40_cpu_device::op_reie()
413{
414   // REIE: Reset I/E
415   op_illegal();
416}
417
418void hmcs40_cpu_device::op_reif0()
419{
420   // REIF0: Reset IF0
421   op_illegal();
422}
423
424void hmcs40_cpu_device::op_reif1()
425{
426   // REIF1: Reset IF1
427   op_illegal();
428}
429
430void hmcs40_cpu_device::op_retf()
431{
432   // RETF: Reset TF
433   op_illegal();
434}
435
436void hmcs40_cpu_device::op_recf()
437{
438   // RECF: Reset CF
439   op_illegal();
440}
441
442void hmcs40_cpu_device::op_ti0()
443{
444   // TI0: Test INT0
445   op_illegal();
446}
447
448void hmcs40_cpu_device::op_ti1()
449{
450   // TI1: Test INT1
451   op_illegal();
452}
453
454void hmcs40_cpu_device::op_tif0()
455{
456   // TIF0: Test IF0
457   op_illegal();
458}
459
460void hmcs40_cpu_device::op_tif1()
461{
462   // TIF1: Test IF1
463   op_illegal();
464}
465
466void hmcs40_cpu_device::op_ttf()
467{
468   // TTF: Test TF
469   op_illegal();
470}
471
472void hmcs40_cpu_device::op_lti()
473{
474   // LTI i: Load Timer/Counter from Immediate
475   op_illegal();
476}
477
478void hmcs40_cpu_device::op_lta()
479{
480   // LTA: Load Timer/Counter from A
481   op_illegal();
482}
483
484void hmcs40_cpu_device::op_lat()
485{
486   // LAT: Load A from Timer/Counter
487   op_illegal();
488}
489
490void hmcs40_cpu_device::op_rtni()
491{
492   // RTNI: Return from Interrupt
493   op_illegal();
494}
495
496
497// Input/Output Instruction
498
499void hmcs40_cpu_device::op_sed()
500{
501   // SED: Set Discrete I/O Latch
502   op_illegal();
503}
504
505void hmcs40_cpu_device::op_red()
506{
507   // RED: Reset Discrete I/O Latch
508   op_illegal();
509}
510
511void hmcs40_cpu_device::op_td()
512{
513   // TD: Test Discrete I/O Latch
514   op_illegal();
515}
516
517void hmcs40_cpu_device::op_sedd()
518{
519   // SEDD n: Set Discrete I/O Latch Direct
520   op_illegal();
521}
522
523void hmcs40_cpu_device::op_redd()
524{
525   // REDD n: Reset Discrete I/O Latch Direct
526   op_illegal();
527}
528
529void hmcs40_cpu_device::op_lar()
530{
531   // LAR p: Load A from R-Port Register
532   op_illegal();
533}
534
535void hmcs40_cpu_device::op_lbr()
536{
537   // LBR p: Load B from R-Port Register
538   op_illegal();
539}
540
541void hmcs40_cpu_device::op_lra()
542{
543   // LRA p: Load R-Port Register from A
544   op_illegal();
545}
546
547void hmcs40_cpu_device::op_lrb()
548{
549   // LRB p: Load R-Port Register from B
550   op_illegal();
551}
552
553void hmcs40_cpu_device::op_p()
554{
555   // P p: Pattern Generation
556   op_illegal();
557}
558
559
560// Control Instruction
561
562void hmcs40_cpu_device::op_nop()
563{
564   // NOP: No Operation
565}
trunk/src/mame/mame.mak
r244759r244760
152152CPUS += ARCOMPACT
153153CPUS += AMIS2000
154154CPUS += UCOM4
155CPUS += HMCS40
155156
156157#-------------------------------------------------
157158# specify available sound cores
trunk/src/mess/mess.mak
r244759r244760
136136CPUS += ARCOMPACT
137137CPUS += AMIS2000
138138CPUS += UCOM4
139CPUS += HMCS40
139140
140141#-------------------------------------------------
141142# specify available sound cores; some of these are
trunk/src/tools/unidasm.c
r244759r244760
9494CPU_DISASSEMBLE( hd6301 );
9595CPU_DISASSEMBLE( hd6309 );
9696CPU_DISASSEMBLE( hd63701 );
97CPU_DISASSEMBLE( hmcs40 );
9798CPU_DISASSEMBLE( hyperstone_generic );
9899CPU_DISASSEMBLE( i4004 );
99100CPU_DISASSEMBLE( i8008 );
r244759r244760
243244   { "hd6301",     _8bit,  0, CPU_DISASSEMBLE_NAME(hd6301) },
244245   { "hd6309",     _8bit,  0, CPU_DISASSEMBLE_NAME(hd6309) },
245246   { "hd63701",    _8bit,  0, CPU_DISASSEMBLE_NAME(hd63701) },
247   { "hmcs40",     _16be,  0, CPU_DISASSEMBLE_NAME(hmcs40) },
246248   { "hyperstone", _16be,  0, CPU_DISASSEMBLE_NAME(hyperstone_generic) },
247249   { "i4004",      _8bit,  0, CPU_DISASSEMBLE_NAME(i4004) },
248250   { "i8008",      _8bit,  0, CPU_DISASSEMBLE_NAME(i8008) },

https://github.com/mamedev/mame/commit/93472ffab2a4d910fa9965088224cf24a0f67b80

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