MAME SVN History

199869 Revisions

r35316 Saturday 17th January, 2015 at 17:37:20 UTC by Brian Troha
peplus.c: CG2374 graphics are not specific to the X002374P poker data set. Move the CG2374 down into the X000055P sets to retain them - NW

[/branches/kale/src/emu/cpu/m6502]	m4510.c m6502.h om4510.lst om65ce02.lst
[/branches/kale/src/emu/drivers]	xtal.h
[/branches/kale/src/mame/drivers]	peplus.c
[/branches/kale/src/mess/drivers]	c65.c
[/branches/kale/src/mess/includes]	c65.h
[/branches/kale/src/mess/machine]	c65.c

branches/kale/src/emu/cpu/m6502/m4510.c
r243827	r243828
75	75	nomap = true;
76	76
77	77	// Wild guess, this setting makes the cpu start executing some code in the c65 driver
78		//map_offset[1] = 0x2e000;
79		//map_enable = 0x80;
	78	map_offset[1] = 0x30000;
	79	map_enable = 0x80;
80	80	m65ce02_device::device_reset();
81	81	}
82	82
r243827	r243828
86	86	{
87	87	address = map(address);
88	88	}
89
	89
90	90	return true;
91	91	}
92	92

branches/kale/src/emu/cpu/m6502/m6502.h
r243827	r243828
220	220
221	221	// inline helpers
222	222	static inline bool page_changing(UINT16 base, int delta) { return ((base + delta) ^ base) & 0xff00; }
223		static inline UINT16 set_l(UINT16 base, UINT16 val) { return (base & 0xff00) \| val; }
224		static inline UINT16 set_h(UINT16 base, UINT16 val) { return (base & 0x00ff) \| (val << 8); }
	223	static inline UINT16 set_l(UINT16 base, UINT8 val) { return (base & 0xff00) \| val; }
	224	static inline UINT16 set_h(UINT16 base, UINT8 val) { return (base & 0x00ff) \| (val << 8); }
225	225
226	226	inline void dec_SP() { SP = set_l(SP, SP-1); }
227	227	inline void inc_SP() { SP = set_l(SP, SP+1); }

branches/kale/src/emu/cpu/m6502/om4510.lst
r243827	r243828
9	9	map_offset[0] = (A<<8) \| ((X & 0xf) << 16);
10	10	map_offset[1] = (Y<<8) \| ((Z & 0xf) << 16);
11	11	map_enable = ((X & 0xf0) >> 4) \| (Z & 0xf0);
12		logerror("MAP execute\n");
13		logerror("0x0000 - 0x1fff = %08x\n",map_enable & 1 ? map_offset[0]+0x0000 : 0x0000);
14		logerror("0x2000 - 0x3fff = %08x\n",map_enable & 2 ? map_offset[0]+0x2000 : 0x2000);
15		logerror("0x4000 - 0x5fff = %08x\n",map_enable & 4 ? map_offset[0]+0x4000 : 0x4000);
16		logerror("0x6000 - 0x7fff = %08x\n",map_enable & 8 ? map_offset[0]+0x6000 : 0x6000);
17		logerror("0x8000 - 0x9fff = %08x\n",map_enable & 16 ? map_offset[1]+0x8000 : 0x8000);
18		logerror("0xa000 - 0xbfff = %08x\n",map_enable & 32 ? map_offset[1]+0xa000 : 0xa000);
19		logerror("0xc000 - 0xdfff = %08x\n",map_enable & 64 ? map_offset[1]+0xc000 : 0xc000);
20		logerror("0xe000 - 0xffff = %08x\n",map_enable & 128 ? map_offset[1]+0xe000 : 0xe000);
21	12	prefetch();

branches/kale/src/emu/cpu/m6502/om65ce02.lst
r243827	r243828
344	344	bra_rw2
345	345	TMP = read_pc();
346	346	TMP = set_h(TMP, read_pc());
347		PC += TMP ~~- 1~~;
	347	PC += TMP;
348	348	prefetch();
349	349
350	350	brk_ce_imp
r243827	r243828
419	419	cle_imp
420	420	read_pc_noinc();
421	421	P &= ~F_E;
422		logerror("CLE\n");
423	422	prefetch();
424	423
425	424	cli_ce_imp

branches/kale/src/emu/drivers/xtal.h
r243827	r243828
57	57	XTAL_2_5MHz = 2500000, /* Janken Man units */
58	58	XTAL_3MHz = 3000000, /* Probably only used to drive 68705 or similar MCUs on 80's Taito PCBs */
59	59	XTAL_3_12MHz = 3120000, /* SP0250 clock on Gottlieb games */
60		XTAL_3_5MHz = 3500000, /* Reported by Commodore 65 document, true xtal unchecked on PCB */
61	60	XTAL_3_52128MHz = 3521280, /* RCA COSMAC VIP */
62	61	XTAL_3_579545MHz = 3579545, /* NTSC color subcarrier, extremely common, used on 100's of PCBs (Keytronic custom part #48-300-010 is equivalent) */
63	62	XTAL_3_6864MHz = 3686400, /* CPS3 */

branches/kale/src/mame/drivers/peplus.c
r243827	r243828
3687	3687	ROM_REGION( 0x020000, "gfx1", 0 )
3688	3688	ROM_LOAD( "mro-cg2153.u72", 0x00000, 0x8000, CRC(004c9c8e) SHA1(ec3fa9d2c658de59e722d9979513d6b0c71d5742) ) /* 05/01/95 @ IGT L95-1123 */
3689	3689	ROM_LOAD( "mgo-cg2153.u73", 0x08000, 0x8000, CRC(e6843b35) SHA1(2d5219a3cb054ce8b470797c0496c7e24e94ed81) )
3690		ROM_LOAD( "mbo-cg2153.u74", 0x10000, 0x8000, CRC(e3e28611) SHA1(d040f1df6203dc0bd6a79a391fb90fb930f8dd1a) ) /* Custom Arizona Charlie's Casino gra~~phi~~cs */
	3690	ROM_LOAD( "mbo-cg2153.u74", 0x10000, 0x8000, CRC(e3e28611) SHA1(d040f1df6203dc0bd6a79a391fb90fb930f8dd1a) ) /* Custom Arizona Charlie's Casino card backs */
3691	3691	ROM_LOAD( "mxo-cg2153.u75", 0x18000, 0x8000, CRC(3ae44f7e) SHA1(00d625b60bffef6ce622cb50a3aa93b92131f578) )
3692	3692
3693	3693	ROM_REGION( 0x100, "proms", 0 )
r243827	r243828
5393	5393	ROM_LOAD( "x000055p.u66", 0x00000, 0x10000, CRC(e06819df) SHA1(36590c4588b8036908e63714fbb3e77d23e60eae) ) /* Deuces Wild Poker */
5394	5394
5395	5395	ROM_REGION( 0x020000, "gfx1", 0 )
5396		ROM_LOAD( "mro-cg2291.u77", 0x00000, 0x8000, CRC(db4e491c) SHA1(e371e7b236962a0f30640c683d3a0a302c51aee9) ) /* Custom The Orleans gra~~phi~~cs */
	5396	ROM_LOAD( "mro-cg2291.u77", 0x00000, 0x8000, CRC(db4e491c) SHA1(e371e7b236962a0f30640c683d3a0a302c51aee9) ) /* Custom The Orleans card backs */
5397	5397	ROM_LOAD( "mgo-cg2291.u78", 0x08000, 0x8000, CRC(17bb35f8) SHA1(ba9e8aa3ff42b17c7be6ee46c70db22d8e60e52c) ) /* Compatible with most "standard" game sets */
5398	5398	ROM_LOAD( "mbo-cg2291.u79", 0x10000, 0x8000, CRC(de1036e4) SHA1(774bbcda301754dc4a606974248847a2264c3827) )
5399	5399	ROM_LOAD( "mxo-cg2291.u80", 0x18000, 0x8000, CRC(7049403c) SHA1(3a29a00fb8dfdb30dba757c1536151827ea09068) )
r243827	r243828
5418	5418	ROM_LOAD( "x000055p.u66", 0x00000, 0x10000, CRC(e06819df) SHA1(36590c4588b8036908e63714fbb3e77d23e60eae) ) /* Deuces Wild Poker */
5419	5419
5420	5420	ROM_REGION( 0x020000, "gfx1", 0 )
5421		ROM_LOAD( "mro-cg2399.u72", 0x00000, 0x8000, CRC(0424f4ba) SHA1(c8b192a6f63c8c9937cb3923d27b9ba2c39823cd) ) /* Custom The Fun Ships gra~~phi~~cs */
	5421	ROM_LOAD( "mro-cg2399.u72", 0x00000, 0x8000, CRC(0424f4ba) SHA1(c8b192a6f63c8c9937cb3923d27b9ba2c39823cd) ) /* Custom The Fun Ships card backs */
5422	5422	ROM_LOAD( "mgo-cg2399.u73", 0x08000, 0x8000, CRC(5848a2fa) SHA1(4173a473016b7a776d2b59bf3ded0be35bd43721) )
5423	5423	ROM_LOAD( "mbo-cg2399.u74", 0x10000, 0x8000, CRC(5c3e16f6) SHA1(a4aa457f239527bffa6472e0d6f9d836f796b326) )
5424	5424	ROM_LOAD( "mxo-cg2399.u75", 0x18000, 0x8000, CRC(bd7669d5) SHA1(4343a9764fd563e2e1cdd8558f2f53f77006b159) )
r243827	r243828
5443	5443	ROM_LOAD( "x000055p.u66", 0x00000, 0x10000, CRC(e06819df) SHA1(36590c4588b8036908e63714fbb3e77d23e60eae) ) /* Deuces Wild Poker */
5444	5444
5445	5445	ROM_REGION( 0x020000, "gfx1", 0 )
5446		ROM_LOAD( "mro-cg2185.u77", 0x00000, 0x8000, CRC(7e64bd1a) SHA1(e988a380ee58078bf5bdc7747e83aed1393cfad8) ) /* 07/10/95 @ IGT L95-1506 */
5447		ROM_LOAD( "mgo-cg2185.u78", 0x08000, 0x8000, CRC(d4127893) SHA1(75039c45ba6fd171a66876c91abc3191c7feddfc) )
5448		ROM_LOAD( "mbo-cg2185.u79", 0x10000, 0x8000, CRC(17dba955) SHA1(5f77379c88839b3a04e235e4fb0120c77e17b60e) )
5449		ROM_LOAD( "mxo-cg2185.u80", 0x18000, 0x8000, CRC(583eb3b1) SHA1(4a2952424969917fb1594698a779fe5a1e99bff5) )
	5446	ROM_LOAD( "mro-cg2374.u72", 0x00000, 0x8000, CRC(ceeb714d) SHA1(6de908d04bcaa243195943affa9ad0d725de5c81) ) /* Custom Horseshoe Casino card backs */
	5447	ROM_LOAD( "mgo-cg2374.u73", 0x08000, 0x8000, CRC(d0fabad5) SHA1(438ebe074fa3eaa3073ef042f481449f416d0665) )
	5448	ROM_LOAD( "mbo-cg2374.u74", 0x10000, 0x8000, CRC(9a0fbc8d) SHA1(aa39f47cbeaf8218fd2d753c9a350e9eab5df5d3) )
	5449	ROM_LOAD( "mxo-cg2374.u75", 0x18000, 0x8000, CRC(99814562) SHA1(2d8e132f4cc4edd06332c0327927219513b22832) )
5450	5450
5451	5451	ROM_REGION( 0x200, "proms", 0 )
5452		ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(~~4b57569~~f) SHA1(fa29c0f62~~7e7~~c~~e799~~5~~1ec~~6dade~~c114~~8~~64144~~f~~37d~~) )
	5452	ROM_LOAD( "capx2374.u43", 0x0000, 0x0200, CRC(f922e1b8) SHA1(4aa5291c59431c022dc0561a6e3b38209f60286a) )
5453	5453	ROM_END
5454	5454
5455	5455	ROM_START( pex0055pd ) /* Superboard : Deuces Wild Poker (X000055P+XP000035) */
r243827	r243828
7940	7940	ROM_LOAD( "x002374p.u66", 0x00000, 0x10000, CRC(fc4b6c8d) SHA1(b101f9042bd54dbfdeed4c7a3acf3798096f6857) ) /* Super Aces Poker */
7941	7941
7942	7942	ROM_REGION( 0x020000, "gfx1", 0 )
7943		ROM_LOAD( "mro-cg2374.u72", 0x00000, 0x8000, CRC(ceeb714d) SHA1(6de908d04bcaa243195943affa9ad0d725de5c81) ) /* Custom Horseshoe Casino card backs */
7944		ROM_LOAD( "mgo-cg2374.u73", 0x08000, 0x8000, CRC(d0fabad5) SHA1(438ebe074fa3eaa3073ef042f481449f416d0665) )
7945		ROM_LOAD( "mbo-cg2374.u74", 0x10000, 0x8000, CRC(9a0fbc8d) SHA1(aa39f47cbeaf8218fd2d753c9a350e9eab5df5d3) )
7946		ROM_LOAD( "mxo-cg2374.u75", 0x18000, 0x8000, CRC(99814562) SHA1(2d8e132f4cc4edd06332c0327927219513b22832) )
	7943	ROM_LOAD( "mro-cg2324.u77", 0x00000, 0x8000, CRC(6eceef42) SHA1(a2ddd2a3290c41e510f483c6b633fe0002694d0b) )
	7944	ROM_LOAD( "mgo-cg2324.u78", 0x08000, 0x8000, CRC(26d0acbe) SHA1(09a9127deb88185cd5b748bac657461eadb2f48f) )
	7945	ROM_LOAD( "mbo-cg2324.u79", 0x10000, 0x8000, CRC(47baee32) SHA1(d8af09022ccb5fc06aa3aa4c200a734b66cbee00) )
	7946	ROM_LOAD( "mxo-cg2324.u80", 0x18000, 0x8000, CRC(60449fc0) SHA1(251d1e04786b70c1d2bc7b02f3b69cd58ac76398) )
7947	7947
7948	7948	ROM_REGION( 0x200, "proms", 0 )
7949		ROM_LOAD( "capx2374.u43", 0x0000, 0x0200, CRC(~~f922e1~~b8) SHA1(4aa5291c~~59431c~~022dc0561a6e~~3b3~~8~~209f~~6~~0286a~~) )
	7949	ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
7950	7950	ROM_END
7951	7951
7952	7952	ROM_START( pex2377p ) /* Superboard : Super Double Bonus Poker (X002377P+XP000112) */
r243827	r243828
9265	9265	GAMEL(1995, pex0055p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000019) Deuces Wild Poker", 0, layout_pe_poker )
9266	9266	GAMEL(1995, pex0055pa, pex0055p, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000022) Deuces Wild Poker (The Orleans)", 0, layout_pe_poker )
9267	9267	GAMEL(1995, pex0055pb, pex0055p, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000023) Deuces Wild Poker (The Fun Ships)", 0, layout_pe_poker )
9268		GAMEL(1995, pex0055pc, pex0055p, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000028) Deuces Wild Poker", 0, layout_pe_poker )
	9268	GAMEL(1995, pex0055pc, pex0055p, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000028) Deuces Wild Poker (Horseshoe)", 0, layout_pe_poker )
9269	9269	GAMEL(1995, pex0055pd, pex0055p, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000035) Deuces Wild Poker", 0, layout_pe_poker )
9270	9270	GAMEL(1995, pex0055pe, pex0055p, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000038) Deuces Wild Poker", 0, layout_pe_poker )
9271	9271	GAMEL(1995, pex0055pf, pex0055p, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X000055P+XP000040) Deuces Wild Poker", 0, layout_pe_poker )
r243827	r243828
9363	9363	GAMEL(1995, pex2308p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X002308P+XP000112) Triple Double Bonus Poker", 0, layout_pe_poker )
9364	9364	GAMEL(1995, pex2310p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X002310P+XP000112) Triple Double Bonus Poker", 0, layout_pe_poker )
9365	9365	GAMEL(1995, pex2314p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X002314P+XP000112) Triple Bonus Poker Plus", 0, layout_pe_poker )
9366		GAMEL(1995, pex2374p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X002374P+XP000112) Super Aces Poker ~~(Horseshoe)~~", 0, layout_pe_poker )
	9366	GAMEL(1995, pex2374p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X002374P+XP000112) Super Aces Poker", 0, layout_pe_poker )
9367	9367	GAMEL(1995, pex2377p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X002377P+XP000112) Super Double Bonus Poker", 0, layout_pe_poker )
9368	9368	GAMEL(1995, pex2419p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X002419P+XP000064) Deuces Wild Bonus Poker - French", 0, layout_pe_poker )
9369	9369	GAMEL(1995, pex2420p, 0, peplus, peplus_poker, peplus_state, peplussb, ROT0, "IGT - International Game Technology", "Player's Edge Plus (X002420P+XP000064) Deuces Wild Bonus Poker - French", 0, layout_pe_poker )

branches/kale/src/mess/drivers/c65.c
r243827	r243828
1		// license: MAME
2		// copyright-holders: Angelo Salese
3	1	/***************************************************************************
4	2
5		C=65 / C=64DX (c) 1991 Commodore
	3	commodore c65 home computer
	4	PeT mess@utanet.at
6	5
7		Attempt at rewriting the driver ...
	6	documention
	7	www.funet.fi
8	8
9		TODO:
10		- Dies as soon as it enters into DOS ROM (bp 0x9d1a, it never returns due of a bad stack pointer read);
	9	***************************************************************************/
11	10
12		Note:
13		- VIC-4567 will be eventually be added via compile switch, once that I
14		get the hang of the system (and checking where the old code fails
15		eventually)
	11	/*
16	12
17		***************************************************************************/
	13	2008 - Driver Updates
	14	---------------------
18	15
	16	(most of the informations are taken from http://www.zimmers.net/cbmpics/ )
19	17
20		#include "emu.h"
21		#include "cpu/m6502/m4510.h"
22	18
23		#define ~~MAIN_CLOCK~~ ~~XTAL_3_5MHz~~
	19	[CBM systems which belong to this driver]
24	20
25		class c65_state : public driver_device
26		{
27		public:
28		c65_state(const machine_config &mconfig, device_type type, const char *tag)
29		: driver_device(mconfig, type, tag),
30		m_maincpu(*this, "maincpu"),
31		m_screen(*this, "screen"),
32		m_palette(*this, "palette"),
33		m_workram(*this, "wram"),
34		m_palred(*this, "redpal"),
35		m_palgreen(*this, "greenpal"),
36		m_palblue(*this, "bluepal"),
37		m_dmalist(*this, "dmalist"),
38		m_cram(*this, "cram"),
39		m_gfxdecode(*this, "gfxdecode")
40		{ }
	21	* Commodore 65 (1989)
41	22
42		// devices
43		required_device<m4510_device> m_maincpu;
44		required_device<screen_device> m_screen;
45		required_device<palette_device> m_palette;
46		required_shared_ptr<UINT8> m_workram;
47		required_shared_ptr<UINT8> m_palred;
48		required_shared_ptr<UINT8> m_palgreen;
49		required_shared_ptr<UINT8> m_palblue;
50		required_shared_ptr<UINT8> m_dmalist;
51		required_shared_ptr<UINT8> m_cram;
52		required_device<gfxdecode_device> m_gfxdecode;
	23	Also known as C64 DX at early stages of the project. It was cancelled
	24	around 1990-1991. Only few units survive (they were sold after Commodore
	25	liquidation in 1994).
53	26
54		DECLARE_READ8_MEMBER(vic4567_dummy_r);
55		DECLARE_WRITE8_MEMBER(vic4567_dummy_w);
56		DECLARE_WRITE8_MEMBER(PalRed_w);
57		DECLARE_WRITE8_MEMBER(PalGreen_w);
58		DECLARE_WRITE8_MEMBER(PalBlue_w);
59		DECLARE_WRITE8_MEMBER(DMAgic_w);
60		DECLARE_READ8_MEMBER(CIASelect_r);
61		DECLARE_WRITE8_MEMBER(CIASelect_w);
62
63		DECLARE_READ8_MEMBER(dummy_r);
64
65		// screen updates
66		UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
67		DECLARE_PALETTE_INIT(c65);
68		DECLARE_DRIVER_INIT(c65);
69		DECLARE_DRIVER_INIT(c65pal);
70
71		INTERRUPT_GEN_MEMBER(vic3_vblank_irq);
72		protected:
73		// driver_device overrides
74		virtual void machine_start();
75		virtual void machine_reset();
	27	CPU: CSG 4510 (3.54 MHz)
	28	RAM: 128 kilobytes, expandable to 8 megabytes
	29	ROM: 128 kilobytes
	30	Video: CSG 4569 "VIC-III" (6 Video modes; Resolutions from 320x200 to
	31	1280x400; 80 columns text; Palette of 4096 colors)
	32	Sound: CSG 8580 "SID" x2 (6 voice stereo synthesizer/digital sound
	33	capabilities)
	34	Ports: CSG 4510 (2 Joystick/Mouse ports; CBM Serial port; CBM 'USER'
	35	port; CBM Monitor port; Power and reset switches; C65 bus drive
	36	port; RGBI video port; 2 RCA audio ports; RAM expansion port; C65
	37	expansion port)
	38	Keyboard: Full-sized 77 key QWERTY (12 programmable function keys;
	39	4 direction cursor-pad)
	40	Additional Hardware: Built in 3.5" DD disk drive (1581 compatible)
	41	Miscellaneous: Partially implemented Commodore 64 emulation
76	42
77		virtual void video_start();
78		private:
79		UINT8 m_VIC2_IRQPend, m_VIC2_IRQMask;
80		UINT8 m_VIC3_ControlA,m_VIC3_ControlB;
81		void PalEntryFlush(UINT8 offset);
82		void DMAgicExecute(address_space &space,UINT32 address);
83		};
	43	[Notes]
84	44
85		void c65_state::video_start()
	45	The datasette port was removed here. C65 supports an additional "dumb"
	46	drive externally. It also features, in addition to the standard CBM
	47	bus serial (available in all modes), a Fast and a Burst serial bus
	48	(both available in C65 mode only)
	49
	50	*/
	51
	52
	53	#include "emu.h"
	54	#include "cpu/m6502/m4510.h"
	55	#include "machine/mos6526.h"
	56	#include "machine/cbm_snqk.h"
	57	#include "includes/c65.h"
	58	#include "bus/cbmiec/cbmiec.h"
	59	#include "machine/ram.h"
	60
	61	static void cbm_c65_quick_sethiaddress( address_space &space, UINT16 hiaddress )
86	62	{
	63	space.write_byte(0x82, hiaddress & 0xff);
	64	space.write_byte(0x83, hiaddress >> 8);
87	65	}
88	66
89		UI~~NT32~~ c65_state~~::screen_update( screen_device &screen~~, bitmap_~~ind16 &bitmap,~~ c~~onst rectangle &cliprect~~ )
	67	QUICKLOAD_LOAD_MEMBER( c65_state, cbm_c65 )
90	68	{
91		int y,x;
92		gfx_element *gfx = m_gfxdecode->gfx(0);
	69	return general_cbm_loadsnap(image, file_type, quickload_size, m_maincpu->space(AS_PROGRAM), 0, cbm_c65_quick_sethiaddress);
	70	}
93	71
94		for(y=0;y<30;y++)
95		{
96		for(x=0;x<40;x++)
97		{
98		UINT8 tile = m_workram[x+y*40+0x800];
99		gfx->opaque(bitmap,cliprect,tile,0,0,0,x8,y8);
100		}
101		}
	72	/*************************************
	73	*
	74	* Main CPU memory handlers
	75	*
	76	*************************************/
102	77
103		return 0;
104		}
	78	static ADDRESS_MAP_START( c65_mem , AS_PROGRAM, 8, c65_state )
	79	AM_RANGE(0x00000, 0x07fff) AM_RAMBANK("bank11")
	80	AM_RANGE(0x08000, 0x09fff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank12")
	81	AM_RANGE(0x0a000, 0x0bfff) AM_READ_BANK("bank2") AM_WRITE_BANK("bank13")
	82	AM_RANGE(0x0c000, 0x0cfff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank14")
	83	AM_RANGE(0x0d000, 0x0d7ff) AM_READ_BANK("bank4") AM_WRITE_BANK("bank5")
	84	AM_RANGE(0x0d800, 0x0dbff) AM_READ_BANK("bank6") AM_WRITE_BANK("bank7")
	85	AM_RANGE(0x0dc00, 0x0dfff) AM_READ_BANK("bank8") AM_WRITE_BANK("bank9")
	86	AM_RANGE(0x0e000, 0x0ffff) AM_READ_BANK("bank10") AM_WRITE_BANK("bank15")
	87	AM_RANGE(0x10000, 0x1f7ff) AM_RAM
	88	AM_RANGE(0x1f800, 0x1ffff) AM_RAM AM_SHARE("colorram")
105	89
106		READ8_MEMBER(c65_state::vic4567_dummy_r)
107		{
108		UINT8 res;
	90	AM_RANGE(0x20000, 0x23fff) AM_ROM /* &c65_dos, maps to 0x8000 */
	91	AM_RANGE(0x24000, 0x28fff) AM_ROM /* reserved */
	92	AM_RANGE(0x29000, 0x29fff) AM_ROM AM_SHARE("c65_chargen")
	93	AM_RANGE(0x2a000, 0x2bfff) AM_ROM AM_SHARE("basic")
	94	AM_RANGE(0x2c000, 0x2cfff) AM_ROM AM_SHARE("interface")
	95	AM_RANGE(0x2d000, 0x2dfff) AM_ROM AM_SHARE("chargen")
	96	AM_RANGE(0x2e000, 0x2ffff) AM_ROM AM_SHARE("kernal")
109	97
110		res=0xff;
111		switch(offset)
112		{
113		case 0x11:
114		res = (m_screen->vpos() & 0x100) >> 1;
115		return res;
116		case 0x12:
117		res = (m_screen->vpos() & 0xff);
118		return res;
119		case 0x19:
120		return m_VIC2_IRQPend;
121		case 0x30:
122		return m_VIC3_ControlA;
123		case 0x31:
124		return m_VIC3_ControlB;
125		}
126
127		if(!space.debugger_access())
128		printf("%02x\n",offset); // TODO: PC
129		return res;
130		}
	98	AM_RANGE(0x30000, 0x31fff) AM_ROM /&c65_monitor, monitor maps to 0x6000 /
	99	AM_RANGE(0x32000, 0x37fff) AM_ROM /&c65_basic, /
	100	AM_RANGE(0x38000, 0x3bfff) AM_ROM /&c65_graphics, /
	101	AM_RANGE(0x3c000, 0x3dfff) AM_ROM /* reserved */
	102	AM_RANGE(0x3e000, 0x3ffff) AM_ROM /* &c65_kernal, */
131	103
132		WRITE8_MEMBER(c65_state::vic4567_dummy_w)
	104	AM_RANGE(0x40000, 0x7ffff) AM_NOP
	105	/* 8 megabyte full address space! */
	106	ADDRESS_MAP_END
	107
	108
	109	/*************************************
	110	*
	111	* Input Ports
	112	*
	113	*************************************/
	114
	115	static INPUT_PORTS_START( c65 )
	116	PORT_START( "ROW0" )
	117	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Crsr Down Up") PORT_CODE(KEYCODE_RALT) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) PORT_CHAR(UCHAR_MAMEKEY(UP))
	118	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F5))
	119	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F3))
	120	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1))
	121	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F7))
	122	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Crsr Right Left") PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
	123	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
	124	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("INST DEL") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) PORT_CHAR(UCHAR_MAMEKEY(INSERT))
	125
	126	PORT_START( "ROW1" )
	127	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift (Left)") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
	128	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('E')
	129	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('S')
	130	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('Z')
	131	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
	132	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('A')
	133	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('W')
	134	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
	135
	136	PORT_START( "ROW2" )
	137	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('X')
	138	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('T')
	139	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('F')
	140	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('C')
	141	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
	142	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('D')
	143	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('R')
	144	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
	145
	146	PORT_START( "ROW3" )
	147	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('V')
	148	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('U')
	149	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('H')
	150	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('B')
	151	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
	152	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('G')
	153	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y')
	154	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
	155
	156	PORT_START( "ROW4" )
	157	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('N')
	158	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('O')
	159	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('K')
	160	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('M')
	161	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
	162	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('J')
	163	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('I')
	164	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
	165
	166	PORT_START( "ROW5" )
	167	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
	168	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@')
	169	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(':') PORT_CHAR('[')
	170	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
	171	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('-')
	172	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('L')
	173	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('P')
	174	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('+')
	175
	176	PORT_START( "ROW6" )
	177	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
	178	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("\xE2\x86\x91 Pi") PORT_CODE(KEYCODE_DEL) PORT_CHAR(0x2191) PORT_CHAR(0x03C0)
	179	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('=')
	180	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift (Right)") PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
	181	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("CLR HOME") PORT_CODE(KEYCODE_INSERT) PORT_CHAR(UCHAR_MAMEKEY(HOME))
	182	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(';') PORT_CHAR(']')
	183	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('*')
	184	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('\xA3')
	185
	186	PORT_START( "ROW7" )
	187	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("RUN STOP") PORT_CODE(KEYCODE_HOME)
	188	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q')
	189	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("CBM") PORT_CODE(KEYCODE_LALT)
	190	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
	191	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
	192	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_SHIFT_2)
	193	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("\xE2\x86\x90") PORT_CODE(KEYCODE_TILDE) PORT_CHAR(0x2190)
	194	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
	195	PORT_START("FUNCT")
	196	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("ESC") PORT_CODE(KEYCODE_F1)
	197	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F13 F14") PORT_CODE(KEYCODE_F11)
	198	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F11 F12") PORT_CODE(KEYCODE_F10)
	199	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F9 F10") PORT_CODE(KEYCODE_F9)
	200	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("HELP") PORT_CODE(KEYCODE_F12)
	201	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("ALT") PORT_CODE(KEYCODE_F2) /* non blocking */
	202	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB)
	203	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("NO SCRL") PORT_CODE(KEYCODE_F4)
	204
	205	PORT_START( "SPECIAL" ) /* special keys */
	206	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Restore") PORT_CODE(KEYCODE_PRTSCR)
	207	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift Lock (switch)") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
	208	PORT_CONFNAME( 0x20, 0x00, "(C65) Caps Lock (switch)") PORT_CODE(KEYCODE_F3)
	209	PORT_CONFSETTING( 0x00, DEF_STR( Off ) )
	210	PORT_CONFSETTING( 0x20, DEF_STR( On ) )
	211	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED )
	212
	213	PORT_START("CTRLSEL") /* Controller selection */
	214	PORT_CONFNAME( 0x07, 0x00, "Gameport A" )
	215	PORT_CONFSETTING( 0x00, DEF_STR( Joystick ) )
	216	PORT_CONFSETTING( 0x01, "Paddles 1 & 2" )
	217	PORT_CONFSETTING( 0x02, "Mouse 1351" )
	218	PORT_CONFSETTING( 0x03, "Mouse (Non Proportional) 1350" )
	219	PORT_CONFSETTING( 0x04, "Lightpen" )
	220	// PORT_CONFSETTING( 0x05, "Koala Pad" )
	221	PORT_CONFSETTING( 0x06, "Lightgun" )
	222	PORT_CONFSETTING( 0x07, "No Device Connected" )
	223	PORT_CONFNAME( 0x70, 0x00, "Gameport B" )
	224	PORT_CONFSETTING( 0x00, DEF_STR( Joystick ) )
	225	PORT_CONFSETTING( 0x10, "Paddles 3 & 4" )
	226	// PORT_CONFSETTING( 0x20, "Mouse 1351" )
	227	// PORT_CONFSETTING( 0x30, "Mouse (Non Proportional) 1350" )
	228	PORT_CONFSETTING( 0x70, "No Device Connected" )
	229	PORT_CONFNAME( 0x80, 0x00, "Swap Gameport A and B") PORT_CODE(KEYCODE_F1) PORT_TOGGLE
	230	PORT_CONFSETTING( 0x00, DEF_STR( No ) )
	231	PORT_CONFSETTING( 0x80, DEF_STR( Yes ) )
	232
	233	PORT_START("JOY1_1B")
	234	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
	235	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
	236	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
	237	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
	238	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
	239	PORT_BIT( 0xe0, IP_ACTIVE_HIGH, IPT_UNUSED )
	240
	241	PORT_START("JOY2_1B")
	242	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_HOME) PORT_CODE(JOYCODE_Y_UP_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
	243	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_END) PORT_CODE(JOYCODE_Y_DOWN_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
	244	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_DEL) PORT_CODE(JOYCODE_X_LEFT_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
	245	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_PGDN) PORT_CODE(JOYCODE_X_RIGHT_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
	246	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_CODE(KEYCODE_INSERT) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
	247	PORT_BIT( 0xe0, IP_ACTIVE_HIGH, IPT_UNUSED )
	248
	249	/* Mouse Commodore 1350 was basically working as a Joystick */
	250	PORT_START("JOY1_2B")
	251	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("Mouse 1350 Up") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
	252	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("Mouse 1350 Down") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
	253	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("Mouse 1350 Left") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
	254	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("Mouse 1350 Right") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
	255	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1) PORT_NAME("Mouse 1350 Button 1") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
	256	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(1) PORT_NAME("Mouse 1350 Button 2") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
	257	PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
	258
	259	/* Still to verify how many mices you were able to plug into a c64 */
	260	/* Only one, for now */
	261	PORT_START("JOY2_2B")
	262	PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED )
	263	/* PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_HOME) PORT_CODE(JOYCODE_Y_UP_SWITCH)
	264	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_END) PORT_CODE(JOYCODE_Y_DOWN_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
	265	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_DEL) PORT_CODE(JOYCODE_X_LEFT_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
	266	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_PGDN) PORT_CODE(JOYCODE_X_RIGHT_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
	267	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_CODE(KEYCODE_INSERT) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
	268	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2) PORT_CODE(KEYCODE_PGUP) PORT_CODE(JOYCODE_BUTTON2) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
	269	PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
	270	*/
	271	PORT_START("PADDLE1")
	272	PORT_BIT( 0xff, 128, IPT_PADDLE) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_MINMAX(0,255) PORT_CENTERDELTA(0) PORT_CODE_DEC(KEYCODE_LEFT) PORT_CODE_INC(KEYCODE_RIGHT) PORT_CODE_DEC(JOYCODE_X_LEFT_SWITCH) PORT_CODE_INC(JOYCODE_X_RIGHT_SWITCH) PORT_PLAYER(1) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x01)
	273
	274	PORT_START("PADDLE2")
	275	PORT_BIT( 0xff, 128, IPT_PADDLE) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_MINMAX(0,255) PORT_CENTERDELTA(0) PORT_CODE_DEC(KEYCODE_DOWN) PORT_CODE_INC(KEYCODE_UP) PORT_CODE_DEC(JOYCODE_Y_UP_SWITCH) PORT_CODE_INC(JOYCODE_Y_DOWN_SWITCH) PORT_PLAYER(2) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x01)
	276
	277	PORT_START("PADDLE3")
	278	PORT_BIT( 0xff, 128, IPT_PADDLE) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_MINMAX(0,255) PORT_CENTERDELTA(0) PORT_CODE_DEC(KEYCODE_HOME) PORT_CODE_INC(KEYCODE_PGUP) PORT_PLAYER(3) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x10)
	279
	280	PORT_START("PADDLE4")
	281	PORT_BIT( 0xff, 128, IPT_PADDLE) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_MINMAX(0,255) PORT_CENTERDELTA(0) PORT_CODE_DEC(KEYCODE_END) PORT_CODE_INC(KEYCODE_PGDN) PORT_PLAYER(4) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x10)
	282
	283	PORT_START("TRACKX")
	284	PORT_BIT( 0x7e, 0x00, IPT_TRACKBALL_X) PORT_SENSITIVITY(100) PORT_KEYDELTA(0) PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x02)
	285
	286	PORT_START("TRACKY")
	287	PORT_BIT( 0x7e, 0x00, IPT_TRACKBALL_Y) PORT_SENSITIVITY(100) PORT_KEYDELTA(0) PORT_PLAYER(1) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x02)
	288
	289	PORT_START("LIGHTX")
	290	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X) PORT_NAME("Lightpen X Axis") PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x04)
	291
	292	PORT_START("LIGHTY")
	293	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y) PORT_NAME("Lightpen Y Axis") PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x04)
	294
	295	PORT_START("OTHER")
	296	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1) PORT_NAME("Paddle 1 Button") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x01)
	297	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2) PORT_NAME("Paddle 2 Button") PORT_CODE(KEYCODE_LALT) PORT_CODE(JOYCODE_BUTTON2) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x01)
	298	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON3) PORT_NAME("Paddle 3 Button") PORT_CODE(KEYCODE_INSERT) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x10)
	299	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON4) PORT_NAME("Paddle 4 Button") PORT_CODE(KEYCODE_DEL) PORT_CODE(JOYCODE_BUTTON2) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x10)
	300	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1) PORT_NAME("Lightpen Signal") PORT_CODE(KEYCODE_LCONTROL) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x04)
	301	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1) PORT_NAME("Mouse Button Left") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x02)
	302	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON2) PORT_NAME("Mouse Button Right") PORT_CODE(KEYCODE_LALT) PORT_CODE(JOYCODE_BUTTON2) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x02)INPUT_PORTS_END
	303
	304
	305	static INPUT_PORTS_START( c65ger )
	306	PORT_INCLUDE( c65 )
	307
	308	PORT_MODIFY( "ROW1" )
	309	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Z { Y }") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z')
	310	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("3 # { 3 Paragraph }") PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
	311
	312	PORT_MODIFY( "ROW3" )
	313	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y { Z }") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y')
	314	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("7 ' { 7 / }") PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
	315
	316	PORT_MODIFY( "ROW4" )
	317	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("0 { = }") PORT_CODE(KEYCODE_0) PORT_CHAR('0')
	318
	319	PORT_MODIFY( "ROW5" )
	320	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(", < { ; }") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
	321	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Paragraph \xE2\x86\x91 { \xc3\xbc }") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR(0x00A7) PORT_CHAR(0x2191)
	322	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(": [ { \xc3\xa4 }") PORT_CODE(KEYCODE_COLON) PORT_CHAR(':') PORT_CHAR('[')
	323	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(". > { : }") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
	324	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("- { ' ` }") PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('-')
	325	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("+ { \xc3\x9f ? }") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('+')
	326
	327	PORT_MODIFY( "ROW6" )
	328	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/ ? { - _ }") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
	329	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Sum Pi { ] \\ }") PORT_CODE(KEYCODE_DEL) PORT_CHAR(0x03A3) PORT_CHAR(0x03C0)
	330	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("= { # ' }") PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('=')
	331	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("; ] { \xc3\xb6 }") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(';') PORT_CHAR(']')
	332	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("* ` { + * }") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('*') PORT_CHAR('`')
	333	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("\\ { [ \xE2\x86\x91 }") PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('\xa3')
	334
	335	PORT_MODIFY( "ROW7" )
	336	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("_ { < > }") PORT_CODE(KEYCODE_TILDE) PORT_CHAR('_')
	337
	338	PORT_MODIFY("SPECIAL") /* special keys */
	339	PORT_DIPNAME( 0x20, 0x00, "(C65) DIN ASC (switch)") PORT_CODE(KEYCODE_F3)
	340	PORT_DIPSETTING( 0x00, "ASC" )
	341	PORT_DIPSETTING( 0x20, "DIN" )
	342	INPUT_PORTS_END
	343
	344
	345
	346	/*************************************
	347	*
	348	* Sound definitions
	349	*
	350	*************************************/
	351
	352	int c65_state::c64_paddle_read( device_t *device, address_space &space, int which )
133	353	{
134		switch(offset)
	354	int pot1 = 0xff, pot2 = 0xff, pot3 = 0xff, pot4 = 0xff, temp;
	355	UINT8 cia0porta = machine().device<mos6526_device>("cia_0")->pa_r(space, 0);
	356	int controller1 = ioport("CTRLSEL")->read() & 0x07;
	357	int controller2 = ioport("CTRLSEL")->read() & 0x70;
	358	/* Notice that only a single input is defined for Mouse & Lightpen in both ports */
	359	switch (controller1)
135	360	{
136		case 0x19:
137		m_VIC2_IRQPend = data & 0x8f;
	361	case 0x01:
	362	if (which)
	363	pot2 = ioport("PADDLE2")->read();
	364	else
	365	pot1 = ioport("PADDLE1")->read();
138	366	break;
139		case 0x1a:
140		m_VIC2_IRQMask = data & 0xf;
	367
	368	case 0x02:
	369	if (which)
	370	pot2 = ioport("TRACKY")->read();
	371	else
	372	pot1 = ioport("TRACKX")->read();
141	373	break;
142		/* KEY register, handles vic-iii and vic-ii modes via two consecutive writes
143		0xa5 -> 0x96 vic-iii mode
144		any other write vic-ii mode
145		*/
146		//case 0x2f: break;
147		case 0x30:
148		if((data & 0xfe) != 0x64)
149		printf("CONTROL A %02x\n",data);
150		m_VIC3_ControlA = data;
	374
	375	case 0x03:
	376	if (which && (ioport("JOY1_2B")->read() & 0x20)) /* Joy1 Button 2 */
	377	pot1 = 0x00;
151	378	break;
152		case 0x31:
153		printf("CONTROL B %02x\n",data);
154		m_VIC3_ControlB = data;
	379
	380	case 0x04:
	381	if (which)
	382	pot2 = ioport("LIGHTY")->read();
	383	else
	384	pot1 = ioport("LIGHTX")->read();
155	385	break;
	386
	387	case 0x06:
	388	if (which && (ioport("OTHER")->read() & 0x04)) /* Lightpen Signal */
	389	pot2 = 0x00;
	390	break;
	391
	392	case 0x00:
	393	case 0x07:
	394	break;
	395
156	396	default:
157		if(!space.debugger_access())
158		printf("%02x %02x\n",offset,data);
	397	logerror("Invalid Controller Setting %d\n", controller1);
159	398	break;
160	399	}
161	400
162		}
	401	switch (controller2)
	402	{
	403	case 0x10:
	404	if (which)
	405	pot4 = ioport("PADDLE4")->read();
	406	else
	407	pot3 = ioport("PADDLE3")->read();
	408	break;
163	409
164		void c65_state::PalEntryFlush(UINT8 offset)
165		{
166		m_palette->set_pen_color(offset, pal4bit(m_palred[offset]), pal4bit(m_palgreen[offset]), pal4bit(m_palblue[offset]));
167		}
	410	case 0x20:
	411	if (which)
	412	pot4 = ioport("TRACKY")->read();
	413	else
	414	pot3 = ioport("TRACKX")->read();
	415	break;
168	416
169		WRITE8_MEMBER(c65_state::PalRed_w)
170		{
171		m_palred[offset] = data;
172		PalEntryFlush(offset);
173		}
	417	case 0x30:
	418	if (which && (ioport("JOY2_2B")->read() & 0x20)) /* Joy2 Button 2 */
	419	pot4 = 0x00;
	420	break;
174	421
175		WRITE8_MEMBER(c65_state::PalGreen_w)
176		{
177		m_palblue[offset] = data;
178		PalEntryFlush(offset);
179		}
	422	case 0x40:
	423	if (which)
	424	pot4 = ioport("LIGHTY")->read();
	425	else
	426	pot3 = ioport("LIGHTX")->read();
	427	break;
180	428
181		WRITE8_MEMBER(c65_state::PalBlue_w)
182		{
183		m_palgreen[offset] = data;
184		PalEntryFlush(offset);
185		}
	429	case 0x60:
	430	if (which && (ioport("OTHER")->read() & 0x04)) /* Lightpen Signal */
	431	pot4 = 0x00;
	432	break;
186	433
187		void c65_state::DMAgicExecute(address_space &space,UINT32 address)
188		{
189		UINT8 cmd;// = space.read_byte(address++);
190		UINT16 length; //= space.read_byte(address++);
191		UINT32 src, dst;
192		static const char *const dma_cmd_string[] =
	434	case 0x00:
	435	case 0x70:
	436	break;
	437
	438	default:
	439	logerror("Invalid Controller Setting %d\n", controller1);
	440	break;
	441	}
	442
	443	if (ioport("CTRLSEL")->read() & 0x80) /* Swap */
193	444	{
194		"COPY", // 0
195		"MIX",
196		"SWAP",
197		"FILL"
198		};
199		cmd = space.read_byte(address++);
200		length = space.read_byte(address++);
201		length\|=(space.read_byte(address++)<<8);
202		src = space.read_byte(address++);
203		src\|=(space.read_byte(address++)<<8);
204		src\|=(space.read_byte(address++)<<16);
205		dst = space.read_byte(address++);
206		dst\|=(space.read_byte(address++)<<8);
207		dst\|=(space.read_byte(address++)<<16);
	445	temp = pot1; pot1 = pot3; pot3 = temp;
	446	temp = pot2; pot2 = pot4; pot4 = temp;
	447	}
208	448
209		switch(cmd & 3)
	449	switch (cia0porta & 0xc0)
210	450	{
211		case 0: // copy - TODO: untested
212		{
213		if(length != 1)
214		printf("DMAgic %s %02x -> %08x %04x (CHAIN=%s)\n",dma_cmd_string[cmd & 3],src,dst,length,cmd & 4 ? "yes" : "no");
215		UINT32 SourceIndex;
216		UINT32 DestIndex;
217		UINT16 SizeIndex;
218		SourceIndex = src & 0xfffff;
219		DestIndex = dst & 0xfffff;
220		SizeIndex = length;
221		do
222		{
223		space.write_byte(DestIndex++,space.read_byte(SourceIndex++));
224		SizeIndex--;
225		}while(SizeIndex != 0);
	451	case 0x40:
	452	return which ? pot2 : pot1;
226	453
227		return;
228		}
229		case 3: // fill
230		{
231		/* TODO: upper bits of source */
232		printf("DMAgic %s %02x -> %08x %04x (CHAIN=%s)\n",dma_cmd_string[cmd & 3],src & 0xff,dst,length,cmd & 4 ? "yes" : "no");
233		UINT8 FillValue;
234		UINT32 DestIndex;
235		UINT16 SizeIndex;
236		FillValue = src & 0xff;
237		DestIndex = dst & 0xfffff;
238		SizeIndex = length;
239		do
240		{
241		space.write_byte(DestIndex++,FillValue);
242		SizeIndex--;
243		}while(SizeIndex != 0);
244		}
245		return;
246		}
247		printf("DMAgic %s %08x %08x %04x (CHAIN=%s)\n",dma_cmd_string[cmd & 3],src,dst,length,cmd & 4 ? "yes" : "no");
248		}
	454	case 0x80:
	455	return which ? pot4 : pot3;
249	456
	457	case 0xc0:
	458	return which ? pot2 : pot1;
250	459
251		WRITE8_MEMBER(c65_state::DMAgic_w)
252		{
253		m_dmalist[offset] = data;
254		if(offset == 0)
255		DMAgicExecute(space,(m_dmalist[0])\|(m_dmalist[1]<<8)\|(m_dmalist[2]<<16));
	460	default:
	461	return 0;
	462	}
256	463	}
257	464
258		READ8_MEMBER(c65_state::~~CIASelec~~t_r)
	465	READ8_MEMBER( c65_state::sid_potx_r )
259	466	{
260		if(m_VIC3_ControlA & 1)
261		return m_cram[offset];
262		else
263		{
264		// CIA
265		}
266
267		return 0;
	467	return c64_paddle_read(m_sid_r, space, 0);
268	468	}
269	469
270		WRITE8_MEMBER(c65_state::~~CIASelec~~t_w)
	470	READ8_MEMBER( c65_state::sid_poty_r )
271	471	{
272		if(m_VIC3_ControlA & 1)
273		m_cram[offset] = data;
274		else
275		{
276		// CIA
277		}
278
	472	return c64_paddle_read(m_sid_r, space, 1);
279	473	}
280	474
281		READ8_MEMBER(c65_state::dummy_r)
	475
	476	/*************************************
	477	*
	478	* VIC III interfaces
	479	*
	480	*************************************/
	481
	482	UINT32 c65_state::screen_update_c65(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
282	483	{
	484	m_vic->video_update(bitmap, cliprect);
283	485	return 0;
284	486	}
285	487
286		static ADDRESS_MAP_START( c65_map, AS_PROGRAM, 8, c65_state )
287		AM_RANGE(0x00000, 0x07fff) AM_RAM AM_SHARE("wram") // TODO: bank
288		AM_RANGE(0x0c800, 0x0cfff) AM_ROM AM_REGION("maincpu", 0xc800)
289		AM_RANGE(0x0d000, 0x0d07f) AM_READWRITE(vic4567_dummy_r,vic4567_dummy_w) // 0x0d000, 0x0d07f VIC-4567
290		AM_RANGE(0x0d080, 0x0d081) AM_READ(dummy_r) // 0x0d080, 0x0d09f FDC
291		// 0x0d0a0, 0x0d0ff Ram Expansion Control (REC)
292		AM_RANGE(0x0d100, 0x0d1ff) AM_RAM_WRITE(PalRed_w) AM_SHARE("redpal")// 0x0d100, 0x0d1ff Red Palette
293		AM_RANGE(0x0d200, 0x0d2ff) AM_RAM_WRITE(PalGreen_w) AM_SHARE("greenpal") // 0x0d200, 0x0d2ff Green Palette
294		AM_RANGE(0x0d300, 0x0d3ff) AM_RAM_WRITE(PalBlue_w) AM_SHARE("bluepal") // 0x0d300, 0x0d3ff Blue Palette
295		// 0x0d400, 0x0d4*f Right SID
296		// 0x0d440, 0x0d4*f Left SID
297		// 0x0d600, 0x0d6** UART
298		AM_RANGE(0x0d700, 0x0d702) AM_WRITE(DMAgic_w) AM_SHARE("dmalist") // 0x0d700, 0x0d7** DMAgic
299		//AM_RANGE(0x0d703, 0x0d703) AM_READ(DMAgic_r)
300		// 0x0d800, 0x0d8** Color matrix
301		AM_RANGE(0x0dc00, 0x0dfff) AM_READWRITE(CIASelect_r,CIASelect_w) AM_SHARE("cram")
302		// 0x0dc00, 0x0dc** CIA-1
303		// 0x0dd00, 0x0dd** CIA-2
304		// 0x0de00, 0x0de** Ext I/O Select 1
305		// 0x0df00, 0x0df** Ext I/O Select 2 (RAM window?)
306		AM_RANGE(0x0e000, 0x0ffff) AM_ROM AM_REGION("maincpu",0x0e000)
307		AM_RANGE(0x10000, 0x1f7ff) AM_RAM
308		AM_RANGE(0x1f800, 0x1ffff) AM_RAM // VRAM attributes
309		AM_RANGE(0x20000, 0x3ffff) AM_ROM AM_REGION("maincpu",0)
310		ADDRESS_MAP_END
311
312
313
314		static INPUT_PORTS_START( c65 )
315		/* dummy active high structure */
316		PORT_START("SYSA")
317		PORT_DIPNAME( 0x01, 0x00, "SYSA" )
318		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
319		PORT_DIPSETTING( 0x01, DEF_STR( On ) )
320		PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
321		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
322		PORT_DIPSETTING( 0x02, DEF_STR( On ) )
323		PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
324		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
325		PORT_DIPSETTING( 0x04, DEF_STR( On ) )
326		PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
327		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
328		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
329		PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
330		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
331		PORT_DIPSETTING( 0x10, DEF_STR( On ) )
332		PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
333		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
334		PORT_DIPSETTING( 0x20, DEF_STR( On ) )
335		PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
336		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
337		PORT_DIPSETTING( 0x40, DEF_STR( On ) )
338		PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
339		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
340		PORT_DIPSETTING( 0x80, DEF_STR( On ) )
341
342		/* dummy active low structure */
343		PORT_START("DSWA")
344		PORT_DIPNAME( 0x01, 0x01, "DSWA" )
345		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
346		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
347		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
348		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
349		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
350		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
351		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
352		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
353		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
354		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
355		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
356		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
357		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
358		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
359		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
360		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
361		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
362		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
363		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
364		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
365		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
366		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
367		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
368		INPUT_PORTS_END
369
370
371		void c65_state::machine_start()
	488	READ8_MEMBER(c65_state::c65_lightpen_x_cb)
372	489	{
	490	return ioport("LIGHTX")->read() & ~0x01;
373	491	}
374	492
375		~~void~~ c65_state::machine_~~reset(~~)
	493	READ8_MEMBER(c65_state::c65_lightpen_y_cb)
376	494	{
	495	return ioport("LIGHTY")->read() & ~0x01;
377	496	}
378	497
379
380		PALETTE_INIT_MEMBER(c65_state, c65)
	498	READ8_MEMBER(c65_state::c65_lightpen_button_cb)
381	499	{
382		// ~~TODO:~~ initial ~~state?~~
	500	return ioport("OTHER")->read() & 0x04;
383	501	}
384	502
385		static ~~const gfx~~_~~layout~~ char~~layout =~~
	503	READ8_MEMBER(c65_state::c65_c64_mem_r)
386	504	{
387		8,8,
388		0x1000/8,
389		1,
390		{ RGN_FRAC(0,1) },
391		{ 0, 1, 2, 3, 4, 5, 6, 7 },
392		{ 08, 18, 28, 38, 48, 58, 68, 78 },
393		8*8
394		};
	505	return m_memory[offset];
	506	}
395	507
396		static GFXDECODE_START( c65 )
397		GFXDECODE_ENTRY( "maincpu", 0xd000, charlayout, 0, 1 ) // another identical copy is at 0x9000
398		GFXDECODE_END
399
400		INTERRUPT_GEN_MEMBER(c65_state::vic3_vblank_irq)
	508	INTERRUPT_GEN_MEMBER(c65_state::vic3_raster_irq)
401	509	{
402		//if(m_VIC2_IRQMask & 1)
403		// m_maincpu->set_input_line(M4510_IRQ_LINE,HOLD_LINE);
	510	m_vic->raster_interrupt_gen();
404	511	}
405	512
	513	/*************************************
	514	*
	515	* Machine driver
	516	*
	517	*************************************/
	518
406	519	static MACHINE_CONFIG_START( c65, c65_state )
407
408	520	/* basic machine hardware */
409		MCFG_CPU_ADD("maincpu",M4510,MAIN_CLOCK)
410		MCFG_CPU_PROGRAM_MAP(c65_map)
411		MCFG_CPU_VBLANK_INT_DRIVER("screen",c65_state,vic3_vblank_irq)
	521	MCFG_CPU_ADD("maincpu", M4510, 3500000) /* or VIC6567_CLOCK, */
	522	MCFG_CPU_PROGRAM_MAP(c65_mem)
	523	MCFG_CPU_VBLANK_INT_DRIVER("screen", c65_state, c65_frame_interrupt)
	524	MCFG_CPU_PERIODIC_INT_DRIVER(c65_state, vic3_raster_irq, VIC6567_HRETRACERATE)
412	525
	526	MCFG_MACHINE_START_OVERRIDE(c65_state, c65 )
	527
413	528	/* video hardware */
414	529	MCFG_SCREEN_ADD("screen", RASTER)
415		// MCFG_SCREEN_REFRESH_RATE(60)
416		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
417		MCFG_SCREEN_UPDATE_DRIVER(c65_state, screen_update)
418		// MCFG_SCREEN_SIZE(328, 328)
419		// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
420		MCFG_SCREEN_RAW_PARAMS(MAIN_CLOCK, 910, 0, 320, 525, 0, 240) // mods needed
421		MCFG_SCREEN_PALETTE("palette")
	530	MCFG_SCREEN_REFRESH_RATE(VIC6567_VRETRACERATE)
	531	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
	532	MCFG_SCREEN_SIZE(525 * 2, 520 * 2)
	533	MCFG_SCREEN_VISIBLE_AREA(VIC6567_STARTVISIBLECOLUMNS ,(VIC6567_STARTVISIBLECOLUMNS + VIC6567_VISIBLECOLUMNS - 1) * 2, VIC6567_STARTVISIBLELINES, VIC6567_STARTVISIBLELINES + VIC6567_VISIBLELINES - 1)
	534	MCFG_SCREEN_UPDATE_DRIVER(c65_state, screen_update_c65)
	535	MCFG_SCREEN_PALETTE("vic3:palette")
422	536
423		MCFG_GFXDECODE_ADD("gfxdecode", "palette", c65)
	537	MCFG_DEVICE_ADD("vic3", VIC3, 0)
	538	MCFG_VIC3_CPU("maincpu")
	539	MCFG_VIC3_TYPE(VIC4567_NTSC)
	540	MCFG_VIC3_LIGHTPEN_X_CB(READ8(c65_state, c65_lightpen_x_cb))
	541	MCFG_VIC3_LIGHTPEN_Y_CB(READ8(c65_state, c65_lightpen_y_cb))
	542	MCFG_VIC3_LIGHTPEN_BUTTON_CB(READ8(c65_state, c65_lightpen_button_cb))
	543	MCFG_VIC3_DMA_READ_CB(READ8(c65_state, c65_dma_read))
	544	MCFG_VIC3_DMA_READ_COLOR_CB(READ8(c65_state, c65_dma_read_color))
	545	MCFG_VIC3_INTERRUPT_CB(WRITELINE(c65_state, c65_vic_interrupt))
	546	MCFG_VIC3_PORT_CHANGED_CB(WRITE8(c65_state, c65_bankswitch_interface))
	547	MCFG_VIC3_C64_MEM_R_CB(READ8(c65_state, c65_c64_mem_r))
424	548
425		MCFG_PALETTE_ADD("palette", 0x100)
426		MCFG_PALETTE_INIT_OWNER(c65_state, c65)
	549	/* sound hardware */
	550	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
	551	MCFG_SOUND_ADD("sid_r", MOS8580, 985248)
	552	MCFG_MOS6581_POTX_CALLBACK(READ8(c65_state, sid_potx_r))
	553	MCFG_MOS6581_POTY_CALLBACK(READ8(c65_state, sid_poty_r))
	554	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
	555	MCFG_SOUND_ADD("sid_l", MOS8580, 985248)
	556	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
427	557
	558	/* quickload */
	559	MCFG_QUICKLOAD_ADD("quickload", c65_state, cbm_c65, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
	560
	561	/* cia */
	562	MCFG_DEVICE_ADD("cia_0", MOS6526, 3500000)
	563	MCFG_MOS6526_TOD(60)
	564	MCFG_MOS6526_IRQ_CALLBACK(WRITELINE(c65_state, c65_cia0_interrupt))
	565	MCFG_MOS6526_PA_INPUT_CALLBACK(READ8(c65_state, c65_cia0_port_a_r))
	566	MCFG_MOS6526_PB_INPUT_CALLBACK(READ8(c65_state, c65_cia0_port_b_r))
	567	MCFG_MOS6526_PB_OUTPUT_CALLBACK(WRITE8(c65_state, c65_cia0_port_b_w))
	568
	569	MCFG_DEVICE_ADD("cia_1", MOS6526, 3500000)
	570	MCFG_MOS6526_TOD(60)
	571	MCFG_MOS6526_IRQ_CALLBACK(WRITELINE(c65_state, c65_cia1_interrupt))
	572	MCFG_MOS6526_PA_INPUT_CALLBACK(READ8(c65_state, c65_cia1_port_a_r))
	573	MCFG_MOS6526_PA_OUTPUT_CALLBACK(WRITE8(c65_state, c65_cia1_port_a_w))
	574
	575	/* floppy from serial bus */
	576	MCFG_CBM_IEC_ADD(NULL)
	577
	578	/* internal ram */
	579	MCFG_RAM_ADD(RAM_TAG)
	580	MCFG_RAM_DEFAULT_SIZE("128K")
	581	MCFG_RAM_EXTRA_OPTIONS("640K,4224K")
	582	MACHINE_CONFIG_END
	583
	584	static MACHINE_CONFIG_DERIVED( c65pal, c65 )
	585	MCFG_SCREEN_MODIFY("screen")
	586	MCFG_SCREEN_REFRESH_RATE(VIC6569_VRETRACERATE)
	587	MCFG_SCREEN_SIZE(625 * 2, 520 * 2)
	588	MCFG_SCREEN_VISIBLE_AREA(VIC6569_STARTVISIBLECOLUMNS, (VIC6569_STARTVISIBLECOLUMNS + VIC6569_VISIBLECOLUMNS - 1) * 2, VIC6569_STARTVISIBLELINES, VIC6569_STARTVISIBLELINES + VIC6569_VISIBLELINES - 1)
	589	MCFG_SCREEN_PALETTE("vic3:palette")
	590
	591	MCFG_DEVICE_MODIFY("vic3")
	592	MCFG_VIC3_TYPE(VIC4567_PAL)
	593
428	594	/* sound hardware */
429		MCFG_SPEAKER_STANDARD_MONO("mono")
430		// MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/4)
431		// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
	595	MCFG_SOUND_REPLACE("sid_r", MOS8580, 1022727)
	596	MCFG_MOS6581_POTX_CALLBACK(READ8(c65_state, sid_potx_r))
	597	MCFG_MOS6581_POTY_CALLBACK(READ8(c65_state, sid_poty_r))
	598	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
	599	MCFG_SOUND_REPLACE("sid_l", MOS8580, 1022727)
	600	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
	601
	602	/* cia */
	603	MCFG_DEVICE_MODIFY("cia_0")
	604	MCFG_MOS6526_TOD(50)
	605
	606	MCFG_DEVICE_MODIFY("cia_1")
	607	MCFG_MOS6526_TOD(50)
432	608	MACHINE_CONFIG_END
433	609
434	610
435		/***************************************************************************
	611	/*************************************
	612	*
	613	* ROM definition(s)
	614	*
	615	*************************************/
436	616
437		Game driver(s)
438	617
439		***************************************************************************/
440
441	618	ROM_START( c65 )
442		ROM_REGION( 0x20000, "maincpu", 0 )
	619	ROM_REGION( 0x400000, "maincpu", 0 )
443	620	ROM_SYSTEM_BIOS( 0, "910111", "V0.9.910111" )
444		ROMX_LOAD( "910111.bin", 0x0000, 0x20000, CRC(c5d8d32e) SHA1(71c05f098eff29d306b0170e2c1cdeadb1a5f206), ROM_BIOS(1) )
	621	ROMX_LOAD( "910111.bin", 0x20000, 0x20000, CRC(c5d8d32e) SHA1(71c05f098eff29d306b0170e2c1cdeadb1a5f206), ROM_BIOS(1) )
445	622	ROM_SYSTEM_BIOS( 1, "910523", "V0.9.910523" )
446		ROMX_LOAD( "910523.bin", 0x0000, 0x20000, CRC(e8235dd4) SHA1(e453a8e7e5b95de65a70952e9d48012191e1b3e7), ROM_BIOS(2) )
	623	ROMX_LOAD( "910523.bin", 0x20000, 0x20000, CRC(e8235dd4) SHA1(e453a8e7e5b95de65a70952e9d48012191e1b3e7), ROM_BIOS(2) )
447	624	ROM_SYSTEM_BIOS( 2, "910626", "V0.9.910626" )
448		ROMX_LOAD( "910626.bin", 0x0000, 0x20000, CRC(12527742) SHA1(07c185b3bc58410183422f7ac13a37ddd330881b), ROM_BIOS(3) )
	625	ROMX_LOAD( "910626.bin", 0x20000, 0x20000, CRC(12527742) SHA1(07c185b3bc58410183422f7ac13a37ddd330881b), ROM_BIOS(3) )
449	626	ROM_SYSTEM_BIOS( 3, "910828", "V0.9.910828" )
450		ROMX_LOAD( "910828.bin", 0x0000, 0x20000, CRC(3ee40b06) SHA1(b63d970727a2b8da72a0a8e234f3c30a20cbcb26), ROM_BIOS(4) )
	627	ROMX_LOAD( "910828.bin", 0x20000, 0x20000, CRC(3ee40b06) SHA1(b63d970727a2b8da72a0a8e234f3c30a20cbcb26), ROM_BIOS(4) )
451	628	ROM_SYSTEM_BIOS( 4, "911001", "V0.9.911001" )
452		ROMX_LOAD( "911001.bin", 0x0000, 0x20000, CRC(0888b50f) SHA1(129b9a2611edaebaa028ac3e3f444927c8b1fc5d), ROM_BIOS(5) )
	629	ROMX_LOAD( "911001.bin", 0x20000, 0x20000, CRC(0888b50f) SHA1(129b9a2611edaebaa028ac3e3f444927c8b1fc5d), ROM_BIOS(5) )
453	630	ROM_END
454	631
455	632	ROM_START( c64dx )
456		ROM_REGION( 0x20000, "maincpu", 0 )
457		ROM_LOAD( "910429.bin", 0x0000, 0x20000, CRC(b025805c) SHA1(c3b05665684f74adbe33052a2d10170a1063ee7d) )
	633	ROM_REGION( 0x400000, "maincpu", 0 )
	634	ROM_LOAD( "910429.bin", 0x20000, 0x20000, CRC(b025805c) SHA1(c3b05665684f74adbe33052a2d10170a1063ee7d) )
458	635	ROM_END
459	636
460		DRIVER_INIT_MEMBER(c65_state,c65)
461		{
462		// m_dma.version = 2;
463		// c65_common_driver_init();
464		}
	637	/***************************************************************************
465	638
466		DRIVER_INIT_MEMBER(c65_state,c65pal)
467		{
468		// m_dma.version = 1;
469		// c65_common_driver_init();
470		// m_pal = 1;
471		}
	639	Game driver(s)
472	640
473		COMP( 1991, c65, 0, 0, c65, c65, c65_state, c65, "Commodore Business Machines", "Commodore 65 Development System (Prototype, NTSC)", GAME_NOT_WORKING )
474		COMP( 1991, c64dx, c65, 0, c65, c65, c65_state, c65pal, "Commodore Business Machines", "Commodore 64DX Development System (Prototype, PAL, German)", GAME_NOT_WORKING )
	641	***************************************************************************/
	642
	643	/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
	644
	645	COMP( 1991, c65, 0, 0, c65, c65, c65_state, c65, "Commodore Business Machines", "Commodore 65 Development System (Prototype, NTSC)", GAME_NOT_WORKING )
	646	COMP( 1991, c64dx, c65, 0, c65pal, c65ger, c65_state, c65pal, "Commodore Business Machines", "Commodore 64DX Development System (Prototype, PAL, German)", GAME_NOT_WORKING )

branches/kale/src/mess/includes/c65.h
r243827	r243828
	1	/*****************************************************************************
	2	*
	3	* includes/c65.h
	4	*
	5	****************************************************************************/
1	6
	7	#ifndef C65_H_
	8	#define C65_H_
	9
	10	#include "machine/mos6526.h"
	11	#include "bus/cbmiec/cbmiec.h"
	12	#include "imagedev/snapquik.h"
	13	#include "machine/ram.h"
	14	#include "sound/mos6581.h"
	15	#include "video/vic4567.h"
	16
	17	#define C64_MAX_ROMBANK 64 // .crt files contain multiple 'CHIPs', i.e. rom banks (of variable size) with headers. Known carts have at most 64 'CHIPs'.
	18
	19	struct C64_ROM {
	20	int addr, size, index, start;
	21	};
	22
	23	struct c64_cart_t {
	24	C64_ROM bank[C64_MAX_ROMBANK];
	25	INT8 game;
	26	INT8 exrom;
	27	UINT8 mapper;
	28	UINT8 n_banks;
	29	};
	30
	31	struct dma_t
	32	{
	33	int version;
	34	UINT8 data[4];
	35	};
	36
	37	struct fdc_t
	38	{
	39	int state;
	40
	41	UINT8 reg[0x0f];
	42
	43	UINT8 buffer[0x200];
	44	int cpu_pos;
	45	int fdc_pos;
	46
	47	UINT16 status;
	48
	49	attotime time;
	50	int head,track,sector;
	51	};
	52
	53	struct expansion_ram_t
	54	{
	55	UINT8 reg;
	56	};
	57
	58	class c65_state : public driver_device
	59	{
	60	public:
	61	c65_state(const machine_config &mconfig, device_type type, const char *tag)
	62	: driver_device(mconfig, type, tag),
	63	m_cia0(*this, "cia_0"),
	64	m_cia1(*this, "cia_1"),
	65	m_sid_r(*this, "sid_r"),
	66	m_vic(*this, "vic3"),
	67	m_iec(*this, CBM_IEC_TAG),
	68	m_colorram(*this, "colorram"),
	69	m_basic(*this, "basic"),
	70	m_chargen(*this, "chargen"),
	71	m_kernal(*this, "kernal"),
	72	m_c65_chargen(*this, "c65_chargen"),
	73	m_interface(*this, "interface"),
	74	m_roml_writable(0),
	75	m_maincpu(*this, "maincpu"),
	76	m_ram(*this, RAM_TAG) { }
	77
	78	required_device<mos6526_device> m_cia0;
	79	required_device<mos6526_device> m_cia1;
	80	required_device<mos6581_device> m_sid_r;
	81	required_device<vic3_device> m_vic;
	82	optional_device<cbm_iec_device> m_iec;
	83
	84	required_shared_ptr<UINT8> m_colorram;
	85	required_shared_ptr<UINT8> m_basic;
	86	required_shared_ptr<UINT8> m_chargen;
	87	required_shared_ptr<UINT8> m_kernal;
	88	required_shared_ptr<UINT8> m_c65_chargen;
	89	required_shared_ptr<UINT8> m_interface;
	90	int m_old_level;
	91	int m_old_data;
	92	int m_old_exrom;
	93	int m_old_game;
	94	UINT8 m_vicirq;
	95	emu_timer *m_datasette_timer;
	96	emu_timer *m_cartridge_timer;
	97	UINT8 *m_memory;
	98	int m_pal;
	99	int m_tape_on;
	100	UINT8 *m_c64_roml;
	101	UINT8 *m_c64_romh;
	102	UINT8 *m_vicaddr;
	103	UINT8 *m_c128_vicaddr;
	104	UINT8 m_game;
	105	UINT8 m_exrom;
	106	UINT8 *m_io_mirror;
	107	UINT8 m_port_data;
	108	UINT8 *m_roml;
	109	UINT8 *m_romh;
	110	int m_roml_writable;
	111	int m_ultimax;
	112	int m_cia1_on;
	113	int m_io_enabled;
	114	int m_is_sx64;
	115	UINT8 *m_io_ram_w_ptr;
	116	UINT8 *m_io_ram_r_ptr;
	117	c64_cart_t m_cart;
	118	int m_nmilevel; int m_charset_select;
	119	int m_c64mode;
	120	UINT8 m_6511_port;
	121	UINT8 m_keyline;
	122	int m_old_value;
	123	dma_t m_dma;
	124	int m_dump_dma;
	125	fdc_t m_fdc;
	126	expansion_ram_t m_expansion_ram;
	127	int m_io_on;
	128	int m_io_dc00_on;
	129	int m_cia0_irq, m_cia1_irq;
	130	DECLARE_DRIVER_INIT(c65);
	131	DECLARE_DRIVER_INIT(c65pal);
	132
	133	DECLARE_READ8_MEMBER( c64_lightpen_x_cb );
	134	DECLARE_READ8_MEMBER( c64_lightpen_y_cb );
	135	DECLARE_READ8_MEMBER( c64_lightpen_button_cb );
	136	DECLARE_READ8_MEMBER( c64_dma_read );
	137	DECLARE_READ8_MEMBER( c64_dma_read_ultimax );
	138	DECLARE_READ8_MEMBER( c64_dma_read_color );
	139	DECLARE_WRITE_LINE_MEMBER( c64_vic_interrupt );
	140	DECLARE_READ8_MEMBER( c64_rdy_cb );
	141	DECLARE_READ8_MEMBER( sid_potx_r );
	142	DECLARE_READ8_MEMBER( sid_poty_r );
	143	DECLARE_MACHINE_START(c65);
	144	UINT32 screen_update_c65(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	145	INTERRUPT_GEN_MEMBER(vic3_raster_irq);
	146	INTERRUPT_GEN_MEMBER(c65_frame_interrupt);
	147	DECLARE_READ8_MEMBER(c65_cia0_port_a_r);
	148	DECLARE_READ8_MEMBER(c65_cia0_port_b_r);
	149	DECLARE_WRITE8_MEMBER(c65_cia0_port_b_w);
	150	DECLARE_READ8_MEMBER(c65_cia1_port_a_r);
	151	DECLARE_WRITE8_MEMBER(c65_cia1_port_a_w);
	152	DECLARE_WRITE_LINE_MEMBER(c65_cia1_interrupt);
	153	void c64_legacy_driver_init();
	154	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( c64_cart );
	155	DECLARE_DEVICE_IMAGE_UNLOAD_MEMBER( c64_cart );
	156	DECLARE_WRITE_LINE_MEMBER(c65_cia0_interrupt);
	157	DECLARE_READ8_MEMBER(c65_lightpen_x_cb);
	158	DECLARE_READ8_MEMBER(c65_lightpen_y_cb);
	159	DECLARE_READ8_MEMBER(c65_lightpen_button_cb);
	160	DECLARE_READ8_MEMBER(c65_c64_mem_r);
	161	DECLARE_READ8_MEMBER(c65_dma_read);
	162	DECLARE_READ8_MEMBER(c65_dma_read_color);
	163	DECLARE_WRITE_LINE_MEMBER(c65_vic_interrupt);
	164	DECLARE_WRITE8_MEMBER(c65_bankswitch_interface);
	165	DECLARE_READ8_MEMBER( c65_read_mem );
	166	DECLARE_WRITE8_MEMBER( c65_write_mem );
	167	DECLARE_READ8_MEMBER( c65_ram_expansion_r );
	168	DECLARE_WRITE8_MEMBER( c65_ram_expansion_w );
	169	DECLARE_WRITE8_MEMBER( c65_write_io );
	170	DECLARE_WRITE8_MEMBER( c65_write_io_dc00 );
	171	DECLARE_READ8_MEMBER( c65_read_io );
	172	DECLARE_READ8_MEMBER( c65_read_io_dc00 );
	173	DECLARE_QUICKLOAD_LOAD_MEMBER( cbm_c65 );
	174
	175	int c64_paddle_read( device_t *device, address_space &space, int which );
	176	void c65_nmi( );
	177	void c65_irq( int level );
	178	void c65_dma_port_w( int offset, int value );
	179	int c65_dma_port_r( int offset );
	180	void c65_6511_port_w( int offset, int value );
	181	int c65_6511_port_r( int offset );
	182	void c65_fdc_state(void);
	183	void c65_fdc_w( int offset, int data );
	184	int c65_fdc_r( int offset );
	185	void c65_bankswitch( );
	186	void c65_colorram_write( int offset, int value );
	187	void c65_common_driver_init( );
	188
	189	required_device<cpu_device> m_maincpu;
	190	required_device<ram_device> m_ram;
	191	};
	192
	193	MACHINE_CONFIG_EXTERN( c64_cartslot );
	194
	195	#endif /* C65_H_ */

branches/kale/src/mess/machine/c65.c
r243827	r243828
	1	/***************************************************************************
	2	commodore c65 home computer
	3	peter.trauner@jk.uni-linz.ac.at
	4	documention
	5	www.funet.fi
	6	***************************************************************************/
1	7
	8	#include "emu.h"
	9
	10	#include "includes/c65.h"
	11	#include "cpu/m6502/m4510.h"
	12	#include "sound/mos6581.h"
	13	#include "machine/mos6526.h"
	14	#include "bus/cbmiec/cbmiec.h"
	15	#include "machine/ram.h"
	16	#include "video/vic4567.h"
	17	#include "imagedev/cassette.h"
	18	#include "crsshair.h"
	19	#include "formats/cbm_tap.h"
	20
	21	#define VERBOSE_LEVEL 0
	22	#define DBG_LOG( MACHINE, N, M, A ) \
	23	do { \
	24	if(VERBOSE_LEVEL >= N) \
	25	{ \
	26	if( M ) \
	27	logerror("%11.6f: %-24s", MACHINE.time().as_double(), (char*) M ); \
	28	logerror A; \
	29	} \
	30	} while (0)
	31
	32
	33
	34	/***********************************************
	35
	36	Input Reading - Common Components
	37
	38	***********************************************/
	39
	40	/* These are needed by c64, c65 and c128, each machine has also additional specific
	41	components in its INTERRUPT_GEN */
	42
	43	/* keyboard lines */
	44	UINT8 c64_keyline[10];
	45
	46	void cbm_common_init(void)
	47	{
	48	int i;
	49
	50	for (i = 0; i < ARRAY_LENGTH(c64_keyline); i++)
	51	c64_keyline[i] = 0xff;
	52	}
	53
	54	static TIMER_CALLBACK( lightpen_tick )
	55	{
	56	if (((machine.root_device().ioport("CTRLSEL")->read() & 0x07) == 0x04) \|\| ((machine.root_device().ioport("CTRLSEL")->read() & 0x07) == 0x06))
	57	{
	58	/* enable lightpen crosshair */
	59	crosshair_set_screen(machine, 0, CROSSHAIR_SCREEN_ALL);
	60	}
	61	else
	62	{
	63	/* disable lightpen crosshair */
	64	crosshair_set_screen(machine, 0, CROSSHAIR_SCREEN_NONE);
	65	}
	66	}
	67
	68	void cbm_common_interrupt( device_t *device )
	69	{
	70	int value, i;
	71	int controller1 = device->machine().root_device().ioport("CTRLSEL")->read() & 0x07;
	72	int controller2 = device->machine().root_device().ioport("CTRLSEL")->read() & 0x70;
	73	static const char *const c64ports[] = { "ROW0", "ROW1", "ROW2", "ROW3", "ROW4", "ROW5", "ROW6", "ROW7" };
	74
	75	/* Lines 0-7 : common keyboard */
	76	for (i = 0; i < 8; i++)
	77	{
	78	value = 0xff;
	79	value &= ~device->machine().root_device().ioport(c64ports[i])->read();
	80
	81	/* Shift Lock is mapped on Left Shift */
	82	if ((i == 1) && (device->machine().root_device().ioport("SPECIAL")->read() & 0x40))
	83	value &= ~0x80;
	84
	85	c64_keyline[i] = value;
	86	}
	87
	88
	89	value = 0xff;
	90	switch(controller1)
	91	{
	92	case 0x00:
	93	value &= ~device->machine().root_device().ioport("JOY1_1B")->read(); /* Joy1 Directions + Button 1 */
	94	break;
	95
	96	case 0x01:
	97	if (device->machine().root_device().ioport("OTHER")->read() & 0x40) /* Paddle2 Button */
	98	value &= ~0x08;
	99	if (device->machine().root_device().ioport("OTHER")->read() & 0x80) /* Paddle1 Button */
	100	value &= ~0x04;
	101	break;
	102
	103	case 0x02:
	104	if (device->machine().root_device().ioport("OTHER")->read() & 0x02) /* Mouse Button Left */
	105	value &= ~0x10;
	106	if (device->machine().root_device().ioport("OTHER")->read() & 0x01) /* Mouse Button Right */
	107	value &= ~0x01;
	108	break;
	109
	110	case 0x03:
	111	value &= ~(device->machine().root_device().ioport("JOY1_2B")->read() & 0x1f); /* Joy1 Directions + Button 1 */
	112	break;
	113
	114	case 0x04:
	115	/* was there any input on the lightpen? where is it mapped? */
	116	// if (device->machine().root_device().ioport("OTHER")->read() & 0x04) /* Lightpen Signal */
	117	// value &= ?? ;
	118	break;
	119
	120	case 0x07:
	121	break;
	122
	123	default:
	124	logerror("Invalid Controller 1 Setting %d\n", controller1);
	125	break;
	126	}
	127
	128	c64_keyline[8] = value;
	129
	130
	131	value = 0xff;
	132	switch(controller2)
	133	{
	134	case 0x00:
	135	value &= ~device->machine().root_device().ioport("JOY2_1B")->read(); /* Joy2 Directions + Button 1 */
	136	break;
	137
	138	case 0x10:
	139	if (device->machine().root_device().ioport("OTHER")->read() & 0x10) /* Paddle4 Button */
	140	value &= ~0x08;
	141	if (device->machine().root_device().ioport("OTHER")->read() & 0x20) /* Paddle3 Button */
	142	value &= ~0x04;
	143	break;
	144
	145	case 0x20:
	146	if (device->machine().root_device().ioport("OTHER")->read() & 0x02) /* Mouse Button Left */
	147	value &= ~0x10;
	148	if (device->machine().root_device().ioport("OTHER")->read() & 0x01) /* Mouse Button Right */
	149	value &= ~0x01;
	150	break;
	151
	152	case 0x30:
	153	value &= ~(device->machine().root_device().ioport("JOY2_2B")->read() & 0x1f); /* Joy2 Directions + Button 1 */
	154	break;
	155
	156	case 0x40:
	157	/* was there any input on the lightpen? where is it mapped? */
	158	// if (device->machine().root_device().ioport("OTHER")->read() & 0x04) /* Lightpen Signal */
	159	// value &= ?? ;
	160	break;
	161
	162	case 0x70:
	163	break;
	164
	165	default:
	166	logerror("Invalid Controller 2 Setting %d\n", controller2);
	167	break;
	168	}
	169
	170	c64_keyline[9] = value;
	171
	172	// vic2_frame_interrupt does nothing so this is not necessary
	173	// vic2_frame_interrupt (device);
	174
	175	/* check if lightpen has been chosen as input: if so, enable crosshair */
	176	device->machine().scheduler().timer_set(attotime::zero, FUNC(lightpen_tick));
	177
	178	set_led_status (device->machine(), 1, device->machine().root_device().ioport("SPECIAL")->read() & 0x40 ? 1 : 0); /* Shift Lock */
	179	set_led_status (device->machine(), 0, device->machine().root_device().ioport("CTRLSEL")->read() & 0x80 ? 1 : 0); /* Joystick Swap */
	180	}
	181
	182
	183	/***********************************************
	184
	185	CIA Common Handlers
	186
	187	***********************************************/
	188
	189	/* These are shared by c64, c65 and c128. c65 and c128 also have additional specific
	190	components (to select/read additional keyboard lines) */
	191
	192	/*
	193	* CIA 0 - Port A
	194	* bits 7-0 keyboard line select
	195	* bits 7,6: paddle select( 01 port a, 10 port b)
	196	* bit 4: joystick a fire button
	197	* bits 3,2: Paddles port a fire button
	198	* bits 3-0: joystick a direction
	199	*
	200	* CIA 0 - Port B
	201	* bits 7-0: keyboard raw values
	202	* bit 4: joystick b fire button, lightpen select
	203	* bits 3,2: paddle b fire buttons (left,right)
	204	* bits 3-0: joystick b direction
	205	*
	206	* flag cassette read input, serial request in
	207	* irq to irq connected
	208	*/
	209
	210	UINT8 cbm_common_cia0_port_a_r( device_t *device, UINT8 output_b )
	211	{
	212	UINT8 value = 0xff;
	213
	214	if (!(output_b & 0x80))
	215	{
	216	UINT8 t = 0xff;
	217	if (!(c64_keyline[7] & 0x80)) t &= ~0x80;
	218	if (!(c64_keyline[6] & 0x80)) t &= ~0x40;
	219	if (!(c64_keyline[5] & 0x80)) t &= ~0x20;
	220	if (!(c64_keyline[4] & 0x80)) t &= ~0x10;
	221	if (!(c64_keyline[3] & 0x80)) t &= ~0x08;
	222	if (!(c64_keyline[2] & 0x80)) t &= ~0x04;
	223	if (!(c64_keyline[1] & 0x80)) t &= ~0x02;
	224	if (!(c64_keyline[0] & 0x80)) t &= ~0x01;
	225	value &= t;
	226	}
	227
	228	if (!(output_b & 0x40))
	229	{
	230	UINT8 t = 0xff;
	231	if (!(c64_keyline[7] & 0x40)) t &= ~0x80;
	232	if (!(c64_keyline[6] & 0x40)) t &= ~0x40;
	233	if (!(c64_keyline[5] & 0x40)) t &= ~0x20;
	234	if (!(c64_keyline[4] & 0x40)) t &= ~0x10;
	235	if (!(c64_keyline[3] & 0x40)) t &= ~0x08;
	236	if (!(c64_keyline[2] & 0x40)) t &= ~0x04;
	237	if (!(c64_keyline[1] & 0x40)) t &= ~0x02;
	238	if (!(c64_keyline[0] & 0x40)) t &= ~0x01;
	239	value &= t;
	240	}
	241
	242	if (!(output_b & 0x20))
	243	{
	244	UINT8 t = 0xff;
	245	if (!(c64_keyline[7] & 0x20)) t &= ~0x80;
	246	if (!(c64_keyline[6] & 0x20)) t &= ~0x40;
	247	if (!(c64_keyline[5] & 0x20)) t &= ~0x20;
	248	if (!(c64_keyline[4] & 0x20)) t &= ~0x10;
	249	if (!(c64_keyline[3] & 0x20)) t &= ~0x08;
	250	if (!(c64_keyline[2] & 0x20)) t &= ~0x04;
	251	if (!(c64_keyline[1] & 0x20)) t &= ~0x02;
	252	if (!(c64_keyline[0] & 0x20)) t &= ~0x01;
	253	value &= t;
	254	}
	255
	256	if (!(output_b & 0x10))
	257	{
	258	UINT8 t = 0xff;
	259	if (!(c64_keyline[7] & 0x10)) t &= ~0x80;
	260	if (!(c64_keyline[6] & 0x10)) t &= ~0x40;
	261	if (!(c64_keyline[5] & 0x10)) t &= ~0x20;
	262	if (!(c64_keyline[4] & 0x10)) t &= ~0x10;
	263	if (!(c64_keyline[3] & 0x10)) t &= ~0x08;
	264	if (!(c64_keyline[2] & 0x10)) t &= ~0x04;
	265	if (!(c64_keyline[1] & 0x10)) t &= ~0x02;
	266	if (!(c64_keyline[0] & 0x10)) t &= ~0x01;
	267	value &= t;
	268	}
	269
	270	if (!(output_b & 0x08))
	271	{
	272	UINT8 t = 0xff;
	273	if (!(c64_keyline[7] & 0x08)) t &= ~0x80;
	274	if (!(c64_keyline[6] & 0x08)) t &= ~0x40;
	275	if (!(c64_keyline[5] & 0x08)) t &= ~0x20;
	276	if (!(c64_keyline[4] & 0x08)) t &= ~0x10;
	277	if (!(c64_keyline[3] & 0x08)) t &= ~0x08;
	278	if (!(c64_keyline[2] & 0x08)) t &= ~0x04;
	279	if (!(c64_keyline[1] & 0x08)) t &= ~0x02;
	280	if (!(c64_keyline[0] & 0x08)) t &= ~0x01;
	281	value &= t;
	282	}
	283
	284	if (!(output_b & 0x04))
	285	{
	286	UINT8 t = 0xff;
	287	if (!(c64_keyline[7] & 0x04)) t &= ~0x80;
	288	if (!(c64_keyline[6] & 0x04)) t &= ~0x40;
	289	if (!(c64_keyline[5] & 0x04)) t &= ~0x20;
	290	if (!(c64_keyline[4] & 0x04)) t &= ~0x10;
	291	if (!(c64_keyline[3] & 0x04)) t &= ~0x08;
	292	if (!(c64_keyline[2] & 0x04)) t &= ~0x04;
	293	if (!(c64_keyline[1] & 0x04)) t &= ~0x02;
	294	if (!(c64_keyline[0] & 0x04)) t &= ~0x01;
	295	value &= t;
	296	}
	297
	298	if (!(output_b & 0x02))
	299	{
	300	UINT8 t = 0xff;
	301	if (!(c64_keyline[7] & 0x02)) t &= ~0x80;
	302	if (!(c64_keyline[6] & 0x02)) t &= ~0x40;
	303	if (!(c64_keyline[5] & 0x02)) t &= ~0x20;
	304	if (!(c64_keyline[4] & 0x02)) t &= ~0x10;
	305	if (!(c64_keyline[3] & 0x02)) t &= ~0x08;
	306	if (!(c64_keyline[2] & 0x02)) t &= ~0x04;
	307	if (!(c64_keyline[1] & 0x02)) t &= ~0x02;
	308	if (!(c64_keyline[0] & 0x02)) t &= ~0x01;
	309	value &= t;
	310	}
	311
	312	if (!(output_b & 0x01))
	313	{
	314	UINT8 t = 0xff;
	315	if (!(c64_keyline[7] & 0x01)) t &= ~0x80;
	316	if (!(c64_keyline[6] & 0x01)) t &= ~0x40;
	317	if (!(c64_keyline[5] & 0x01)) t &= ~0x20;
	318	if (!(c64_keyline[4] & 0x01)) t &= ~0x10;
	319	if (!(c64_keyline[3] & 0x01)) t &= ~0x08;
	320	if (!(c64_keyline[2] & 0x01)) t &= ~0x04;
	321	if (!(c64_keyline[1] & 0x01)) t &= ~0x02;
	322	if (!(c64_keyline[0] & 0x01)) t &= ~0x01;
	323	value &= t;
	324	}
	325
	326	if ( device->machine().root_device().ioport("CTRLSEL")->read() & 0x80 )
	327	value &= c64_keyline[8];
	328	else
	329	value &= c64_keyline[9];
	330
	331	return value;
	332	}
	333
	334	UINT8 cbm_common_cia0_port_b_r( device_t *device, UINT8 output_a )
	335	{
	336	UINT8 value = 0xff;
	337
	338	if (!(output_a & 0x80)) value &= c64_keyline[7];
	339	if (!(output_a & 0x40)) value &= c64_keyline[6];
	340	if (!(output_a & 0x20)) value &= c64_keyline[5];
	341	if (!(output_a & 0x10)) value &= c64_keyline[4];
	342	if (!(output_a & 0x08)) value &= c64_keyline[3];
	343	if (!(output_a & 0x04)) value &= c64_keyline[2];
	344	if (!(output_a & 0x02)) value &= c64_keyline[1];
	345	if (!(output_a & 0x01)) value &= c64_keyline[0];
	346
	347	if ( device->machine().root_device().ioport("CTRLSEL")->read() & 0x80 )
	348	value &= c64_keyline[9];
	349	else
	350	value &= c64_keyline[8];
	351
	352	return value;
	353	}
	354
	355
	356	/***********************************************
	357
	358	CBM Cartridges
	359
	360	***********************************************/
	361
	362
	363	/* All the cartridge specific code has been moved
	364	to machine/ drivers. Once more informations
	365	surface about the cart expansions for systems
	366	in c65.c, c128.c, cbmb.c and pet.c, the shared
	367	code could be refactored to have here the
	368	common functions */
	369
	370
	371
	372	/***********************************************
	373
	374	CBM Datasette Tapes
	375
	376	***********************************************/
	377
	378	#if 0
	379	const cassette_interface cbm_cassette_interface =
	380	{
	381	cbm_cassette_formats,
	382	NULL,
	383	(cassette_state) (CASSETTE_STOPPED \| CASSETTE_MOTOR_DISABLED \| CASSETTE_SPEAKER_ENABLED),
	384	NULL
	385	};
	386	#endif
	387
	388
	389	/UINT8 c65_basic; */
	390	/UINT8 c65_kernal; */
	391	/UINT8 c65_dos; */
	392	/UINT8 c65_monitor; */
	393	/UINT8 c65_graphics; */
	394
	395
	396	void c65_state::c65_nmi( )
	397	{
	398	if (m_nmilevel != (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq) /* KEY_RESTORE */
	399	{
	400	m_maincpu->set_input_line(INPUT_LINE_NMI, (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq);
	401
	402	m_nmilevel = (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq;
	403	}
	404	}
	405
	406
	407	/***********************************************
	408
	409	CIA Interfaces
	410
	411	***********************************************/
	412
	413	/*
	414	* CIA 0 - Port A keyboard line select
	415	* CIA 0 - Port B keyboard line read
	416	*
	417	* flag cassette read input, serial request in
	418	* irq to irq connected
	419	*
	420	* see machine/cbm.c
	421	*/
	422
	423	READ8_MEMBER(c65_state::c65_cia0_port_a_r)
	424	{
	425	UINT8 cia0portb = m_cia0->pb_r(space, 0);
	426
	427	return cbm_common_cia0_port_a_r(m_cia0, cia0portb);
	428	}
	429
	430	READ8_MEMBER(c65_state::c65_cia0_port_b_r)
	431	{
	432	UINT8 value = 0xff;
	433	UINT8 cia0porta = m_cia0->pa_r(space, 0);
	434
	435	value &= cbm_common_cia0_port_b_r(m_cia0, cia0porta);
	436
	437	if (!(m_6511_port & 0x02))
	438	value &= m_keyline;
	439
	440	return value;
	441	}
	442
	443	WRITE8_MEMBER(c65_state::c65_cia0_port_b_w)
	444	{
	445	// was there lightpen support in c65 video chip?
	446	// vic3_device *vic3 = machine().device<vic3_device>("vic3");
	447	// vic3->lightpen_write(data & 0x10);
	448	}
	449
	450	void c65_state::c65_irq( int level )
	451	{
	452	if (level != m_old_level)
	453	{
	454	DBG_LOG(machine(), 3, "mos4510", ("irq %s\n", level ? "start" : "end"));
	455	m_maincpu->set_input_line(M4510_IRQ_LINE, level);
	456	m_old_level = level;
	457	}
	458	}
	459
	460	/* is this correct for c65 as well as c64? */
	461	WRITE_LINE_MEMBER(c65_state::c65_cia0_interrupt)
	462	{
	463	m_cia0_irq = state;
	464	c65_irq(state \|\| m_vicirq);
	465	}
	466
	467	/* is this correct for c65 as well as c64? */
	468	WRITE_LINE_MEMBER(c65_state::c65_vic_interrupt)
	469	{
	470	#if 1
	471	if (state != m_vicirq)
	472	{
	473	c65_irq (state \|\| m_cia0_irq);
	474	m_vicirq = state;
	475	}
	476	#endif
	477	}
	478
	479	/*
	480	* CIA 1 - Port A
	481	* bit 7 serial bus data input
	482	* bit 6 serial bus clock input
	483	* bit 5 serial bus data output
	484	* bit 4 serial bus clock output
	485	* bit 3 serial bus atn output
	486	* bit 2 rs232 data output
	487	* bits 1-0 vic-chip system memory bank select
	488	*
	489	* CIA 1 - Port B
	490	* bit 7 user rs232 data set ready
	491	* bit 6 user rs232 clear to send
	492	* bit 5 user
	493	* bit 4 user rs232 carrier detect
	494	* bit 3 user rs232 ring indicator
	495	* bit 2 user rs232 data terminal ready
	496	* bit 1 user rs232 request to send
	497	* bit 0 user rs232 received data
	498	*
	499	* flag restore key or rs232 received data input
	500	* irq to nmi connected ?
	501	*/
	502	READ8_MEMBER(c65_state::c65_cia1_port_a_r)
	503	{
	504	UINT8 value = 0xff;
	505
	506	if (!m_iec->clk_r())
	507	value &= ~0x40;
	508
	509	if (!m_iec->data_r())
	510	value &= ~0x80;
	511
	512	return value;
	513	}
	514
	515	WRITE8_MEMBER(c65_state::c65_cia1_port_a_w)
	516	{
	517	static const int helper[4] = {0xc000, 0x8000, 0x4000, 0x0000};
	518
	519	m_iec->atn_w(!BIT(data, 3));
	520	m_iec->clk_w(!BIT(data, 4));
	521	m_iec->data_w(!BIT(data, 5));
	522
	523	m_vicaddr = m_memory + helper[data & 0x03];
	524	}
	525
	526	WRITE_LINE_MEMBER(c65_state::c65_cia1_interrupt)
	527	{
	528	m_cia1_irq = state;
	529	c65_nmi();
	530	}
	531
	532	/***********************************************
	533
	534	Memory Handlers
	535
	536	***********************************************/
	537
	538	/* processor has only 1 mega address space !? */
	539	/* and system 8 megabyte */
	540	/* dma controller and bankswitch hardware ?*/
	541	READ8_MEMBER( c65_state::c65_read_mem )
	542	{
	543	UINT8 result;
	544	if (offset <= 0x0ffff)
	545	result = m_memory[offset];
	546	else
	547	result = space.read_byte(offset);
	548	return result;
	549	}
	550
	551	WRITE8_MEMBER( c65_state::c65_write_mem )
	552	{
	553	if (offset <= 0x0ffff)
	554	m_memory[offset] = data;
	555	else
	556	space.write_byte(offset, data);
	557	}
	558
	559	/* dma chip at 0xd700
	560	used:
	561	writing banknumber to offset 2
	562	writing hibyte to offset 1
	563	writing lobyte to offset 0
	564	cpu holded, dma transfer(data at address) executed, cpu activated
	565
	566	command data:
	567	0 command (0 copy, 3 fill)
	568	1,2 length
	569	3,4,5 source
	570	6,7,8 dest
	571	9 subcommand
	572	10 mod
	573
	574	version 1:
	575	seldom copy (overlapping) from 0x402002 to 0x402008
	576	(making place for new line in basic area)
	577	for whats this bit 0x400000, or is this really the address?
	578	maybe means add counter to address for access,
	579	so allowing up or down copies, and reordering copies
	580
	581	version 2:
	582	cmd 0x30 used for this
	583	*/
	584	void c65_state::c65_dma_port_w( int offset, int value )
	585	{
	586	PAIR pair, src, dst, len;
	587	UINT8 cmd, fill;
	588	int i;
	589	address_space &space = m_maincpu->space(AS_PROGRAM);
	590
	591	switch (offset & 3)
	592	{
	593	case 2:
	594	case 1:
	595	m_dma.data[offset & 3] = value;
	596	break;
	597	case 0:
	598	pair.b.h3 = 0;
	599	pair.b.h2 = m_dma.data[2];
	600	pair.b.h = m_dma.data[1];
	601	pair.b.l = m_dma.data[0]=value;
	602	cmd = c65_read_mem(space, pair.d++);
	603	len.w.h = 0;
	604	len.b.l = c65_read_mem(space, pair.d++);
	605	len.b.h = c65_read_mem(space, pair.d++);
	606	src.b.h3 = 0;
	607	fill = src.b.l = c65_read_mem(space, pair.d++);
	608	src.b.h = c65_read_mem(space, pair.d++);
	609	src.b.h2 = c65_read_mem(space, pair.d++);
	610	dst.b.h3 = 0;
	611	dst.b.l = c65_read_mem(space, pair.d++);
	612	dst.b.h = c65_read_mem(space, pair.d++);
	613	dst.b.h2 = c65_read_mem(space, pair.d++);
	614
	615	switch (cmd)
	616	{
	617	case 0:
	618	if (src.d == 0x3ffff) m_dump_dma = 1;
	619	if (m_dump_dma)
	620	DBG_LOG(space.machine(), 1,"dma copy job",
	621	("len:%.4x src:%.6x dst:%.6x sub:%.2x modrm:%.2x\n",
	622	len.w.l, src.d, dst.d, c65_read_mem(space, pair.d),
	623	c65_read_mem(space, pair.d + 1) ) );
	624	if ((m_dma.version == 1)
	625	&& ( (src.d&0x400000) \|\| (dst.d & 0x400000)))
	626	{
	627	if (!(src.d & 0x400000))
	628	{
	629	dst.d &= ~0x400000;
	630	for (i = 0; i < len.w.l; i++)
	631	c65_write_mem(space, dst.d--, c65_read_mem(space, src.d++));
	632	}
	633	else if (!(dst.d & 0x400000))
	634	{
	635	src.d &= ~0x400000;
	636	for (i = 0; i < len.w.l; i++)
	637	c65_write_mem(space, dst.d++, c65_read_mem(space, src.d--));
	638	}
	639	else
	640	{
	641	src.d &= ~0x400000;
	642	dst.d &= ~0x400000;
	643	for (i = 0; i < len.w.l; i++)
	644	c65_write_mem(space, --dst.d, c65_read_mem(space, --src.d));
	645	}
	646	}
	647	else
	648	{
	649	for (i = 0; i < len.w.l; i++)
	650	c65_write_mem(space, dst.d++, c65_read_mem(space, src.d++));
	651	}
	652	break;
	653	case 3:
	654	DBG_LOG(space.machine(), 3,"dma fill job",
	655	("len:%.4x value:%.2x dst:%.6x sub:%.2x modrm:%.2x\n",
	656	len.w.l, fill, dst.d, c65_read_mem(space, pair.d),
	657	c65_read_mem(space, pair.d + 1)));
	658	for (i = 0; i < len.w.l; i++)
	659	c65_write_mem(space, dst.d++, fill);
	660	break;
	661	case 0x30:
	662	DBG_LOG(space.machine(), 1,"dma copy down",
	663	("len:%.4x src:%.6x dst:%.6x sub:%.2x modrm:%.2x\n",
	664	len.w.l, src.d, dst.d, c65_read_mem(space, pair.d),
	665	c65_read_mem(space, pair.d + 1) ) );
	666	for (i = 0; i < len.w.l; i++)
	667	c65_write_mem(space, dst.d--,c65_read_mem(space, src.d--));
	668	break;
	669	default:
	670	DBG_LOG(space.machine(), 1,"dma job",
	671	("cmd:%.2x len:%.4x src:%.6x dst:%.6x sub:%.2x modrm:%.2x\n",
	672	cmd,len.w.l, src.d, dst.d, c65_read_mem(space, pair.d),
	673	c65_read_mem(space, pair.d + 1)));
	674	}
	675	break;
	676	default:
	677	DBG_LOG(space.machine(), 1, "dma chip write", ("%.3x %.2x\n", offset, value));
	678	break;
	679	}
	680	}
	681
	682	int c65_state::c65_dma_port_r( int offset )
	683	{
	684	/* offset 3 bit 7 in progress ? */
	685	DBG_LOG(machine(), 2, "dma chip read", ("%.3x\n", offset));
	686	return 0x7f;
	687	}
	688
	689	void c65_state::c65_6511_port_w( int offset, int value )
	690	{
	691	if (offset == 7)
	692	{
	693	m_6511_port = value;
	694	}
	695	DBG_LOG(machine(), 2, "r6511 write", ("%.2x %.2x\n", offset, value));
	696	}
	697
	698	int c65_state::c65_6511_port_r( int offset )
	699	{
	700	int data = 0xff;
	701
	702	if (offset == 7)
	703	{
	704	if (ioport("SPECIAL")->read() & 0x20)
	705	data &= ~1;
	706	}
	707	DBG_LOG(machine(), 2, "r6511 read", ("%.2x\n", offset));
	708
	709	return data;
	710	}
	711
	712	/* one docu states custom 4191 disk controller
	713	(for 2 1MB MFM disk drives, 1 internal, the other extern (optional) 1565
	714	with integrated 512 byte buffer
	715
	716	0->0 reset ?
	717
	718	0->1, 0->0, wait until 2 positiv, 1->0 ???
	719
	720	0->0, 0 not 0 means no drive ???, other system entries
	721
	722
	723	reg 0 write/read
	724	0,1 written
	725	bit 1 set
	726	bit 2 set
	727	bit 3 set
	728	bit 4 set
	729
	730
	731	reg 0 read
	732	bit 0
	733	bit 1
	734	bit 2
	735	0..2 ->$1d4
	736
	737	reg 1 write
	738	$01 written
	739	$18 written
	740	$46 written
	741	$80 written
	742	$a1 written
	743	$01 written, dec
	744	$10 written
	745
	746	reg 2 read/write?(lsr)
	747	bit 2
	748	bit 4
	749	bit 5 busy waiting until zero, then reading reg 7
	750	bit 6 operation not activ flag!? or set overflow pin used
	751	bit 7 busy flag?
	752
	753	reg 3 read/write?(rcr)
	754	bit 1
	755	bit 3
	756	bit 7 busy flag?
	757
	758	reg 4
	759	track??
	760	0 written
	761	read -> $1d2
	762	cmp #$50
	763	bcs
	764
	765
	766	reg 5
	767	sector ??
	768	1 written
	769	read -> $1d3
	770	cmp #$b bcc
	771
	772
	773	reg 6
	774	head ??
	775	0 written
	776	read -> $1d1
	777	cmp #2 bcc
	778
	779	reg 7 read
	780	#4e written
	781	12 times 0, a1 a1 a1 fe written
	782
	783	reg 8 read
	784	#ff written
	785	16 times #ff written
	786
	787	reg 9
	788	#60 written
	789
	790	might use the set overflow input
	791
	792	$21a6c 9a6c format
	793	$21c97 9c97 write operation
	794	$21ca0 9ca0 get byte?
	795	$21cab 9cab read reg 7
	796	$21caf 9caf write reg 7
	797	$21cb3
	798	*/
	799
	800	#define FDC_LOST 4
	801	#define FDC_CRC 8
	802	#define FDC_RNF 0x10
	803	#define FDC_BUSY 0x80
	804	#define FDC_IRQ 0x200
	805
	806	#define FDC_CMD_MOTOR_SPIN_UP 0x10
	807
	808	#if 0
	809	void c65_state::c65_fdc_state(void)
	810	{
	811	switch (m_fdc.state)
	812	{
	813	case FDC_CMD_MOTOR_SPIN_UP:
	814	if (machine().time() - m_fdc.time)
	815	{
	816	m_fdc.state = 0;
	817	m_fdc.status &= ~FDC_BUSY;
	818	}
	819	break;
	820	}
	821	}
	822	#endif
	823
	824	void c65_state::c65_fdc_w( int offset, int data )
	825	{
	826	DBG_LOG(machine(), 1, "fdc write", ("%.5x %.2x %.2x\n", machine().device("maincpu")->safe_pc(), offset, data));
	827	switch (offset & 0xf)
	828	{
	829	case 0:
	830	m_fdc.reg[0] = data;
	831	break;
	832	case 1:
	833	m_fdc.reg[1] = data;
	834	switch (data & 0xf9)
	835	{
	836	case 0x20: // wait for motor spin up
	837	m_fdc.status &= ~(FDC_IRQ\|FDC_LOST\|FDC_CRC\|FDC_RNF);
	838	m_fdc.status \|= FDC_BUSY;
	839	m_fdc.time = machine().time();
	840	m_fdc.state = FDC_CMD_MOTOR_SPIN_UP;
	841	break;
	842	case 0: // cancel
	843	m_fdc.status &= ~(FDC_BUSY);
	844	m_fdc.state = 0;
	845	break;
	846	case 0x80: // buffered write
	847	case 0x40: // buffered read
	848	case 0x81: // unbuffered write
	849	case 0x41: // unbuffered read
	850	case 0x30:case 0x31: // step
	851	break;
	852	}
	853	break;
	854	case 2: case 3: // read only
	855	break;
	856	case 4:
	857	m_fdc.reg[offset & 0xf] = data;
	858	m_fdc.track = data;
	859	break;
	860	case 5:
	861	m_fdc.reg[offset & 0xf] = data;
	862	m_fdc.sector = data;
	863	break;
	864	case 6:
	865	m_fdc.reg[offset & 0xf] = data;
	866	m_fdc.head = data;
	867	break;
	868	case 7:
	869	m_fdc.buffer[m_fdc.cpu_pos++] = data;
	870	break;
	871	default:
	872	m_fdc.reg[offset & 0xf] = data;
	873	break;
	874	}
	875	}
	876
	877	int c65_state::c65_fdc_r( int offset )
	878	{
	879	UINT8 data = 0;
	880	switch (offset & 0xf)
	881	{
	882	case 0:
	883	data = m_fdc.reg[0];
	884	break;
	885	case 1:
	886	data = m_fdc.reg[1];
	887	break;
	888	case 2:
	889	data = m_fdc.status;
	890	break;
	891	case 3:
	892	data = m_fdc.status >> 8;
	893	break;
	894	case 4:
	895	data = m_fdc.track;
	896	break;
	897	case 5:
	898	data = m_fdc.sector;
	899	break;
	900	case 6:
	901	data = m_fdc.head;
	902	break;
	903	case 7:
	904	data = m_fdc.buffer[m_fdc.cpu_pos++];
	905	break;
	906	default:
	907	data = m_fdc.reg[offset & 0xf];
	908	break;
	909	}
	910	DBG_LOG(machine(), 1, "fdc read", ("%.5x %.2x %.2x\n", machine().device("maincpu")->safe_pc(), offset, data));
	911	return data;
	912	}
	913
	914	/* version 1 ramcheck
	915	write 0:0
	916	read write read write 80000,90000,f0000
	917	write 0:8
	918	read write read write 80000,90000,f0000
	919
	920	version 2 ramcheck???
	921	read 0:
	922	write 0:0
	923	read 0:
	924	first read and second read bit 0x80 set --> nothing
	925	write 0:0
	926	read 0
	927	write 0:ff
	928	*/
	929
	930	READ8_MEMBER( c65_state::c65_ram_expansion_r )
	931	{
	932	UINT8 data = 0xff;
	933	if (m_ram->size() > (128 * 1024))
	934	data = m_expansion_ram.reg;
	935	return data;
	936	}
	937
	938	WRITE8_MEMBER( c65_state::c65_ram_expansion_w )
	939	{
	940	offs_t expansion_ram_begin;
	941	offs_t expansion_ram_end;
	942
	943	if (m_ram->size() > (128 * 1024))
	944	{
	945	m_expansion_ram.reg = data;
	946
	947	expansion_ram_begin = 0x80000;
	948	expansion_ram_end = 0x80000 + (m_ram->size() - 128*1024) - 1;
	949
	950	if (data == 0x00) {
	951	space.install_readwrite_bank(expansion_ram_begin, expansion_ram_end,"bank16");
	952	membank("bank16")->set_base(m_ram->pointer() + 128*1024);
	953	} else {
	954	space.nop_readwrite(expansion_ram_begin, expansion_ram_end);
	955	}
	956	}
	957	}
	958
	959	WRITE8_MEMBER( c65_state::c65_write_io )
	960	{
	961	mos6581_device *sid_0 = machine().device<mos6581_device>("sid_r");
	962	mos6581_device *sid_1 = machine().device<mos6581_device>("sid_l");
	963	vic3_device *vic3 = machine().device<vic3_device>("vic3");
	964
	965	switch (offset & 0xf00)
	966	{
	967	case 0x000:
	968	if (offset < 0x80)
	969	vic3->port_w(space, offset & 0x7f, data);
	970	else if (offset < 0xa0)
	971	c65_fdc_w(offset & 0x1f, data);
	972	else
	973	{
	974	c65_ram_expansion_w(space, offset & 0x1f, data, mem_mask);
	975	/ram expansion crtl optional /
	976	}
	977	break;
	978	case 0x100:
	979	case 0x200:
	980	case 0x300:
	981	vic3->palette_w(space, offset - 0x100, data);
	982	break;
	983	case 0x400:
	984	if (offset<0x420) /* maybe 0x20 */
	985	sid_0->write(space, offset & 0x3f, data);
	986	else if (offset<0x440)
	987	sid_1->write(space, offset & 0x3f, data);
	988	else
	989	DBG_LOG(machine(), 1, "io write", ("%.3x %.2x\n", offset, data));
	990	break;
	991	case 0x500:
	992	DBG_LOG(machine(), 1, "io write", ("%.3x %.2x\n", offset, data));
	993	break;
	994	case 0x600:
	995	c65_6511_port_w(offset & 0xff,data);
	996	break;
	997	case 0x700:
	998	c65_dma_port_w(offset & 0xff, data);
	999	break;
	1000	}
	1001	}
	1002
	1003	WRITE8_MEMBER( c65_state::c65_write_io_dc00 )
	1004	{
	1005	switch (offset & 0xf00)
	1006	{
	1007	case 0x000:
	1008	m_cia0->write(space, offset, data);
	1009	break;
	1010	case 0x100:
	1011	m_cia1->write(space, offset, data);
	1012	break;
	1013	case 0x200:
	1014	case 0x300:
	1015	DBG_LOG(machine(), 1, "io write", ("%.3x %.2x\n", offset+0xc00, data));
	1016	break;
	1017	}
	1018	}
	1019
	1020	READ8_MEMBER( c65_state::c65_read_io )
	1021	{
	1022	mos6581_device *sid_0 = machine().device<mos6581_device>("sid_r");
	1023	mos6581_device *sid_1 = machine().device<mos6581_device>("sid_l");
	1024	vic3_device *vic3 = machine().device<vic3_device>("vic3");
	1025
	1026	switch (offset & 0xf00)
	1027	{
	1028	case 0x000:
	1029	if (offset < 0x80)
	1030	return vic3->port_r(space, offset & 0x7f);
	1031	if (offset < 0xa0)
	1032	return c65_fdc_r(offset & 0x1f);
	1033	else
	1034	{
	1035	return c65_ram_expansion_r(space, offset & 0x1f, mem_mask);
	1036	/return; ram expansion crtl optional /
	1037	}
	1038	case 0x100:
	1039	case 0x200:
	1040	case 0x300:
	1041	/* read only !? */
	1042	DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset));
	1043	break;
	1044	case 0x400:
	1045	if (offset < 0x420)
	1046	return sid_0->read(space, offset & 0x3f);
	1047	if (offset < 0x440)
	1048	return sid_1->read(space, offset & 0x3f);
	1049	DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset));
	1050	break;
	1051	case 0x500:
	1052	DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset));
	1053	break;
	1054	case 0x600:
	1055	return c65_6511_port_r(offset&0xff);
	1056	case 0x700:
	1057	return c65_dma_port_r(offset&0xff);
	1058	}
	1059	return 0xff;
	1060	}
	1061
	1062	READ8_MEMBER( c65_state::c65_read_io_dc00 )
	1063	{
	1064	switch (offset & 0x300)
	1065	{
	1066	case 0x000:
	1067	return m_cia0->read(space, offset);
	1068	case 0x100:
	1069	return m_cia1->read(space, offset);
	1070	case 0x200:
	1071	case 0x300:
	1072	DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset+0xc00));
	1073	break;
	1074	}
	1075	return 0xff;
	1076	}
	1077
	1078
	1079	/*
	1080	d02f:
	1081	init a5 96 written (seems to be switch to c65 or vic3 mode)
	1082	go64 0 written
	1083	*/
	1084
	1085	/* bit 1 external sync enable (genlock)
	1086	bit 2 palette enable
	1087	bit 6 vic3 c65 character set */
	1088	WRITE8_MEMBER(c65_state::c65_bankswitch_interface)
	1089	{
	1090	DBG_LOG(machine(), 2, "c65 bankswitch", ("%.2x\n",data));
	1091
	1092	if (m_io_on)
	1093	{
	1094	if (data & 1)
	1095	{
	1096	membank("bank8")->set_base(m_colorram + 0x400);
	1097	membank("bank9")->set_base(m_colorram + 0x400);
	1098	m_maincpu->space(AS_PROGRAM).install_read_bank(0x0dc00, 0x0dfff, "bank8");
	1099	m_maincpu->space(AS_PROGRAM).install_write_bank(0x0dc00, 0x0dfff, "bank9");
	1100	}
	1101	else
	1102	{
	1103	m_maincpu->space(AS_PROGRAM).install_read_handler(0x0dc00, 0x0dfff, read8_delegate(FUNC(c65_state::c65_read_io_dc00),this));
	1104	m_maincpu->space(AS_PROGRAM).install_write_handler(0x0dc00, 0x0dfff, write8_delegate(FUNC(c65_state::c65_write_io_dc00),this));
	1105	}
	1106	}
	1107
	1108	m_io_dc00_on = !(data & 1);
	1109	#if 0
	1110	/* cartridge roms !?*/
	1111	if (data & 0x08)
	1112	membank("bank1")->set_base(m_roml);
	1113	else
	1114	membank("bank1")->set_base(m_memory + 0x8000);
	1115
	1116	if (data & 0x10)
	1117	membank("bank2")->set_base(m_basic);
	1118	else
	1119	membank("bank2")->set_base(m_memory + 0xa000);
	1120	#endif
	1121	if ((m_old_value^data) & 0x20)
	1122	{
	1123	/* bankswitching faulty when doing actual page */
	1124	if (data & 0x20)
	1125	membank("bank3")->set_base(m_basic);
	1126	else
	1127	membank("bank3")->set_base(m_memory + 0xc000);
	1128	}
	1129	m_charset_select = data & 0x40;
	1130	#if 0
	1131	/* cartridge roms !?*/
	1132	if (data & 0x80)
	1133	membank("bank8")->set_base(m_kernal);
	1134	else
	1135	membank("bank6")->set_base(m_memory + 0xe000);
	1136	#endif
	1137	m_old_value = data;
	1138	}
	1139
	1140	void c65_state::c65_bankswitch( )
	1141	{
	1142	int data, loram, hiram, charen;
	1143
	1144	data = 0x00; // machine().device<m4510_device>("maincpu")->get_port();
	1145	if (data == m_old_data)
	1146	return;
	1147
	1148	DBG_LOG(machine(), 1, "bankswitch", ("%d\n", data & 7));
	1149	loram = (data & 1) ? 1 : 0;
	1150	hiram = (data & 2) ? 1 : 0;
	1151	charen = (data & 4) ? 1 : 0;
	1152
	1153	if ((!m_game && m_exrom) \|\| (loram && hiram && !m_exrom))
	1154	membank("bank1")->set_base(m_roml);
	1155	else
	1156	membank("bank1")->set_base(m_memory + 0x8000);
	1157
	1158	if ((!m_game && m_exrom && hiram) \|\| (!m_exrom))
	1159	membank("bank2")->set_base(m_romh);
	1160	else if (loram && hiram)
	1161	membank("bank2")->set_base(m_basic);
	1162	else
	1163	membank("bank2")->set_base(m_memory + 0xa000);
	1164
	1165	if ((!m_game && m_exrom) \|\| (charen && (loram \|\| hiram)))
	1166	{
	1167	m_io_on = 1;
	1168	membank("bank6")->set_base(m_colorram);
	1169	membank("bank7")->set_base(m_colorram);
	1170
	1171	if (m_io_dc00_on)
	1172	{
	1173	m_maincpu->space(AS_PROGRAM).install_read_handler(0x0dc00, 0x0dfff, read8_delegate(FUNC(c65_state::c65_read_io_dc00),this));
	1174	m_maincpu->space(AS_PROGRAM).install_write_handler(0x0dc00, 0x0dfff, write8_delegate(FUNC(c65_state::c65_write_io_dc00),this));
	1175	}
	1176	else
	1177	{
	1178	m_maincpu->space(AS_PROGRAM).install_read_bank(0x0dc00, 0x0dfff, "bank8");
	1179	m_maincpu->space(AS_PROGRAM).install_write_bank(0x0dc00, 0x0dfff, "bank9");
	1180	membank("bank8")->set_base(m_colorram + 0x400);
	1181	membank("bank9")->set_base(m_colorram + 0x400);
	1182	}
	1183	m_maincpu->space(AS_PROGRAM).install_read_handler(0x0d000, 0x0d7ff, read8_delegate(FUNC(c65_state::c65_read_io),this));
	1184	m_maincpu->space(AS_PROGRAM).install_write_handler(0x0d000, 0x0d7ff, write8_delegate(FUNC(c65_state::c65_write_io),this));
	1185	}
	1186	else
	1187	{
	1188	m_io_on = 0;
	1189	membank("bank5")->set_base(m_memory + 0xd000);
	1190	membank("bank7")->set_base(m_memory + 0xd800);
	1191	membank("bank9")->set_base(m_memory + 0xdc00);
	1192	if (!charen && (loram \|\| hiram))
	1193	{
	1194	membank("bank4")->set_base(m_chargen);
	1195	membank("bank6")->set_base(m_chargen + 0x800);
	1196	membank("bank8")->set_base(m_chargen + 0xc00);
	1197	}
	1198	else
	1199	{
	1200	membank("bank4")->set_base(m_memory + 0xd000);
	1201	membank("bank6")->set_base(m_memory + 0xd800);
	1202	membank("bank8")->set_base(m_memory + 0xdc00);
	1203	}
	1204	m_maincpu->space(AS_PROGRAM).install_read_bank(0x0d000, 0x0d7ff, "bank4");
	1205	m_maincpu->space(AS_PROGRAM).install_write_bank(0x0d000, 0x0d7ff, "bank5");
	1206	}
	1207
	1208	if (!m_game && m_exrom)
	1209	{
	1210	membank("bank10")->set_base(m_romh);
	1211	}
	1212	else
	1213	{
	1214	if (hiram)
	1215	{
	1216	membank("bank10")->set_base(m_kernal);
	1217	}
	1218	else
	1219	{
	1220	membank("bank10")->set_base(m_memory + 0xe000);
	1221	}
	1222	}
	1223	m_old_data = data;
	1224	}
	1225
	1226	#ifdef UNUSED_FUNCTION
	1227	void c65_state::c65_colorram_write( int offset, int value )
	1228	{
	1229	m_colorram[offset & 0x7ff] = value \| 0xf0;
	1230	}
	1231	#endif
	1232
	1233	/*
	1234	* only 14 address lines
	1235	* a15 and a14 portlines
	1236	* 0x1000-0x1fff, 0x9000-0x9fff char rom
	1237	*/
	1238	READ8_MEMBER(c65_state::c65_dma_read)
	1239	{
	1240	if (!m_game && m_exrom)
	1241	{
	1242	if (offset < 0x3000)
	1243	return m_memory[offset];
	1244	return m_romh[offset & 0x1fff];
	1245	}
	1246	if ((m_vicaddr == m_memory) \|\| (m_vicaddr == m_memory + 0x8000))
	1247	{
	1248	if (offset < 0x1000)
	1249	return m_vicaddr[offset & 0x3fff];
	1250	if (offset < 0x2000) {
	1251	if (m_charset_select)
	1252	return m_chargen[offset & 0xfff];
	1253	else
	1254	return m_chargen[offset & 0xfff];
	1255	}
	1256	return m_vicaddr[offset & 0x3fff];
	1257	}
	1258	return m_vicaddr[offset & 0x3fff];
	1259	}
	1260
	1261	READ8_MEMBER(c65_state::c65_dma_read_color)
	1262	{
	1263	if (m_c64mode)
	1264	return m_colorram[offset & 0x3ff] & 0xf;
	1265	return m_colorram[offset & 0x7ff];
	1266	}
	1267
	1268	void c65_state::c65_common_driver_init( )
	1269	{
	1270	m_memory = auto_alloc_array_clear(machine(), UINT8, 0x10000);
	1271	membank("bank11")->set_base(m_memory + 0x00000);
	1272	membank("bank12")->set_base(m_memory + 0x08000);
	1273	membank("bank13")->set_base(m_memory + 0x0a000);
	1274	membank("bank14")->set_base(m_memory + 0x0c000);
	1275	membank("bank15")->set_base(m_memory + 0x0e000);
	1276
	1277	cbm_common_init();
	1278	m_keyline = 0xff;
	1279
	1280	m_pal = 0;
	1281	m_charset_select = 0;
	1282	m_6511_port = 0xff;
	1283	m_vicirq = 0;
	1284	m_old_data = -1;
	1285
	1286	/* C65 had no datasette port */
	1287	m_tape_on = 0;
	1288	m_game = 1;
	1289	m_exrom = 1;
	1290
	1291	/memset(m_memory + 0x40000, 0, 0x800000 - 0x40000); /
	1292	}
	1293
	1294	DRIVER_INIT_MEMBER(c65_state,c65)
	1295	{
	1296	m_dma.version = 2;
	1297	c65_common_driver_init();
	1298	}
	1299
	1300	DRIVER_INIT_MEMBER(c65_state,c65pal)
	1301	{
	1302	m_dma.version = 1;
	1303	c65_common_driver_init();
	1304	m_pal = 1;
	1305	}
	1306
	1307	MACHINE_START_MEMBER(c65_state,c65)
	1308	{
	1309	/* clear upper memory */
	1310	memset(m_ram->pointer() + 1281024, 0xff, m_ram->size() - 1281024);
	1311
	1312	//removed cbm_drive_0_config (SERIAL, 10);
	1313	//removed cbm_drive_1_config (SERIAL, 11);
	1314	m_vicaddr = m_memory;
	1315
	1316	m_c64mode = 0;
	1317
	1318	c65_bankswitch_interface(m_maincpu->space(AS_PROGRAM),0,0xff);
	1319	c65_bankswitch();
	1320	}
	1321
	1322
	1323	INTERRUPT_GEN_MEMBER(c65_state::c65_frame_interrupt)
	1324	{
	1325	int value;
	1326
	1327	c65_nmi();
	1328
	1329	/* common keys input ports */
	1330	cbm_common_interrupt(&device);
	1331
	1332	/* c65 specific: function keys input ports */
	1333	value = 0xff;
	1334
	1335	value &= ~ioport("FUNCT")->read();
	1336	m_keyline = value;
	1337	}

https://github.com/mamedev/mame/commit/065e9be8fd413540ba31b6ec18d7dc10b65bfd6e

199869 Revisions