MAME SVN History

199869 Revisions

r35301 Thursday 26th February, 2015 at 15:39:42 UTC by Carl
(mess) pcd_kbd: "private field 'm_data' is not used" (nw)

[/trunk]	makefile
[src/emu]	emucore.h
[src/emu/cpu]	cpu.mak
[src/emu/cpu/h8]	h8.c h8.h h83002.c h83002.h h83006.c h83006.h h83008.c h83008.h h83048.c h83048.h h83337.c h83337.h ~~h8_dma.c~~ ~~h8_dma.h~~ h8_sci.c ~~h8_watchdog.c~~ ~~h8_watchdog.h~~ h8s2245.c h8s2245.h h8s2320.c h8s2320.h h8s2357.c h8s2357.h h8s2655.c h8s2655.h
[src/emu/cpu/m6502]	m6502.c
[src/emu/cpu/m68000x]	~~m68000.c~~ ~~m68000.h~~ ~~m68000.lst~~ ~~m68kmake.py~~
[src/emu/machine]	atahle.c tmp68301.c tmp68301.h wozfdc.c
[src/emu/sound]	~~la32.c~~ ~~la32.h~~ sound.mak
[src/emu/ui]	ui.c
[src/lib/formats]	ap2_dsk.c
[src/mame/drivers]	csplayh5.c namcos23.c naomi.c niyanpai.c realbrk.c seta2.c
[src/mame/includes]	dc.h
[src/mame/video]	powervr2.c powervr2.h
[src/mess]	mess.lst mess.mak
[src/mess/drivers]	dccons.c ~~lg.c~~ ~~mt735.c~~ rmt32.c wicat.c ymmu100.c
[src/mess/machine]	nextmo.c nextmo.h pcd_kbd.c pcd_kbd.h
[src/mess/tools/floptool]	main.c
[src/mess/video]	atarist.c
[src/osd/modules/netdev]	taptun.c

trunk/makefile
r243812	r243813
24	24	#-------------------------------------------------
25	25
26	26	ifndef TARGET
27		TARGET = ume
	27	TARGET = mame
28	28	endif
29	29
30	30	ifndef SUBTARGET
r243812	r243813
182	182	# ARCHOPTS = -mcpu=G4 # optimize for G4
183	183	# note that we leave this commented by default so that you can
184	184	# configure this in your environment and never have to think about it
185		ARCHOPTS = ~~-march=native~~
	185	# ARCHOPTS =
186	186
187		NOWERROR=1
188	187
189	188
190	189	#-------------------------------------------------
r243812	r243813
222	221	#-------------------------------------------------
223	222
224	223	# uncomment next line if you are building for a 64-bit target
225		PTR64 = 1
	224	# PTR64 = 1
226	225
227	226	# uncomment next line if you are building for a big-endian target
228	227	# BIGENDIAN = 1
r243812	r243813
287	286
288	287	# specify optimization level or leave commented to use the default
289	288	# (default is OPTIMIZE = 3 normally, or OPTIMIZE = 0 with symbols)
290		OPTIMIZE = 3
	289	# OPTIMIZE = 3
291	290
292		USE_NETWORK = 1
293	291
294	292	###########################################################################
295	293	################## END USER-CONFIGURABLE OPTIONS ######################
r243812	r243813
365	363
366	364	# compiler, linker and utilities
367	365	ifneq ($(TARGETOS),emscripten)
368		AR = ar
369		CC = gcc
370		LD = g++
	366	AR = @ar
	367	CC = @gcc
	368	LD = @g++
371	369	endif
372		MD = mkdir$(EXE)
373		RM = rm -f
374		OBJDUMP = objdump
375		PYTHON = python2
	370	MD = -mkdir$(BUILD_EXE)
	371	RM = @rm -f
	372	OBJDUMP = @objdump
	373	PYTHON = @python
376	374
377	375	#-------------------------------------------------
378	376	# form the name of the executable
r243812	r243813
397	395
398	396	# 64-bit builds get a '64' suffix
399	397	ifeq ($(PTR64),1)
400		SUFFIX64 =
	398	SUFFIX64 = 64
401	399	endif
402	400
403	401	# debug builds just get the 'd' suffix and nothing more
r243812	r243813
477	475	ifdef DEBUG
478	476	DEFS += -DMAME_DEBUG
479	477	else
480		#DEFS += -DNDEBUG
	478	DEFS += -DNDEBUG
481	479	endif
482	480
483	481	# define MAME_PROFILER if we are a profiling build
r243812	r243813
567	565	endif
568	566
569	567	# add the optimization flag
570		OPT= -O$(OPTIMIZE)
571		CCOMFLAGS += $(OPT)
572		#CCOMFLAGS += -g$(SYMLEVEL) -fno-omit-frame-pointer
	568	CCOMFLAGS += -O$(OPTIMIZE)
573	569
574	570	# add the error warning flag
575	571	ifndef NOWERROR
r243812	r243813
668	664
669	665	# LDFLAGS are used generally; LDFLAGSEMULATOR are additional
670	666	# flags only used when linking the core emulator
671		LDFLAGS = -g
	667	LDFLAGS =
672	668	ifneq ($(TARGETOS),macosx)
673	669	ifneq ($(TARGETOS),os2)
674	670	ifneq ($(TARGETOS),solaris)
r243812	r243813
686	682	# strip symbols and other metadata in non-symbols and non profiling builds
687	683	ifndef SYMBOLS
688	684	ifneq ($(TARGETOS),macosx)
689		LDFLAGS +=
	685	LDFLAGS += -s
690	686	endif
691	687	endif
692	688
r243812	r243813
891	887	maketree: $(sort $(OBJDIRS))
892	888
893	889	clean: $(OSDCLEAN)
	890	@echo Deleting object tree $(OBJ)...
894	891	$(RM) -r $(OBJ)
	892	@echo Deleting $(EMULATOR)...
895	893	$(RM) $(EMULATOR)
	894	@echo Deleting $(TOOLS)...
896	895	$(RM) $(TOOLS)
897	896	@echo Deleting dependencies...
898	897	$(RM) depend_emu.mak
r243812	r243813
900	899	$(RM) depend_mess.mak
901	900	$(RM) depend_ume.mak
902	901	ifdef MAP
	902	@echo Deleting $(FULLNAME).map...
903	903	$(RM) $(FULLNAME).map
904	904	endif
905	905	ifdef SYMBOLS
r243812	r243813
972	972	#-------------------------------------------------
973	973
974	974	$(OBJ)/%.o: $(SRC)/%.c \| $(OSPREBUILD)
	975	@echo Compiling $<...
975	976	$(CC) $(CDEFS) $(CFLAGS) -c $< -o $@
976	977	ifdef CPPCHECK
977	978	@$(CPPCHECK) $(CPPCHECKFLAGS) $<
r243812	r243813
985	986	endif
986	987
987	988	$(OBJ)/%.pp: $(SRC)/%.c \| $(OSPREBUILD)
	989	@echo Compiling $<...
988	990	$(CC) $(CDEFS) $(CFLAGS) -E $< -o $@
989	991	ifdef CPPCHECK
990	992	@$(CPPCHECK) $(CPPCHECKFLAGS) $<
991	993	endif
992	994
993	995	$(OBJ)/%.s: $(SRC)/%.c \| $(OSPREBUILD)
	996	@echo Compiling $<...
994	997	$(CC) $(CDEFS) $(CFLAGS) -S $< -o $@
995	998	ifdef CPPCHECK
996	999	@$(CPPCHECK) $(CPPCHECKFLAGS) $<
r243812	r243813
1026	1029	@cp $< $@
1027	1030	else
1028	1031	$(OBJ)/%.a:
	1032	@echo Archiving $@...
1029	1033	$(RM) $@
1030	1034	$(AR) $(ARFLAGS) $@ $^
1031	1035	endif
1032	1036
1033		$(OBJ)/%.so:
1034		$(RM) $@
1035		$(AR) $(ARFLAGS) $@ $^
1036		# $(CC) -shared -o $@ $^
1037
1038	1037	ifeq ($(TARGETOS),macosx)
1039	1038	$(OBJ)/%.o: $(SRC)/%.m \| $(OSPREBUILD)
1040	1039	@echo Objective-C compiling $<...

trunk/src/emu/cpu/cpu.mak
r243812	r243813
573	573	$(CPUOBJ)/h8/h83048.o \
574	574	$(CPUOBJ)/h8/h8s2245.o $(CPUOBJ)/h8/h8s2320.o $(CPUOBJ)/h8/h8s2357.o \
575	575	$(CPUOBJ)/h8/h8s2655.o \
576		$(CPUOBJ)/h8/h8_adc.o $(CPUOBJ)/h8/h8_dma.o $(CPUOBJ)/h8/h8_port.o $(CPUOBJ)/h8/h8_intc.o \
577		$(CPUOBJ)/h8/h8_timer8.o $(CPUOBJ)/h8/h8_timer16.o $(CPUOBJ)/h8/h8_sci.o $(CPUOBJ)/h8/h8_watchdog.o
578
	576	$(CPUOBJ)/h8/h8_adc.o $(CPUOBJ)/h8/h8_port.o $(CPUOBJ)/h8/h8_intc.o \
	577	$(CPUOBJ)/h8/h8_timer8.o $(CPUOBJ)/h8/h8_timer16.o $(CPUOBJ)/h8/h8_sci.o
579	578	DASMOBJS +=
580	579	endif
581	580
r243812	r243813
609	608	$(CPUSRC)/h8/h8_port.h \
610	609	$(CPUSRC)/h8/h8_timer8.h \
611	610	$(CPUSRC)/h8/h8_timer16.h \
612		$(CPUSRC)/h8/h8_sci.h \
613		$(CPUSRC)/h8/h8_watchdog.h
	611	$(CPUSRC)/h8/h8_sci.h
614	612
615	613	$(CPUOBJ)/h8/h83002.o: $(CPUSRC)/h8/h83002.c \
616	614	$(CPUSRC)/h8/h83002.h \
r243812	r243813
620	618	$(CPUSRC)/h8/h8_adc.h \
621	619	$(CPUSRC)/h8/h8_port.h \
622	620	$(CPUSRC)/h8/h8_timer16.h \
623		$(CPUSRC)/h8/h8_sci.h \
624		$(CPUSRC)/h8/h8_watchdog.h
	621	$(CPUSRC)/h8/h8_sci.h
625	622
626	623	$(CPUOBJ)/h8/h83006.o: $(CPUSRC)/h8/h83006.c \
627	624	$(CPUSRC)/h8/h83006.h \
r243812	r243813
632	629	$(CPUSRC)/h8/h8_port.h \
633	630	$(CPUSRC)/h8/h8_timer8.h \
634	631	$(CPUSRC)/h8/h8_timer16.h \
635		$(CPUSRC)/h8/h8_sci.h \
636		$(CPUSRC)/h8/h8_watchdog.h
	632	$(CPUSRC)/h8/h8_sci.h
637	633
638	634	$(CPUOBJ)/h8/h83008.o: $(CPUSRC)/h8/h83008.c \
639	635	$(CPUSRC)/h8/h83008.h \
r243812	r243813
644	640	$(CPUSRC)/h8/h8_port.h \
645	641	$(CPUSRC)/h8/h8_timer8.h \
646	642	$(CPUSRC)/h8/h8_timer16.h \
647		$(CPUSRC)/h8/h8_sci.h \
648		$(CPUSRC)/h8/h8_watchdog.h
	643	$(CPUSRC)/h8/h8_sci.h
649	644
650	645	$(CPUOBJ)/h8/h83048.o: $(CPUSRC)/h8/h83048.c \
651	646	$(CPUSRC)/h8/h83048.h \
r243812	r243813
655	650	$(CPUSRC)/h8/h8_adc.h \
656	651	$(CPUSRC)/h8/h8_port.h \
657	652	$(CPUSRC)/h8/h8_timer16.h \
658		$(CPUSRC)/h8/h8_sci.h \
659		$(CPUSRC)/h8/h8_watchdog.h
	653	$(CPUSRC)/h8/h8_sci.h
660	654
661	655	$(CPUOBJ)/h8/h8s2245.o: $(CPUSRC)/h8/h8s2245.c \
662	656	$(CPUSRC)/h8/h8s2245.h \
r243812	r243813
668	662	$(CPUSRC)/h8/h8_port.h \
669	663	$(CPUSRC)/h8/h8_timer8.h \
670	664	$(CPUSRC)/h8/h8_timer16.h \
671		$(CPUSRC)/h8/h8_sci.h \
672		$(CPUSRC)/h8/h8_watchdog.h
	665	$(CPUSRC)/h8/h8_sci.h
673	666
674	667	$(CPUOBJ)/h8/h8s2320.o: $(CPUSRC)/h8/h8s2320.c \
675	668	$(CPUSRC)/h8/h8s2320.h \
r243812	r243813
678	671	$(CPUSRC)/h8/h8.h \
679	672	$(CPUSRC)/h8/h8_intc.h \
680	673	$(CPUSRC)/h8/h8_adc.h \
681		$(CPUSRC)/h8/h8_dma.h \
682	674	$(CPUSRC)/h8/h8_port.h \
683	675	$(CPUSRC)/h8/h8_timer8.h \
684	676	$(CPUSRC)/h8/h8_timer16.h \
685		$(CPUSRC)/h8/h8_sci.h \
686		$(CPUSRC)/h8/h8_watchdog.h
	677	$(CPUSRC)/h8/h8_sci.h
687	678
688	679	$(CPUOBJ)/h8/h8s2357.o: $(CPUSRC)/h8/h8s2357.c \
689	680	$(CPUSRC)/h8/h8s2357.h \
r243812	r243813
695	686	$(CPUSRC)/h8/h8_port.h \
696	687	$(CPUSRC)/h8/h8_timer8.h \
697	688	$(CPUSRC)/h8/h8_timer16.h \
698		$(CPUSRC)/h8/h8_sci.h \
699		$(CPUSRC)/h8/h8_watchdog.h
	689	$(CPUSRC)/h8/h8_sci.h
700	690
701	691	$(CPUOBJ)/h8/h8s2655.o: $(CPUSRC)/h8/h8s2655.c \
702	692	$(CPUSRC)/h8/h8s2655.h \
r243812	r243813
709	699	$(CPUSRC)/h8/h8_port.h \
710	700	$(CPUSRC)/h8/h8_timer8.h \
711	701	$(CPUSRC)/h8/h8_timer16.h \
712		$(CPUSRC)/h8/h8_sci.h \
713		$(CPUSRC)/h8/h8_watchdog.h
	702	$(CPUSRC)/h8/h8_sci.h
714	703
715	704	$(CPUOBJ)/h8/h8_intc.o: $(CPUSRC)/h8/h8_intc.c \
716	705	$(CPUSRC)/h8/h8_intc.h \
r243812	r243813
721	710	$(CPUSRC)/h8/h8_intc.h \
722	711	$(CPUSRC)/h8/h8.h
723	712
724		$(CPUOBJ)/h8/h8_dma.o: $(CPUSRC)/h8/h8_dma.c \
725		$(CPUSRC)/h8/h8_dma.h \
726		$(CPUSRC)/h8/h8_intc.h \
727		$(CPUSRC)/h8/h8.h
728
729	713	$(CPUOBJ)/h8/h8_port.o: $(CPUSRC)/h8/h8_port.c \
730	714	$(CPUSRC)/h8/h8_port.h \
731	715	$(CPUSRC)/h8/h8.h
732	716
733		$(CPUOBJ)/h8/h8_timer8.o: $(CPUSRC)/h8/h8_timer8.c \
734		$(CPUSRC)/h8/h8_timer8.h \
735		$(CPUSRC)/h8/h8_intc.h \
736		$(CPUSRC)/h8/h8.h
737
738	717	$(CPUOBJ)/h8/h8_timer16.o: $(CPUSRC)/h8/h8_timer16.c \
739	718	$(CPUSRC)/h8/h8_timer16.h \
740	719	$(CPUSRC)/h8/h8_intc.h \
r243812	r243813
745	724	$(CPUSRC)/h8/h8_intc.h \
746	725	$(CPUSRC)/h8/h8.h
747	726
748		$(CPUOBJ)/h8/h8_watchdog.o: $(CPUSRC)/h8/h8_watchdog.c \
749		$(CPUSRC)/h8/h8_watchdog.h \
750		$(CPUSRC)/h8/h8_intc.h \
751		$(CPUSRC)/h8/h8.h
752
753	727	# rule to generate the C files
754	728	$(CPUOBJ)/h8/h8.inc: $(CPUSRC)/h8/h8make.py $(CPUSRC)/h8/h8.lst
755	729	@echo Generating H8-300 source file...
r243812	r243813
1650	1624
1651	1625	BUILD += $(M68KMAKE)
1652	1626
1653		$(M68KMAKE): $(CPUOBJ)/m68000/m68kmake.o
	1627	$(M68KMAKE): $(CPUOBJ)/m68000/m68kmake.o $(LIBOCORE)
1654	1628	@echo Linking $@...
1655	1629	$(LD) $(LDFLAGS) $(OSDBGLDFLAGS) $^ $(BASELIBS) -o $@
1656	1630	endif
r243812	r243813
1663	1637	$(CPUSRC)/m68000/m68kcpu.h: $(CPUOBJ)/m68000/m68kops.c
1664	1638
1665	1639
1666		$(CPUOBJ)/m68000x/deco16.inc: $(CPUSRC)/m6502/m6502make.py $(CPUSRC)/m6502/odeco16.lst $(CPUSRC)/m6502/ddeco16.lst
1667		@echo Generating DECO16 source file...
1668		$(PYTHON) $(CPUSRC)/m6502/m6502make.py deco16_device $(CPUSRC)/m6502/odeco16.lst $(CPUSRC)/m6502/ddeco16.lst $@
1669	1640
1670
1671	1641	#-------------------------------------------------
1672		# Motorola 68000, alternative implementation
1673		#-------------------------------------------------
1674		ifneq ($(filter M680X0,$(CPUS)),)
1675		OBJDIRS += $(CPUOBJ)/m68000x
1676		CPUOBJS += $(CPUOBJ)/m68000x/m68000.o
1677		DASMOBJS +=
1678		endif
1679
1680		$(CPUOBJ)/m68000x/m68000.o: $(CPUSRC)/m68000x/m68000.c \
1681		$(CPUOBJ)/m68000x/m68000.inc \
1682		$(CPUSRC)/m68000x/m68000.h
1683
1684		$(CPUOBJ)/m68000x/m68000.inc: $(CPUSRC)/m68000x/m68kmake.py $(CPUSRC)/m68000x/m68000.lst
1685		@echo Generating M68000 source file...
1686		$(PYTHON) $(CPUSRC)/m68000x/m68kmake.py m68000x_device $(CPUSRC)/m68000x/m68000.lst $@
1687
1688		#-------------------------------------------------
1689	1642	# Motorola/Freescale dsp56k
1690	1643	#@src/emu/cpu/dsp56k/dsp56k.h,CPUS += DSP56156
1691	1644	#-------------------------------------------------

trunk/src/emu/cpu/h8/h8.c
r243812	r243813
295	295	return 10;
296	296	}
297	297
298		void h8_device::disassemble_am(char &buffer, int am, offs_t pc, const UINT8 oprom, UINT32 opcode, int ~~slot, int~~ offset)
	298	void h8_device::disassemble_am(char &buffer, int am, offs_t pc, const UINT8 oprom, UINT32 opcode, int offset)
299	299	{
300	300	static const char *const r8_names[16] = {
301	301	"r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h",
r243812	r243813
420	420	break;
421	421
422	422	case DASM_abs32:
423		if(slot == 3)
	423	if(offset >= 8)
424	424	buffer += sprintf(buffer, "@%08x", (oprom[offset-6] << 24) \| (oprom[offset-5] << 16) \| (oprom[offset-4] << 8) \| oprom[offset-3]);
425	425	else
426	426	buffer += sprintf(buffer, "@%08x", (oprom[offset-4] << 24) \| (oprom[offset-3] << 16) \| (oprom[offset-2] << 8) \| oprom[offset-1]);
r243812	r243813
520	520
521	521	if(e.am1 != DASM_none) {
522	522	*buffer++ = ' ';
523		disassemble_am(buffer, e.am1, pc, oprom, slot[e.slot], e.~~slot, e.~~flags & DASMFLAG_LENGTHMASK);
	523	disassemble_am(buffer, e.am1, pc, oprom, slot[e.slot], e.flags & DASMFLAG_LENGTHMASK);
524	524	}
525	525	if(e.am2 != DASM_none) {
526	526	*buffer++ = ',';
527	527	*buffer++ = ' ';
528		disassemble_am(buffer, e.am2, pc, oprom, slot[e.slot], e.~~slot, e.~~flags & DASMFLAG_LENGTHMASK);
	528	disassemble_am(buffer, e.am2, pc, oprom, slot[e.slot], e.flags & DASMFLAG_LENGTHMASK);
529	529	}
530	530	return e.flags \| DASMFLAG_SUPPORTED;
531	531	}
r243812	r243813
556	556
557	557	void h8_device::write8(UINT32 adr, UINT8 data)
558	558	{
	559	// logerror("W %06x %02x\n", adr & 0xffffff, data);
559	560	icount--;
560	561	program->write_byte(adr, data);
561	562	}
r243812	r243813
568	569
569	570	void h8_device::write16(UINT32 adr, UINT16 data)
570	571	{
	572	// logerror("W %06x %04x\n", adr & 0xfffffe, data);
571	573	icount--;
572	574	program->write_word(adr & ~1, data);
573	575	}

trunk/src/emu/cpu/h8/h8.h
r243812	r243813
220	220	static const disasm_entry disasm_entries[];
221	221
222	222	offs_t disassemble_generic(char buffer, offs_t pc, const UINT8 oprom, const UINT8 opram, UINT32 options, const disasm_entry table);
223		void disassemble_am(char &buffer, int am, offs_t pc, const UINT8 oprom, UINT32 opcode, int ~~slot, int~~ offset);
	223	void disassemble_am(char &buffer, int am, offs_t pc, const UINT8 oprom, UINT32 opcode, int offset);
224	224
225	225	virtual void do_exec_full();
226	226	virtual void do_exec_partial();

trunk/src/emu/cpu/h8/h83002.c
r243812	r243813
21	21	timer16_3(*this, "timer16:3"),
22	22	timer16_4(*this, "timer16:4"),
23	23	sci0(*this, "sci0"),
24		sci1(*this, "sci1"),
25		watchdog(*this, "watchdog")
	24	sci1(*this, "sci1")
26	25	{
27	26	}
28	27
r243812	r243813
44	43	MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:4", 2, 2, "intc", 40)
45	44	MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
46	45	MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
47		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
48	46	MACHINE_CONFIG_END
49	47
50	48	DEVICE_ADDRESS_MAP_START(map, 16, h83002_device)
r243812	r243813
89	87	AM_RANGE(0xffff98, 0xffff9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
90	88	AM_RANGE(0xffff9c, 0xffff9f) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tbr_r, tbr_w )
91	89
92		AM_RANGE(0xffffa8, 0xffffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
93		AM_RANGE(0xffffaa, 0xffffab) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
94
95	90	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
96	91	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
97	92	AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
r243812	r243813
194	189	add_event(event_time, timer16_2->internal_update(current_time));
195	190	add_event(event_time, timer16_3->internal_update(current_time));
196	191	add_event(event_time, timer16_4->internal_update(current_time));
197		add_event(event_time, watchdog->internal_update(current_time));
198	192
199	193	recompute_bcount(event_time);
200	194	}

trunk/src/emu/cpu/h8/h83002.h
r243812	r243813
46	46	#include "h8_adc.h"
47	47	#include "h8_port.h"
48	48	#include "h8_intc.h"
49		#include "h8_timer16.h"
50	49	#include "h8_sci.h"
51		#include "h8_wat~~chdog~~.h"
	50	#include "h8_timer16.h"
52	51
53	52	class h83002_device : public h8h_device {
54	53	public:
r243812	r243813
75	74	required_device<h8h_timer16_channel_device> timer16_4;
76	75	required_device<h8_sci_device> sci0;
77	76	required_device<h8_sci_device> sci1;
78		required_device<h8_watchdog_device> watchdog;
79	77
80	78	UINT8 syscr;
81	79

trunk/src/emu/cpu/h8/h83006.c
r243812	r243813
26	26	timer16_2(*this, "timer16:2"),
27	27	sci0(*this, "sci0"),
28	28	sci1(*this, "sci1"),
29		sci2(*this, "sci2"),
30		watchdog(*this, "watchdog")
	29	sci2(*this, "sci2")
31	30	{
32	31	}
33	32
r243812	r243813
52	51	timer16_2(*this, "timer16:2"),
53	52	sci0(*this, "sci0"),
54	53	sci1(*this, "sci1"),
55		sci2(*this, "sci2"),
56		watchdog(*this, "watchdog")
	54	sci2(*this, "sci2")
57	55	{
58	56	ram_start = 0xfff720;
59	57	}
r243812	r243813
86	84	MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
87	85	MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
88	86	MCFG_H8_SCI_ADD("sci2", "intc", 60, 61, 62, 63)
89		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
90	87	MACHINE_CONFIG_END
91	88
92	89	DEVICE_ADDRESS_MAP_START(map, 16, h83006_device)
r243812	r243813
133	130	AM_RANGE(0xffff84, 0xffff87) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
134	131	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
135	132	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
136		AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
137		AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
138	133	AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
139	134	AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_3", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
140	135	AM_RANGE(0xffff92, 0xffff93) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
r243812	r243813
245	240	add_event(event_time, timer16_0->internal_update(current_time));
246	241	add_event(event_time, timer16_1->internal_update(current_time));
247	242	add_event(event_time, timer16_2->internal_update(current_time));
248		add_event(event_time, watchdog->internal_update(current_time));
249	243
250	244	recompute_bcount(event_time);
251	245	}

trunk/src/emu/cpu/h8/h83006.h
r243812	r243813
46	46	#include "h8_adc.h"
47	47	#include "h8_port.h"
48	48	#include "h8_intc.h"
	49	#include "h8_sci.h"
49	50	#include "h8_timer8.h"
50	51	#include "h8_timer16.h"
51		#include "h8_sci.h"
52		#include "h8_watchdog.h"
53	52
54	53	class h83006_device : public h8h_device {
55	54	public:
r243812	r243813
80	79	required_device<h8_sci_device> sci0;
81	80	required_device<h8_sci_device> sci1;
82	81	required_device<h8_sci_device> sci2;
83		required_device<h8_watchdog_device> watchdog;
84	82
85	83	UINT8 syscr;
86	84	UINT32 ram_start;

trunk/src/emu/cpu/h8/h83008.c
r243812	r243813
23	23	timer16_1(*this, "timer16:1"),
24	24	timer16_2(*this, "timer16:2"),
25	25	sci0(*this, "sci0"),
26		sci1(*this, "sci1"),
27		watchdog(*this, "watchdog")
	26	sci1(*this, "sci1")
28	27	{
29	28	}
30	29
r243812	r243813
48	47	MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:2", 2, 2, "intc", 32)
49	48	MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
50	49	MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
51		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
52	50	MACHINE_CONFIG_END
53	51
54	52	DEVICE_ADDRESS_MAP_START(map, 16, h83008_device)
r243812	r243813
95	93	AM_RANGE(0xffff84, 0xffff87) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
96	94	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
97	95	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
98		AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
99		AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
100	96	AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
101	97	AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_3", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
102	98	AM_RANGE(0xffff92, 0xffff93) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
r243812	r243813
199	195	add_event(event_time, timer16_0->internal_update(current_time));
200	196	add_event(event_time, timer16_1->internal_update(current_time));
201	197	add_event(event_time, timer16_2->internal_update(current_time));
202		add_event(event_time, watchdog->internal_update(current_time));
203	198
204	199	recompute_bcount(event_time);
205	200	}

trunk/src/emu/cpu/h8/h83008.h
r243812	r243813
46	46	#include "h8_adc.h"
47	47	#include "h8_port.h"
48	48	#include "h8_intc.h"
	49	#include "h8_sci.h"
49	50	#include "h8_timer8.h"
50	51	#include "h8_timer16.h"
51		#include "h8_sci.h"
52		#include "h8_watchdog.h"
53	52
54	53	class h83008_device : public h8h_device {
55	54	public:
r243812	r243813
79	78	required_device<h8h_timer16_channel_device> timer16_2;
80	79	required_device<h8_sci_device> sci0;
81	80	required_device<h8_sci_device> sci1;
82		required_device<h8_watchdog_device> watchdog;
83	81
84	82	UINT8 syscr;
85	83

trunk/src/emu/cpu/h8/h83048.c
r243812	r243813
28	28	timer16_3(*this, "timer16:3"),
29	29	timer16_4(*this, "timer16:4"),
30	30	sci0(*this, "sci0"),
31		sci1(*this, "sci1"),
32		watchdog(*this, "watchdog")
	31	sci1(*this, "sci1")
33	32	{
34	33	}
35	34
r243812	r243813
55	54	timer16_3(*this, "timer16:3"),
56	55	timer16_4(*this, "timer16:4"),
57	56	sci0(*this, "sci0"),
58		sci1(*this, "sci1"),
59		watchdog(*this, "watchdog")
	57	sci1(*this, "sci1")
60	58	{
61	59	ram_start = 0xffef10;
62	60	}
r243812	r243813
101	99	MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:4", 2, 2, "intc", 40)
102	100	MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
103	101	MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
104		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
105	102	MACHINE_CONFIG_END
106	103
107	104	DEVICE_ADDRESS_MAP_START(map, 16, h83048_device)
r243812	r243813
146	143	AM_RANGE(0xffff98, 0xffff9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
147	144	AM_RANGE(0xffff9c, 0xffff9f) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tbr_r, tbr_w )
148	145
149		AM_RANGE(0xffffa8, 0xffffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
150		AM_RANGE(0xffffaa, 0xffffab) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
151
152	146	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
153	147	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
154	148	AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
r243812	r243813
262	256	add_event(event_time, timer16_2->internal_update(current_time));
263	257	add_event(event_time, timer16_3->internal_update(current_time));
264	258	add_event(event_time, timer16_4->internal_update(current_time));
265		add_event(event_time, watchdog->internal_update(current_time));
266	259
267	260	recompute_bcount(event_time);
268	261	}

trunk/src/emu/cpu/h8/h83048.h
r243812	r243813
54	54	#include "h8_adc.h"
55	55	#include "h8_port.h"
56	56	#include "h8_intc.h"
57		#include "h8_timer16.h"
58	57	#include "h8_sci.h"
59		#include "h8_wat~~chdog~~.h"
	58	#include "h8_timer16.h"
60	59
61	60	class h83048_device : public h8h_device {
62	61	public:
r243812	r243813
88	87	required_device<h8h_timer16_channel_device> timer16_4;
89	88	required_device<h8_sci_device> sci0;
90	89	required_device<h8_sci_device> sci1;
91		required_device<h8_watchdog_device> watchdog;
92	90
93	91	UINT32 ram_start;
94	92	UINT8 syscr;

trunk/src/emu/cpu/h8/h83337.c
r243812	r243813
24	24	timer16(*this, "timer16"),
25	25	timer16_0(*this, "timer16:0"),
26	26	sci0(*this, "sci0"),
27		sci1(*this, "sci1"),
28		watchdog(*this, "watchdog")
	27	sci1(*this, "sci1")
29	28	{
30	29	}
31	30
r243812	r243813
47	46	timer16(*this, "timer16"),
48	47	timer16_0(*this, "timer16:0"),
49	48	sci0(*this, "sci0"),
50		sci1(*this, "sci1"),
51		watchdog(*this, "watchdog")
	49	sci1(*this, "sci1")
52	50	{
53	51	ram_start = 0xf780;
54	52	}
r243812	r243813
83	81	MCFG_H8_TIMER16_CHANNEL_ADD("timer16:0", 4, 0, "intc", 32)
84	82	MCFG_H8_SCI_ADD("sci0", "intc", 27, 28, 29, 30)
85	83	MCFG_H8_SCI_ADD("sci1", "intc", 31, 32, 33, 34)
86		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 36, h8_watchdog_device::B)
87	84	MACHINE_CONFIG_END
88	85
89	86	DEVICE_ADDRESS_MAP_START(map, 16, h83337_device)
r243812	r243813
103	100	// AM_RANGE(0xff96, 0xff97) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tocr_r, tocr_w, 0x00ff)
104	101	AM_RANGE(0xff98, 0xff9f) AM_DEVREAD( "timer16:0", h8_timer16_channel_device, tgr_r )
105	102
106		AM_RANGE(0xffa8, 0xffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
107	103	AM_RANGE(0xffac, 0xffad) AM_DEVREADWRITE8("port1", h8_port_device, pcr_r, pcr_w, 0xff00)
108	104	AM_RANGE(0xffac, 0xffad) AM_DEVREADWRITE8("port2", h8_port_device, pcr_r, pcr_w, 0x00ff)
109	105	AM_RANGE(0xffae, 0xffaf) AM_DEVREADWRITE8("port3", h8_port_device, pcr_r, pcr_w, 0xff00)
r243812	r243813
190	186	add_event(event_time, timer8_0->internal_update(current_time));
191	187	add_event(event_time, timer8_1->internal_update(current_time));
192	188	add_event(event_time, timer16_0->internal_update(current_time));
193		add_event(event_time, watchdog->internal_update(current_time));
194	189
195	190	recompute_bcount(event_time);
196	191	}

trunk/src/emu/cpu/h8/h83337.h
r243812	r243813
50	50	#define __H83337_H__
51	51
52	52	#include "h8.h"
53		#include "h8_intc.h"
54	53	#include "h8_adc.h"
55	54	#include "h8_port.h"
	55	#include "h8_intc.h"
56	56	#include "h8_timer8.h"
57	57	#include "h8_timer16.h"
58	58	#include "h8_sci.h"
59		#include "h8_watchdog.h"
60	59
61	60	class h83337_device : public h8_device {
62	61	public:
r243812	r243813
90	89	required_device<h8_timer16_channel_device> timer16_0;
91	90	required_device<h8_sci_device> sci0;
92	91	required_device<h8_sci_device> sci1;
93		required_device<h8_watchdog_device> watchdog;
94	92
95	93	UINT8 syscr;
96	94	UINT32 ram_start;

trunk/src/emu/cpu/h8/h8_dma.c
r243812	r243813
1		#include "emu.h"
2		#include "h8_dma.h"
3
4		const device_type H8_DMA = &device_creator<h8_dma_device>;
5		const device_type H8_DMA_CHANNEL = &device_creator<h8_dma_channel_device>;
6
7		h8_dma_device::h8_dma_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
8		device_t(mconfig, H8_DMA, "H8 DMA controller", tag, owner, clock, "h8_dma", __FILE__)
9		{
10		}
11
12		void h8_dma_device::device_start()
13		{
14		}
15
16		void h8_dma_device::device_reset()
17		{
18		dmabcr = 0x0000;
19		dmawer = 0x00;
20		}
21
22		READ8_MEMBER(h8_dma_device::dmawer_r)
23		{
24		logerror("%s: dmawer_r\n", tag());
25		return dmawer;
26		}
27
28		WRITE8_MEMBER(h8_dma_device::dmawer_w)
29		{
30		dmawer = data;
31		logerror("%s: dmawer_w %02x\n", tag(), data);
32		}
33
34		READ8_MEMBER(h8_dma_device::dmatcr_r)
35		{
36		logerror("%s: dmatcr_r\n", tag());
37		return dmatcr;
38		}
39
40		WRITE8_MEMBER(h8_dma_device::dmatcr_w)
41		{
42		dmatcr = data;
43		logerror("%s: dmatcr_w %02x\n", tag(), data);
44		}
45
46		READ16_MEMBER(h8_dma_device::dmabcr_r)
47		{
48		logerror("%s: dmabcr_r\n", tag());
49		return dmabcr;
50		}
51
52		WRITE16_MEMBER(h8_dma_device::dmabcr_w)
53		{
54		COMBINE_DATA(&dmabcr);
55		logerror("%s: dmabcr_w %04x\n", tag(), dmabcr);
56		if(dmabcr & 0x40)
57		dmabcr &= ~0x40;
58		}
59
60
61
62		h8_dma_channel_device::h8_dma_channel_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
63		device_t(mconfig, H8_DMA_CHANNEL, "H8 DMA channel", tag, owner, clock, "h8_dma_channel", __FILE__)
64		{
65		}
66
67		void h8_dma_channel_device::set_info(const char *intc, int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf)
68		{
69		}
70
71		void h8_dma_channel_device::device_start()
72		{
73		}
74
75		void h8_dma_channel_device::device_reset()
76		{
77		}
78
79		READ16_MEMBER(h8_dma_channel_device::marah_r)
80		{
81		logerror("%s: marah_r\n", tag());
82		return 0x0000;
83		}
84
85		WRITE16_MEMBER(h8_dma_channel_device::marah_w)
86		{
87		logerror("%s: marah_w %04x\n", tag(), data);
88		}
89
90		READ16_MEMBER(h8_dma_channel_device::maral_r)
91		{
92		logerror("%s: maral_r\n", tag());
93		return 0x0000;
94		}
95
96		WRITE16_MEMBER(h8_dma_channel_device::maral_w)
97		{
98		logerror("%s: maral_w %04x\n", tag(), data);
99		}
100
101		READ16_MEMBER(h8_dma_channel_device::ioara_r)
102		{
103		logerror("%s: iorar_r\n", tag());
104		return 0x0000;
105		}
106
107		WRITE16_MEMBER(h8_dma_channel_device::ioara_w)
108		{
109		logerror("%s: ioara_w %04x\n", tag(), data);
110		}
111
112		READ16_MEMBER(h8_dma_channel_device::etcra_r)
113		{
114		logerror("%s: etcra_r\n", tag());
115		return 0x0000;
116		}
117
118		WRITE16_MEMBER(h8_dma_channel_device::etcra_w)
119		{
120		logerror("%s: etcra_w %04x\n", tag(), data);
121		}
122
123		READ16_MEMBER(h8_dma_channel_device::marbh_r)
124		{
125		logerror("%s: marbh_r\n", tag());
126		return 0x0000;
127		}
128
129		WRITE16_MEMBER(h8_dma_channel_device::marbh_w)
130		{
131		logerror("%s: marbh_w %04x\n", tag(), data);
132		}
133
134		READ16_MEMBER(h8_dma_channel_device::marbl_r)
135		{
136		logerror("%s: marbl_r\n", tag());
137		return 0x0000;
138		}
139
140		WRITE16_MEMBER(h8_dma_channel_device::marbl_w)
141		{
142		logerror("%s: marbl_w %04x\n", tag(), data);
143		}
144
145		READ16_MEMBER(h8_dma_channel_device::ioarb_r)
146		{
147		logerror("%s: ioarb_r\n", tag());
148		return 0x0000;
149		}
150
151		WRITE16_MEMBER(h8_dma_channel_device::ioarb_w)
152		{
153		logerror("%s: ioarb_w %04x\n", tag(), data);
154		}
155
156		READ16_MEMBER(h8_dma_channel_device::etcrb_r)
157		{
158		logerror("%s: etcrb_r\n", tag());
159		return 0x0000;
160		}
161
162		WRITE16_MEMBER(h8_dma_channel_device::etcrb_w)
163		{
164		logerror("%s: etcrb_w %04x\n", tag(), data);
165		}
166
167		READ8_MEMBER(h8_dma_channel_device::dmacr_r)
168		{
169		logerror("%s: dmacr_r %d\n", tag(), offset);
170		return 0x00;
171		}
172
173		WRITE8_MEMBER(h8_dma_channel_device::dmacr_w)
174		{
175		logerror("%s: dmacr_w %d, %02x\n", tag(), offset, data);
176		}

trunk/src/emu/cpu/h8/h8_dma.h
r243812	r243813
1		/***************************************************************************
2
3		h8_dma.h
4
5		H8 DMA
6
7		****************************************************************************
8
9		Copyright Olivier Galibert
10		All rights reserved.
11
12		Redistribution and use in source and binary forms, with or without
13		modification, are permitted provided that the following conditions are
14		met:
15
16		* Redistributions of source code must retain the above copyright
17		notice, this list of conditions and the following disclaimer.
18		* Redistributions in binary form must reproduce the above copyright
19		notice, this list of conditions and the following disclaimer in
20		the documentation and/or other materials provided with the
21		distribution.
22		* Neither the name 'MAME' nor the names of its contributors may be
23		used to endorse or promote products derived from this software
24		without specific prior written permission.
25
26		THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR
27		IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28		WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29		DISCLAIMED. IN NO EVENT SHALL OLIVIER GALIBERT BE LIABLE FOR ANY DIRECT,
30		INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31		(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32		SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33		HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34		STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
35		IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36		POSSIBILITY OF SUCH DAMAGE.
37
38		***************************************************************************/
39
40		#ifndef __H8_DMA_H__
41		#define __H8_DMA_H__
42
43		#include "h8.h"
44		#include "h8_intc.h"
45
46		#define MCFG_H8_DMA_ADD( _tag ) \
47		MCFG_DEVICE_ADD( _tag, H8_DMA, 0 )
48
49		#define MCFG_H8_DMA_CHANNEL_ADD( _tag, intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf ) \
50		MCFG_DEVICE_ADD( _tag, H8_DMA_CHANNEL, 0 ) \
51		downcast<h8_dma_channel_device *>(device)->set_info(intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf);
52
53		class h8_dma_device : public device_t {
54		public:
55		h8_dma_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
56
57		DECLARE_READ8_MEMBER(dmawer_r);
58		DECLARE_WRITE8_MEMBER(dmawer_w);
59		DECLARE_READ8_MEMBER(dmatcr_r);
60		DECLARE_WRITE8_MEMBER(dmatcr_w);
61		DECLARE_READ16_MEMBER(dmabcr_r);
62		DECLARE_WRITE16_MEMBER(dmabcr_w);
63
64		protected:
65		virtual void device_start();
66		virtual void device_reset();
67
68		UINT8 dmawer, dmatcr;
69		UINT16 dmabcr;
70		};
71
72		class h8_dma_channel_device : public device_t {
73		public:
74		enum {
75		NONE = -1,
76		DREQ_LEVEL = -2,
77		DREQ_EDGE = -3
78		};
79
80		enum {
81		MODE8_MEM_MEM,
82		MODE8_DACK_MEM,
83		MODE8_MEM_DACK,
84		MODE16_MEM_MEM,
85		MODE16_DACK_MEM,
86		MODE16_MEM_DACK
87		};
88
89		h8_dma_channel_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
90
91		void set_info(const char *intc, int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf);
92
93		DECLARE_READ16_MEMBER(marah_r);
94		DECLARE_WRITE16_MEMBER(marah_w);
95		DECLARE_READ16_MEMBER(maral_r);
96		DECLARE_WRITE16_MEMBER(maral_w);
97		DECLARE_READ16_MEMBER(ioara_r);
98		DECLARE_WRITE16_MEMBER(ioara_w);
99		DECLARE_READ16_MEMBER(etcra_r);
100		DECLARE_WRITE16_MEMBER(etcra_w);
101		DECLARE_READ16_MEMBER(marbh_r);
102		DECLARE_WRITE16_MEMBER(marbh_w);
103		DECLARE_READ16_MEMBER(marbl_r);
104		DECLARE_WRITE16_MEMBER(marbl_w);
105		DECLARE_READ16_MEMBER(ioarb_r);
106		DECLARE_WRITE16_MEMBER(ioarb_w);
107		DECLARE_READ16_MEMBER(etcrb_r);
108		DECLARE_WRITE16_MEMBER(etcrb_w);
109		DECLARE_READ8_MEMBER(dmacr_r);
110		DECLARE_WRITE8_MEMBER(dmacr_w);
111
112		protected:
113		virtual void device_start();
114		virtual void device_reset();
115		};
116
117		extern const device_type H8_DMA;
118		extern const device_type H8_DMA_CHANNEL;
119
120		#endif

trunk/src/emu/cpu/h8/h8_sci.c
r243812	r243813
14	14	external_clock_period = attotime::never;
15	15	}
16	16
17		void h8_sci_device::set_info(const char *_intc_tag, int eri, int rxi, int txi, int tei)
	17	void h8_sci_device::set_info(const char *_intc_tag,int eri, int rxi, int txi, int tei)
18	18	{
19	19	intc_tag = _intc_tag;
20	20	eri_int = eri;

trunk/src/emu/cpu/h8/h8_watchdog.c
r243812	r243813
1		#include "emu.h"
2		#include "h8_watchdog.h"
3
4		const device_type H8_WATCHDOG = &device_creator<h8_watchdog_device>;
5
6		const int h8_watchdog_device::div_bh[8] = { 1, 6, 7, 9, 11, 13, 15, 17 };
7		const int h8_watchdog_device::div_s [8] = { 1, 5, 6, 7, 8, 9, 11, 12 };
8
9		h8_watchdog_device::h8_watchdog_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
10		device_t(mconfig, H8_WATCHDOG, "H8 watchdog", tag, owner, clock, "h8_watchdog", __FILE__),
11		cpu(*this, DEVICE_SELF_OWNER)
12		{
13		}
14
15		void h8_watchdog_device::set_info(const char *_intc_tag, int _irq, int _type)
16		{
17		intc_tag = _intc_tag;
18		irq = _irq;
19		type = _type;
20		}
21
22
23		UINT64 h8_watchdog_device::internal_update(UINT64 current_time)
24		{
25		tcnt_update(current_time);
26		if(tcsr & TCSR_TME) {
27		int shift = (type == S ? div_s : div_bh)[tcsr & TCSR_CKS];
28		UINT64 spos = tcnt_cycle_base >> shift;
29		return (spos + 0x100 - tcnt) << shift;
30
31		} else
32		return 0;
33		}
34
35		void h8_watchdog_device::tcnt_update(UINT64 cur_time)
36		{
37		if(tcsr & TCSR_TME) {
38		int shift = (type == S ? div_s : div_bh)[tcsr & TCSR_CKS];
39		if(!cur_time)
40		cur_time = cpu->total_cycles();
41		UINT64 spos = tcnt_cycle_base >> shift;
42		UINT64 epos = cur_time >> shift;
43
44		int next_tcnt = tcnt + int(epos - spos);
45		tcnt = next_tcnt;
46		tcnt_cycle_base = cur_time;
47		// logerror("%s: %10lld tcnt %02x -> %03x shift=%d\n", tag(), cur_time, tcnt, next_tcnt, shift);
48
49		if(next_tcnt >= 0x100) {
50		if(tcsr & TCSR_WT) {
51		logerror("%s: watchdog triggered\n", tag());
52		if(type == B && !(tcsr & TCSR_NMI))
53		intc->internal_interrupt(3);
54		else
55		cpu->reset();
56
57		} else {
58		if(!(tcsr & TCSR_OVF)) {
59		tcsr \|= TCSR_OVF;
60		intc->internal_interrupt(irq);
61		}
62		}
63		}
64		} else
65		tcnt = 0;
66
67		}
68
69		READ16_MEMBER(h8_watchdog_device::wd_r)
70		{
71		tcnt_update();
72
73		logerror("%s: read\n", tag());
74		return 0;
75		}
76
77		WRITE16_MEMBER(h8_watchdog_device::wd_w)
78		{
79		if(mem_mask != 0xffff)
80		return;
81
82		if((data & 0xff00) == 0xa500) {
83		tcnt_update();
84		tcsr = data & 0xff;
85		tcsr \|= type == B ? 0x10 : 0x18;
86		cpu->internal_update();
87		}
88
89		if((data & 0xff00) == 0x5a00) {
90		if(tcsr & TCSR_TME) {
91		tcnt = data & 0xff;
92		tcnt_cycle_base = cpu->total_cycles();
93		// logerror("%s: %10lld tcnt = %02x\n", tag(), tcnt_cycle_base, tcnt);
94		}
95		cpu->internal_update();
96		}
97		}
98
99		READ16_MEMBER(h8_watchdog_device::rst_r)
100		{
101		logerror("%s: rst_r\n", tag());
102		return 0;
103		}
104
105		WRITE16_MEMBER(h8_watchdog_device::rst_w)
106		{
107		if((data & 0xff00) == 0xa500)
108		logerror("%s: wowf_w %02x\n", tag(), data & 0xff);
109		if((data & 0xff00) == 0x5a00)
110		logerror("%s: rtse_w %02x\n", tag(), data & 0xff);
111		}
112
113		void h8_watchdog_device::device_start()
114		{
115		intc = siblingdevice<h8_intc_device>(intc_tag);
116		}
117
118		void h8_watchdog_device::device_reset()
119		{
120		tcnt = 0x00;
121		tcnt_cycle_base = cpu->total_cycles();
122		tcsr = type == B ? 0x10 : 0x18;
123		rst = type == S ? 0x1f : 0x3f;
124		}

trunk/src/emu/cpu/h8/h8_watchdog.h
r243812	r243813
1		/***************************************************************************
2
3		h8_watchdog.h
4
5		H8 watchdog/timer
6
7		****************************************************************************
8
9		Copyright Olivier Galibert
10		All rights reserved.
11
12		Redistribution and use in source and binary forms, with or without
13		modification, are permitted provided that the following conditions are
14		met:
15
16		* Redistributions of source code must retain the above copyright
17		notice, this list of conditions and the following disclaimer.
18		* Redistributions in binary form must reproduce the above copyright
19		notice, this list of conditions and the following disclaimer in
20		the documentation and/or other materials provided with the
21		distribution.
22		* Neither the name 'MAME' nor the names of its contributors may be
23		used to endorse or promote products derived from this software
24		without specific prior written permission.
25
26		THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR
27		IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28		WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29		DISCLAIMED. IN NO EVENT SHALL OLIVIER GALIBERT BE LIABLE FOR ANY DIRECT,
30		INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31		(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32		SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33		HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34		STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
35		IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36		POSSIBILITY OF SUCH DAMAGE.
37
38		***************************************************************************/
39
40		#ifndef __H8_WATCHDOG_H__
41		#define __H8_WATCHDOG_H__
42
43		#include "h8.h"
44		#include "h8_intc.h"
45
46		#define MCFG_H8_WATCHDOG_ADD( _tag, intc, irq, type ) \
47		MCFG_DEVICE_ADD( _tag, H8_WATCHDOG, 0 ) \
48		downcast<h8_watchdog_device *>(device)->set_info(intc, irq, type);
49
50		class h8_watchdog_device : public device_t {
51		public:
52		enum { B, H, S };
53
54		h8_watchdog_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
55
56		void set_info(const char *intc, int irq, int type);
57
58		UINT64 internal_update(UINT64 current_time);
59
60		DECLARE_READ16_MEMBER(wd_r);
61		DECLARE_WRITE16_MEMBER(wd_w);
62		DECLARE_READ16_MEMBER(rst_r);
63		DECLARE_WRITE16_MEMBER(rst_w);
64
65		protected:
66		virtual void device_start();
67		virtual void device_reset();
68
69		private:
70		enum {
71		TCSR_CKS = 0x07,
72		TCSR_NMI = 0x08,
73		TCSR_TME = 0x20,
74		TCSR_WT = 0x40,
75		TCSR_OVF = 0x80,
76
77		RST_RSTS = 0x20,
78		RST_RSTE = 0x40,
79		RST_RSTEO = 0x40,
80		RST_WRST = 0x80
81		};
82
83		static const int div_bh[8];
84		static const int div_s[8];
85
86		required_device<h8_device> cpu;
87		h8_intc_device *intc;
88		const char *intc_tag;
89		int irq;
90		int type;
91		UINT8 tcnt, tcsr, rst;
92		UINT64 tcnt_cycle_base;
93
94		void tcnt_update(UINT64 current_time = 0);
95		};
96
97		extern const device_type H8_WATCHDOG;
98
99		#endif

trunk/src/emu/cpu/h8/h8s2245.c
r243812	r243813
31	31	timer16_2(*this, "timer16:2"),
32	32	sci0(*this, "sci0"),
33	33	sci1(*this, "sci1"),
34		sci2(*this, "sci2"),
35		watchdog(*this, "watchdog")
	34	sci2(*this, "sci2")
36	35	{
37	36	}
38	37
r243812	r243813
60	59	timer16_2(*this, "timer16:2"),
61	60	sci0(*this, "sci0"),
62	61	sci1(*this, "sci1"),
63		sci2(*this, "sci2"),
64		watchdog(*this, "watchdog")
	62	sci2(*this, "sci2")
65	63	{
66	64	ram_start = 0xffec00;
67	65	}
r243812	r243813
133	131	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
134	132	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
135	133	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
136		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
137	134	MACHINE_CONFIG_END
138	135
139	136	DEVICE_ADDRESS_MAP_START(map, 16, h8s2245_device)
r243812	r243813
220	217	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
221	218	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
222	219	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
223		AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
224		AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
225	220	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
226	221	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
227	222	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
r243812	r243813
245	240	AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
246	241	AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
247	242	AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
	243
248	244	ADDRESS_MAP_END
249	245
250	246	machine_config_constructor h8s2245_device::device_mconfig_additions() const
r243812	r243813
321	317	add_event(event_time, timer16_0->internal_update(current_time));
322	318	add_event(event_time, timer16_1->internal_update(current_time));
323	319	add_event(event_time, timer16_2->internal_update(current_time));
324		add_event(event_time, watchdog->internal_update(current_time));
325	320
326	321	recompute_bcount(event_time);
327	322	}

trunk/src/emu/cpu/h8/h8s2245.h
r243812	r243813
50	50	#define __H8S2245_H__
51	51
52	52	#include "h8s2000.h"
53		#include "h8_intc.h"
54	53	#include "h8_adc.h"
55	54	#include "h8_port.h"
	55	#include "h8_intc.h"
	56	#include "h8_sci.h"
56	57	#include "h8_timer8.h"
57	58	#include "h8_timer16.h"
58		#include "h8_sci.h"
59		#include "h8_watchdog.h"
60	59
61	60	class h8s2245_device : public h8s2000_device {
62	61	public:
r243812	r243813
90	89	required_device<h8_sci_device> sci0;
91	90	required_device<h8_sci_device> sci1;
92	91	required_device<h8_sci_device> sci2;
93		required_device<h8_watchdog_device> watchdog;
94	92
95	93	UINT32 ram_start;
96	94	UINT8 syscr;

trunk/src/emu/cpu/h8/h8s2320.c
r243812	r243813
16	16	h8s2000_device(mconfig, type, name, tag, owner, clock, shortname, source, address_map_delegate(FUNC(h8s2320_device::map), this)),
17	17	intc(*this, "intc"),
18	18	adc(*this, "adc"),
19		dma(*this, "dma"),
20		dma0(*this, "dma:0"),
21		dma1(*this, "dma:1"),
22	19	port1(*this, "port1"),
23	20	port2(*this, "port2"),
24	21	port3(*this, "port3"),
r243812	r243813
43	40	timer16_5(*this, "timer16:5"),
44	41	sci0(*this, "sci0"),
45	42	sci1(*this, "sci1"),
46		sci2(*this, "sci2"),
47		watchdog(*this, "watchdog")
	43	sci2(*this, "sci2")
48	44	{
49	45	}
50	46
r243812	r243813
52	48	h8s2000_device(mconfig, H8S2320, "H8S/2320", tag, owner, clock, "h8s2320", __FILE__, address_map_delegate(FUNC(h8s2320_device::map), this)),
53	49	intc(*this, "intc"),
54	50	adc(*this, "adc"),
55		dma(*this, "dma"),
56		dma0(*this, "dma:0"),
57		dma1(*this, "dma:1"),
58	51	port1(*this, "port1"),
59	52	port2(*this, "port2"),
60	53	port3(*this, "port3"),
r243812	r243813
79	72	timer16_5(*this, "timer16:5"),
80	73	sci0(*this, "sci0"),
81	74	sci1(*this, "sci1"),
82		sci2(*this, "sci2"),
83		watchdog(*this, "watchdog")
	75	sci2(*this, "sci2")
84	76	{
85	77	ram_start = 0xffec00;
86	78	}
r243812	r243813
136	128	static MACHINE_CONFIG_FRAGMENT(h8s2320)
137	129	MCFG_H8S_INTC_ADD("intc")
138	130	MCFG_H8_ADC_2320_ADD("adc", "intc", 28)
139		MCFG_H8_DMA_ADD("dma")
140		MCFG_H8_DMA_CHANNEL_ADD("dma:0", "intc", 72, h8_dma_channel_device::NONE, 28, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 82, 81, 86, 85, 32, 40, 44, 48, 56, 60, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
141		MCFG_H8_DMA_CHANNEL_ADD("dma:1", "intc", 74, h8_dma_channel_device::NONE, 28, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 82, 81, 86, 85, 32, 40, 44, 48, 56, 60, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
142	131	MCFG_H8_PORT_ADD("port1", h8_device::PORT_1, 0x00, 0x00)
143	132	MCFG_H8_PORT_ADD("port2", h8_device::PORT_2, 0x00, 0x00)
144	133	MCFG_H8_PORT_ADD("port3", h8_device::PORT_3, 0xc0, 0xc0)
r243812	r243813
214	203	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
215	204	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
216	205	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
217		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
218	206	MACHINE_CONFIG_END
219	207
220	208	DEVICE_ADDRESS_MAP_START(map, 16, h8s2320_device)
221	209	AM_RANGE(ram_start, 0xfffbff) AM_RAM
222	210
223		AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
224		AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
225		AM_RANGE(0xfffe82, 0xfffe83) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
226		AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
227		AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
228		AM_RANGE(0xfffe86, 0xfffe87) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tcnt_r, tcnt_w )
229		AM_RANGE(0xfffe88, 0xfffe8f) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tgr_r, tgr_w )
230		AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
231		AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
232		AM_RANGE(0xfffe92, 0xfffe93) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
233		AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
234		AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
235		AM_RANGE(0xfffe96, 0xfffe97) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tcnt_r, tcnt_w )
236		AM_RANGE(0xfffe98, 0xfffe9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
237		AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
238		AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
239		AM_RANGE(0xfffea2, 0xfffea3) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
240		AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
241		AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
242		AM_RANGE(0xfffea6, 0xfffea7) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tcnt_r, tcnt_w )
243		AM_RANGE(0xfffea8, 0xfffeab) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tgr_r, tgr_w )
244		AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port1", h8_port_device, ddr_w, 0xff00)
245		AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port2", h8_port_device, ddr_w, 0x00ff)
246		AM_RANGE(0xfffeb2, 0xfffeb3) AM_DEVWRITE8( "port3", h8_port_device, ddr_w, 0xff00)
247		AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port5", h8_port_device, ddr_w, 0xff00)
248		AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port6", h8_port_device, ddr_w, 0x00ff)
249		AM_RANGE(0xfffeb8, 0xfffeb9) AM_DEVWRITE8( "porta", h8_port_device, ddr_w, 0x00ff)
250		AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portb", h8_port_device, ddr_w, 0xff00)
251		AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portc", h8_port_device, ddr_w, 0x00ff)
252		AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "portd", h8_port_device, ddr_w, 0xff00)
253		AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "porte", h8_port_device, ddr_w, 0x00ff)
254		AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portf", h8_port_device, ddr_w, 0xff00)
255		AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portg", h8_port_device, ddr_w, 0x00ff)
256		AM_RANGE(0xfffec0, 0xfffec1) AM_DEVREADWRITE8("intc", h8s_intc_device, icr_r, icr_w, 0xffff)
257		AM_RANGE(0xfffec2, 0xfffec3) AM_DEVREADWRITE8("intc", h8s_intc_device, icrc_r, icrc_w, 0xff00)
258		AM_RANGE(0xfffec4, 0xfffecd) AM_DEVREADWRITE8("intc", h8s_intc_device, ipr_r, ipr_w, 0xffff)
259		AM_RANGE(0xfffece, 0xfffecf) AM_DEVREADWRITE8("intc", h8s_intc_device, iprk_r, iprk_w, 0xff00)
	211	AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	212	AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	213	AM_RANGE(0xfffe82, 0xfffe83) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
	214	AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	215	AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	216	AM_RANGE(0xfffe86, 0xfffe87) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tcnt_r, tcnt_w )
	217	AM_RANGE(0xfffe88, 0xfffe8f) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tgr_r, tgr_w )
	218	AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	219	AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	220	AM_RANGE(0xfffe92, 0xfffe93) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
	221	AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	222	AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	223	AM_RANGE(0xfffe96, 0xfffe97) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tcnt_r, tcnt_w )
	224	AM_RANGE(0xfffe98, 0xfffe9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
	225	AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	226	AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	227	AM_RANGE(0xfffea2, 0xfffea3) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
	228	AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	229	AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	230	AM_RANGE(0xfffea6, 0xfffea7) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tcnt_r, tcnt_w )
	231	AM_RANGE(0xfffea8, 0xfffeab) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tgr_r, tgr_w )
	232	AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port1", h8_port_device, ddr_w, 0xff00)
	233	AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port2", h8_port_device, ddr_w, 0x00ff)
	234	AM_RANGE(0xfffeb2, 0xfffeb3) AM_DEVWRITE8( "port3", h8_port_device, ddr_w, 0xff00)
	235	AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port5", h8_port_device, ddr_w, 0xff00)
	236	AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port6", h8_port_device, ddr_w, 0x00ff)
	237	AM_RANGE(0xfffeb8, 0xfffeb9) AM_DEVWRITE8( "porta", h8_port_device, ddr_w, 0x00ff)
	238	AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portb", h8_port_device, ddr_w, 0xff00)
	239	AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portc", h8_port_device, ddr_w, 0x00ff)
	240	AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "portd", h8_port_device, ddr_w, 0xff00)
	241	AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "porte", h8_port_device, ddr_w, 0x00ff)
	242	AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portf", h8_port_device, ddr_w, 0xff00)
	243	AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portg", h8_port_device, ddr_w, 0x00ff)
	244	AM_RANGE(0xfffec0, 0xfffec1) AM_DEVREADWRITE8("intc", h8s_intc_device, icr_r, icr_w, 0xffff)
	245	AM_RANGE(0xfffec2, 0xfffec3) AM_DEVREADWRITE8("intc", h8s_intc_device, icrc_r, icrc_w, 0xff00)
	246	AM_RANGE(0xfffec4, 0xfffecd) AM_DEVREADWRITE8("intc", h8s_intc_device, ipr_r, ipr_w, 0xffff)
	247	AM_RANGE(0xfffece, 0xfffecf) AM_DEVREADWRITE8("intc", h8s_intc_device, iprk_r, iprk_w, 0xff00)
	248	AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrh_r, iscrh_w, 0xff00)
	249	AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrl_r, iscrl_w, 0x00ff)
	250	AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, ier_r, ier_w, 0xff00)
	251	AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, isr_r, isr_w, 0x00ff)
	252	AM_RANGE(0xffff38, 0xffff39) AM_READWRITE8( syscr_r, syscr_w, 0x00ff)
260	253
261		AM_RANGE(0xfffee0, 0xfffee1) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marah_r, marah_w )
262		AM_RANGE(0xfffee2, 0xfffee3) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, maral_r, maral_w )
263		AM_RANGE(0xfffee4, 0xfffee5) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, ioara_r, ioara_w )
264		AM_RANGE(0xfffee6, 0xfffee7) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, etcra_r, etcra_w )
265		AM_RANGE(0xfffee8, 0xfffee9) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marbh_r, marbh_w )
266		AM_RANGE(0xfffeea, 0xfffeeb) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marbl_r, marbl_w )
267		AM_RANGE(0xfffeec, 0xfffeed) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, ioarb_r, ioarb_w )
268		AM_RANGE(0xfffeee, 0xfffeef) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, etcrb_r, etcrb_w )
269		AM_RANGE(0xfffef0, 0xfffef1) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marah_r, marah_w )
270		AM_RANGE(0xfffef2, 0xfffef3) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, maral_r, maral_w )
271		AM_RANGE(0xfffef4, 0xfffef5) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, ioara_r, ioara_w )
272		AM_RANGE(0xfffef6, 0xfffef7) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, etcra_r, etcra_w )
273		AM_RANGE(0xfffef8, 0xfffef9) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marbh_r, marbh_w )
274		AM_RANGE(0xfffefa, 0xfffefb) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marbl_r, marbl_w )
275		AM_RANGE(0xfffefc, 0xfffefd) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, ioarb_r, ioarb_w )
276		AM_RANGE(0xfffefe, 0xfffeff) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, etcrb_r, etcrb_w )
277		AM_RANGE(0xffff00, 0xffff01) AM_DEVREADWRITE8("dma", h8_dma_device, dmawer_r, dmawer_w, 0xff00)
278		AM_RANGE(0xffff00, 0xffff01) AM_DEVREADWRITE8("dma", h8_dma_device, dmatcr_r, dmatcr_w, 0x00ff)
279		AM_RANGE(0xffff02, 0xffff03) AM_DEVREADWRITE8("dma:0", h8_dma_channel_device, dmacr_r, dmacr_w, 0xffff)
280		AM_RANGE(0xffff04, 0xffff05) AM_DEVREADWRITE8("dma:1", h8_dma_channel_device, dmacr_r, dmacr_w, 0xffff)
281		AM_RANGE(0xffff06, 0xffff07) AM_DEVREADWRITE( "dma", h8_dma_device, dmabcr_r, dmabcr_w )
282		AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrh_r, iscrh_w, 0xff00)
283		AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrl_r, iscrl_w, 0x00ff)
284		AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, ier_r, ier_w, 0xff00)
285		AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, isr_r, isr_w, 0x00ff)
286		AM_RANGE(0xffff38, 0xffff39) AM_READWRITE8( syscr_r, syscr_w, 0x00ff)
	254	AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port1", h8_port_device, port_r, 0xff00)
	255	AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port2", h8_port_device, port_r, 0x00ff)
	256	AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port3", h8_port_device, port_r, 0xff00)
	257	AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port4", h8_port_device, port_r, 0x00ff)
	258	AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port5", h8_port_device, port_r, 0xff00)
	259	AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port6", h8_port_device, port_r, 0x00ff)
	260	AM_RANGE(0xffff58, 0xffff59) AM_DEVREAD8( "porta", h8_port_device, port_r, 0x00ff)
	261	AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portb", h8_port_device, port_r, 0xff00)
	262	AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portc", h8_port_device, port_r, 0x00ff)
	263	AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "portd", h8_port_device, port_r, 0xff00)
	264	AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "porte", h8_port_device, port_r, 0x00ff)
	265	AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portf", h8_port_device, port_r, 0xff00)
	266	AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portg", h8_port_device, port_r, 0x00ff)
	267	AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port1", h8_port_device, dr_r, dr_w, 0xff00)
	268	AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port2", h8_port_device, dr_r, dr_w, 0x00ff)
	269	AM_RANGE(0xffff62, 0xffff63) AM_DEVREADWRITE8("port3", h8_port_device, dr_r, dr_w, 0xff00)
	270	AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port5", h8_port_device, dr_r, dr_w, 0xff00)
	271	AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port6", h8_port_device, dr_r, dr_w, 0x00ff)
	272	AM_RANGE(0xffff68, 0xffff69) AM_DEVREADWRITE8("porta", h8_port_device, dr_r, dr_w, 0x00ff)
	273	AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portb", h8_port_device, dr_r, dr_w, 0xff00)
	274	AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portc", h8_port_device, dr_r, dr_w, 0x00ff)
	275	AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("portd", h8_port_device, dr_r, dr_w, 0xff00)
	276	AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("porte", h8_port_device, dr_r, dr_w, 0x00ff)
	277	AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portf", h8_port_device, dr_r, dr_w, 0xff00)
	278	AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portg", h8_port_device, dr_r, dr_w, 0x00ff)
	279	AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("porta", h8_port_device, pcr_r, pcr_w, 0xff00)
	280	AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("portb", h8_port_device, pcr_r, pcr_w, 0x00ff)
	281	AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portc", h8_port_device, pcr_r, pcr_w, 0xff00)
	282	AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portd", h8_port_device, pcr_r, pcr_w, 0x00ff)
	283	AM_RANGE(0xffff74, 0xffff75) AM_DEVREADWRITE8("porte", h8_port_device, pcr_r, pcr_w, 0xff00)
	284	AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("port3", h8_port_device, odr_r, odr_w, 0xff00)
	285	AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("porta", h8_port_device, odr_r, odr_w, 0x00ff)
	286	AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
	287	AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
	288	AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
	289	AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, tdr_r, tdr_w, 0x00ff)
	290	AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREADWRITE8("sci0", h8_sci_device, ssr_r, ssr_w, 0xff00)
	291	AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREAD8( "sci0", h8_sci_device, rdr_r, 0x00ff)
	292	AM_RANGE(0xffff7e, 0xffff7f) AM_DEVREADWRITE8("sci0", h8_sci_device, scmr_r, scmr_w, 0xff00)
	293	AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, smr_r, smr_w, 0xff00)
	294	AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, brr_r, brr_w, 0x00ff)
	295	AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, scr_r, scr_w, 0xff00)
	296	AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, tdr_r, tdr_w, 0x00ff)
	297	AM_RANGE(0xffff84, 0xffff85) AM_DEVREADWRITE8("sci1", h8_sci_device, ssr_r, ssr_w, 0xff00)
	298	AM_RANGE(0xffff84, 0xffff85) AM_DEVREAD8( "sci1", h8_sci_device, rdr_r, 0x00ff)
	299	AM_RANGE(0xffff86, 0xffff87) AM_DEVREADWRITE8("sci1", h8_sci_device, scmr_r, scmr_w, 0xff00)
	300	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, smr_r, smr_w, 0xff00)
	301	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, brr_r, brr_w, 0x00ff)
	302	AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, scr_r, scr_w, 0xff00)
	303	AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, tdr_r, tdr_w, 0x00ff)
	304	AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE8("sci2", h8_sci_device, ssr_r, ssr_w, 0xff00)
	305	AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREAD8( "sci2", h8_sci_device, rdr_r, 0x00ff)
	306	AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE8("sci2", h8_sci_device, scmr_r, scmr_w, 0xff00)
	307	AM_RANGE(0xffff90, 0xffff97) AM_DEVREAD8( "adc", h8_adc_device, addr8_r, 0xffff)
	308	AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcsr_r, adcsr_w, 0xff00)
	309	AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcr_r, adcr_w, 0x00ff)
287	310
288		AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port1", h8_port_device, port_r, 0xff00)
289		AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port2", h8_port_device, port_r, 0x00ff)
290		AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port3", h8_port_device, port_r, 0xff00)
291		AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port4", h8_port_device, port_r, 0x00ff)
292		AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port5", h8_port_device, port_r, 0xff00)
293		AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port6", h8_port_device, port_r, 0x00ff)
294		AM_RANGE(0xffff58, 0xffff59) AM_DEVREAD8( "porta", h8_port_device, port_r, 0x00ff)
295		AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portb", h8_port_device, port_r, 0xff00)
296		AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portc", h8_port_device, port_r, 0x00ff)
297		AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "portd", h8_port_device, port_r, 0xff00)
298		AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "porte", h8_port_device, port_r, 0x00ff)
299		AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portf", h8_port_device, port_r, 0xff00)
300		AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portg", h8_port_device, port_r, 0x00ff)
301		AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port1", h8_port_device, dr_r, dr_w, 0xff00)
302		AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port2", h8_port_device, dr_r, dr_w, 0x00ff)
303		AM_RANGE(0xffff62, 0xffff63) AM_DEVREADWRITE8("port3", h8_port_device, dr_r, dr_w, 0xff00)
304		AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port5", h8_port_device, dr_r, dr_w, 0xff00)
305		AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port6", h8_port_device, dr_r, dr_w, 0x00ff)
306		AM_RANGE(0xffff68, 0xffff69) AM_DEVREADWRITE8("porta", h8_port_device, dr_r, dr_w, 0x00ff)
307		AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portb", h8_port_device, dr_r, dr_w, 0xff00)
308		AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portc", h8_port_device, dr_r, dr_w, 0x00ff)
309		AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("portd", h8_port_device, dr_r, dr_w, 0xff00)
310		AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("porte", h8_port_device, dr_r, dr_w, 0x00ff)
311		AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portf", h8_port_device, dr_r, dr_w, 0xff00)
312		AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portg", h8_port_device, dr_r, dr_w, 0x00ff)
313		AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("porta", h8_port_device, pcr_r, pcr_w, 0xff00)
314		AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("portb", h8_port_device, pcr_r, pcr_w, 0x00ff)
315		AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portc", h8_port_device, pcr_r, pcr_w, 0xff00)
316		AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portd", h8_port_device, pcr_r, pcr_w, 0x00ff)
317		AM_RANGE(0xffff74, 0xffff75) AM_DEVREADWRITE8("porte", h8_port_device, pcr_r, pcr_w, 0xff00)
318		AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("port3", h8_port_device, odr_r, odr_w, 0xff00)
319		AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("porta", h8_port_device, odr_r, odr_w, 0x00ff)
320		AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
321		AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
322		AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
323		AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, tdr_r, tdr_w, 0x00ff)
324		AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREADWRITE8("sci0", h8_sci_device, ssr_r, ssr_w, 0xff00)
325		AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREAD8( "sci0", h8_sci_device, rdr_r, 0x00ff)
326		AM_RANGE(0xffff7e, 0xffff7f) AM_DEVREADWRITE8("sci0", h8_sci_device, scmr_r, scmr_w, 0xff00)
327		AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, smr_r, smr_w, 0xff00)
328		AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, brr_r, brr_w, 0x00ff)
329		AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, scr_r, scr_w, 0xff00)
330		AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, tdr_r, tdr_w, 0x00ff)
331		AM_RANGE(0xffff84, 0xffff85) AM_DEVREADWRITE8("sci1", h8_sci_device, ssr_r, ssr_w, 0xff00)
332		AM_RANGE(0xffff84, 0xffff85) AM_DEVREAD8( "sci1", h8_sci_device, rdr_r, 0x00ff)
333		AM_RANGE(0xffff86, 0xffff87) AM_DEVREADWRITE8("sci1", h8_sci_device, scmr_r, scmr_w, 0xff00)
334		AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, smr_r, smr_w, 0xff00)
335		AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, brr_r, brr_w, 0x00ff)
336		AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, scr_r, scr_w, 0xff00)
337		AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, tdr_r, tdr_w, 0x00ff)
338		AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE8("sci2", h8_sci_device, ssr_r, ssr_w, 0xff00)
339		AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREAD8( "sci2", h8_sci_device, rdr_r, 0x00ff)
340		AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE8("sci2", h8_sci_device, scmr_r, scmr_w, 0xff00)
341		AM_RANGE(0xffff90, 0xffff97) AM_DEVREAD8( "adc", h8_adc_device, addr8_r, 0xffff)
342		AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcsr_r, adcsr_w, 0xff00)
343		AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcr_r, adcr_w, 0x00ff)
	311	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
	312	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
	313	AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
	314	AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcsr_r, tcsr_w, 0x00ff)
	315	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcor_r, tcor_w, 0xff00)
	316	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
	317	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
	318	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
344	319
345		AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
346		AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
347		AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
348		AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcsr_r, tcsr_w, 0x00ff)
349		AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcor_r, tcor_w, 0xff00)
350		AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
351		AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
352		AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
353		AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
354		AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
355		AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
356		AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
	320	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
	321	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
357	322
358		AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
359		AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
360		AM_RANGE(0xffffd2, 0xffffd3) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
361		AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
362		AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
363		AM_RANGE(0xffffd6, 0xffffd7) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
364		AM_RANGE(0xffffd8, 0xffffdf) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tgr_r, tgr_w )
365		AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
366		AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
367		AM_RANGE(0xffffe2, 0xffffe3) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
368		AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
369		AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
370		AM_RANGE(0xffffe6, 0xffffe7) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tcnt_r, tcnt_w )
371		AM_RANGE(0xffffe8, 0xffffeb) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tgr_r, tgr_w )
372		AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
373		AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
374		AM_RANGE(0xfffff2, 0xfffff3) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
375		AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
376		AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
377		AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
378		AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
	323	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	324	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	325	AM_RANGE(0xffffd2, 0xffffd3) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
	326	AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	327	AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	328	AM_RANGE(0xffffd6, 0xffffd7) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
	329	AM_RANGE(0xffffd8, 0xffffdf) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tgr_r, tgr_w )
	330	AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	331	AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	332	AM_RANGE(0xffffe2, 0xffffe3) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
	333	AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	334	AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	335	AM_RANGE(0xffffe6, 0xffffe7) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tcnt_r, tcnt_w )
	336	AM_RANGE(0xffffe8, 0xffffeb) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tgr_r, tgr_w )
	337	AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	338	AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	339	AM_RANGE(0xfffff2, 0xfffff3) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
	340	AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	341	AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	342	AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
	343	AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
379	344	ADDRESS_MAP_END
380	345
381	346	machine_config_constructor h8s2320_device::device_mconfig_additions() const
r243812	r243813
460	425	add_event(event_time, timer16_3->internal_update(current_time));
461	426	add_event(event_time, timer16_4->internal_update(current_time));
462	427	add_event(event_time, timer16_5->internal_update(current_time));
463		add_event(event_time, watchdog->internal_update(current_time));
464	428
465	429	recompute_bcount(event_time);
466	430	}

trunk/src/emu/cpu/h8/h8s2320.h
r243812	r243813
55	55	#define __H8S2320_H__
56	56
57	57	#include "h8s2000.h"
58		#include "h8_intc.h"
59	58	#include "h8_adc.h"
60		#include "h8_dma.h"
61	59	#include "h8_port.h"
	60	#include "h8_intc.h"
	61	#include "h8_sci.h"
62	62	#include "h8_timer8.h"
63	63	#include "h8_timer16.h"
64		#include "h8_sci.h"
65		#include "h8_watchdog.h"
66	64
67	65	class h8s2320_device : public h8s2000_device {
68	66	public:
r243812	r243813
75	73	protected:
76	74	required_device<h8s_intc_device> intc;
77	75	required_device<h8_adc_device> adc;
78		optional_device<h8_dma_device> dma;
79		optional_device<h8_dma_channel_device> dma0;
80		optional_device<h8_dma_channel_device> dma1;
81	76	required_device<h8_port_device> port1;
82	77	required_device<h8_port_device> port2;
83	78	required_device<h8_port_device> port3;
r243812	r243813
103	98	required_device<h8_sci_device> sci0;
104	99	required_device<h8_sci_device> sci1;
105	100	required_device<h8_sci_device> sci2;
106		required_device<h8_watchdog_device> watchdog;
107	101
108	102	UINT32 ram_start;
109	103	UINT8 syscr;

trunk/src/emu/cpu/h8/h8s2357.c
r243812	r243813
36	36	timer16_5(*this, "timer16:5"),
37	37	sci0(*this, "sci0"),
38	38	sci1(*this, "sci1"),
39		sci2(*this, "sci2"),
40		watchdog(*this, "watchdog")
	39	sci2(*this, "sci2")
41	40	{
42	41	}
43	42
r243812	r243813
69	68	timer16_5(*this, "timer16:5"),
70	69	sci0(*this, "sci0"),
71	70	sci1(*this, "sci1"),
72		sci2(*this, "sci2"),
73		watchdog(*this, "watchdog")
	71	sci2(*this, "sci2")
74	72	{
75	73	ram_start = 0xffdc00;
76	74	}
r243812	r243813
183	181	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
184	182	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
185	183	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
186		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
187	184	MACHINE_CONFIG_END
188	185
189	186	DEVICE_ADDRESS_MAP_START(map, 16, h8s2357_device)
r243812	r243813
293	290	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
294	291	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
295	292	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
296		AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
297		AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
298	293	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
299	294	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
300	295	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
r243812	r243813
402	397	add_event(event_time, timer16_3->internal_update(current_time));
403	398	add_event(event_time, timer16_4->internal_update(current_time));
404	399	add_event(event_time, timer16_5->internal_update(current_time));
405		add_event(event_time, watchdog->internal_update(current_time));
406	400
407	401	recompute_bcount(event_time);
408	402	}

trunk/src/emu/cpu/h8/h8s2357.h
r243812	r243813
52	52	#define __H8S2357_H__
53	53
54	54	#include "h8s2000.h"
55		#include "h8_intc.h"
56	55	#include "h8_adc.h"
57	56	#include "h8_port.h"
	57	#include "h8_intc.h"
	58	#include "h8_sci.h"
58	59	#include "h8_timer8.h"
59	60	#include "h8_timer16.h"
60		#include "h8_sci.h"
61		#include "h8_watchdog.h"
62	61
63	62	class h8s2357_device : public h8s2000_device {
64	63	public:
r243812	r243813
96	95	required_device<h8_sci_device> sci0;
97	96	required_device<h8_sci_device> sci1;
98	97	required_device<h8_sci_device> sci2;
99		required_device<h8_watchdog_device> watchdog;
100	98
101	99	UINT32 ram_start;
102	100	unsigned char syscr;

trunk/src/emu/cpu/h8/h8s2655.c
r243812	r243813
32	32	timer16_5(*this, "timer16:5"),
33	33	sci0(*this, "sci0"),
34	34	sci1(*this, "sci1"),
35		sci2(*this, "sci2"),
36		watchdog(*this, "watchdog")
	35	sci2(*this, "sci2")
37	36	{
38	37	has_trace = true;
39	38	}
r243812	r243813
66	65	timer16_5(*this, "timer16:5"),
67	66	sci0(*this, "sci0"),
68	67	sci1(*this, "sci1"),
69		sci2(*this, "sci2"),
70		watchdog(*this, "watchdog")
	68	sci2(*this, "sci2")
71	69
72	70	{
73	71	has_trace = true;
r243812	r243813
156	154	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
157	155	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
158	156	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
159		MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
160	157	MACHINE_CONFIG_END
161	158
162	159	DEVICE_ADDRESS_MAP_START(map, 16, h8s2655_device)
r243812	r243813
267	264	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
268	265	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
269	266	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
270		AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
271		AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
272	267	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
273	268	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
274	269	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
r243812	r243813
409	404	add_event(event_time, timer16_3->internal_update(current_time));
410	405	add_event(event_time, timer16_4->internal_update(current_time));
411	406	add_event(event_time, timer16_5->internal_update(current_time));
412		add_event(event_time, watchdog->internal_update(current_time));
413	407
414	408	recompute_bcount(event_time);
415	409	}

trunk/src/emu/cpu/h8/h8s2655.h
r243812	r243813
44	44	#define __H8S2655_H__
45	45
46	46	#include "h8s2600.h"
47		#include "h8_intc.h"
48	47	#include "h8_adc.h"
49	48	#include "h8_port.h"
	49	#include "h8_intc.h"
50	50	#include "h8_timer8.h"
51	51	#include "h8_timer16.h"
52	52	#include "h8_sci.h"
53		#include "h8_watchdog.h"
54	53
55	54	class h8s2655_device : public h8s2600_device {
56	55	public:
r243812	r243813
88	87	required_device<h8_sci_device> sci0;
89	88	required_device<h8_sci_device> sci1;
90	89	required_device<h8_sci_device> sci2;
91		required_device<h8_watchdog_device> watchdog;
92	90
93	91	UINT8 syscr;
94	92

trunk/src/emu/cpu/m6502/m6502.c
r243812	r243813
409	409	inst_state = IR \| inst_state_base;
410	410	if(machine().debug_flags & DEBUG_FLAG_ENABLED)
411	411	debugger_instruction_hook(this, NPC);
412		if(1) {
413		UINT8 dx[3];
414		dx[0] = mintf->read_decrypted(NPC);
415		dx[1] = mintf->read_decrypted(NPC+1);
416		dx[2] = mintf->read_decrypted(NPC+2);
417		char buf[256];
418		disasm_disassemble(buf, NPC, dx, dx, 0);
419		logerror("%09d : %04x %s\n", 2*UINT32(total_cycles()), NPC, buf);
420		}
421	412	}
422	413	do_exec_full();
423	414	}

trunk/src/emu/emucore.h
r243812	r243813
218	218	#undef assert
219	219	#undef assert_always
220	220
	221	#ifdef MAME_DEBUG
221	222	#define assert(x) do { if (!(x)) throw emu_fatalerror("assert: %s:%d: %s", __FILE__, __LINE__, #x); } while (0)
222	223	#define assert_always(x, msg) do { if (!(x)) throw emu_fatalerror("Fatal error: %s\nCaused by assert: %s:%d: %s", msg, __FILE__, __LINE__, #x); } while (0)
	224	#else
	225	#define assert(x) do { } while (0)
	226	#define assert_always(x, msg) do { if (!(x)) throw emu_fatalerror("Fatal error: %s (%s:%d)", msg, __FILE__, __LINE__); } while (0)
	227	#endif
223	228
224	229
225	230	// macros to convert radians to degrees and degrees to radians
r243812	r243813
311	316	template<class _Dest, class _Source>
312	317	inline _Dest downcast(_Source *src)
313	318	{
	319	#if defined(MAME_DEBUG) && !defined(MAME_DEBUG_FAST)
314	320	try {
315	321	if (dynamic_cast<_Dest>(src) != src)
316	322	{
r243812	r243813
324	330	{
325	331	report_bad_cast(typeid(src), typeid(_Dest));
326	332	}
	333	#endif
327	334	return static_cast<_Dest>(src);
328	335	}
329	336
330	337	template<class _Dest, class _Source>
331	338	inline _Dest downcast(_Source &src)
332	339	{
	340	#if defined(MAME_DEBUG) && !defined(MAME_DEBUG_FAST)
333	341	try {
334	342	if (&dynamic_cast<_Dest>(src) != &src)
335	343	{
r243812	r243813
343	351	{
344	352	report_bad_cast(typeid(src), typeid(_Dest));
345	353	}
	354	#endif
346	355	return static_cast<_Dest>(src);
347	356	}
348	357

trunk/src/emu/machine/atahle.c
r243812	r243813
2	2	// copyright-holders:smf
3	3	#include "atahle.h"
4	4
5		#define VERBOSE 1
6		#define PRINTF_IDE_COMMANDS 1
	5	#define VERBOSE 0
	6	#define PRINTF_IDE_COMMANDS 0
7	7
8	8	#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
9	9	#define LOGPRINT(x) do { if (VERBOSE) logerror x; if (PRINTF_IDE_COMMANDS) osd_printf_debug x; } while (0)

trunk/src/emu/machine/tmp68301.c
r243812	r243813
18	18	#include "machine/tmp68301.h"
19	19
20	20	const device_type TMP68301 = &device_creator<tmp68301_device>;
21		const device_type TMP68301_SERIAL = &device_creator<tmp68301_serial_device>;
22		const device_type TMP68301_RS232 = &device_creator<tmp68301_rs232_device>;
23	21
24	22	static ADDRESS_MAP_START( tmp68301_regs, AS_0, 16, tmp68301_device )
25	23	// AM_RANGE(0x000,0x3ff) AM_RAM
26		AM_RANGE(0x094,0x095) AM_READWRITE (imr_r, imr_w)
27		AM_RANGE(0x098,0x099) AM_READWRITE (iisr_r, iisr_w)
	24	AM_RANGE(0x094,0x095) AM_READWRITE(imr_r,imr_w)
	25	AM_RANGE(0x098,0x099) AM_READWRITE(iisr_r,iisr_w)
28	26
29	27	/* Parallel Port */
30		AM_RANGE(0x100,0x101) AM_READWRITE (pdir_r, pdir_w)
31		AM_RANGE(0x10a,0x10b) AM_READWRITE (pdr_r, pdr_w)
	28	AM_RANGE(0x100,0x101) AM_READWRITE(pdir_r,pdir_w)
	29	AM_RANGE(0x10a,0x10b) AM_READWRITE(pdr_r,pdr_w)
32	30
33	31	/* Serial Port */
34		AM_RANGE(0x180,0x181) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, smr_r, smr_w, 0x00ff)
35		AM_RANGE(0x182,0x183) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, scmr_r, scmr_w, 0x00ff)
36		AM_RANGE(0x184,0x185) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, sbrr_r, sbrr_w, 0x00ff)
37		AM_RANGE(0x186,0x187) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, ssr_r, ssr_w, 0x00ff)
38		AM_RANGE(0x188,0x189) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, sdr_r, sdr_w, 0x00ff)
39
40		AM_RANGE(0x18c,0x18d) AM_READWRITE8(spr_r, spr_w, 0x00ff)
41		AM_RANGE(0x18e,0x18f) AM_READWRITE8(scr_r, scr_w, 0x00ff)
42
43		AM_RANGE(0x190,0x191) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, smr_r, smr_w, 0x00ff)
44		AM_RANGE(0x192,0x193) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, scmr_r, scmr_w, 0x00ff)
45		AM_RANGE(0x194,0x195) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, sbrr_r, sbrr_w, 0x00ff)
46		AM_RANGE(0x196,0x197) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, ssr_r, ssr_w, 0x00ff)
47		AM_RANGE(0x198,0x199) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, sdr_r, sdr_w, 0x00ff)
48
49		AM_RANGE(0x1a0,0x1a1) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, smr_r, smr_w, 0x00ff)
50		AM_RANGE(0x1a2,0x1a3) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, scmr_r, scmr_w, 0x00ff)
51		AM_RANGE(0x1a4,0x1a5) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, sbrr_r, sbrr_w, 0x00ff)
52		AM_RANGE(0x1a6,0x1a7) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, ssr_r, ssr_w, 0x00ff)
53		AM_RANGE(0x1a8,0x1a9) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, sdr_r, sdr_w, 0x00ff)
	32	AM_RANGE(0x18e,0x18f) AM_READWRITE(scr_r,scr_w)
54	33	ADDRESS_MAP_END
55	34
56		static MACHINE_CONFIG_FRAGMENT( tmp68301 )
57		MCFG_TMP68301_RS232_ADD ("ser0")
58		MCFG_TMP68301_SERIAL_ADD("ser1")
59		MCFG_TMP68301_SERIAL_ADD("ser2")
60		MACHINE_CONFIG_END
61
62	35	// IRQ Mask register, 0x94
63	36	READ16_MEMBER(tmp68301_device::imr_r)
64	37	{
r243812	r243813
81	54	COMBINE_DATA(&m_iisr);
82	55	}
83	56
	57	// Serial Control Register (TODO: 8-bit wide)
	58	READ16_MEMBER(tmp68301_device::scr_r)
	59	{
	60	return m_scr;
	61	}
	62
	63	WRITE16_MEMBER(tmp68301_device::scr_w)
	64	{
	65	/*
	66	*--- ---- CKSE
	67	--*- ---- RES
	68	---- ---* INTM
	69	*/
	70
	71	COMBINE_DATA(&m_scr);
	72	m_scr &= 0xa1;
	73	}
	74
84	75	/* Parallel direction: 1 = output, 0 = input */
85	76	READ16_MEMBER(tmp68301_device::pdir_r)
86	77	{
r243812	r243813
108	99	device_memory_interface(mconfig, *this),
109	100	m_in_parallel_cb(*this),
110	101	m_out_parallel_cb(*this),
111		m_ser0(*this, "ser0"),
112		m_ser1(*this, "ser1"),
113		m_ser2(*this, "ser2"),
114	102	m_space_config("regs", ENDIANNESS_LITTLE, 16, 10, 0, NULL, *ADDRESS_MAP_NAME(tmp68301_regs))
115	103	{
116	104	}
117	105
118		void tmp68301_device::set_cpu_tag(const char *tag)
119		{
120		m_cpu_tag = tag;
121		}
122	106
123	107	//-------------------------------------------------
124	108	// device_start - device-specific startup
r243812	r243813
132	116
133	117	m_in_parallel_cb.resolve_safe(0);
134	118	m_out_parallel_cb.resolve_safe();
135
136		m_cpu = machine().device<m68000_device>(m_cpu_tag);
137	119	}
138	120
139	121	//-------------------------------------------------
r243812	r243813
148	130	m_IE[i] = 0;
149	131
150	132	m_imr = 0x7f7; // mask all irqs
151		m_scr = 0x00;
152		m_spr = 0x00;
153
154		double prescaled_clock = double(m_cpu->unscaled_clock())/256;
155		m_ser0->set_prescaled_clock(prescaled_clock);
156		m_ser1->set_prescaled_clock(prescaled_clock);
157		m_ser2->set_prescaled_clock(prescaled_clock);
158	133	}
159	134
160	135	//-------------------------------------------------
r243812	r243813
167	142	return (spacenum == AS_0) ? &m_space_config : NULL;
168	143	}
169	144
170		machine_config_constructor tmp68301_device::device_mconfig_additions() const
171		{
172		return MACHINE_CONFIG_NAME(tmp68301);
173		}
174
175	145	//**************************************************************************
176	146	// INLINE HELPERS
177	147	//**************************************************************************
r243812	r243813
220	190	m_irq_vector[level] = IVNR & 0x00e0;
221	191	m_irq_vector[level] += 4+i;
222	192
223		m_cpu->set_input_line(level,HOLD_LINE);
	193	machine().firstcpu->set_input_line(level,HOLD_LINE);
224	194	}
225	195
226	196	if (TCR & 0x0080) // N/1
r243812	r243813
263	233	{
264	234	int scale = (TCR & 0x3c00)>>10; // P4..1
265	235	if (scale > 8) scale = 8;
266		duration = attotime::from_hz(m_cpu->unscaled_clock()) * ((1 << scale) * max);
	236	duration = attotime::from_hz(machine().firstcpu->unscaled_clock()) * ((1 << scale) * max);
267	237	}
268	238	break;
269	239	}
r243812	r243813
305	275
306	276	m_IE[i] = 0; // Interrupts are edge triggerred
307	277
308		m_cpu->set_input_line(level,HOLD_LINE);
	278	machine().firstcpu->set_input_line(level,HOLD_LINE);
309	279	}
310	280	}
311	281	}
r243812	r243813
343	313	void tmp68301_device::external_interrupt_0() { m_IE[0] = 1; update_irq_state(); }
344	314	void tmp68301_device::external_interrupt_1() { m_IE[1] = 1; update_irq_state(); }
345	315	void tmp68301_device::external_interrupt_2() { m_IE[2] = 1; update_irq_state(); }
346
347
348		// Serial subsystem
349
350		tmp68301_serial_device::tmp68301_serial_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
351		device_t(mconfig, TMP68301_SERIAL, "TMP68301 Serial", tag, owner, clock, "tmp68301_serial", __FILE__),
352		tx_cb(*this)
353		{
354		}
355
356		tmp68301_serial_device::tmp68301_serial_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source) :
357		device_t(mconfig, type, name, tag, owner, clock, shortname, source),
358		tx_cb(*this)
359		{
360		}
361
362		tmp68301_rs232_device::tmp68301_rs232_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
363		tmp68301_serial_device(mconfig, TMP68301_SERIAL, "TMP68301 RS232", tag, owner, clock, "tmp68301_rs232", __FILE__),
364		rts_cb(*this),
365		dtr_cb(*this)
366		{
367		}
368
369		void tmp68301_serial_device::device_start()
370		{
371		prescaled_clock = 0;
372		clock_interval = attotime::never;
373		}
374
375		void tmp68301_serial_device::device_reset()
376		{
377		smr = 0xc2;
378		scmr = 0x10;
379		ssr = 0x04;
380		sbrr = 0x00;
381		clock_interval = attotime::never;
382		}
383
384		void tmp68301_rs232_device::device_start()
385		{
386		tmp68301_serial_device::device_start();
387		}
388
389		void tmp68301_rs232_device::device_reset()
390		{
391		tmp68301_serial_device::device_reset();
392		}
393
394		READ8_MEMBER(tmp68301_device::scr_r)
395		{
396		return m_scr;
397		}
398
399		WRITE8_MEMBER(tmp68301_device::scr_w)
400		{
401		logerror("%s: scr_w %02x clokc=%s reset=%s serial_int=%s (%06x)\n", tag(), data,
402		data & 0x80 ? "internal" : "external",
403		data & 0x40 ? "on" : "off",
404		data & 0x01 ? "off" : "on",
405		space.device().safe_pc());
406
407		/*
408		*--- ---- CKSE
409		--*- ---- RES
410		---- ---* INTM
411		*/
412
413		m_scr = data & 0xa1;
414		recalc_serial_clock();
415		}
416
417		READ8_MEMBER(tmp68301_device::spr_r)
418		{
419		logerror("%s: spr_r (%06x)\n", tag(), space.device().safe_pc());
420		return m_spr;
421		}
422
423		WRITE8_MEMBER(tmp68301_device::spr_w)
424		{
425		logerror("%s: spr_w %02x (%06x)\n", tag(), data, space.device().safe_pc());
426		m_spr = data;
427		recalc_serial_clock();
428		}
429
430		void tmp68301_device::recalc_serial_clock()
431		{
432		double prescaled_clock = m_scr & 0x20 ? 0 : m_spr ? double(m_cpu->unscaled_clock())/m_spr : double(clock())/256;
433		m_ser0->set_prescaled_clock(prescaled_clock);
434		m_ser1->set_prescaled_clock(prescaled_clock);
435		m_ser2->set_prescaled_clock(prescaled_clock);
436		}
437
438		READ8_MEMBER(tmp68301_serial_device::smr_r)
439		{
440		logerror("%s: smr_r (%06x)\n", tag(), space.device().safe_pc());
441		return smr;
442		}
443
444		WRITE8_MEMBER(tmp68301_serial_device::smr_w)
445		{
446		logerror("%s: smr_w %02x rx_int=%s tx_int=%s er_int=%s mode=%d%c%c (%06x)\n",
447		tag(), data,
448		data & 0x80 ? "off" : "on",
449		data & 0x02 ? "off" : "on",
450		data & 0x40 ? "off" : "on",
451		5 + ((data >> 2) & 3),
452		data & 0x10 ? data & 0x20 ? 'o' : 'e' : 'n',
453		data & 0x01 ? '2' : '1',
454		space.device().safe_pc());
455		smr = data;
456		}
457
458		READ8_MEMBER(tmp68301_serial_device::scmr_r)
459		{
460		logerror("%s: scmr_r (%06x)\n", tag(), space.device().safe_pc());
461		return scmr;
462		}
463
464		WRITE8_MEMBER(tmp68301_serial_device::scmr_w)
465		{
466		logerror("%s: scmr_w %02x ers=%s break=%s rx=%s tx=%s rts=%s dtr=%s (%06x)\n", tag(), data,
467		data & 0x10 ? "reset" : "off",
468		data & 0x08 ? "on" : "off",
469		data & 0x04 ? "on" : "off",
470		data & 0x01 ? "on" : "off",
471		data & 0x20 ? "low" : "high",
472		data & 0x02 ? "low" : "high",
473		space.device().safe_pc());
474		scmr = data;
475		}
476
477		READ8_MEMBER(tmp68301_serial_device::sbrr_r)
478		{
479		logerror("%s: sbrr_r (%06x)\n", tag(), space.device().safe_pc());
480		return sbrr;
481		}
482
483		WRITE8_MEMBER(tmp68301_serial_device::sbrr_w)
484		{
485		logerror("%s: sbrr_w %02x (%06x)\n", tag(), data, space.device().safe_pc());
486		sbrr = data;
487		clock_update();
488		}
489
490		READ8_MEMBER(tmp68301_serial_device::ssr_r)
491		{
492		logerror("%s: ssr_r (%06x)\n", tag(), space.device().safe_pc());
493		return ssr;
494		}
495
496		WRITE8_MEMBER(tmp68301_serial_device::ssr_w)
497		{
498		logerror("%s: ssr_w %02x (%06x)\n", tag(), data, space.device().safe_pc());
499		ssr = data;
500		}
501
502		READ8_MEMBER(tmp68301_serial_device::sdr_r)
503		{
504		logerror("%s: sdr_r (%06x)\n", tag(), space.device().safe_pc());
505		return 0x00;
506		}
507
508		WRITE8_MEMBER(tmp68301_serial_device::sdr_w)
509		{
510		logerror("%s: sdr_w %02x (%06x)\n", tag(), data, space.device().safe_pc());
511		}
512
513		void tmp68301_serial_device::set_prescaled_clock(double clock)
514		{
515		prescaled_clock = clock;
516		clock_update();
517		}
518
519		void tmp68301_serial_device::clock_update()
520		{
521		if(!prescaled_clock \|\| !sbrr \|\| (sbrr & (sbrr - 1))) {
522		clock_interval = attotime::never;
523		return;
524		}
525
526		double base_rate = prescaled_clock / sbrr;
527		clock_interval = attotime::from_seconds(1/base_rate);
528		logerror("%s: Baud rate %gHz\n", tag(), base_rate/8);
529		}

trunk/src/emu/machine/tmp68301.h
r243812	r243813
1	1	#ifndef TMP68301_H
2	2	#define TMP68301_H
3	3
4		#include "cpu/m68000/m68000.h"
5
6	4	//**************************************************************************
7	5	// INTERFACE CONFIGURATION MACROS
8	6	//**************************************************************************
9	7
10		#define MCFG_TMP68301_ADD(_tag, _cpu) \
11		MCFG_DEVICE_ADD( _tag, TMP68301, 0 ) \
12		downcast<tmp68301_device *>(device)->set_cpu_tag(_cpu);
13
14	8	/* TODO: serial ports, frequency & hook it up with m68k */
15	9	#define MCFG_TMP68301_IN_PARALLEL_CB(_devcb) \
16	10	devcb = &tmp68301_device::set_in_parallel_callback(*device, DEVCB_##_devcb);
r243812	r243813
18	12	#define MCFG_TMP68301_OUT_PARALLEL_CB(_devcb) \
19	13	devcb = &tmp68301_device::set_out_parallel_callback(*device, DEVCB_##_devcb);
20	14
21		#define MCFG_TMP68301_SERIAL_ADD( _tag ) \
22		MCFG_DEVICE_ADD( _tag, TMP68301_SERIAL, 0 )
23	15
24		#define MCFG_TMP68301_RS232_ADD( _tag ) \
25		MCFG_DEVICE_ADD( _tag, TMP68301_RS232, 0 )
26
27		#define MCFG_TMP68301_SERIAL_TX_CALLBACK(_devcb) \
28		devcb = &tmp68301_serial_device::set_tx_cb(*device, DEVCB_##_devcb);
29
30		#define MCFG_TMP68301_SERIAL_RTS_CALLBACK(_devcb) \
31		devcb = &tmp68301_rs232_device::set_rts_cb(*device, DEVCB_##_devcb);
32
33		#define MCFG_TMP68301_SERIAL_DTR_CALLBACK(_devcb) \
34		devcb = &tmp68301_rs232_device::set_str_cb(*device, DEVCB_##_devcb);
35
36	16	//**************************************************************************
37	17	// TYPE DEFINITIONS
38	18	//**************************************************************************
39	19
40		class tmp68301_serial_device : public device_t
41		{
42		public:
43		tmp68301_serial_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
44		tmp68301_serial_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
45	20
46		DECLARE_READ8_MEMBER(smr_r);
47		DECLARE_WRITE8_MEMBER(smr_w);
48		DECLARE_READ8_MEMBER(scmr_r);
49		DECLARE_WRITE8_MEMBER(scmr_w);
50		DECLARE_READ8_MEMBER(sbrr_r);
51		DECLARE_WRITE8_MEMBER(sbrr_w);
52		DECLARE_READ8_MEMBER(ssr_r);
53		DECLARE_WRITE8_MEMBER(ssr_w);
54		DECLARE_READ8_MEMBER(sdr_r);
55		DECLARE_WRITE8_MEMBER(sdr_w);
56	21
57		DECLARE_WRITE_LINE_MEMBER(rx_w);
58
59		template<class _Object> static devcb_base &set_tx_cb(device_t &device, _Object object) { return downcast<tmp68301_serial_device &>(device).tx_cb.set_callback(object); }
60
61		void set_prescaled_clock(double clock);
62
63		protected:
64		devcb_write_line tx_cb;
65		attotime clock_interval;
66		double prescaled_clock;
67
68		UINT8 smr, scmr, ssr, sbrr;
69
70		virtual void device_start();
71		virtual void device_reset();
72
73		void clock_update();
74		};
75
76		class tmp68301_rs232_device : public tmp68301_serial_device {
77		public:
78		tmp68301_rs232_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
79
80		DECLARE_WRITE_LINE_MEMBER(cts_w);
81		DECLARE_WRITE_LINE_MEMBER(dsr_w);
82
83		template<class _Object> static devcb_base &set_rts_cb(device_t &device, _Object object) { return downcast<tmp68301_rs232_device &>(device).rts_cb.set_callback(object); }
84		template<class _Object> static devcb_base &set_dtr_cb(device_t &device, _Object object) { return downcast<tmp68301_rs232_device &>(device).dtr_cb.set_callback(object); }
85
86		protected:
87		devcb_write_line rts_cb, dtr_cb;
88
89		virtual void device_start();
90		virtual void device_reset();
91		};
92
93	22	class tmp68301_device : public device_t,
94	23	public device_memory_interface
95	24	{
r243812	r243813
100	29	template<class _Object> static devcb_base &set_in_parallel_callback(device_t &device, _Object object) { return downcast<tmp68301_device &>(device).m_in_parallel_cb.set_callback(object); }
101	30	template<class _Object> static devcb_base &set_out_parallel_callback(device_t &device, _Object object) { return downcast<tmp68301_device &>(device).m_out_parallel_cb.set_callback(object); }
102	31
103		void set_cpu_tag(const char *tag);
104
105	32	// Hardware Registers
106	33	DECLARE_READ16_MEMBER( regs_r );
107	34	DECLARE_WRITE16_MEMBER( regs_w );
r243812	r243813
115	42	DECLARE_WRITE16_MEMBER(imr_w);
116	43	DECLARE_READ16_MEMBER(iisr_r);
117	44	DECLARE_WRITE16_MEMBER(iisr_w);
	45	DECLARE_READ16_MEMBER(scr_r);
	46	DECLARE_WRITE16_MEMBER(scr_w);
118	47	DECLARE_READ16_MEMBER(pdr_r);
119	48	DECLARE_WRITE16_MEMBER(pdr_w);
120	49	DECLARE_READ16_MEMBER(pdir_r);
121	50	DECLARE_WRITE16_MEMBER(pdir_w);
122	51
123		DECLARE_READ8_MEMBER(spr_r);
124		DECLARE_WRITE8_MEMBER(spr_w);
125		DECLARE_READ8_MEMBER(scr_r);
126		DECLARE_WRITE8_MEMBER(scr_w);
127
128	52	IRQ_CALLBACK_MEMBER(irq_callback);
129	53	protected:
130	54	// device-level overrides
131	55	virtual void device_start();
132	56	virtual void device_reset();
133	57	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
134		virtual machine_config_constructor device_mconfig_additions() const;
135	58
136	59	private:
137	60	devcb_read16 m_in_parallel_cb;
138	61	devcb_write16 m_out_parallel_cb;
139	62
140		required_device<tmp68301_rs232_device> m_ser0;
141		required_device<tmp68301_serial_device> m_ser1;
142		required_device<tmp68301_serial_device> m_ser2;
143
144		const char *m_cpu_tag;
145		m68000_device *m_cpu;
146
147	63	// internal state
148	64	UINT16 m_regs[0x400];
149	65
r243812	r243813
158	74
159	75	UINT16 m_imr;
160	76	UINT16 m_iisr;
	77	UINT16 m_scr;
161	78	UINT16 m_pdir;
162	79
163		UINT8 m_scr, m_spr;
164
165	80	inline UINT16 read_word(offs_t address);
166	81	inline void write_word(offs_t address, UINT16 data);
167	82	const address_space_config m_space_config;
168
169		void recalc_serial_clock();
170	83	};
171	84
172	85	extern const device_type TMP68301;
173		extern const device_type TMP68301_SERIAL;
174		extern const device_type TMP68301_RS232;
175	86
176	87	#endif

trunk/src/emu/machine/wozfdc.c
r243812	r243813
414	414	void wozfdc_device::lss_sync()
415	415	{
416	416	attotime tm = machine().time();
417		if(~~false && (~~!predicted_lss.tm.is_never() && predicted_lss.tm <= tm))
	417	if(!predicted_lss.tm.is_never() && predicted_lss.tm <= tm)
418	418	commit_predicted();
419	419
420	420	while(cur_lss.tm < tm) {
r243812	r243813
432	432
433	433	attotime next_flux = floppy ? floppy->get_next_transition(cur_lss.tm - attotime::from_usec(1)) : attotime::never;
434	434
435		bool trace = limit != attotime::never;
436	435	if(limit == attotime::never)
437	436	limit = machine().time() + attotime::from_usec(50);
438		// trace = false;
439	437
440	438	UINT64 cycles = cur_lss.cycles;
441	439	UINT64 cycles_limit = time_to_cycles(limit);
r243812	r243813
457	455	if(cycles_next_trans > cycles_next_flux_down && cycles < cycles_next_flux_down)
458	456	cycles_next_trans = cycles_next_flux_down;
459	457
460		char ebuf[32];
461		if(cycles_next_flux == UINT64(-1))
462		strcpy(ebuf, "-");
463		else
464		sprintf(ebuf, "%09u", UINT32(cycles_next_flux));
465
466	458	while(cycles < cycles_next_trans) {
467	459	UINT8 opcode = m_rom_p6[address];
468		if(trace)
469		logerror("%09u : %9s %02x %02x (%02x)\n", UINT32(cycles), ebuf, address, opcode, cur_lss.data_reg);
	460
470	461	if(mode_write) {
471	462	if((write_line_active && !(address & 0x80)) \|\|
472	463	(!write_line_active && (address & 0x80))) {

trunk/src/emu/sound/la32.c
r243812	r243813
1		#include "emu.h"
2		#include "la32.h"
3
4		const device_type LA32 = &device_creator<la32_device>;
5
6		// These 3 tables are present on the die. They're the only tables in there
7		// 2*((n+1)/512) 8192
8		const UINT16 la32_device::exp2_table[0x200] = {
9		0xff5, 0xfea, 0xfdf, 0xfd4, 0xfc9, 0xfbe, 0xfb3, 0xfa8, 0xf9d, 0xf92, 0xf87, 0xf7c, 0xf71, 0xf66, 0xf5b, 0xf50,
10		0xf46, 0xf3b, 0xf30, 0xf25, 0xf1a, 0xf10, 0xf05, 0xefa, 0xeef, 0xee5, 0xeda, 0xecf, 0xec5, 0xeba, 0xeaf, 0xea5,
11		0xe9a, 0xe8f, 0xe85, 0xe7a, 0xe70, 0xe65, 0xe5b, 0xe50, 0xe46, 0xe3b, 0xe31, 0xe26, 0xe1c, 0xe11, 0xe07, 0xdfd,
12		0xdf2, 0xde8, 0xddd, 0xdd3, 0xdc9, 0xdbe, 0xdb4, 0xdaa, 0xda0, 0xd95, 0xd8b, 0xd81, 0xd77, 0xd6c, 0xd62, 0xd58,
13		0xd4e, 0xd44, 0xd3a, 0xd30, 0xd25, 0xd1b, 0xd11, 0xd07, 0xcfd, 0xcf3, 0xce9, 0xcdf, 0xcd5, 0xccb, 0xcc1, 0xcb7,
14		0xcad, 0xca3, 0xc99, 0xc8f, 0xc86, 0xc7c, 0xc72, 0xc68, 0xc5e, 0xc54, 0xc4a, 0xc41, 0xc37, 0xc2d, 0xc23, 0xc1a,
15		0xc10, 0xc06, 0xbfc, 0xbf3, 0xbe9, 0xbdf, 0xbd6, 0xbcc, 0xbc2, 0xbb9, 0xbaf, 0xba6, 0xb9c, 0xb93, 0xb89, 0xb7f,
16		0xb76, 0xb6c, 0xb63, 0xb59, 0xb50, 0xb47, 0xb3d, 0xb34, 0xb2a, 0xb21, 0xb17, 0xb0e, 0xb05, 0xafb, 0xaf2, 0xae9,
17		0xadf, 0xad6, 0xacd, 0xac3, 0xaba, 0xab1, 0xaa8, 0xa9e, 0xa95, 0xa8c, 0xa83, 0xa7a, 0xa70, 0xa67, 0xa5e, 0xa55,
18		0xa4c, 0xa43, 0xa3a, 0xa31, 0xa28, 0xa1e, 0xa15, 0xa0c, 0xa03, 0x9fa, 0x9f1, 0x9e8, 0x9df, 0x9d6, 0x9ce, 0x9c5,
19		0x9bc, 0x9b3, 0x9aa, 0x9a1, 0x998, 0x98f, 0x986, 0x97e, 0x975, 0x96c, 0x963, 0x95a, 0x951, 0x949, 0x940, 0x937,
20		0x92e, 0x926, 0x91d, 0x914, 0x90c, 0x903, 0x8fa, 0x8f2, 0x8e9, 0x8e0, 0x8d8, 0x8cf, 0x8c7, 0x8be, 0x8b5, 0x8ad,
21		0x8a4, 0x89c, 0x893, 0x88b, 0x882, 0x87a, 0x871, 0x869, 0x860, 0x858, 0x850, 0x847, 0x83f, 0x836, 0x82e, 0x826,
22		0x81d, 0x815, 0x80c, 0x804, 0x7fc, 0x7f4, 0x7eb, 0x7e3, 0x7db, 0x7d2, 0x7ca, 0x7c2, 0x7ba, 0x7b1, 0x7a9, 0x7a1,
23		0x799, 0x791, 0x789, 0x780, 0x778, 0x770, 0x768, 0x760, 0x758, 0x750, 0x748, 0x740, 0x738, 0x730, 0x727, 0x71f,
24		0x717, 0x70f, 0x707, 0x6ff, 0x6f8, 0x6f0, 0x6e8, 0x6e0, 0x6d8, 0x6d0, 0x6c8, 0x6c0, 0x6b8, 0x6b0, 0x6a8, 0x6a1,
25		0x699, 0x691, 0x689, 0x681, 0x67a, 0x672, 0x66a, 0x662, 0x65a, 0x653, 0x64b, 0x643, 0x63c, 0x634, 0x62c, 0x624,
26		0x61d, 0x615, 0x60e, 0x606, 0x5fe, 0x5f7, 0x5ef, 0x5e7, 0x5e0, 0x5d8, 0x5d1, 0x5c9, 0x5c2, 0x5ba, 0x5b3, 0x5ab,
27		0x5a4, 0x59c, 0x595, 0x58d, 0x586, 0x57e, 0x577, 0x56f, 0x568, 0x560, 0x559, 0x552, 0x54a, 0x543, 0x53c, 0x534,
28		0x52d, 0x525, 0x51e, 0x517, 0x510, 0x508, 0x501, 0x4fa, 0x4f2, 0x4eb, 0x4e4, 0x4dd, 0x4d5, 0x4ce, 0x4c7, 0x4c0,
29		0x4b9, 0x4b1, 0x4aa, 0x4a3, 0x49c, 0x495, 0x48e, 0x487, 0x480, 0x478, 0x471, 0x46a, 0x463, 0x45c, 0x455, 0x44e,
30		0x447, 0x440, 0x439, 0x432, 0x42b, 0x424, 0x41d, 0x416, 0x40f, 0x408, 0x401, 0x3fa, 0x3f3, 0x3ec, 0x3e6, 0x3df,
31		0x3d8, 0x3d1, 0x3ca, 0x3c3, 0x3bc, 0x3b5, 0x3af, 0x3a8, 0x3a1, 0x39a, 0x393, 0x38d, 0x386, 0x37f, 0x378, 0x372,
32		0x36b, 0x364, 0x35d, 0x357, 0x350, 0x349, 0x343, 0x33c, 0x335, 0x32f, 0x328, 0x321, 0x31b, 0x314, 0x30e, 0x307,
33		0x300, 0x2fa, 0x2f3, 0x2ed, 0x2e6, 0x2e0, 0x2d9, 0x2d3, 0x2cc, 0x2c5, 0x2bf, 0x2b8, 0x2b2, 0x2ac, 0x2a5, 0x29f,
34		0x298, 0x292, 0x28b, 0x285, 0x27e, 0x278, 0x272, 0x26b, 0x265, 0x25f, 0x258, 0x252, 0x24b, 0x245, 0x23f, 0x238,
35		0x232, 0x22c, 0x226, 0x21f, 0x219, 0x213, 0x20c, 0x206, 0x200, 0x1fa, 0x1f4, 0x1ed, 0x1e7, 0x1e1, 0x1db, 0x1d5,
36		0x1ce, 0x1c8, 0x1c2, 0x1bc, 0x1b6, 0x1b0, 0x1a9, 0x1a3, 0x19d, 0x197, 0x191, 0x18b, 0x185, 0x17f, 0x179, 0x173,
37		0x16d, 0x167, 0x161, 0x15b, 0x155, 0x14f, 0x149, 0x143, 0x13d, 0x137, 0x131, 0x12b, 0x125, 0x11f, 0x119, 0x113,
38		0x10d, 0x107, 0x101, 0x0fb, 0x0f6, 0x0f0, 0x0ea, 0x0e4, 0x0de, 0x0d8, 0x0d2, 0x0cd, 0x0c7, 0x0c1, 0x0bb, 0x0b5,
39		0x0b0, 0x0aa, 0x0a4, 0x09e, 0x098, 0x093, 0x08d, 0x087, 0x082, 0x07c, 0x076, 0x070, 0x06b, 0x065, 0x05f, 0x05a,
40		0x054, 0x04e, 0x049, 0x043, 0x03d, 0x038, 0x032, 0x02d, 0x027, 0x021, 0x01c, 0x016, 0x011, 0x00b, 0x006, 0x000,
41		};
42
43		// exp2_table[n-1] - exp2_table[n] except for the last three values
44		const UINT8 la32_device::exp2_delta_table[0x200] = {
45		0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb, 0xb,
46		0xa, 0xb, 0xb, 0xb, 0xb, 0xa, 0xb, 0xb, 0xb, 0xa, 0xb, 0xb, 0xa, 0xb, 0xb, 0xa,
47		0xb, 0xb, 0xa, 0xb, 0xa, 0xb, 0xa, 0xb, 0xa, 0xb, 0xa, 0xb, 0xa, 0xb, 0xa, 0xa,
48		0xb, 0xa, 0xb, 0xa, 0xa, 0xb, 0xa, 0xa, 0xa, 0xb, 0xa, 0xa, 0xa, 0xb, 0xa, 0xa,
49		0xa, 0xa, 0xa, 0xa, 0xb, 0xa, 0xa, 0xa, 0xa, 0xa, 0xa, 0xa, 0xa, 0xa, 0xa, 0xa,
50		0xa, 0xa, 0xa, 0xa, 0x9, 0xa, 0xa, 0xa, 0xa, 0xa, 0xa, 0x9, 0xa, 0xa, 0xa, 0x9,
51		0xa, 0xa, 0xa, 0x9, 0xa, 0xa, 0x9, 0xa, 0xa, 0x9, 0xa, 0x9, 0xa, 0x9, 0xa, 0xa,
52		0x9, 0xa, 0x9, 0xa, 0x9, 0x9, 0xa, 0x9, 0xa, 0x9, 0xa, 0x9, 0x9, 0xa, 0x9, 0x9,
53		0xa, 0x9, 0x9, 0xa, 0x9, 0x9, 0x9, 0xa, 0x9, 0x9, 0x9, 0x9, 0xa, 0x9, 0x9, 0x9,
54		0x9, 0x9, 0x9, 0x9, 0x9, 0xa, 0x9, 0x9, 0x9, 0x9, 0x9, 0x9, 0x9, 0x9, 0x8, 0x9,
55		0x9, 0x9, 0x9, 0x9, 0x9, 0x9, 0x9, 0x8, 0x9, 0x9, 0x9, 0x9, 0x9, 0x8, 0x9, 0x9,
56		0x9, 0x8, 0x9, 0x9, 0x8, 0x9, 0x9, 0x8, 0x9, 0x9, 0x8, 0x9, 0x8, 0x9, 0x9, 0x8,
57		0x9, 0x8, 0x9, 0x8, 0x9, 0x8, 0x9, 0x8, 0x9, 0x8, 0x8, 0x9, 0x8, 0x9, 0x8, 0x8,
58		0x9, 0x8, 0x9, 0x8, 0x8, 0x8, 0x9, 0x8, 0x8, 0x9, 0x8, 0x8, 0x8, 0x9, 0x8, 0x8,
59		0x8, 0x8, 0x8, 0x9, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x9, 0x8,
60		0x8, 0x8, 0x8, 0x8, 0x7, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x8, 0x7,
61		0x8, 0x8, 0x8, 0x8, 0x7, 0x8, 0x8, 0x8, 0x8, 0x7, 0x8, 0x8, 0x7, 0x8, 0x8, 0x8,
62		0x7, 0x8, 0x7, 0x8, 0x8, 0x7, 0x8, 0x8, 0x7, 0x8, 0x7, 0x8, 0x7, 0x8, 0x7, 0x8,
63		0x7, 0x8, 0x7, 0x8, 0x7, 0x8, 0x7, 0x8, 0x7, 0x8, 0x7, 0x7, 0x8, 0x7, 0x7, 0x8,
64		0x7, 0x8, 0x7, 0x7, 0x7, 0x8, 0x7, 0x7, 0x8, 0x7, 0x7, 0x7, 0x8, 0x7, 0x7, 0x7,
65		0x7, 0x8, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x8, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
66		0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x6, 0x7,
67		0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x6, 0x7, 0x7, 0x7, 0x7, 0x6, 0x7, 0x7, 0x7, 0x6,
68		0x7, 0x7, 0x7, 0x6, 0x7, 0x7, 0x6, 0x7, 0x7, 0x6, 0x7, 0x7, 0x6, 0x7, 0x6, 0x7,
69		0x7, 0x6, 0x7, 0x6, 0x7, 0x6, 0x7, 0x6, 0x7, 0x7, 0x6, 0x7, 0x6, 0x6, 0x7, 0x6,
70		0x7, 0x6, 0x7, 0x6, 0x7, 0x6, 0x6, 0x7, 0x6, 0x6, 0x7, 0x6, 0x7, 0x6, 0x6, 0x7,
71		0x6, 0x6, 0x6, 0x7, 0x6, 0x6, 0x7, 0x6, 0x6, 0x6, 0x6, 0x7, 0x6, 0x6, 0x6, 0x6,
72		0x7, 0x6, 0x6, 0x6, 0x6, 0x6, 0x7, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6,
73		0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6,
74		0x6, 0x6, 0x6, 0x6, 0x5, 0x6, 0x6, 0x6, 0x6, 0x6, 0x6, 0x5, 0x6, 0x6, 0x6, 0x6,
75		0x5, 0x6, 0x6, 0x6, 0x6, 0x5, 0x6, 0x6, 0x5, 0x6, 0x6, 0x6, 0x5, 0x6, 0x6, 0x5,
76		0x6, 0x6, 0x5, 0x6, 0x6, 0x5, 0x6, 0x5, 0x6, 0x6, 0x5, 0x6, 0x5, 0x6, 0x4, 0x5,
77		};
78
79		// -1024log2(sin(n+0.5)pi/1024) except for n=0
80		const UINT16 la32_device::logsin_table[0x200] = {
81		0x1fff, 0x1f0e, 0x1c1b, 0x1a2a, 0x18b7, 0x178e, 0x1698, 0x15c4, 0x150b, 0x1467, 0x13d3, 0x134d, 0x12d2, 0x1260, 0x11f7, 0x1194,
82		0x1138, 0x10e1, 0x108f, 0x1041, 0x0ff8, 0x0fb1, 0x0f6e, 0x0f2e, 0x0ef1, 0x0eb6, 0x0e7d, 0x0e47, 0x0e12, 0x0ddf, 0x0dae, 0x0d7e,
83		0x0d50, 0x0d24, 0x0cf8, 0x0cce, 0x0ca6, 0x0c7e, 0x0c57, 0x0c31, 0x0c0d, 0x0be9, 0x0bc6, 0x0ba4, 0x0b82, 0x0b62, 0x0b42, 0x0b23,
84		0x0b04, 0x0ae6, 0x0ac9, 0x0aac, 0x0a90, 0x0a74, 0x0a59, 0x0a3f, 0x0a24, 0x0a0b, 0x09f2, 0x09d9, 0x09c0, 0x09a9, 0x0991, 0x097a,
85		0x0963, 0x094d, 0x0937, 0x0921, 0x090b, 0x08f6, 0x08e2, 0x08cd, 0x08b9, 0x08a5, 0x0891, 0x087e, 0x086b, 0x0858, 0x0845, 0x0833,
86		0x0821, 0x080f, 0x07fe, 0x07ec, 0x07db, 0x07ca, 0x07b9, 0x07a9, 0x0798, 0x0788, 0x0778, 0x0768, 0x0759, 0x0749, 0x073a, 0x072b,
87		0x071c, 0x070d, 0x06fe, 0x06f0, 0x06e2, 0x06d4, 0x06c6, 0x06b8, 0x06aa, 0x069c, 0x068f, 0x0682, 0x0674, 0x0667, 0x065a, 0x064e,
88		0x0641, 0x0634, 0x0628, 0x061c, 0x0610, 0x0603, 0x05f7, 0x05ec, 0x05e0, 0x05d4, 0x05c9, 0x05bd, 0x05b2, 0x05a7, 0x059c, 0x0591,
89		0x0586, 0x057b, 0x0570, 0x0565, 0x055b, 0x0550, 0x0546, 0x053c, 0x0531, 0x0527, 0x051d, 0x0513, 0x0509, 0x04ff, 0x04f6, 0x04ec,
90		0x04e2, 0x04d9, 0x04d0, 0x04c6, 0x04bd, 0x04b4, 0x04ab, 0x04a1, 0x0498, 0x048f, 0x0487, 0x047e, 0x0475, 0x046c, 0x0464, 0x045b,
91		0x0453, 0x044a, 0x0442, 0x043a, 0x0431, 0x0429, 0x0421, 0x0419, 0x0411, 0x0409, 0x0401, 0x03f9, 0x03f2, 0x03ea, 0x03e2, 0x03db,
92		0x03d3, 0x03cc, 0x03c4, 0x03bd, 0x03b5, 0x03ae, 0x03a7, 0x03a0, 0x0398, 0x0391, 0x038a, 0x0383, 0x037c, 0x0375, 0x036f, 0x0368,
93		0x0361, 0x035a, 0x0353, 0x034d, 0x0346, 0x0340, 0x0339, 0x0333, 0x032c, 0x0326, 0x031f, 0x0319, 0x0313, 0x030d, 0x0306, 0x0300,
94		0x02fa, 0x02f4, 0x02ee, 0x02e8, 0x02e2, 0x02dc, 0x02d6, 0x02d1, 0x02cb, 0x02c5, 0x02bf, 0x02ba, 0x02b4, 0x02ae, 0x02a9, 0x02a3,
95		0x029e, 0x0298, 0x0293, 0x028d, 0x0288, 0x0282, 0x027d, 0x0278, 0x0273, 0x026d, 0x0268, 0x0263, 0x025e, 0x0259, 0x0254, 0x024f,
96		0x024a, 0x0245, 0x0240, 0x023b, 0x0236, 0x0231, 0x022c, 0x0228, 0x0223, 0x021e, 0x0219, 0x0215, 0x0210, 0x020b, 0x0207, 0x0202,
97		0x01fe, 0x01f9, 0x01f5, 0x01f0, 0x01ec, 0x01e7, 0x01e3, 0x01df, 0x01da, 0x01d6, 0x01d2, 0x01ce, 0x01c9, 0x01c5, 0x01c1, 0x01bd,
98		0x01b9, 0x01b5, 0x01b1, 0x01ad, 0x01a9, 0x01a5, 0x01a1, 0x019d, 0x0199, 0x0195, 0x0191, 0x018d, 0x018a, 0x0186, 0x0182, 0x017e,
99		0x017a, 0x0177, 0x0173, 0x016f, 0x016c, 0x0168, 0x0165, 0x0161, 0x015e, 0x015a, 0x0157, 0x0153, 0x0150, 0x014c, 0x0149, 0x0145,
100		0x0142, 0x013f, 0x013b, 0x0138, 0x0135, 0x0132, 0x012e, 0x012b, 0x0128, 0x0125, 0x0122, 0x011e, 0x011b, 0x0118, 0x0115, 0x0112,
101		0x010f, 0x010c, 0x0109, 0x0106, 0x0103, 0x0100, 0x00fd, 0x00fb, 0x00f8, 0x00f5, 0x00f2, 0x00ef, 0x00ec, 0x00ea, 0x00e7, 0x00e4,
102		0x00e1, 0x00df, 0x00dc, 0x00d9, 0x00d7, 0x00d4, 0x00d1, 0x00cf, 0x00cc, 0x00ca, 0x00c7, 0x00c5, 0x00c2, 0x00c0, 0x00bd, 0x00bb,
103		0x00b8, 0x00b6, 0x00b4, 0x00b1, 0x00af, 0x00ad, 0x00aa, 0x00a8, 0x00a6, 0x00a3, 0x00a1, 0x009f, 0x009d, 0x009b, 0x0098, 0x0096,
104		0x0094, 0x0092, 0x0090, 0x008e, 0x008c, 0x008a, 0x0088, 0x0086, 0x0084, 0x0082, 0x0080, 0x007e, 0x007c, 0x007a, 0x0078, 0x0076,
105		0x0074, 0x0072, 0x0070, 0x006e, 0x006d, 0x006b, 0x0069, 0x0067, 0x0066, 0x0064, 0x0062, 0x0060, 0x005f, 0x005d, 0x005b, 0x005a,
106		0x0058, 0x0057, 0x0055, 0x0053, 0x0052, 0x0050, 0x004f, 0x004d, 0x004c, 0x004a, 0x0049, 0x0047, 0x0046, 0x0045, 0x0043, 0x0042,
107		0x0040, 0x003f, 0x003e, 0x003c, 0x003b, 0x003a, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033, 0x0032, 0x0031, 0x0030, 0x002f, 0x002e,
108		0x002c, 0x002b, 0x002a, 0x0029, 0x0028, 0x0027, 0x0026, 0x0025, 0x0024, 0x0023, 0x0022, 0x0021, 0x0020, 0x001f, 0x001e, 0x001d,
109		0x001c, 0x001b, 0x001a, 0x001a, 0x0019, 0x0018, 0x0017, 0x0016, 0x0016, 0x0015, 0x0014, 0x0013, 0x0013, 0x0012, 0x0011, 0x0010,
110		0x0010, 0x000f, 0x000e, 0x000e, 0x000d, 0x000d, 0x000c, 0x000b, 0x000b, 0x000a, 0x000a, 0x0009, 0x0009, 0x0008, 0x0008, 0x0007,
111		0x0007, 0x0006, 0x0006, 0x0006, 0x0005, 0x0005, 0x0005, 0x0004, 0x0004, 0x0004, 0x0003, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002,
112		0x0002, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
113		};
114
115		la32_device::la32_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
116		: device_t(mconfig, LA32, "LA32", tag, owner, clock, "la32", __FILE__),
117		device_sound_interface(mconfig, *this),
118		irq_cb(*this),
119		sample_cb(*this)
120		{
121		}
122
123
124		void la32_device::device_start()
125		{
126		irq_cb.resolve_safe();
127		sample_cb.resolve_safe();
128		stream = stream_alloc(0, 4, 32000);
129		timer = timer_alloc(0);
130		timer->adjust(attotime::from_hz(320002), 0, attotime::from_hz(320002));
131		}
132
133		void la32_device::device_reset()
134		{
135		timer_phase = false;
136		irq_count = 0;
137		for(int i=0; i<32; i++)
138		partials[i].reset();
139		}
140
141		void la32_device::ramp_t::reset()
142		{
143		cur_value = 0;
144		increment = 0;
145		target = 0;
146		done = true;
147		}
148
149		bool la32_device::ramp_t::check_done() const
150		{
151		UINT8 value = cur_value >> 18;
152		if(increment & 0x80)
153		return value <= target;
154		else
155		return value >= target;
156		}
157
158		bool la32_device::ramp_t::step()
159		{
160		if(done \|\| !(increment & 0x7f))
161		return false;
162		if(!check_done()) {
163		UINT32 stepval = 0;
164		if(increment & 0x7f) {
165		stepval = (0x40000 \| (exp2_table[(~((increment & 7) << 6)) & 0x1ff] << 6)) >> (15 - ((increment >> 3) & 15));
166		if(increment & 0x80)
167		stepval = ~stepval;
168		cur_value = (cur_value + stepval) & 0x3ffffff;
169		}
170		}
171		if(check_done()) {
172		cur_value = target << 18;
173		done = true;
174		return true;
175		}
176		return false;
177		}
178
179		void la32_device::ramp_t::set_increment(UINT8 i)
180		{
181		increment = i;
182		}
183
184		void la32_device::ramp_t::set_target(UINT8 t)
185		{
186		target = t;
187		done = false;
188		}
189
190		void la32_device::partial_t::reset()
191		{
192		base_adr_cutoff = 0;
193		flags = 0;
194		len_flags = 0;
195		pulse_width = 0;
196		pitch = 0;
197		tva.reset();
198		tvf.reset();
199		irq_ramp = irq_sample = false;
200		}
201
202		astring la32_device::tts(attotime t)
203		{
204		char buf[256];
205		int nsec = t.attoseconds / ATTOSECONDS_PER_NANOSECOND;
206		sprintf(buf, "%4d.%03d,%03d,%03d", int(t.seconds), nsec/1000000, (nsec/1000)%1000, nsec % 1000);
207		return buf;
208		}
209
210		astring la32_device::ttsn()
211		{
212		return tts(machine().time());
213		}
214
215		void la32_device::sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples)
216		{
217		// logerror("%s: %s: stream update %d\n", tag(), ttsn().cstr(), samples);
218		for(int i=0; i<4; i++)
219		memset(outputs[i], 0, samples*sizeof(stream_sample_t));
220		}
221
222		UINT16 la32_device::compute_output_pcm(partial_t &p)
223		{
224		if(p.pitch != 0xffff)
225		fprintf(stderr, "Pitch %04x\n", p.pitch);
226		return 0;
227		}
228
229		UINT16 la32_device::compute_output_synthetic(partial_t &p)
230		{
231		return 0;
232		}
233
234		void la32_device::step_ramp(partial_t &p, ramp_t &r)
235		{
236		if(r.step() && !p.irq_ramp) {
237		p.irq_ramp = true;
238		irq_count++;
239		if(irq_count == 1)
240		irq_cb(true);
241		}
242		}
243
244		UINT16 la32_device::compute_output(partial_t &p)
245		{
246		if(!p.active())
247		return 0;
248		step_ramp(p, p.tva);
249		step_ramp(p, p.tvf);
250		if(p.pcm())
251		return compute_output_pcm(p);
252		else
253		return compute_output_synthetic(p);
254		}
255
256		void la32_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
257		{
258		timer_phase = !timer_phase;
259		sample_cb(timer_phase);
260		if(timer_phase) {
261		for(int i=0; i<32; i+=2) {
262		UINT16 o0 = compute_output(partials[i]);
263		UINT16 o1 = compute_output(partials[i+1]);
264		}
265		}
266		}
267
268		READ8_MEMBER(la32_device::read)
269		{
270		// On 400?
271		// bit 7 = 0, low bits = partial+1, end of sample
272		// bit 7 = 1, bit 5 = 0, ?
273		// bit 7 = 1, bit 5 = 1, ramp done
274
275		offset /= 2;
276		UINT8 res = 0xff;
277		for(int i=0; res == 0xff && i<32; i++) {
278		if(partials[i].irq_sample) {
279		partials[i].irq_sample = false;
280		res = (i+1) & 0x1f;
281		irq_count--;
282
283		} else if(partials[i].irq_ramp) {
284		partials[i].irq_ramp = false;
285		res = 0xc0 \| i;
286		irq_count--;
287		}
288		}
289
290		if(res != 0xff && !irq_count)
291		irq_cb(false);
292
293		logerror("%s: read %03x %02x\n", tag(), offset, res);
294		return res;
295		}
296
297		WRITE8_MEMBER(la32_device::write)
298		{
299		offset /= 2;
300
301		if(offset & 0x400) {
302		int partial = (offset >> 1) & 31;
303		partial_t &p = partials[partial];
304		int slot = ((offset >> 5) & 0xe) \| (offset & 1);
305
306		switch(slot) {
307		case 0x0: // c00
308		p.tva.set_increment(data);
309		break;
310
311		case 0x1: // c02
312		p.tva.set_target(data);
313		logerror("%s:%02x: tva = (%02x, %02x)\n", tag(), partial, p.tva.target, p.tva.increment);
314		break;
315
316		case 0x2: // c80
317		p.pulse_width = data;
318		logerror("%s:%02x: pulse_width = %02x\n", tag(), partial, p.pulse_width);
319		break;
320
321		case 0x3: // c82
322		p.base_adr_cutoff = data;
323		if(p.pcm())
324		logerror("%s:%02x: pcm base adr = %x\n", tag(), partial, p.base_adr());
325		else
326		logerror("%s:%02x: base cutoff = %x\n", tag(), partial, p.base_cutoff());
327		break;
328
329		case 0x4: // d00
330		p.tvf.set_increment(data);
331		break;
332
333		case 0x5: // d02
334		p.tvf.set_target(data);
335		logerror("%s:%02x: tvf = (%02x, %02x)\n", tag(), partial, p.tvf.target, p.tvf.increment);
336		break;
337
338		case 0x6: // d80
339		p.pitch = (p.pitch & 0xff00) \| data;
340		break;
341
342		case 0x7: // d82
343		p.pitch = (p.pitch & 0x00ff) \| (data << 8);
344		logerror("%s:%02x: pitch = %x\n", tag(), partial, p.pitch);
345		break;
346
347		case 0x8: // e00
348		p.flags = data;
349		if(p.active())
350		logerror("%s:%02x: %s, %s=%d, ringmod=%d, chan=%d, pan=%d\n", tag(), partial, p.pcm() ? "pcm" : "synthetic", p.pcm() ? "interp" : "saw", p.pcm() ? p.interpolate() : p.sawtooth(), p.ring_modulation(), p.channel(), p.pan());
351		else
352		logerror("%s:%02x: disabled\n", tag(), partial);
353		break;
354
355		case 0x9: // e02
356		p.len_flags = data;
357		if(p.pcm())
358		logerror("%s:%02x: len=%x, loop=%d\n", tag(), partial, p.len(), p.loop());
359		else
360		logerror("%s:%02x: resonance=%02x\n", tag(), partial, p.resonance());
361		break;
362
363		// a e80
364		// b e82
365		// c f00
366		// d f02
367		// e f80
368		// f f82
369
370		default:
371		logerror("%s: write %02x.%02x, %02x (%x)\n", tag(), partial, slot, data, space.device().safe_pc());
372		break;
373		}
374
375		} else
376		logerror("%s: write %03x, %02x\n", tag(), offset, data);
377		}
378

trunk/src/emu/sound/la32.h
r243812	r243813
1		#ifndef __LA32_H__
2		#define __LA32_H__
3
4		#define MCFG_LA32_ADD(_tag) \
5		MCFG_DEVICE_ADD(_tag, LA32, 0)
6
7		#define MCFG_LA32_IRQ_CALLBACK(_cb) \
8		downcast<la32_device *>(device)->set_irq(DEVCB_##_cb);
9
10		#define MCFG_LA32_SAMPLE_CALLBACK(_cb) \
11		downcast<la32_device *>(device)->set_sample(DEVCB_##_cb);
12
13		class la32_device : public device_t,
14		public device_sound_interface
15		{
16		public:
17		la32_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
18
19		DECLARE_READ8_MEMBER(read);
20		DECLARE_WRITE8_MEMBER(write);
21
22		template<class _cb> void set_irq(_cb cb) {
23		irq_cb.set_callback(cb);
24		}
25
26		template<class _cb> void set_sample(_cb cb) {
27		sample_cb.set_callback(cb);
28		}
29
30		protected:
31		virtual void device_start();
32		virtual void device_reset();
33		virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
34		virtual void sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples);
35
36		private:
37		const static UINT16 exp2_table[0x200];
38		const static UINT8 exp2_delta_table[0x200];
39		const static UINT16 logsin_table[0x200];
40
41		struct ramp_t {
42		UINT32 cur_value;
43		UINT8 increment;
44		UINT8 target;
45		bool done;
46
47		bool check_done() const;
48		bool step();
49		void reset();
50		void set_increment(UINT8 i);
51		void set_target(UINT8 t);
52		};
53
54		struct partial_t {
55		ramp_t tva, tvf;
56
57		UINT16 pitch;
58		UINT8 base_adr_cutoff;
59		UINT8 flags, len_flags, pulse_width;
60
61		bool irq_ramp, irq_sample;
62
63		bool pcm() const { return flags & 0x80; }
64		bool interpolate() const { return flags & 0x40; }
65		bool sawtooth() const { return flags & 0x40; }
66		bool ring_modulation() { return flags & 0x20; }
67		bool active() const { return flags & 0x10; }
68		bool channel() const { return flags & 0x08; }
69		UINT8 pan() const { return flags & 0x07; }
70
71		UINT32 base_adr() const { return ((len_flags & 1) << 19) \| (base_adr_cutoff << 11); }
72		UINT8 base_cutoff() const { return base_adr_cutoff; }
73		UINT32 len() const { return 0x800 << ((len_flags >> 4) & 7); }
74		bool loop() const { return len_flags & 0x80; }
75		UINT8 resonance() const { return len_flags & 0x1f; }
76		void reset();
77		};
78
79		bool timer_phase;
80		sound_stream *stream;
81		emu_timer *timer;
82		partial_t partials[32];
83		int irq_count;
84
85		devcb_write_line irq_cb, sample_cb;
86
87		astring tts(attotime t);
88		astring ttsn();
89
90		void step_ramp(partial_t &p, ramp_t &r);
91		UINT16 compute_output_pcm(partial_t &p);
92		UINT16 compute_output_synthetic(partial_t &p);
93		UINT16 compute_output(partial_t &p);
94		};
95
96		extern const device_type LA32;
97
98		#endif

trunk/src/emu/sound/sound.mak
r243812	r243813
360	360	endif
361	361
362	362
363		#-------------------------------------------------
364		# Roland LA32 Linear-additive synthesis chip
365		#-------------------------------------------------
366	363
367		ifneq ($(filter LA32,$(SOUNDS)),)
368		SOUNDOBJS += $(SOUNDOBJ)/la32.o
369		endif
370
371
372
373	364	#-------------------------------------------------
374	365	# LMC1992 mixer chip
375	366	#@src/emu/sound/lmc1992.h,SOUNDS += LMC1992

trunk/src/emu/ui/ui.c
r243812	r243813
316	316
317	317	// disable everything if we are using -str for 300 or fewer seconds, or if we're the empty driver,
318	318	// or if we are debugging
319		if (~~1 \|\|~~ !first_time \|\| (str > 0 && str < 60*5) \|\| &machine().system() == &GAME_NAME(___empty) \|\| (machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	319	if (!first_time \|\| (str > 0 && str < 60*5) \|\| &machine().system() == &GAME_NAME(___empty) \|\| (machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
320	320	show_gameinfo = show_warnings = show_disclaimer = show_mandatory_fileman = FALSE;
321	321
322	322	#ifdef SDLMAME_EMSCRIPTEN

trunk/src/lib/formats/ap2_dsk.c
r243812	r243813
444	444	}
445	445	xorvalue ^= oldvalue;
446	446	nibble[28+i] = translate6[xorvalue & 0x3F];
447		if(track == 0)
448		fprintf(stderr, "%x.%03x: %02x %02x\n", sector, i, oldvalue, nibble[28+i]);
449	447	xorvalue = oldvalue;
450	448	}
451	449
r243812	r243813
701	699	raw_w(track_data, offset, 24, 0xd5aaad);
702	700
703	701	UINT8 pval = 0x00;
704		int ss=i;
705	702	for(int i=0; i<342; i++) {
706	703	UINT8 nval;
707	704	if(i >= 0x56)
r243812	r243813
717	714	((sdata[i+0xac] & 0x01) << 5) \|
718	715	((sdata[i+0xac] & 0x02) << 3);
719	716	}
720		if(track == 0)
721		fprintf(stderr, "%x.%03x: %02x %02x\n", ss, i, nval, translate6[nval ^ pval]);
722	717	raw_w(track_data, offset, 8, translate6[nval ^ pval]);
723	718	pval = nval;
724	719	}

trunk/src/mame/drivers/csplayh5.c
r243812	r243813
21	21	After returning a correct status code, tmp68301 sends "FSDVD04.MPG00001<CR>" to serial, probably tries
22	22	to playback the file ...
23	23
24		serial: prescaler (spr) = a0
25		baud rate (sbrr0) = 2
26
27		H8 typing:
28		- at least h8h
29		- watchdog at ffffffaa/ffffffa8 = a500 5a00 ok 3002 3044
30		- ffffffaf/ad/ac = 05 18 23 ok 3002 3044 (refresh controller)
31		- p6ddr \|= 06
32		- p6dr \|= 02
33		- p8ddr = fe
34		- p8dr = ff
35		- p9ddr = c3
36		- p9dr = cf
37		- paddr = ff
38		- padr = 1f
39		- pbddr = 3f
40		- pbdr = 19
41		- abwcr = 06
42		- ipra = 1f a4/a3/a2/a1/a0
43		- iprb = e8 b7/b6/b5/b3
44		- ier = 00
45		- iscr = 10
46		- tstr = e0
47		- tsnc = e0
48		- tmdr = 80
49		(etc)
50
51
52	24	***********************************************************************************************************/
53	25
54	26	#include "emu.h"
r243812	r243813
88	60	DECLARE_READ16_MEMBER(test_r);
89	61	DECLARE_READ8_MEMBER(csplayh5_sound_r);
90	62	DECLARE_WRITE8_MEMBER(csplayh5_soundclr_w);
91		DECLARE_READ8_MEMBER(r40020_r);
92		DECLARE_WRITE8_MEMBER(r40020_w);
	63
93	64	DECLARE_READ8_MEMBER(soundcpu_portd_r);
94	65	DECLARE_WRITE8_MEMBER(soundcpu_porta_w);
95	66	DECLARE_WRITE8_MEMBER(soundcpu_dac2_w);
96	67	DECLARE_WRITE8_MEMBER(soundcpu_dac1_w);
97	68	DECLARE_WRITE8_MEMBER(soundcpu_porte_w);
98	69
99		DECLARE_READ8_MEMBER(ext_r);
100		DECLARE_WRITE8_MEMBER(ext_w);
101
102	70	DECLARE_DRIVER_INIT(mjmania);
103	71	DECLARE_DRIVER_INIT(csplayh5);
104	72	DECLARE_DRIVER_INIT(fuudol);
r243812	r243813
116	84
117	85
118	86
	87	#define USE_H8 0
	88
119	89	// from MSX2 driver, may be not accurate for this HW
120	90	#define MSX2_XBORDER_PIXELS 16
121	91	#define MSX2_YBORDER_PIXELS 28
r243812	r243813
171	141	AM_RANGE(0xc00000, 0xc7ffff) AM_RAM AM_SHARE("nvram") AM_MIRROR(0x380000) // work RAM
172	142	ADDRESS_MAP_END
173	143
	144	#if USE_H8
174	145	READ16_MEMBER(csplayh5_state::test_r)
175	146	{
176	147	return machine().rand();
177	148	}
178	149
179		READ8_MEMBER(csplayh5_state::r40020_r)
180		{
181		logerror("read %05x (%06x)\n", 0x40020+offset, int(space.device().safe_pc()));
182		if(space.device().safe_pc() == 0x7a54)
183		return 0x08;
184		if(space.device().safe_pc() == 0x7a3c)
185		return 0x01;
186		return 0x00;
187		}
188
189		WRITE8_MEMBER(csplayh5_state::r40020_w)
190		{
191		logerror("%05x = %02x (%06x)\n", 0x40020+offset, data, int(space.device().safe_pc()));
192		}
193
194	150	static ADDRESS_MAP_START( csplayh5_sub_map, AS_PROGRAM, 16, csplayh5_state )
195	151	AM_RANGE(0x000000, 0x01ffff) AM_ROM
196	152
197		AM_RANGE(0x020008, 0x02000f) AM_READWRITE8(ext_r, ext_w, 0xff00)
	153	AM_RANGE(0x04002a, 0x04002b) AM_READ(test_r)
	154	AM_RANGE(0x040036, 0x040037) AM_READ(test_r)
198	155
199		AM_RANGE(0x040020, 0x04002f) AM_READWRITE8(r40020_r, r40020_w, 0xffff)
200
201	156	AM_RANGE(0x078000, 0x07ffff) AM_RAM AM_SHARE("nvram")
202	157	AM_RANGE(0x080000, 0x0fffff) AM_RAM
203	158	ADDRESS_MAP_END
r243812	r243813
206	161	static ADDRESS_MAP_START( csplayh5_sub_io_map, AS_IO, 16, csplayh5_state )
207	162
208	163	ADDRESS_MAP_END
	164	#endif
209	165
210	166
211		READ8_MEMBER(csplayh5_state::ext_r)
212		{
213		return 0x08;
214		}
215
216		WRITE8_MEMBER(csplayh5_state::ext_w)
217		{
218		// logerror("ext_w %d, %02x\n", offset, data);
219		}
220
221	167	/*
222	168	sound HW is identical to Niyanpai
223	169	*/
r243812	r243813
275	221	}
276	222
277	223
	224
	225
	226
	227
278	228	static ADDRESS_MAP_START( csplayh5_sound_map, AS_PROGRAM, 8, csplayh5_state )
279	229	AM_RANGE(0x0000, 0x77ff) AM_ROM
280	230	AM_RANGE(0x7800, 0x7fff) AM_RAM
r243812	r243813
507	457	static MACHINE_CONFIG_START( csplayh5, csplayh5_state )
508	458
509	459	/* basic machine hardware */
510		MCFG_CPU_ADD("maincpu",M68000,16000000) /* TMP68301-16~~, gives a 6250bps serial~~ */
	460	MCFG_CPU_ADD("maincpu",M68000,16000000) /* TMP68301-16 */
511	461	MCFG_CPU_PROGRAM_MAP(csplayh5_map)
512	462	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
513	463
514	464	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", csplayh5_state, csplayh5_irq, "screen", 0, 1)
515	465
516		MCFG_~~TMP68301~~_ADD("tmp68301", ~~"maincpu"~~)
	466	MCFG_DEVICE_ADD("tmp68301", TMP68301, 0)
517	467
518		MCFG_CPU_ADD("subcpu", H83002, 17600000) /* unknown clock, 17.6MHz gives a 6250bps serial too */
	468	#if USE_H8
	469	MCFG_CPU_ADD("subcpu", H83002, 16000000) /* unknown clock */
519	470	MCFG_CPU_PROGRAM_MAP(csplayh5_sub_map)
520	471	MCFG_CPU_IO_MAP(csplayh5_sub_io_map)
	472	#endif
521	473
522	474	MCFG_CPU_ADD("audiocpu", TMPZ84C011, 8000000) /* TMPZ84C011, unknown clock */
523	475	MCFG_CPU_CONFIG(daisy_chain_sound)

trunk/src/mame/drivers/namcos23.c
r243812	r243813
84	84	return
85	85
86	86
87		c8000000:
88		8011e384:
89		if((a2000000.w & 0xfff0 != 0x0080) (c417_r, 808e or 008e)
90		+10.w = 2
91		+16.w = 42
92		+16.w = 23c0
93		+10.w = 3
94		801deaf0.w *0x28 -> +12.w (fixed)
95
96
97
98
99		':maincpu' (801142FC): unmapped program memory write to 0C800010 = 00020000 & FFFF0000
100		':maincpu' (801143A8): unmapped program memory write to 0C800010 = 00020000 & FFFF0000
101		':maincpu' (801143B4): unmapped program memory write to 0C800014 = 00000042 & 0000FFFF
102		':maincpu' (801143C0): unmapped program memory write to 0C800014 = 000023C0 & 0000FFFF
103		':maincpu' (801143CC): unmapped program memory write to 0C800010 = 00030000 & FFFF0000
104		':maincpu' (801143E0): unmapped program memory write to 0C800010 = 00000000 & 0000FFFF
105		':maincpu' (801143E0): unmapped program memory write to 0C800010 = 00000000 & 0000FFFF
106		':maincpu' (801143E0): unmapped program memory write to 0C800010 = 00000000 & 0000FFFF
107		':maincpu' (801143E0): unmapped program memory write to 0C800010 = 00000000 & 0000FFFF
108
109	87	****************************************************************************
110	88
111	89	Namco System 23 and Super System 23 Hardware Overview (last updated 7th April 2013 at 12.49am)
r243812	r243813
1283	1261
1284	1262	enum { MODEL, FLUSH };
1285	1263
1286		#define RECORD 0
1287
1288		FILE *videolog;
1289
1290	1264	struct namcos23_render_entry
1291	1265	{
1292	1266	int type;
r243812	r243813
1542	1516	UINT16 nthword(const UINT32 *pSource, int offs);
1543	1517	inline INT32 u32_to_s24(UINT32 v);
1544	1518	inline INT32 u32_to_s10(UINT32 v);
1545		float f24_to_f32(UINT32 v);
1546
1547	1519	INT32 *c435_getv(UINT16 id);
1548	1520	INT16 *c435_getm(UINT16 id);
1549	1521
1550		void c435_state_set_interrupt(const UINT16 *param);
1551		void c435_state_set_projection_matrix_line(const UINT16 *param);
1552		void c435_state_set(UINT16 type, const UINT16 *param);
1553		int c435_get_state_entry_size(UINT16 type);
1554
1555	1522	void c435_matrix_matrix_mul();
1556	1523	void c435_matrix_set();
1557	1524	void c435_vector_set();
1558	1525	void c435_matrix_vector_mul();
1559	1526	void c435_vector_matrix_mul();
1560		void c435_state_set();
1561	1527	void c435_scaling_set();
	1528	void c435_state_set_interrupt();
	1529	void c435_state_set();
1562	1530	void c435_render();
1563	1531	void c435_flush();
1564	1532
r243812	r243813
1608	1576	return v & 0x200 ? v \| 0xfffffe00 : v & 0x1ff;
1609	1577	}
1610	1578
1611		float namcos23_state::f24_to_f32(UINT32 v)
1612		{
1613		// 8 bits exponent, 16 mantissa
1614		// mantissa is 16-bits signed, 2-complement
1615		// value is m * 2**(e-46)
1616		// 1 is e=32, m=0x4000, -1 is e=31, m=0x8000
1617	1579
1618		// This code turns it into a standard float
1619		if(!v)
1620		return 0;
1621
1622		UINT32 r = v & 0x8000 ? 0x80000000 : 0;
1623		UINT16 m = r ? -v : v;
1624		UINT8 e = (v >> 16) + 0x60;
1625		while(!(m & 0x8000)) {
1626		m <<= 1;
1627		e--;
1628		}
1629
1630		r = r \| (e << 23) \| ((m & 0x7fff) << 8);
1631		return (float )&r;
1632		}
1633
1634	1580	INLINE UINT8 light(UINT8 c, float l)
1635	1581	{
1636	1582	if(l < 1)
r243812	r243813
1662	1608	return m_matrices[id];
1663	1609	}
1664	1610
1665		void namcos23_state::c435_state_set_interrupt(const UINT16 *param)
1666		{
1667		if(param[0] & 1)
1668		update_main_interrupts(m_main_irqcause \| MAIN_C435_IRQ);
1669		else
1670		update_main_interrupts(m_main_irqcause & ~MAIN_C435_IRQ);
1671		}
1672
1673		void namcos23_state::c435_state_set_projection_matrix_line(const UINT16 *param)
1674		{
1675		// timecrs2:
1676		// sx = 640/2, sy = 480/2, t = tan(fov/2) (fov=45 degrees)
1677		// line 1: 1 0 -(sx-a)/(sx/t) 0 -1 0 -(sx+a)/(sx/t) 0
1678		// line 2: 0 1 -(sy-b)/(sx/t) 0 0 -1 -(sy+b)/(sx/t) 0
1679		// line 3: 0 0 -1 c 0 0 0 sx/t
1680
1681		/*
1682		f/ar 0 0 0
1683		0 f 0 0
1684		0 0 (F+N)/(N-F) 2FN/(N-F)
1685		0 0 -1 0
1686		*/
1687
1688		logerror("projection matrix line:");
1689		for(int i=0; i<8; i++)
1690		logerror(" %f", f24_to_f32((param[2i+1] << 16) \| param[2i+2]));
1691		logerror("\n");
1692		}
1693
1694		void namcos23_state::c435_state_set(UINT16 type, const UINT16 *param)
1695		{
1696		switch(type) {
1697		case 0x0001: c435_state_set_interrupt(param); break;
1698		case 0x00c8: c435_state_set_projection_matrix_line(param); break;
1699		default:
1700		// logerror("WARNING: Unhandled state type %04x\n", type);
1701		break;
1702		}
1703		}
1704
1705		int namcos23_state::c435_get_state_entry_size(UINT16 type)
1706		{
1707		switch(type) {
1708		case 0x0001: return 1;
1709		case 0x0009: return 19;
1710		case 0x0042: return 41;
1711		case 0x0046: return 13;
1712		case 0x00c0: return 33;
1713		case 0x00c6: return 13;
1714		case 0x00c8: return 17;
1715		default:
1716		logerror("WARNING: Unknown size for state type %04x\n", type);
1717		return -1;
1718		}
1719		}
1720
1721	1611	void namcos23_state::c435_matrix_matrix_mul() // 0.0
1722	1612	{
1723	1613	if((m_c435_buffer[0] & 0xf) != 4)
r243812	r243813
1728	1618	if(m_c435_buffer[3] != 0xffff)
1729	1619	logerror("WARNING: c435_matrix_matrix_mul with +2=%04x\n", m_c435_buffer[3]);
1730	1620
1731
1732		if(0 && m_c435_buffer[0] != 0x0004)
1733		fprintf(stderr, "c435_matrix_matrix_mul header %04x\n", m_c435_buffer[0]);
1734		if(m_c435_buffer[3] != 0xffff)
1735		fprintf(stderr, "c435_matrix_matrix_mul with +2=%04x\n", m_c435_buffer[3]);
1736
1737
1738	1621	INT16 *t = c435_getm(m_c435_buffer[1]);
1739	1622	const INT16 *m2 = c435_getm(m_c435_buffer[2]);
1740	1623	const INT16 *m1 = c435_getm(m_c435_buffer[4]);
r243812	r243813
1758	1641	return;
1759	1642	}
1760	1643
1761		if(1 && m_c435_buffer[0] != 0x0814 && m_c435_buffer[0] != 0x1014)
1762		fprintf(stderr, "c435_matrix_vector_mul header %04x\n", m_c435_buffer[0]);
1763
1764
1765	1644	if(m_c435_buffer[3] != 0xffff) {
1766	1645	INT32 *t = c435_getv(m_c435_buffer[1]);
1767	1646	const INT16 *m = c435_getm(m_c435_buffer[2]);
r243812	r243813
1790	1669	logerror("WARNING: c435_matrix_set with size %d\n", m_c435_buffer[0] & 0xf);
1791	1670	return;
1792	1671	}
1793
1794		if(m_c435_buffer[0] != 0x004a)
1795		fprintf(stderr, "c435_matrix_set header %04x\n", m_c435_buffer[0]);
1796
1797	1672	INT16 *t = c435_getm(m_c435_buffer[1]);
1798	1673	for(int i=0; i<9; i++)
1799	1674	t[i] = m_c435_buffer[i+2];
r243812	r243813
1806	1681	logerror("WARNING: c435_vector_set with size %d\n", m_c435_buffer[0] & 0xf);
1807	1682	return;
1808	1683	}
1809		if(m_c435_buffer[0] != 0x057)
1810		fprintf(stderr, "c435_vector_set header %04x\n", m_c435_buffer[0]);
1811
1812	1684	INT32 *t = c435_getv(m_c435_buffer[1]);
1813	1685	for(int i=0; i<3; i++)
1814	1686	t[i] = u32_to_s24((m_c435_buffer[2i+2] << 16) \| m_c435_buffer[2i+3]);
r243812	r243813
1824	1696	m_scaling = m_c435_buffer[1];
1825	1697	}
1826	1698
1827		void namcos23_state::c435_state_set() // 4.f
	1699	void namcos23_state::c435_state_set_interrupt() // 4.f.0001
1828	1700	{
1829		if((m_c435_buffer[0] & 0xf~~f) ==~~ 0)
	1701	if(m_c435_buffer[0] != 0x4f02)
1830	1702	{
1831		logerror("WARNING: c435_state_set with ~~zero~~ size\n");
	1703	logerror("WARNING: c435_state_set_interrupt with size %d\n", m_c435_buffer[0] & 0xff);
1832	1704	return;
1833	1705	}
1834		int size = c435_get_state_entry_size(m_c435_buffer[1]);
1835		if(size != (m_c435_buffer[0] & 0xff)-1)
	1706	if(m_c435_buffer[2] & 1)
	1707	update_main_interrupts(m_main_irqcause \| MAIN_C435_IRQ);
	1708	else
	1709	update_main_interrupts(m_main_irqcause & ~MAIN_C435_IRQ);
	1710	}
	1711
	1712	void namcos23_state::c435_state_set() // 4.f
	1713	{
	1714	if((m_c435_buffer[0] & 0xff) == 0)
1836	1715	{
1837		logerror("WARNING: c435_state_set size ~~disagreement (type=~~%~~04x, got %~~d~~, expected %d)~~\n", m_c435_buffer[~~1], (m_c435_buffer[~~0] & 0xff~~)-1, size~~);
	1716	logerror("WARNING: c435_state_set with size %d\n", m_c435_buffer[0] & 0xff);
1838	1717	return;
1839	1718	}
1840
1841		c435_state_set(m_c435_buffer[1], m_c435_buffer+2);
	1719	switch(m_c435_buffer[1]) {
	1720	case 0x0001: c435_state_set_interrupt(); break;
	1721	default:
	1722	logerror("WARNING: c435_state_set(%04x, ...)\n", m_c435_buffer[1]);
	1723	break;
	1724	}
1842	1725	}
1843	1726
1844	1727	void namcos23_state::c435_render() // 8
1845	1728	{
1846	1729	if((m_c435_buffer[0] & 0xf) != 3)
1847	1730	{
1848		logerror("WARNING: c435_render with size %d, header %04x\n", m_c435_buffer[0] & 0xf, m_c435_buffer[0]);
	1731	logerror("WARNING: c435_render with size %d, header %04x", m_c435_buffer[0] & 0xf, m_c435_buffer[0]);
1849	1732	return;
1850	1733	}
1851	1734
r243812	r243813
1870	1753	re->model.scaling = use_scaling ? m_scaling / 16384.0 : 1.0;
1871	1754	memcpy(re->model.m, m, sizeof(re->model.m));
1872	1755	memcpy(re->model.v, v, sizeof(re->model.v));
1873		// re->model.v[2] *= 768/420.0;
1874
1875	1756	if(0)
1876		fprintf(stderr, "Render %04x (%f %f %f %f %f %f %f %f %f) (%f %f %f) %f\n",
	1757	fprintf(stderr, "Render %04x (%f %f %f %f %f %f %f %f %f) (%f %f %f)\n",
1877	1758	re->model.model,
1878	1759	re->model.m[0]/16384.0, re->model.m[1]/16384.0, re->model.m[2]/16384.0,
1879	1760	re->model.m[3]/16384.0, re->model.m[4]/16384.0, re->model.m[5]/16384.0,
1880	1761	re->model.m[6]/16384.0, re->model.m[7]/16384.0, re->model.m[8]/16384.0,
1881		re->model.v[0]/16384.0, re->model.v[1]/16384.0, re->model.v[2]/16384.0,
1882		re->model.scaling);
	1762	re->model.v[0]/16384.0, re->model.v[1]/16384.0, re->model.v[2]/16384.0);
1883	1763
1884	1764	render.count[render.cur]++;
1885	1765	}
r243812	r243813
1911	1791	if(m_c435_buffer_pos < psize+1)
1912	1792	return;
1913	1793
1914		if(RECORD) {
1915		fprintf(videolog, "cmd");
1916		for(int p=0; p<m_c435_buffer_pos; p++)
1917		fprintf(videolog, " %04x", m_c435_buffer[p]);
1918		fprintf(videolog, "\n");
1919		fflush(videolog);
1920		}
1921
1922	1794	bool known = true;
1923	1795	switch(h & 0xc000) {
1924	1796	case 0x0000:
r243812	r243813
1955	1827
1956	1828	void namcos23_state::c435_dma(address_space &space, UINT32 adr, UINT32 size)
1957	1829	{
1958		UINT32 oadr = adr;
1959	1830	adr &= 0x1fffffff;
1960	1831
1961
1962		for(int pos=0; pos < size; pos += 2) {
1963		UINT16 v0, v1;
1964		v0 = space.read_word(adr+pos);
1965		v1 = space.read_word(adr+pos+2);
1966
1967		if(v0 == 0x8083 && v1 == 0x0d9e)
1968		fprintf(stderr, "adr=%x %04x %04x\n", oadr+pos, v0, v1);
1969		}
1970
1971	1832	for(int pos=0; pos < size; pos += 2)
1972	1833	c435_pio_w(space.read_word(adr+pos));
1973	1834	}
r243812	r243813
2059	1920	// 480/(2.34375/3.75) = 768
2060	1921
2061	1922	float w = pv.p[0] ? 1/pv.p[0] : 0;
2062		#if 1
2063	1923	pv.x = 320 + 768wpv.x;
2064	1924	pv.y = 240 - 768wpv.y;
2065		#else
2066		pv.x = 320 + 410wpv.x;
2067		pv.y = 240 - 410wpv.y;
2068		#endif
2069	1925	pv.p[0] = w;
2070	1926	}
2071	1927
r243812	r243813
2091	1947	void namcos23_state::render_one_model(const namcos23_render_entry *re)
2092	1948	{
2093	1949	render_t &render = m_render;
2094		if(re->model.model < 0x80) {
2095		logerror("WARNING: model %02x requested\n", re->model.model);
2096		return;
2097		}
2098
2099		if(re->model.model == 3486)
2100		return;
2101
2102	1950	UINT32 adr = m_ptrom[re->model.model];
2103	1951	if(adr >= m_ptrom_limit)
2104	1952	{
r243812	r243813
2354	2202
2355	2203	m_vblank_count++;
2356	2204
2357		if(RECORD) {
2358		fprintf(videolog, "vsync\n");
2359		fflush(videolog);
2360		}
2361
2362	2205	return 0;
2363	2206	}
2364	2207
r243812	r243813
3381	3224	m_c361.timer->adjust(attotime::never);
3382	3225
3383	3226	m_maincpu->mips3drc_add_fastram(0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr()));
3384
3385		if(RECORD) {
3386		videolog = fopen("namcos23-log.txt", "w");
3387		}
3388	3227	}
3389	3228
3390	3229

trunk/src/mame/drivers/naomi.c
r243812	r243813
1510	1510	#include "includes/dc.h"
1511	1511	#include "includes/naomi.h"
1512	1512
1513		#define CPU_CLOCK (75000000)
	1513	#define CPU_CLOCK (200000000)
1514	1514
1515	1515	READ64_MEMBER(naomi_state::naomi_arm_r )
1516	1516	{
r243812	r243813
1634	1634	AM_RANGE(0x0103ff00, 0x0103ffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
1635	1635
1636	1636	/* Area 1 */
1637		AM_RANGE(0x04000000, 0x04ffffff) AM_DEVREADWRITE ("powervr2", powervr2_device, tex64_r, tex64_w)
1638		AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE32("powervr2", powervr2_device, tex32_r, tex32_w, U64(0xffffffffffffffff))
	1637	AM_RANGE(0x04000000, 0x04ffffff) AM_MIRROR(0x02000000) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
	1638	AM_RANGE(0x05000000, 0x05ffffff) AM_MIRROR(0x02000000) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
1639	1639
1640	1640	/* Area 2*/
1641	1641	AM_RANGE(0x08000000, 0x09ffffff) AM_MIRROR(0x02000000) AM_NOP // 'Unassigned'
r243812	r243813
1690	1690	AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
1691	1691
1692	1692	/* Area 1 */
1693		AM_RANGE(0x04000000, 0x04ffffff) AM_DEVREADWRITE ("powervr2", powervr2_device, tex64_r, tex64_w)
1694		AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE32("powervr2", powervr2_device, tex32_r, tex32_w, U64(0xffffffffffffffff))
1695		// AM_RANGE(0x06000000, 0x06ffffff) AM_RAM AM_SHARE("textureram2") // 64 bit access 2nd PVR RAM
1696		// AM_RANGE(0x07000000, 0x07ffffff) AM_RAM AM_SHARE("frameram2")// 32 bit access 2nd PVR RAM
	1693	AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
	1694	AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
	1695	AM_RANGE(0x06000000, 0x06ffffff) AM_RAM AM_SHARE("textureram2") // 64 bit access 2nd PVR RAM
	1696	AM_RANGE(0x07000000, 0x07ffffff) AM_RAM AM_SHARE("frameram2")// 32 bit access 2nd PVR RAM
1697	1697
1698	1698	/* Area 2*/
1699	1699	AM_RANGE(0x085f6800, 0x085f69ff) AM_WRITE(dc_sysctrl_w ) // writes to BOTH PVRs
r243812	r243813
1854	1854	AM_RANGE(0x0103ff00, 0x0103ffff) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
1855	1855
1856	1856	/* Area 1 - half the texture memory, like dreamcast, not naomi */
1857		AM_RANGE(0x04000000, 0x04ffffff) AM_DEVREADWRITE ("powervr2", powervr2_device, tex64_r, tex64_w)
1858		AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE32("powervr2", powervr2_device, tex32_r, tex32_w, U64(0xffffffffffffffff))
	1857	AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_MIRROR(0x00800000) AM_SHARE("dc_texture_ram") // texture memory 64 bit access
	1858	AM_RANGE(0x05000000, 0x057fffff) AM_RAM AM_MIRROR(0x00800000) AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
1859	1859
1860	1860	/* Area 2*/
1861	1861	AM_RANGE(0x08000000, 0x0bffffff) AM_NOP // 'Unassigned'

trunk/src/mame/drivers/niyanpai.c
r243812	r243813
774	774	MCFG_CPU_VBLANK_INT_DRIVER("screen", niyanpai_state, niyanpai_interrupt)
775	775	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
776	776
777		MCFG_~~TMP68301~~_ADD("tmp68301", ~~"maincpu"~~)
	777	MCFG_DEVICE_ADD("tmp68301", TMP68301, 0)
778	778	MCFG_TMP68301_OUT_PARALLEL_CB(WRITE16(niyanpai_state, tmp68301_parallel_port_w))
779	779
780	780	MCFG_CPU_ADD("audiocpu", TMPZ84C011, 8000000) /* TMPZ84C011, 8.00 MHz */

trunk/src/mame/drivers/realbrk.c
r243812	r243813
758	758	MCFG_CPU_VBLANK_INT_DRIVER("screen", realbrk_state, realbrk_interrupt)
759	759	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
760	760
761		MCFG_~~TMP68301~~_ADD("tmp68301", ~~"maincpu"~~)
	761	MCFG_DEVICE_ADD("tmp68301", TMP68301, 0)
762	762	MCFG_TMP68301_OUT_PARALLEL_CB(WRITE16(realbrk_state,realbrk_flipscreen_w))
763	763
764	764	/* video hardware */

trunk/src/mame/drivers/seta2.c
r243812	r243813
2093	2093	MCFG_CPU_VBLANK_INT_DRIVER("screen", seta2_state, seta2_interrupt)
2094	2094	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
2095	2095
2096		MCFG_~~TMP68301~~_ADD("tmp68301", ~~"maincpu"~~)
	2096	MCFG_DEVICE_ADD("tmp68301", TMP68301, 0)
2097	2097
2098	2098	// video hardware
2099	2099	MCFG_SCREEN_ADD("screen", RASTER)
r243812	r243813
2325	2325	MCFG_CPU_VBLANK_INT_DRIVER("screen", seta2_state, seta2_interrupt)
2326	2326	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
2327	2327
2328		MCFG_~~TMP68301~~_ADD("tmp68301", ~~"maincpu"~~) // does this have a ticket dispenser?
	2328	MCFG_DEVICE_ADD("tmp68301", TMP68301, 0) // does this have a ticket dispenser?
2329	2329
2330	2330	// video hardware
2331	2331	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mame/includes/dc.h
r243812	r243813
17	17	public:
18	18	dc_state(const machine_config &mconfig, device_type type, const char *tag)
19	19	: driver_device(mconfig, type, tag),
	20	dc_framebuffer_ram(*this, "frameram"),
	21	dc_texture_ram(*this, "dc_texture_ram"),
20	22	dc_sound_ram(*this, "dc_sound_ram"),
21	23	dc_ram(*this, "dc_ram"),
22	24	m_maincpu(*this, "maincpu"),
r243812	r243813
26	28	m_naomig1(*this, "rom_board"),
27	29	m_aica(*this, "aica") { }
28	30
	31	required_shared_ptr<UINT64> dc_framebuffer_ram; // '32-bit access area'
	32	required_shared_ptr<UINT64> dc_texture_ram; // '64-bit access area'
	33
29	34	required_shared_ptr<UINT32> dc_sound_ram;
30	35	required_shared_ptr<UINT64> dc_ram;
31	36

trunk/src/mame/video/powervr2.c
r243812	r243813
15	15	DEVICE_ADDRESS_MAP_START(ta_map, 32, powervr2_device)
16	16	AM_RANGE(0x0000, 0x0003) AM_READ( id_r)
17	17	AM_RANGE(0x0004, 0x0007) AM_READ( revision_r)
18		AM_RANGE(0x0008, 0x000b) AM_READWRITE(softreset_r, softreset_w)
19		AM_RANGE(0x0014, 0x0017) AM_READWRITE(startrender_r, startrender_w)
20		AM_RANGE(0x0018, 0x001f) AM_READWRITE(test_select_r, test_select_w)
21		AM_RANGE(0x0020, 0x0023) AM_READWRITE(param_base_r, param_base_w)
22		AM_RANGE(0x002c, 0x002f) AM_READWRITE(region_base_r, region_base_w)
23		AM_RANGE(0x0030, 0x0034) AM_READWRITE(span_sort_cfg_r, span_sort_cfg_w)
24		AM_RANGE(0x0040, 0x0043) AM_READWRITE(vo_border_col_r, vo_border_col_w)
25		AM_RANGE(0x0044, 0x0047) AM_READWRITE(fb_r_ctrl_r, fb_r_ctrl_w)
26		AM_RANGE(0x0048, 0x004b) AM_READWRITE(fb_w_ctrl_r, fb_w_ctrl_w)
27		AM_RANGE(0x004c, 0x004f) AM_READWRITE(fb_w_linestride_r, fb_w_linestride_w)
28		AM_RANGE(0x0050, 0x0053) AM_READWRITE(fb_r_sof1_r, fb_r_sof1_w)
29		AM_RANGE(0x0054, 0x0057) AM_READWRITE(fb_r_sof2_r, fb_r_sof2_w)
30		AM_RANGE(0x005c, 0x005f) AM_READWRITE(fb_r_size_r, fb_r_size_w)
31		AM_RANGE(0x0060, 0x0063) AM_READWRITE(fb_w_sof1_r, fb_w_sof1_w)
32		AM_RANGE(0x0064, 0x0067) AM_READWRITE(fb_w_sof2_r, fb_w_sof2_w)
33		AM_RANGE(0x0068, 0x006b) AM_READWRITE(fb_x_clip_r, fb_x_clip_w)
34		AM_RANGE(0x006c, 0x006f) AM_READWRITE(fb_y_clip_r, fb_y_clip_w)
35		AM_RANGE(0x0074, 0x0077) AM_READWRITE(fpu_shad_scale_r, fpu_shad_scale_w)
36		AM_RANGE(0x0078, 0x007b) AM_READWRITE(fpu_cull_val_r, fpu_cull_val_w)
37		AM_RANGE(0x007c, 0x007f) AM_READWRITE(fpu_param_cfg_r, fpu_param_cfg_w)
38		AM_RANGE(0x0080, 0x0083) AM_READWRITE(half_offset_r, half_offset_w)
39		AM_RANGE(0x0084, 0x0087) AM_READWRITE(fpu_perp_val_r, fpu_perp_val_w)
40		AM_RANGE(0x0088, 0x008b) AM_READWRITE(isp_backgnd_d_r, isp_backgnd_d_w)
41		AM_RANGE(0x008c, 0x008f) AM_READWRITE(isp_backgnd_t_r, isp_backgnd_t_w)
42		AM_RANGE(0x0098, 0x009b) AM_READWRITE(isp_feed_cfg_r, isp_feed_cfg_w)
43		AM_RANGE(0x00a0, 0x00a3) AM_READWRITE(sdram_refresh_r, sdram_refresh_w)
44		AM_RANGE(0x00a4, 0x00a7) AM_READWRITE(sdram_arb_cfg_r, sdram_arb_cfg_w)
45		AM_RANGE(0x00a8, 0x00ab) AM_READWRITE(sdram_cfg_r, sdram_cfg_w)
46		AM_RANGE(0x00b0, 0x00b3) AM_READWRITE(fog_col_ram_r, fog_col_ram_w)
47		AM_RANGE(0x00b4, 0x00b7) AM_READWRITE(fog_col_vert_r, fog_col_vert_w)
48		AM_RANGE(0x00b8, 0x00bb) AM_READWRITE(fog_density_r, fog_density_w)
49		AM_RANGE(0x00bc, 0x00bf) AM_READWRITE(fog_clamp_max_r, fog_clamp_max_w)
50		AM_RANGE(0x00c0, 0x00c3) AM_READWRITE(fog_clamp_min_r, fog_clamp_min_w)
51		AM_RANGE(0x00c4, 0x00c7) AM_READWRITE(spg_trigger_pos_r, spg_trigger_pos_w)
52		AM_RANGE(0x00c8, 0x00cb) AM_READWRITE(spg_hblank_int_r, spg_hblank_int_w)
53		AM_RANGE(0x00cc, 0x00cf) AM_READWRITE(spg_vblank_int_r, spg_vblank_int_w)
54		AM_RANGE(0x00d0, 0x00d3) AM_READWRITE(spg_control_r, spg_control_w)
55		AM_RANGE(0x00d4, 0x00d7) AM_READWRITE(spg_hblank_r, spg_hblank_w)
56		AM_RANGE(0x00d8, 0x00db) AM_READWRITE(spg_load_r, spg_load_w)
57		AM_RANGE(0x00dc, 0x00df) AM_READWRITE(spg_vblank_r, spg_vblank_w)
58		AM_RANGE(0x00e0, 0x00e3) AM_READWRITE(spg_width_r, spg_width_w)
59		AM_RANGE(0x00e4, 0x00e7) AM_READWRITE(text_control_r, text_control_w)
60		AM_RANGE(0x00e8, 0x00eb) AM_READWRITE(vo_control_r, vo_control_w)
61		AM_RANGE(0x00ec, 0x00ef) AM_READWRITE(vo_startx_r, vo_startx_w)
62		AM_RANGE(0x00f0, 0x00f3) AM_READWRITE(vo_starty_r, vo_starty_w)
63		AM_RANGE(0x00f4, 0x00f7) AM_READWRITE(scaler_ctl_r, scaler_ctl_w)
64		AM_RANGE(0x0108, 0x010b) AM_READWRITE(pal_ram_ctrl_r, pal_ram_ctrl_w)
	18	AM_RANGE(0x0008, 0x000b) AM_READWRITE(softreset_r, softreset_w)
	19	AM_RANGE(0x0014, 0x0017) AM_WRITE( startrender_w)
	20	// 18 = test select
	21	AM_RANGE(0x0020, 0x0023) AM_READWRITE(param_base_r, param_base_w)
	22	AM_RANGE(0x002c, 0x002f) AM_READWRITE(region_base_r, region_base_w)
	23	// 30 = span sort cfg
	24	AM_RANGE(0x0040, 0x0043) AM_READWRITE(vo_border_col_r, vo_border_col_w)
	25	AM_RANGE(0x0044, 0x0047) AM_READWRITE(fb_r_ctrl_r, fb_r_ctrl_w)
	26	AM_RANGE(0x0048, 0x004b) AM_READWRITE(fb_w_ctrl_r, fb_w_ctrl_w)
	27	AM_RANGE(0x004c, 0x004f) AM_READWRITE(fb_w_linestride_r, fb_w_linestride_w)
	28	AM_RANGE(0x0050, 0x0053) AM_READWRITE(fb_r_sof1_r, fb_r_sof1_w)
	29	AM_RANGE(0x0054, 0x0057) AM_READWRITE(fb_r_sof2_r, fb_r_sof2_w)
	30	AM_RANGE(0x005c, 0x005f) AM_READWRITE(fb_r_size_r, fb_r_size_w)
	31	AM_RANGE(0x0060, 0x0063) AM_READWRITE(fb_w_sof1_r, fb_w_sof1_w)
	32	AM_RANGE(0x0064, 0x0067) AM_READWRITE(fb_w_sof2_r, fb_w_sof2_w)
	33	AM_RANGE(0x0068, 0x006b) AM_READWRITE(fb_x_clip_r, fb_x_clip_w)
	34	AM_RANGE(0x006c, 0x006f) AM_READWRITE(fb_y_clip_r, fb_y_clip_w)
	35	// 74 = fpu_shad_scale
	36	// 78 = fpu_cull_val
	37	AM_RANGE(0x007c, 0x007f) AM_READWRITE(fpu_param_cfg_r, fpu_param_cfg_w)
	38	// 80 = half_offset
	39	// 84 = fpu_perp_val
	40	// 88 = isp_backgnd_d
	41	AM_RANGE(0x008c, 0x008f) AM_READWRITE(isp_backgnd_t_r, isp_backgnd_t_w)
	42	// 98 = isp_feed_cfg
	43	// a0 = sdram_refresh
	44	// a4 = sdram_arb_cfg
	45	// a8 = sdram_cfg
	46	// b0 = fog_col_ram
	47	// b4 = fog_col_vert
	48	// b8 = fog_density
	49	// bc = fog_clamp_max
	50	// c0 = fog_clamp_min
	51	// c4 = spg_trigger_pos
	52	AM_RANGE(0x00c8, 0x00cb) AM_READWRITE(spg_hblank_int_r, spg_hblank_int_w)
	53	AM_RANGE(0x00cc, 0x00cf) AM_READWRITE(spg_vblank_int_r, spg_vblank_int_w)
	54	AM_RANGE(0x00d0, 0x00d3) AM_READWRITE(spg_control_r, spg_control_w)
	55	AM_RANGE(0x00d4, 0x00d7) AM_READWRITE(spg_hblank_r, spg_hblank_w)
	56	AM_RANGE(0x00d8, 0x00db) AM_READWRITE(spg_load_r, spg_load_w)
	57	AM_RANGE(0x00dc, 0x00df) AM_READWRITE(spg_vblank_r, spg_vblank_w)
	58	AM_RANGE(0x00e0, 0x00e3) AM_READWRITE(spg_width_r, spg_width_w)
	59	AM_RANGE(0x00e4, 0x00e7) AM_READWRITE(text_control_r, text_control_w)
	60	AM_RANGE(0x00e8, 0x00eb) AM_READWRITE(vo_control_r, vo_control_w)
	61	AM_RANGE(0x00ec, 0x00ef) AM_READWRITE(vo_startx_r, vo_startx_w)
	62	AM_RANGE(0x00f0, 0x00f3) AM_READWRITE(vo_starty_r, vo_starty_w)
	63	// f4 = scaler_ctl
	64	AM_RANGE(0x0108, 0x010b) AM_READWRITE(pal_ram_ctrl_r, pal_ram_ctrl_w)
65	65	AM_RANGE(0x010c, 0x010f) AM_READ( spg_status_r)
66		AM_RANGE(0x0110, 0x0113) AM_READWRITE(fb_burstctrl_r, fb_burstctrl_w)
67		AM_RANGE(0x0118, 0x011b) AM_READWRITE(y_coeff_r, y_coeff_w)
68		AM_RANGE(0x011c, 0x011f) AM_READWRITE(pt_alpha_ref_r, pt_alpha_ref_w)
69		AM_RANGE(0x0124, 0x0127) AM_READWRITE(ta_ol_base_r, ta_ol_base_w)
70		AM_RANGE(0x0128, 0x012b) AM_READWRITE(ta_isp_base_r, ta_isp_base_w)
71		AM_RANGE(0x012c, 0x012f) AM_READWRITE(ta_ol_limit_r, ta_ol_limit_w)
72		AM_RANGE(0x0130, 0x0133) AM_READWRITE(ta_isp_limit_r, ta_isp_limit_w)
	66	// 110 = fb_burstctrl
	67	// 118 = y_coeff
	68	// 11c = pt_alpha_ref
	69
	70	AM_RANGE(0x0124, 0x0127) AM_READWRITE(ta_ol_base_r, ta_ol_base_w)
	71	AM_RANGE(0x0128, 0x012b) AM_READWRITE(ta_isp_base_r, ta_isp_base_w)
	72	AM_RANGE(0x012c, 0x012f) AM_READWRITE(ta_ol_limit_r, ta_ol_limit_w)
	73	AM_RANGE(0x0130, 0x0133) AM_READWRITE(ta_isp_limit_r, ta_isp_limit_w)
73	74	AM_RANGE(0x0134, 0x0137) AM_READ( ta_next_opb_r)
74	75	AM_RANGE(0x0138, 0x013b) AM_READ( ta_itp_current_r)
75		AM_RANGE(0x013c, 0x013f) AM_READWRITE(ta_glob_tile_clip_r, ta_glob_tile_clip_w)
76		AM_RANGE(0x0140, 0x0143) AM_READWRITE(ta_alloc_ctrl_r, ta_alloc_ctrl_w)
77		AM_RANGE(0x0144, 0x0147) AM_READWRITE(ta_list_init_r, ta_list_init_w)
78		AM_RANGE(0x0148, 0x014b) AM_READWRITE(ta_yuv_tex_base_r, ta_yuv_tex_base_w)
79		AM_RANGE(0x014c, 0x014f) AM_READWRITE(ta_yuv_tex_ctrl_r, ta_yuv_tex_ctrl_w)
80		AM_RANGE(0x0150, 0x0153) AM_READ( ta_yuv_tex_cnt_r)
81		AM_RANGE(0x0160, 0x0163) AM_READWRITE(ta_list_cont_r, ta_list_cont_w)
82		AM_RANGE(0x0164, 0x0167) AM_READWRITE(ta_next_opb_init_r, ta_next_opb_init_w)
	76	// 13c = ta_glob_tile_clip
	77	AM_RANGE(0x0140, 0x0143) AM_READWRITE(ta_alloc_ctrl_r, ta_alloc_ctrl_w)
	78	AM_RANGE(0x0144, 0x0147) AM_READWRITE(ta_list_init_r, ta_list_init_w)
	79	AM_RANGE(0x0148, 0x014b) AM_READWRITE(ta_yuv_tex_base_r, ta_yuv_tex_base_w)
	80	AM_RANGE(0x014c, 0x014f) AM_READWRITE(ta_yuv_tex_ctrl_r, ta_yuv_tex_ctrl_w)
	81	AM_RANGE(0x0150, 0x0153) AM_READWRITE(ta_yuv_tex_cnt_r, ta_yuv_tex_cnt_w)
	82	AM_RANGE(0x0160, 0x0163) AM_WRITE( ta_list_cont_w)
	83	AM_RANGE(0x0164, 0x0167) AM_READWRITE(ta_next_opb_init_r, ta_next_opb_init_w)
83	84
84		AM_RANGE(0x0200, 0x03ff) AM_READWRITE(fog_table_r, fog_table_w)
85		AM_RANGE(0x0600, 0x0f5f) AM_READ (ta_ol_pointers_1_r)
86		AM_RANGE(0x1000, 0x1fff) AM_READWRITE(palette_r, palette_w)
87		AM_RANGE(0x2000, 0x295f) AM_READ (ta_ol_pointers_2_r)
	85	AM_RANGE(0x0200, 0x03ff) AM_READWRITE(fog_table_r, fog_table_w)
	86	AM_RANGE(0x1000, 0x1fff) AM_READWRITE(palette_r, palette_w)
88	87	ADDRESS_MAP_END
89	88
90	89	DEVICE_ADDRESS_MAP_START(pd_dma_map, 32, powervr2_device)
91		AM_RANGE(0x00, 0x03) AM_READWRITE(sb_pdstap_r, sb_pdstap_w)
92		AM_RANGE(0x04, 0x07) AM_READWRITE(sb_pdstar_r, sb_pdstar_w)
93		AM_RANGE(0x08, 0x0b) AM_READWRITE(sb_pdlen_r, sb_pdlen_w)
94		AM_RANGE(0x0c, 0x0f) AM_READWRITE(sb_pddir_r, sb_pddir_w)
95		AM_RANGE(0x10, 0x13) AM_READWRITE(sb_pdtsel_r, sb_pdtsel_w)
96		AM_RANGE(0x14, 0x17) AM_READWRITE(sb_pden_r, sb_pden_w)
97		AM_RANGE(0x18, 0x1b) AM_READWRITE(sb_pdst_r, sb_pdst_w)
98		AM_RANGE(0x80, 0x83) AM_READWRITE(sb_pdapro_r, sb_pdapro_w)
	90	AM_RANGE(0x00, 0x03) AM_READWRITE(sb_pdstap_r, sb_pdstap_w)
	91	AM_RANGE(0x04, 0x07) AM_READWRITE(sb_pdstar_r, sb_pdstar_w)
	92	AM_RANGE(0x08, 0x0b) AM_READWRITE(sb_pdlen_r, sb_pdlen_w)
	93	AM_RANGE(0x0c, 0x0f) AM_READWRITE(sb_pddir_r, sb_pddir_w)
	94	AM_RANGE(0x10, 0x13) AM_READWRITE(sb_pdtsel_r, sb_pdtsel_w)
	95	AM_RANGE(0x14, 0x17) AM_READWRITE(sb_pden_r, sb_pden_w)
	96	AM_RANGE(0x18, 0x1b) AM_READWRITE(sb_pdst_r, sb_pdst_w)
	97	AM_RANGE(0x80, 0x83) AM_READWRITE(sb_pdapro_r, sb_pdapro_w)
99	98	ADDRESS_MAP_END
100	99
101	100	const int powervr2_device::pvr_parconfseq[] = {1,2,3,2,3,4,5,6,5,6,7,8,9,10,11,12,13,14,13,14,15,16,17,16,17,0,0,0,0,0,18,19,20,19,20,21,22,23,22,23};
r243812	r243813
892	891
893	892	}
894	893
895		READ64_MEMBER( powervr2_device::tex64_r )
896		{
897		if(offset & 0x100000)
898		offset ^= 0x300000;
899		return (UINT64(tex32_r(space, offset \| 0x100000, mem_mask >> 32)) << 32) \| tex32_r(space, offset, mem_mask);
900		}
901
902		WRITE64_MEMBER( powervr2_device::tex64_w )
903		{
904		if(offset & 0x100000)
905		offset ^= 0x300000;
906		if(ACCESSING_BITS_0_31)
907		tex32_w(space, offset , data , mem_mask );
908		if(ACCESSING_BITS_32_63)
909		tex32_w(space, offset \| 0x100000, data >> 32, mem_mask >> 32);
910		}
911
912		READ32_MEMBER( powervr2_device::tex32_r )
913		{
914		return sdram[offset];
915		}
916
917		WRITE32_MEMBER( powervr2_device::tex32_w )
918		{
919		COMBINE_DATA(sdram+offset);
920		// logerror("%s: rec tex32_w %06x %08x\n", tag(), offset, sdram[offset]);
921		}
922
923	894	READ32_MEMBER( powervr2_device::id_r )
924	895	{
925	896	return 0x17fd11db;
r243812	r243813
962	933	}
963	934	}
964	935
965		READ32_MEMBER( powervr2_device::startrender_r )
966		{
967		return 0;
968		}
969
970	936	WRITE32_MEMBER( powervr2_device::startrender_w )
971	937	{
972		static const int list_order[5] = { 0, 4, 1, 2, 3 };
973		logerror("%s: rec startrender_w %08x\n", tag(), data);
974
975		UINT32 region_data = (region_base >> 2) & 0x3fffff;
976		bool alt_mode = !(fpu_param_cfg & 0x00200000);
977		int num_list = alt_mode ? 4 : 5;
978		for(;;) {
979		UINT32 head = sdram[region_data];
980		int xtile = (head & 0xfc) >> 2;
981		int ytile = (head & 0x3f00) >> 8;
982		bool zclear = alt_mode ? false : head & 0x40000000;
983		bool presort = alt_mode ? isp_feed_cfg & 0x00000001 : head & 0x20000000;
984		bool flushacc = alt_mode ? false : head & 0x10000000;
985
986		logerror("%s: xt %d yt %d zc %d ps %d fa %d %s\n",
987		tag(), xtile, ytile, zclear, presort, flushacc, head & 0x80000000 ? "end" : "next");
988
989		region_data++;
990		for(int list_idx = 0; list_idx < num_list; list_idx++) {
991		int list_id = alt_mode ? list_idx : list_order[list_idx];
992		logerror("%s: %d: %08x\n", tag(), list_id, sdram[region_data + list_id]);
993		}
994		region_data += num_list;
995
996		if(head & 0x80000000)
997		break;
998		}
999
1000		exit(0);
1001		#if 0
1002	938	dc_state *state = machine().driver_data<dc_state>();
1003	939	g_profiler.start(PROFILER_USER1);
1004	940	#if DEBUG_PVRTA
r243812	r243813
1070	1006	}
1071	1007	// printf("ISP START %d %d\n",sanitycount,m_screen->vpos());
1072	1008	/* Fire ISP irq after a set amount of time TODO: timing of this */
	1009	endofrender_timer_isp->adjust(state->m_maincpu->cycles_to_attotime(sanitycount*25));
1073	1010	break;
1074	1011	}
1075	1012	}
1076		#endif
1077		endofrender_timer_isp->adjust(machine().driver_data<dc_state>()->m_maincpu->cycles_to_attotime(2500));
1078	1013	}
1079	1014
1080		READ32_MEMBER( powervr2_device::test_select_r )
1081		{
1082		return test_select;
1083		}
1084	1015
1085		WRITE32_MEMBER( powervr2_device::test_select_w )
1086		{
1087		logerror("%s: rec test_select_w %08x\n", tag(), data);
1088		COMBINE_DATA(&test_select);
1089		}
1090
1091	1016	READ32_MEMBER( powervr2_device::param_base_r )
1092	1017	{
1093	1018	return param_base;
r243812	r243813
1095	1020
1096	1021	WRITE32_MEMBER( powervr2_device::param_base_w )
1097	1022	{
1098		logerror("%s: rec param_base_w %08x\n", tag(), data);
1099	1023	COMBINE_DATA(&param_base);
1100	1024	}
1101	1025
r243812	r243813
1106	1030
1107	1031	WRITE32_MEMBER( powervr2_device::region_base_w )
1108	1032	{
1109		logerror("%s: rec region_base_w %08x\n", tag(), data);
1110	1033	COMBINE_DATA(&region_base);
1111	1034	}
1112	1035
1113		READ32_MEMBER( powervr2_device::span_sort_cfg_r )
1114		{
1115		return span_sort_cfg;
1116		}
1117
1118		WRITE32_MEMBER( powervr2_device::span_sort_cfg_w )
1119		{
1120		logerror("%s: rec span_sort_cfg_w %08x\n", tag(), data);
1121		COMBINE_DATA(&span_sort_cfg);
1122		}
1123
1124	1036	READ32_MEMBER( powervr2_device::vo_border_col_r )
1125	1037	{
1126	1038	return vo_border_col;
r243812	r243813
1128	1040
1129	1041	WRITE32_MEMBER( powervr2_device::vo_border_col_w )
1130	1042	{
1131		logerror("%s: rec vo_border_col_w %08x\n", tag(), data);
1132	1043	COMBINE_DATA(&vo_border_col);
1133	1044	}
1134	1045
r243812	r243813
1139	1050
1140	1051	WRITE32_MEMBER( powervr2_device::fb_r_ctrl_w )
1141	1052	{
1142		logerror("%s: rec fb_r_ctrl_w %08x\n", tag(), data);
1143	1053	COMBINE_DATA(&fb_r_ctrl);
1144	1054	}
1145	1055
r243812	r243813
1150	1060
1151	1061	WRITE32_MEMBER( powervr2_device::fb_w_ctrl_w )
1152	1062	{
1153		logerror("%s: rec fb_w_ctrl_w %08x\n", tag(), data);
1154	1063	COMBINE_DATA(&fb_w_ctrl);
1155	1064	}
1156	1065
r243812	r243813
1161	1070
1162	1071	WRITE32_MEMBER( powervr2_device::fb_w_linestride_w )
1163	1072	{
1164		logerror("%s: rec fb_w_linestride_w %08x\n", tag(), data);
1165	1073	COMBINE_DATA(&fb_w_linestride);
1166	1074	}
1167	1075
r243812	r243813
1172	1080
1173	1081	WRITE32_MEMBER( powervr2_device::fb_r_sof1_w )
1174	1082	{
1175		logerror("%s: rec fb_r_sof1_w %08x\n", tag(), data);
1176	1083	COMBINE_DATA(&fb_r_sof1);
1177	1084	}
1178	1085
r243812	r243813
1183	1090
1184	1091	WRITE32_MEMBER( powervr2_device::fb_r_sof2_w )
1185	1092	{
1186		logerror("%s: rec fb_r_sof2_w %08x\n", tag(), data);
1187	1093	COMBINE_DATA(&fb_r_sof2);
1188	1094	}
1189	1095
r243812	r243813
1194	1100
1195	1101	WRITE32_MEMBER( powervr2_device::fb_r_size_w )
1196	1102	{
1197		logerror("%s: rec fb_r_size_w %08x\n", tag(), data);
1198	1103	COMBINE_DATA(&fb_r_size);
1199	1104	}
1200	1105
r243812	r243813
1205	1110
1206	1111	WRITE32_MEMBER( powervr2_device::fb_w_sof1_w )
1207	1112	{
1208		logerror("%s: rec fb_w_sof1_w %08x\n", tag(), data);
1209	1113	COMBINE_DATA(&fb_w_sof1);
1210	1114	}
1211	1115
r243812	r243813
1216	1120
1217	1121	WRITE32_MEMBER( powervr2_device::fb_w_sof2_w )
1218	1122	{
1219		logerror("%s: rec fb_w_sof2_w %08x\n", tag(), data);
1220	1123	COMBINE_DATA(&fb_w_sof2);
1221	1124	}
1222	1125
r243812	r243813
1227	1130
1228	1131	WRITE32_MEMBER( powervr2_device::fb_x_clip_w )
1229	1132	{
1230		logerror("%s: rec fb_x_clip_w %08x\n", tag(), data);
1231	1133	COMBINE_DATA(&fb_x_clip);
1232	1134	}
1233	1135
r243812	r243813
1238	1140
1239	1141	WRITE32_MEMBER( powervr2_device::fb_y_clip_w )
1240	1142	{
1241		logerror("%s: rec fb_y_clip_w %08x\n", tag(), data);
1242	1143	COMBINE_DATA(&fb_y_clip);
1243	1144	}
1244	1145
1245		READ32_MEMBER( powervr2_device::fpu_shad_scale_r )
1246		{
1247		return fpu_shad_scale;
1248		}
1249
1250		WRITE32_MEMBER( powervr2_device::fpu_shad_scale_w )
1251		{
1252		logerror("%s: rec fpu_shad_scale_w %08x\n", tag(), data);
1253		COMBINE_DATA(&fpu_shad_scale);
1254		}
1255
1256		READ32_MEMBER( powervr2_device::fpu_cull_val_r )
1257		{
1258		return fpu_cull_val;
1259		}
1260
1261		WRITE32_MEMBER( powervr2_device::fpu_cull_val_w )
1262		{
1263		logerror("%s: rec fpu_cull_val_w %08x\n", tag(), data);
1264		COMBINE_DATA(&fpu_cull_val);
1265		}
1266
1267	1146	READ32_MEMBER( powervr2_device::fpu_param_cfg_r )
1268	1147	{
1269	1148	return fpu_param_cfg;
r243812	r243813
1271	1150
1272	1151	WRITE32_MEMBER( powervr2_device::fpu_param_cfg_w )
1273	1152	{
1274		logerror("%s: rec fpu_param_cfg_w %08x\n", tag(), data);
1275	1153	COMBINE_DATA(&fpu_param_cfg);
1276	1154	}
1277	1155
1278		READ32_MEMBER( powervr2_device::half_offset_r )
1279		{
1280		return half_offset;
1281		}
1282
1283		WRITE32_MEMBER( powervr2_device::half_offset_w )
1284		{
1285		logerror("%s: rec half_offset_w %08x\n", tag(), data);
1286		COMBINE_DATA(&half_offset);
1287		}
1288
1289		READ32_MEMBER( powervr2_device::fpu_perp_val_r )
1290		{
1291		return fpu_perp_val;
1292		}
1293
1294		WRITE32_MEMBER( powervr2_device::fpu_perp_val_w )
1295		{
1296		logerror("%s: rec fpu_perp_val_w %08x\n", tag(), data);
1297		COMBINE_DATA(&fpu_perp_val);
1298		}
1299
1300		READ32_MEMBER( powervr2_device::isp_backgnd_d_r )
1301		{
1302		return isp_backgnd_d;
1303		}
1304
1305		WRITE32_MEMBER( powervr2_device::isp_backgnd_d_w )
1306		{
1307		logerror("%s: rec isp_backgnd_d_w %08x\n", tag(), data);
1308		COMBINE_DATA(&isp_backgnd_d);
1309		}
1310
1311	1156	READ32_MEMBER( powervr2_device::isp_backgnd_t_r )
1312	1157	{
1313	1158	return isp_backgnd_t;
r243812	r243813
1315	1160
1316	1161	WRITE32_MEMBER( powervr2_device::isp_backgnd_t_w )
1317	1162	{
1318		logerror("%s: rec isp_backgnd_t_w %08x\n", tag(), data);
1319	1163	COMBINE_DATA(&isp_backgnd_t);
1320	1164	}
1321	1165
1322		READ32_MEMBER( powervr2_device::isp_feed_cfg_r )
1323		{
1324		return isp_feed_cfg;
1325		}
1326
1327		WRITE32_MEMBER( powervr2_device::isp_feed_cfg_w )
1328		{
1329		logerror("%s: rec isp_feed_cfg_w %08x\n", tag(), data);
1330		COMBINE_DATA(&isp_feed_cfg);
1331		}
1332
1333		READ32_MEMBER( powervr2_device::sdram_refresh_r )
1334		{
1335		return sdram_refresh;
1336		}
1337
1338		WRITE32_MEMBER( powervr2_device::sdram_refresh_w )
1339		{
1340		logerror("%s: rec sdram_refresh_w %08x\n", tag(), data);
1341		COMBINE_DATA(&sdram_refresh);
1342		}
1343
1344		READ32_MEMBER( powervr2_device::sdram_arb_cfg_r )
1345		{
1346		return sdram_arb_cfg;
1347		}
1348
1349		WRITE32_MEMBER( powervr2_device::sdram_arb_cfg_w )
1350		{
1351		logerror("%s: rec sdram_arb_cfg_w %08x\n", tag(), data);
1352		COMBINE_DATA(&sdram_arb_cfg);
1353		}
1354
1355		READ32_MEMBER( powervr2_device::sdram_cfg_r )
1356		{
1357		return sdram_cfg;
1358		}
1359
1360		WRITE32_MEMBER( powervr2_device::sdram_cfg_w )
1361		{
1362		logerror("%s: rec sdram_cfg_w %08x\n", tag(), data);
1363		COMBINE_DATA(&sdram_cfg);
1364		}
1365
1366		READ32_MEMBER( powervr2_device::fog_col_ram_r )
1367		{
1368		return fog_col_ram;
1369		}
1370
1371		WRITE32_MEMBER( powervr2_device::fog_col_ram_w )
1372		{
1373		logerror("%s: rec fog_col_ram_w %08x\n", tag(), data);
1374		COMBINE_DATA(&fog_col_ram);
1375		}
1376
1377		READ32_MEMBER( powervr2_device::fog_col_vert_r )
1378		{
1379		return fog_col_vert;
1380		}
1381
1382		WRITE32_MEMBER( powervr2_device::fog_col_vert_w )
1383		{
1384		logerror("%s: rec fog_col_vert_w %08x\n", tag(), data);
1385		COMBINE_DATA(&fog_col_vert);
1386		}
1387
1388		READ32_MEMBER( powervr2_device::fog_density_r )
1389		{
1390		return fog_density;
1391		}
1392
1393		WRITE32_MEMBER( powervr2_device::fog_density_w )
1394		{
1395		logerror("%s: rec fog_density_w %08x\n", tag(), data);
1396		COMBINE_DATA(&fog_density);
1397		}
1398
1399		READ32_MEMBER( powervr2_device::fog_clamp_max_r )
1400		{
1401		return fog_clamp_max;
1402		}
1403
1404		WRITE32_MEMBER( powervr2_device::fog_clamp_max_w )
1405		{
1406		logerror("%s: rec fog_clamp_max_w %08x\n", tag(), data);
1407		COMBINE_DATA(&fog_clamp_max);
1408		}
1409
1410		READ32_MEMBER( powervr2_device::fog_clamp_min_r )
1411		{
1412		return fog_clamp_min;
1413		}
1414
1415		WRITE32_MEMBER( powervr2_device::fog_clamp_min_w )
1416		{
1417		logerror("%s: rec fog_clamp_min_w %08x\n", tag(), data);
1418		COMBINE_DATA(&fog_clamp_min);
1419		}
1420
1421		READ32_MEMBER( powervr2_device::spg_trigger_pos_r )
1422		{
1423		return spg_trigger_pos;
1424		}
1425
1426		WRITE32_MEMBER( powervr2_device::spg_trigger_pos_w )
1427		{
1428		logerror("%s: rec spg_trigger_pos_w %08x\n", tag(), data);
1429		COMBINE_DATA(&spg_trigger_pos);
1430		}
1431
1432	1166	READ32_MEMBER( powervr2_device::spg_hblank_int_r )
1433	1167	{
1434	1168	return spg_hblank_int;
r243812	r243813
1436	1170
1437	1171	WRITE32_MEMBER( powervr2_device::spg_hblank_int_w )
1438	1172	{
1439		logerror("%s: rec spg_hblank_int_w %08x\n", tag(), data);
1440	1173	COMBINE_DATA(&spg_hblank_int);
1441	1174	/* TODO: timer adjust */
1442	1175	}
r243812	r243813
1448	1181
1449	1182	WRITE32_MEMBER( powervr2_device::spg_vblank_int_w )
1450	1183	{
1451		logerror("%s: rec spg_vblank_int_w %08x\n", tag(), data);
1452	1184	COMBINE_DATA(&spg_vblank_int);
1453	1185
1454	1186	/* clear pending irqs and modify them with the updated ones */
r243812	r243813
1466	1198
1467	1199	WRITE32_MEMBER( powervr2_device::spg_control_w )
1468	1200	{
1469		logerror("%s: rec spg_control_w %08x\n", tag(), data);
1470	1201	COMBINE_DATA(&spg_control);
1471	1202	update_screen_format();
1472	1203
r243812	r243813
1484	1215
1485	1216	WRITE32_MEMBER( powervr2_device::spg_hblank_w )
1486	1217	{
1487		logerror("%s: rec spg_hblank_w %08x\n", tag(), data);
1488	1218	COMBINE_DATA(&spg_hblank);
1489	1219	update_screen_format();
1490	1220	}
r243812	r243813
1496	1226
1497	1227	WRITE32_MEMBER( powervr2_device::spg_load_w )
1498	1228	{
1499		logerror("%s: rec spg_load_w %08x\n", tag(), data);
1500	1229	COMBINE_DATA(&spg_load);
1501	1230	update_screen_format();
1502	1231	}
r243812	r243813
1508	1237
1509	1238	WRITE32_MEMBER( powervr2_device::spg_vblank_w )
1510	1239	{
1511		logerror("%s: rec spg_vblank_w %08x\n", tag(), data);
1512	1240	COMBINE_DATA(&spg_vblank);
1513	1241	update_screen_format();
1514	1242	}
r243812	r243813
1520	1248
1521	1249	WRITE32_MEMBER( powervr2_device::spg_width_w )
1522	1250	{
1523		logerror("%s: rec spg_width_w %08x\n", tag(), data);
1524	1251	COMBINE_DATA(&spg_width);
1525	1252	update_screen_format();
1526	1253	}
r243812	r243813
1532	1259
1533	1260	WRITE32_MEMBER( powervr2_device::text_control_w )
1534	1261	{
1535		logerror("%s: rec text_control_w %08x\n", tag(), data);
1536	1262	COMBINE_DATA(&text_control);
1537	1263	}
1538	1264
r243812	r243813
1543	1269
1544	1270	WRITE32_MEMBER( powervr2_device::vo_control_w )
1545	1271	{
1546		logerror("%s: rec vo_control_w %08x\n", tag(), data);
1547	1272	COMBINE_DATA(&vo_control);
1548	1273	}
1549	1274
r243812	r243813
1554	1279
1555	1280	WRITE32_MEMBER( powervr2_device::vo_startx_w )
1556	1281	{
1557		logerror("%s: rec vo_startx_w %08x\n", tag(), data);
1558	1282	COMBINE_DATA(&vo_startx);
1559	1283	update_screen_format();
1560	1284	}
r243812	r243813
1566	1290
1567	1291	WRITE32_MEMBER( powervr2_device::vo_starty_w )
1568	1292	{
1569		logerror("%s: rec vo_starty_w %08x\n", tag(), data);
1570	1293	COMBINE_DATA(&vo_starty);
1571	1294	update_screen_format();
1572	1295	}
1573	1296
1574		READ32_MEMBER( powervr2_device::scaler_ctl_r )
1575		{
1576		return scaler_ctl;
1577		}
1578
1579		WRITE32_MEMBER( powervr2_device::scaler_ctl_w )
1580		{
1581		logerror("%s: rec scaler_ctl_w %08x\n", tag(), data);
1582		COMBINE_DATA(&scaler_ctl);
1583		}
1584
1585	1297	READ32_MEMBER( powervr2_device::pal_ram_ctrl_r )
1586	1298	{
1587	1299	return pal_ram_ctrl;
r243812	r243813
1589	1301
1590	1302	WRITE32_MEMBER( powervr2_device::pal_ram_ctrl_w )
1591	1303	{
1592		logerror("%s: rec pal_ram_ctrl_w %08x\n", tag(), data);
1593	1304	COMBINE_DATA(&pal_ram_ctrl);
1594	1305	}
1595	1306
r243812	r243813
1613	1324	return (vsync << 13) \| (hsync << 12) \| (blank << 11) \| (fieldnum << 10) \| (m_screen->vpos() & 0x3ff);
1614	1325	}
1615	1326
1616		READ32_MEMBER( powervr2_device::fb_burstctrl_r )
1617		{
1618		return fb_burstctrl;
1619		}
1620	1327
1621		WRITE32_MEMBER( powervr2_device::fb_burstctrl_w )
1622		{
1623		logerror("%s: rec fb_burstctrl_w %08x\n", tag(), data);
1624		COMBINE_DATA(&fb_burstctrl);
1625		}
1626
1627		READ32_MEMBER( powervr2_device::y_coeff_r )
1628		{
1629		return y_coeff;
1630		}
1631
1632		WRITE32_MEMBER( powervr2_device::y_coeff_w )
1633		{
1634		logerror("%s: rec y_coeff_w %08x\n", tag(), data);
1635		COMBINE_DATA(&y_coeff);
1636		}
1637
1638		READ32_MEMBER( powervr2_device::pt_alpha_ref_r )
1639		{
1640		return pt_alpha_ref;
1641		}
1642
1643		WRITE32_MEMBER( powervr2_device::pt_alpha_ref_w )
1644		{
1645		logerror("%s: rec pt_alpha_ref_w %08x\n", tag(), data);
1646		COMBINE_DATA(&pt_alpha_ref);
1647		}
1648
1649	1328	READ32_MEMBER( powervr2_device::ta_ol_base_r )
1650	1329	{
1651	1330	return ta_ol_base;
r243812	r243813
1653	1332
1654	1333	WRITE32_MEMBER( powervr2_device::ta_ol_base_w )
1655	1334	{
1656		logerror("%s: rec ta_ol_base_w %08x\n", tag(), data);
1657	1335	COMBINE_DATA(&ta_ol_base);
1658	1336	}
1659	1337
r243812	r243813
1664	1342
1665	1343	WRITE32_MEMBER( powervr2_device::ta_isp_base_w )
1666	1344	{
1667		logerror("%s: rec ta_isp_base_w %08x\n", tag(), data);
1668	1345	COMBINE_DATA(&ta_isp_base);
1669	1346	}
1670	1347
r243812	r243813
1675	1352
1676	1353	WRITE32_MEMBER( powervr2_device::ta_ol_limit_w )
1677	1354	{
1678		logerror("%s: rec ta_ol_limit_w %08x\n", tag(), data);
1679	1355	COMBINE_DATA(&ta_ol_limit);
1680	1356	}
1681	1357
r243812	r243813
1686	1362
1687	1363	WRITE32_MEMBER( powervr2_device::ta_isp_limit_w )
1688	1364	{
1689		logerror("%s: rec ta_isp_limit_w %08x\n", tag(), data);
1690	1365	COMBINE_DATA(&ta_isp_limit);
1691	1366	}
1692	1367
r243812	r243813
1700	1375	return ta_itp_current;
1701	1376	}
1702	1377
1703		READ32_MEMBER( powervr2_device::ta_glob_tile_clip_r )
1704		{
1705		return ta_glob_tile_clip;
1706		}
1707
1708		WRITE32_MEMBER( powervr2_device::ta_glob_tile_clip_w )
1709		{
1710		logerror("%s: rec ta_glob_tile_clip_w %08x\n", tag(), data);
1711		COMBINE_DATA(&ta_glob_tile_clip);
1712		}
1713
1714	1378	READ32_MEMBER( powervr2_device::ta_alloc_ctrl_r )
1715	1379	{
1716	1380	return ta_alloc_ctrl;
r243812	r243813
1718	1382
1719	1383	WRITE32_MEMBER( powervr2_device::ta_alloc_ctrl_w )
1720	1384	{
1721		logerror("%s: rec ta_alloc_ctrl_w %08x\n", tag(), data);
1722	1385	COMBINE_DATA(&ta_alloc_ctrl);
1723	1386	}
1724	1387
1725		// Dummy read required after write for internal powervr reasons says the manual
1726	1388	READ32_MEMBER( powervr2_device::ta_list_init_r )
1727	1389	{
1728		return 0;
	1390	return 0; //bit 31 always return 0, a probable left-over in Crazy Taxi reads this and discards the read (?)
1729	1391	}
1730	1392
1731		void powervr2_device::ta_list_start()
1732		{
1733		ta_list_idx = -1;
1734		ta_next_list();
1735		ta_olist_pos_base = ta_olist_pos = ta_ol_base;
1736		memset(ta_ol_pointers_1, 0, sizeof(ta_ol_pointers_1));
1737		}
1738
1739	1393	WRITE32_MEMBER( powervr2_device::ta_list_init_w )
1740	1394	{
1741		logerror("%s: rec ta_list_init_w %08x\n", tag(), data);
1742	1395	if(data & 0x80000000) {
1743		ta_next_opb = ta_next_opb_init;
1744		ta_itp_current = ta_isp_base;
1745		ta_list_start();
1746		}
1747
1748		#if 0
1749		if(data & 0x80000000) {
1750	1396	tafifo_pos=0;
1751	1397	tafifo_mask=7;
1752	1398	tafifo_vertexwords=8;
r243812	r243813
1800	1446
1801	1447	g_profiler.stop();
1802	1448	}
1803		#endif
1804	1449	}
1805	1450
1806	1451
r243812	r243813
1811	1456
1812	1457	WRITE32_MEMBER( powervr2_device::ta_yuv_tex_base_w )
1813	1458	{
1814		logerror("%s: rec ta_yuv_tex_base_w %08x\n", tag(), data);
1815	1459	COMBINE_DATA(&ta_yuv_tex_base);
	1460	logerror("%s: ta_yuv_tex_base = %08x\n", tag(), ta_yuv_tex_base);
1816	1461
1817	1462	ta_yuv_index = 0;
1818	1463	ta_yuv_x = 0;
r243812	r243813
1827	1472
1828	1473	WRITE32_MEMBER( powervr2_device::ta_yuv_tex_ctrl_w )
1829	1474	{
1830		logerror("%s: rec ta_yuv_tex_ctrl_w %08x\n", tag(), data);
1831	1475	COMBINE_DATA(&ta_yuv_tex_ctrl);
1832	1476	ta_yuv_x_size = ((ta_yuv_tex_ctrl & 0x3f)+1)*16;
1833	1477	ta_yuv_y_size = (((ta_yuv_tex_ctrl>>8) & 0x3f)+1)*16;
	1478	logerror("%s: ta_yuv_tex_ctrl = %08x\n", tag(), ta_yuv_tex_ctrl);
1834	1479	if(ta_yuv_tex_ctrl & 0x01010000)
1835	1480	fatalerror("YUV with setting %08x",ta_yuv_tex_ctrl);
1836	1481	}
r243812	r243813
1843	1488	return ta_yuv_tex_cnt;
1844	1489	}
1845	1490
1846		// Dummy read required after write for internal powervr reasons says the manual
1847		READ32_MEMBER( powervr2_device::ta_list_cont_r )
	1491	WRITE32_MEMBER( powervr2_device::ta_yuv_tex_cnt_w )
1848	1492	{
1849		return 0;
	1493	debugger_break(machine());
	1494	COMBINE_DATA(&ta_yuv_tex_cnt);
1850	1495	}
1851	1496
1852	1497	WRITE32_MEMBER( powervr2_device::ta_list_cont_w )
1853	1498	{
1854		logerror("%s: rec ta_list_cont_w %08x\n", tag(), data);
1855	1499	if(data & 0x80000000) {
1856	1500	tafifo_listtype= -1; // no list being received
1857	1501	listtype_used \|= (1+4);
r243812	r243813
1865	1509
1866	1510	WRITE32_MEMBER( powervr2_device::ta_next_opb_init_w )
1867	1511	{
1868		logerror("%s: rec ta_next_opb_init_w %08x\n", tag(), data);
1869	1512	COMBINE_DATA(&ta_next_opb_init);
1870	1513	}
1871	1514
r243812	r243813
1880	1523	COMBINE_DATA(fog_table+offset);
1881	1524	}
1882	1525
1883		READ32_MEMBER( powervr2_device::ta_ol_pointers_1_r )
1884		{
1885		return ta_ol_pointers_1[offset];
1886		}
1887
1888		READ32_MEMBER( powervr2_device::ta_ol_pointers_2_r )
1889		{
1890		return ta_ol_pointers_2[offset];
1891		}
1892
1893	1526	READ32_MEMBER( powervr2_device::palette_r )
1894	1527	{
1895	1528	return palette[offset];
r243812	r243813
2067	1700
2068	1701	void powervr2_device::process_ta_fifo()
2069	1702	{
2070		#if 0
2071	1703	/* first byte in the buffer is the Parameter Control Word
2072	1704
2073	1705	pppp pppp gggg gggg oooo oooo oooo oooo
r243812	r243813
2081	1713	receiveddata *rd = &grab[grabsel];
2082	1714
2083	1715	// Para Control
2084		paracontrol=(ta_fifo_buf[0] >> 24) & 0xff;
	1716	paracontrol=(tafifo_buff[0] >> 24) & 0xff;
2085	1717	// 0 end of list
2086	1718	// 1 user tile clip
2087	1719	// 2 object list set
r243812	r243813
2097	1729	{
2098	1730	global_paratype = paratype;
2099	1731	// Group Control
2100		groupcontrol=(ta_fifo_buf[0] >> 16) & 0xff;
	1732	groupcontrol=(tafifo_buff[0] >> 16) & 0xff;
2101	1733	groupen=(groupcontrol >> 7) & 1;
2102	1734	striplen=(groupcontrol >> 2) & 3;
2103	1735	userclip=(groupcontrol >> 0) & 3;
2104	1736	// Obj Control
2105		objcontrol=(ta_fifo_buf[0] >> 0) & 0xffff;
	1737	objcontrol=(tafifo_buff[0] >> 0) & 0xffff;
2106	1738	shadow=(objcontrol >> 7) & 1;
2107	1739	volume=(objcontrol >> 6) & 1;
2108	1740	coltype=(objcontrol >> 4) & 3;
r243812	r243813
2166	1798	{ // user tile clip
2167	1799	#if DEBUG_PVRDLIST
2168	1800	osd_printf_verbose("Para Type 1 User Tile Clip\n");
2169		osd_printf_verbose(" (%d , %d)-(%d , %d)\n", ta_fifo_buf[4], ta_fifo_buf[5], ta_fifo_buf[6], ta_fifo_buf[7]);
	1801	osd_printf_verbose(" (%d , %d)-(%d , %d)\n", tafifo_buff[4], tafifo_buff[5], tafifo_buff[6], tafifo_buff[7]);
2170	1802	#endif
2171	1803	}
2172	1804	else if (paratype == 2)
2173	1805	{ // object list set
2174	1806	#if DEBUG_PVRDLIST
2175		osd_printf_verbose("Para Type 2 Object List Set at %08x\n", ta_fifo_buf[1]);
2176		osd_printf_verbose(" (%d , %d)-(%d , %d)\n", ta_fifo_buf[4], ta_fifo_buf[5], ta_fifo_buf[6], ta_fifo_buf[7]);
	1807	osd_printf_verbose("Para Type 2 Object List Set at %08x\n", tafifo_buff[1]);
	1808	osd_printf_verbose(" (%d , %d)-(%d , %d)\n", tafifo_buff[4], tafifo_buff[5], tafifo_buff[6], tafifo_buff[7]);
2177	1809	#endif
2178	1810	}
2179	1811	else if (paratype == 3)
2180	1812	{
2181	1813	#if DEBUG_PVRDLIST
2182		osd_printf_verbose("Para Type %x Unknown!\n", ta_fifo_buf[0]);
	1814	osd_printf_verbose("Para Type %x Unknown!\n", tafifo_buff[0]);
2183	1815	#endif
2184	1816	}
2185	1817	else
r243812	r243813
2205	1837
2206	1838	if ((paratype == 4) \|\| (paratype == 5))
2207	1839	{ // quad or polygon
2208		depthcomparemode=(ta_fifo_buf[1] >> 29) & 7;
2209		cullingmode=(ta_fifo_buf[1] >> 27) & 3;
2210		zwritedisable=(ta_fifo_buf[1] >> 26) & 1;
2211		cachebypass=(ta_fifo_buf[1] >> 21) & 1;
2212		dcalcctrl=(ta_fifo_buf[1] >> 20) & 1;
2213		volumeinstruction=(ta_fifo_buf[1] >> 29) & 7;
	1840	depthcomparemode=(tafifo_buff[1] >> 29) & 7;
	1841	cullingmode=(tafifo_buff[1] >> 27) & 3;
	1842	zwritedisable=(tafifo_buff[1] >> 26) & 1;
	1843	cachebypass=(tafifo_buff[1] >> 21) & 1;
	1844	dcalcctrl=(tafifo_buff[1] >> 20) & 1;
	1845	volumeinstruction=(tafifo_buff[1] >> 29) & 7;
2214	1846
2215		//textureusize=1 << (3+((ta_fifo_buf[2] >> 3) & 7));
2216		//texturevsize=1 << (3+(ta_fifo_buf[2] & 7));
2217		texturesizes=ta_fifo_buf[2] & 0x3f;
2218		blend_mode = ta_fifo_buf[2] >> 26;
2219		srcselect=(ta_fifo_buf[2] >> 25) & 1;
2220		dstselect=(ta_fifo_buf[2] >> 24) & 1;
2221		fogcontrol=(ta_fifo_buf[2] >> 22) & 3;
2222		colorclamp=(ta_fifo_buf[2] >> 21) & 1;
2223		use_alpha = (ta_fifo_buf[2] >> 20) & 1;
2224		ignoretexalpha=(ta_fifo_buf[2] >> 19) & 1;
2225		flipuv=(ta_fifo_buf[2] >> 17) & 3;
2226		clampuv=(ta_fifo_buf[2] >> 15) & 3;
2227		filtermode=(ta_fifo_buf[2] >> 13) & 3;
2228		sstexture=(ta_fifo_buf[2] >> 12) & 1;
2229		mmdadjust=(ta_fifo_buf[2] >> 8) & 1;
2230		tsinstruction=(ta_fifo_buf[2] >> 6) & 3;
	1847	//textureusize=1 << (3+((tafifo_buff[2] >> 3) & 7));
	1848	//texturevsize=1 << (3+(tafifo_buff[2] & 7));
	1849	texturesizes=tafifo_buff[2] & 0x3f;
	1850	blend_mode = tafifo_buff[2] >> 26;
	1851	srcselect=(tafifo_buff[2] >> 25) & 1;
	1852	dstselect=(tafifo_buff[2] >> 24) & 1;
	1853	fogcontrol=(tafifo_buff[2] >> 22) & 3;
	1854	colorclamp=(tafifo_buff[2] >> 21) & 1;
	1855	use_alpha = (tafifo_buff[2] >> 20) & 1;
	1856	ignoretexalpha=(tafifo_buff[2] >> 19) & 1;
	1857	flipuv=(tafifo_buff[2] >> 17) & 3;
	1858	clampuv=(tafifo_buff[2] >> 15) & 3;
	1859	filtermode=(tafifo_buff[2] >> 13) & 3;
	1860	sstexture=(tafifo_buff[2] >> 12) & 1;
	1861	mmdadjust=(tafifo_buff[2] >> 8) & 1;
	1862	tsinstruction=(tafifo_buff[2] >> 6) & 3;
2231	1863	if (texture == 1)
2232	1864	{
2233		textureaddress=(ta_fifo_buf[3] & 0x1FFFFF) << 3;
2234		scanorder=(ta_fifo_buf[3] >> 26) & 1;
2235		pixelformat=(ta_fifo_buf[3] >> 27) & 7;
2236		mipmapped=(ta_fifo_buf[3] >> 31) & 1;
2237		vqcompressed=(ta_fifo_buf[3] >> 30) & 1;
2238		strideselect=(ta_fifo_buf[3] >> 25) & 1;
2239		paletteselector=(ta_fifo_buf[3] >> 21) & 0x3F;
	1865	textureaddress=(tafifo_buff[3] & 0x1FFFFF) << 3;
	1866	scanorder=(tafifo_buff[3] >> 26) & 1;
	1867	pixelformat=(tafifo_buff[3] >> 27) & 7;
	1868	mipmapped=(tafifo_buff[3] >> 31) & 1;
	1869	vqcompressed=(tafifo_buff[3] >> 30) & 1;
	1870	strideselect=(tafifo_buff[3] >> 25) & 1;
	1871	paletteselector=(tafifo_buff[3] >> 21) & 0x3F;
2240	1872	#if DEBUG_PVRDLIST
2241		osd_printf_verbose(" Texture at %08x format %d\n", (ta_fifo_buf[3] & 0x1FFFFF) << 3, pixelformat);
	1873	osd_printf_verbose(" Texture at %08x format %d\n", (tafifo_buff[3] & 0x1FFFFF) << 3, pixelformat);
2242	1874	#endif
2243	1875	}
2244	1876	if (paratype == 4)
r243812	r243813
2270	1902	{
2271	1903	#if DEBUG_PVRDLIST
2272	1904	osd_printf_verbose(" Vertex modifier volume");
2273		osd_printf_verbose(" A(%f,%f,%f) B(%f,%f,%f) C(%f,%f,%f)", u2f(ta_fifo_buf[1]), u2f(ta_fifo_buf[2]),
2274		u2f(ta_fifo_buf[3]), u2f(ta_fifo_buf[4]), u2f(ta_fifo_buf[5]), u2f(ta_fifo_buf[6]), u2f(ta_fifo_buf[7]),
2275		u2f(ta_fifo_buf[8]), u2f(ta_fifo_buf[9]));
	1905	osd_printf_verbose(" A(%f,%f,%f) B(%f,%f,%f) C(%f,%f,%f)", u2f(tafifo_buff[1]), u2f(tafifo_buff[2]),
	1906	u2f(tafifo_buff[3]), u2f(tafifo_buff[4]), u2f(tafifo_buff[5]), u2f(tafifo_buff[6]), u2f(tafifo_buff[7]),
	1907	u2f(tafifo_buff[8]), u2f(tafifo_buff[9]));
2276	1908	osd_printf_verbose("\n");
2277	1909	#endif
2278	1910	}
r243812	r243813
2280	1912	{
2281	1913	#if DEBUG_PVRDLIST
2282	1914	osd_printf_verbose(" Vertex sprite");
2283		osd_printf_verbose(" A(%f,%f,%f) B(%f,%f,%f) C(%f,%f,%f) D(%f,%f,)", u2f(ta_fifo_buf[1]), u2f(ta_fifo_buf[2]),
2284		u2f(ta_fifo_buf[3]), u2f(ta_fifo_buf[4]), u2f(ta_fifo_buf[5]), u2f(ta_fifo_buf[6]), u2f(ta_fifo_buf[7]),
2285		u2f(ta_fifo_buf[8]), u2f(ta_fifo_buf[9]), u2f(ta_fifo_buf[10]), u2f(ta_fifo_buf[11]));
	1915	osd_printf_verbose(" A(%f,%f,%f) B(%f,%f,%f) C(%f,%f,%f) D(%f,%f,)", u2f(tafifo_buff[1]), u2f(tafifo_buff[2]),
	1916	u2f(tafifo_buff[3]), u2f(tafifo_buff[4]), u2f(tafifo_buff[5]), u2f(tafifo_buff[6]), u2f(tafifo_buff[7]),
	1917	u2f(tafifo_buff[8]), u2f(tafifo_buff[9]), u2f(tafifo_buff[10]), u2f(tafifo_buff[11]));
2286	1918	osd_printf_verbose("\n");
2287	1919	#endif
2288	1920	if (texture == 1)
r243812	r243813
2291	1923	{
2292	1924	strip *ts;
2293	1925	vert *tv = &rd->verts[rd->verts_size];
2294		tv[0].x = u2f(ta_fifo_buf[0x1]);
2295		tv[0].y = u2f(ta_fifo_buf[0x2]);
2296		tv[0].w = u2f(ta_fifo_buf[0x3]);
2297		tv[1].x = u2f(ta_fifo_buf[0x4]);
2298		tv[1].y = u2f(ta_fifo_buf[0x5]);
2299		tv[1].w = u2f(ta_fifo_buf[0x6]);
2300		tv[3].x = u2f(ta_fifo_buf[0x7]);
2301		tv[3].y = u2f(ta_fifo_buf[0x8]);
2302		tv[3].w = u2f(ta_fifo_buf[0x9]);
2303		tv[2].x = u2f(ta_fifo_buf[0xa]);
2304		tv[2].y = u2f(ta_fifo_buf[0xb]);
	1926	tv[0].x = u2f(tafifo_buff[0x1]);
	1927	tv[0].y = u2f(tafifo_buff[0x2]);
	1928	tv[0].w = u2f(tafifo_buff[0x3]);
	1929	tv[1].x = u2f(tafifo_buff[0x4]);
	1930	tv[1].y = u2f(tafifo_buff[0x5]);
	1931	tv[1].w = u2f(tafifo_buff[0x6]);
	1932	tv[3].x = u2f(tafifo_buff[0x7]);
	1933	tv[3].y = u2f(tafifo_buff[0x8]);
	1934	tv[3].w = u2f(tafifo_buff[0x9]);
	1935	tv[2].x = u2f(tafifo_buff[0xa]);
	1936	tv[2].y = u2f(tafifo_buff[0xb]);
2305	1937	tv[2].w = tv[0].w+tv[3].w-tv[1].w;
2306		tv[0].u = u2f(ta_fifo_buf[0xd] & 0xffff0000);
2307		tv[0].v = u2f(ta_fifo_buf[0xd] << 16);
2308		tv[1].u = u2f(ta_fifo_buf[0xe] & 0xffff0000);
2309		tv[1].v = u2f(ta_fifo_buf[0xe] << 16);
2310		tv[3].u = u2f(ta_fifo_buf[0xf] & 0xffff0000);
2311		tv[3].v = u2f(ta_fifo_buf[0xf] << 16);
	1938	tv[0].u = u2f(tafifo_buff[0xd] & 0xffff0000);
	1939	tv[0].v = u2f(tafifo_buff[0xd] << 16);
	1940	tv[1].u = u2f(tafifo_buff[0xe] & 0xffff0000);
	1941	tv[1].v = u2f(tafifo_buff[0xe] << 16);
	1942	tv[3].u = u2f(tafifo_buff[0xf] & 0xffff0000);
	1943	tv[3].v = u2f(tafifo_buff[0xf] << 16);
2312	1944	tv[2].u = tv[0].u+tv[3].u-tv[1].u;
2313	1945	tv[2].v = tv[0].v+tv[3].v-tv[1].v;
2314	1946
r243812	r243813
2325	1957	{
2326	1958	#if DEBUG_PVRDLIST
2327	1959	osd_printf_verbose(" Vertex polygon");
2328		osd_printf_verbose(" V(%f,%f,%f) T(%f,%f)", u2f(ta_fifo_buf[1]), u2f(ta_fifo_buf[2]), u2f(ta_fifo_buf[3]), u2f(ta_fifo_buf[4]), u2f(ta_fifo_buf[5]));
	1960	osd_printf_verbose(" V(%f,%f,%f) T(%f,%f)", u2f(tafifo_buff[1]), u2f(tafifo_buff[2]), u2f(tafifo_buff[3]), u2f(tafifo_buff[4]), u2f(tafifo_buff[5]));
2329	1961	osd_printf_verbose("\n");
2330	1962	#endif
2331	1963	if (rd->verts_size <= 65530)
r243812	r243813
2335	1967	/* -- this is also wildly inaccurate! */
2336	1968	vert *tv = &rd->verts[rd->verts_size];
2337	1969
2338		tv->x=u2f(ta_fifo_buf[1]);
2339		tv->y=u2f(ta_fifo_buf[2]);
2340		tv->w=u2f(ta_fifo_buf[3]);
2341		tv->u=u2f(ta_fifo_buf[4]);
2342		tv->v=u2f(ta_fifo_buf[5]);
	1970	tv->x=u2f(tafifo_buff[1]);
	1971	tv->y=u2f(tafifo_buff[2]);
	1972	tv->w=u2f(tafifo_buff[3]);
	1973	tv->u=u2f(tafifo_buff[4]);
	1974	tv->v=u2f(tafifo_buff[5]);
2343	1975	if (texture == 0)
2344	1976	{
2345	1977	if(coltype == 0)
2346		nontextured_pal_int=ta_fifo_buf[6];
	1978	nontextured_pal_int=tafifo_buff[6];
2347	1979	else if(coltype == 1)
2348	1980	{
2349		nontextured_fpal_a=u2f(ta_fifo_buf[4]);
2350		nontextured_fpal_r=u2f(ta_fifo_buf[5]);
2351		nontextured_fpal_g=u2f(ta_fifo_buf[6]);
2352		nontextured_fpal_b=u2f(ta_fifo_buf[7]);
	1981	nontextured_fpal_a=u2f(tafifo_buff[4]);
	1982	nontextured_fpal_r=u2f(tafifo_buff[5]);
	1983	nontextured_fpal_g=u2f(tafifo_buff[6]);
	1984	nontextured_fpal_b=u2f(tafifo_buff[7]);
2353	1985	}
2354	1986	}
2355	1987
r243812	r243813
2368	2000	}
2369	2001	}
2370	2002	}
2371		#endif
2372	2003	}
2373	2004
2374		const int powervr2_device::ta_packet_len_table[VAR_COUNT*2] = {
2375		// Command packets
2376		8, 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 16, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
2377		// Vertex packets
2378		8, 8, 8, 8, 8, 8, 16, 16, 16, 8, 8, 16, 16, 8, 8, 8, 8, 16, 16, 8, 8, 16, 16, 16, 16, 16, 8, 8, 8, 8
2379		};
2380
2381		int powervr2_device::ta_get_packet_type()
	2005	WRITE64_MEMBER( powervr2_device::ta_fifo_poly_w )
2382	2006	{
2383		UINT32 h = ta_fifo_buf[0];
2384		switch(h >> 29) {
2385		case 0: return CMD_END_OF_LIST;
2386		case 1: return CMD_USER_TILE_CLIP;
2387		case 2: return CMD_OBJECT_LIST_SET;
2388		case 4: case 5: {
2389		if(ta_list_type == -1) {
2390		ta_list_type = (h >> 24) & 7;
2391		if(ta_list_type >= 5) {
2392		ta_list_type = -1;
2393		return VAR_UNKNOWN;
2394		}
2395		}
2396		if(ta_list_type == L_OPAQUE_SHADOW \|\| ta_list_type == L_TRANS_SHADOW)
2397		return SHADOW;
2398
2399		bool vol = h & H_DUAL;
2400		int col = (h & H_COLMODE) >> 4;
2401		bool tex = h & H_TEX;
2402		bool off = h & H_OFF;
2403		bool cuv = h & H_COMPACT_UV;
2404
2405		if((h >> 29) == 5)
2406		return tex ? SPRITE : LINE_SPRITE;
2407
2408		if(vol)
2409		if(tex)
2410		if(cuv)
2411		switch(col) {
2412		case 0: return TRI_T_U8_CUV_DUAL;
2413		case 2: return TRI_T_I_GLB_CUV_DUAL;
2414		case 3: return TRI_T_I_PREV_CUV_DUAL;
2415		}
2416		else
2417		switch(col) {
2418		case 0: return TRI_T_U8_DUAL;
2419		case 2: return TRI_T_I_GLB_DUAL;
2420		case 3: return TRI_T_I_PREV_DUAL;
2421		}
2422		else
2423		switch(col) {
2424		case 0: return TRI_G_U8_DUAL;
2425		case 2: return TRI_G_I_GLB_DUAL;
2426		case 3: return TRI_G_I_PREV_DUAL;
2427		}
2428		else
2429		if(tex)
2430		if(cuv)
2431		switch(col) {
2432		case 0: return TRI_T_U8_CUV;
2433		case 1: return TRI_T_F32_CUV;
2434		case 2: return off ? TRI_T_I_GLB_OFF_CUV : TRI_T_I_GLB_CUV;
2435		case 3: return TRI_T_I_PREV_CUV;
2436		}
2437		else
2438		switch(col) {
2439		case 0: return TRI_T_U8;
2440		case 1: return TRI_T_F32;
2441		case 2: return off ? TRI_T_I_GLB_OFF : TRI_T_I_GLB;
2442		case 3: return TRI_T_I_PREV;
2443		}
2444		else
2445		switch(col) {
2446		case 0: return TRI_G_U8;
2447		case 1: return TRI_G_F32;
2448		case 2: return TRI_G_I_GLB;
2449		case 3: return TRI_G_I_PREV;
2450		}
2451		return VAR_UNKNOWN;
	2007	if (mem_mask == U64(0xffffffffffffffff)) // 64 bit
	2008	{
	2009	tafifo_buff[tafifo_pos]=(UINT32)data;
	2010	tafifo_buff[tafifo_pos+1]=(UINT32)(data >> 32);
	2011	#if DEBUG_FIFO_POLY
	2012	osd_printf_debug("ta_fifo_poly_w: Unmapped write64 %08x = %" I64FMT "x -> %08x %08x\n", 0x10000000+offset*8, data, tafifo_buff[tafifo_pos], tafifo_buff[tafifo_pos+1]);
	2013	#endif
	2014	tafifo_pos += 2;
2452	2015	}
2453		case 7: return ta_cmd_type + VAR_COUNT;
	2016	else
	2017	{
	2018	fatalerror("ta_fifo_poly_w: Only 64 bit writes supported!\n");
2454	2019	}
2455		return VAR_UNKNOWN;
2456		}
2457	2020
2458		const char *powervr2_device::ta_packet_type_name[VAR_COUNT] = {
2459		"tri_g_f32",
2460		"tri_g_i_glb",
2461		"tri_g_i_glb_dual",
2462		"tri_g_i_prev",
2463		"tri_g_i_prev_dual",
2464		"tri_g_u8",
2465		"tri_g_u8_dual",
2466		"tri_t_f32",
2467		"tri_t_f32_cuv",
2468		"tri_t_i_glb",
2469		"tri_t_i_glb_cuv",
2470		"tri_t_i_glb_cuv_dual",
2471		"tri_t_i_glb_dual",
2472		"tri_t_i_glb_off",
2473		"tri_t_i_glb_off_cuv",
2474		"tri_t_i_prev",
2475		"tri_t_i_prev_cuv",
2476		"tri_t_i_prev_cuv_dual",
2477		"tri_t_i_prev_dual",
2478		"tri_t_u8",
2479		"tri_t_u8_cuv",
2480		"tri_t_u8_cuv_dual",
2481		"tri_t_u8_dual",
	2021	tafifo_pos &= tafifo_mask;
2482	2022
2483		"shadow",
2484		"sprite",
2485		"line_sprite",
	2023	// if the command is complete, process it
	2024	if (tafifo_pos == 0)
	2025	process_ta_fifo();
2486	2026
2487		"cmd_end_of_list",
2488		"cmd_user_tile_clip",
2489		"cmd_object_list_set",
2490
2491		"var_unknown"
2492		};
2493
2494		void powervr2_device::mem_write32(UINT32 adr, UINT32 val)
2495		{
2496		logerror("%s: write32 %08x, %08x (%g)\n", tag(), adr/4, val, u2f(val));
2497	2027	}
2498	2028
2499		void powervr2_device::ta_object_list_extend()
2500		{
2501		UINT32 ptr = ta_ol_pointers_1[ta_olist_tile];
2502		switch(ta_olist_block_size) {
2503		case 32: if((ptr & 0x1c) != 0x1c) return; break;
2504		case 64: if((ptr & 0x3c) != 0x3c) return; break;
2505		case 128: if((ptr & 0x7c) != 0x7c) return; break;
2506		}
2507
2508		logerror("%s: list extend\n", tag());
2509		exit(0);
2510		}
2511
2512		void powervr2_device::ta_add_object(UINT32 adr, bool tail)
2513		{
2514		UINT32 ptr = ta_ol_pointers_1[ta_olist_tile];
2515		if(ptr & 0x80000000) {
2516		if(!tail) {
2517		ta_object_list_extend();
2518		ptr = ta_ol_pointers_1[ta_olist_tile];
2519		}
2520		mem_write32(ptr & 0x7fffff, adr);
2521		ta_ol_pointers_1[ta_olist_tile] = (ptr & 0xff800000) \| ((ptr + 4) & 0x7fffff);
2522
2523		if(tail)
2524		ta_object_list_extend();
2525
2526		} else {
2527		mem_write32(ta_olist_pos, adr);
2528		ta_ol_pointers_1[ta_olist_tile] = ((ta_olist_pos + 4) & 0x7fffff) \| (ptr & 0x7f800000) \| 0x80000000;
2529		}
2530		// logerror("%s: ta_ol_pointers_1[%d] = %08x\n", tag(), ta_olist_tile, ta_ol_pointers_1[ta_olist_tile]);
2531		}
2532
2533		void powervr2_device::ta_handle_command_draw()
2534		{
2535		logerror("%s: command %s %08x %08x\n",
2536		tag(),
2537		ta_packet_type_name[ta_packet_type],
2538		ta_fifo_buf[0],
2539		ta_fifo_buf[1]
2540		);
2541
2542		ta_cmd_header = ta_fifo_buf[0];
2543		ta_cmd_instr = ta_fifo_buf[1];
2544
2545		if(ta_packet_type == SPRITE) {
2546		ta_cmd_header = (ta_cmd_header & ~(H_DUAL\|H_COLMODE\|H_GOURAUD)) \| (H_TEX\|H_COMPACT_UV);
2547		ta_cmd_instr = (ta_cmd_instr & ~HI_GOURAUD) \| (HI_TEX\|HI_COMPACT_UV);
2548
2549		} else if(ta_packet_type == LINE_SPRITE) {
2550		ta_cmd_header = ta_cmd_header & ~(H_DUAL\|H_COLMODE\|H_GOURAUD\|H_TEX\|H_OFF\|H_COMPACT_UV);
2551		ta_cmd_instr = ta_cmd_instr & ~(HI_GOURAUD\|HI_TEX\|HI_COMPACT_UV);
2552
2553		} else if(ta_packet_type == SHADOW)
2554		ta_cmd_header = ta_cmd_header & ~(H_DUAL\|H_TEX\|H_OFF\|H_COMPACT_UV);
2555
2556		if(!(ta_cmd_header & H_TEX)) {
2557		ta_cmd_header &= ~H_OFF;
2558		ta_cmd_instr &= ~HI_OFF;
2559		}
2560
2561		if(ta_cmd_header & H_GROUP) {
2562		switch((ta_cmd_header & H_GROUP) >> 18) {
2563		case 0: ta_cmd_strip_length = 1; break;
2564		case 1: ta_cmd_strip_length = 2; break;
2565		case 2: ta_cmd_strip_length = 4; break;
2566		case 3: ta_cmd_strip_length = 6; break;
2567		}
2568		}
2569
2570		ta_cmd_user_clip_mode = (ta_cmd_header & H_UCLIP) >> 16;
2571
2572		if(ta_packet_type == SHADOW) {
2573		ta_cmd_tsp[0] = 0;
2574		ta_cmd_tex[0] = 0;
2575		} else {
2576		ta_cmd_tsp[0] = ta_fifo_buf[2];
2577		ta_cmd_tex[0] = ta_fifo_buf[3];
2578		}
2579
2580		if(ta_packet_type == TRI_G_I_GLB_DUAL \|\|
2581		ta_packet_type == TRI_G_I_PREV_DUAL \|\|
2582		ta_packet_type == TRI_G_U8_DUAL \|\|
2583		ta_packet_type == TRI_T_I_GLB_CUV_DUAL \|\|
2584		ta_packet_type == TRI_T_I_GLB_DUAL \|\|
2585		ta_packet_type == TRI_T_I_PREV_CUV_DUAL \|\|
2586		ta_packet_type == TRI_T_I_PREV_DUAL \|\|
2587		ta_packet_type == TRI_T_U8_CUV_DUAL \|\|
2588		ta_packet_type == TRI_T_U8_DUAL) {
2589
2590		ta_cmd_tsp[1] = ta_fifo_buf[4];
2591		ta_cmd_tex[1] = ta_fifo_buf[5];
2592
2593		} else {
2594		ta_cmd_tsp[1] = 0;
2595		ta_cmd_tex[1] = 0;
2596		}
2597
2598		if(!(ta_cmd_header & H_TEX) && (ta_packet_type != SPRITE) && (ta_packet_type != LINE_SPRITE)) {
2599		ta_cmd_tex[0] = 0;
2600		ta_cmd_tex[1] = 0;
2601		}
2602
2603		switch(ta_packet_type) {
2604		case TRI_G_I_GLB:
2605		case TRI_T_I_GLB:
2606		case TRI_T_I_GLB_CUV:
2607		ta_load_color_f32(ta_cmd_color_base[0], ta_fifo_buf+4);
2608		break;
2609		case TRI_T_I_GLB_OFF:
2610		case TRI_T_I_GLB_OFF_CUV:
2611		ta_load_color_f32(ta_cmd_color_base[0], ta_fifo_buf+8);
2612		ta_load_color_f32(ta_cmd_color_offset[0], ta_fifo_buf+12);
2613		break;
2614		case TRI_G_I_GLB_DUAL:
2615		case TRI_T_I_GLB_DUAL:
2616		case TRI_T_I_GLB_CUV_DUAL:
2617		ta_load_color_f32(ta_cmd_color_base[0], ta_fifo_buf+8);
2618		ta_load_color_f32(ta_cmd_color_base[1], ta_fifo_buf+12);
2619		break;
2620		case SPRITE:
2621		case LINE_SPRITE:
2622		ta_cmd_color_sprite_base = ta_fifo_buf[4];
2623		ta_cmd_color_sprite_offset = ta_fifo_buf[5];
2624		break;
2625		}
2626		}
2627
2628		void powervr2_device::ta_next_list()
2629		{
2630		for(ta_list_idx++; ta_list_idx < 5; ta_list_idx++)
2631		if((ta_alloc_ctrl >> (4*ta_list_idx)) & 3) {
2632		ta_olist_block_size = 16 << ((ta_alloc_ctrl >> (4*ta_list_idx)) & 3);
2633		ta_olist_line_size = ta_olist_block_size*((ta_glob_tile_clip & 0x3f)+1);
2634		return;
2635		}
2636		ta_olist_block_size = 0;
2637		ta_vertex_count = 0;
2638		ta_vertex_odd_tri = false;
2639		ta_list_type = -1;
2640		ta_vertex_shadow_first = true;
2641		}
2642
2643		void powervr2_device::ta_bbox_merge(ta_bbox &bb, const ta_bbox &src) const
2644		{
2645		if(bb.min_x > src.min_x)
2646		bb.min_x = src.min_x;
2647		if(bb.min_y > src.min_y)
2648		bb.min_y = src.min_y;
2649		if(bb.max_x < src.max_x)
2650		bb.max_x = src.max_x;
2651		if(bb.max_y < src.max_y)
2652		bb.max_y = src.max_y;
2653		}
2654
2655		bool powervr2_device::ta_bbox_vertex(ta_bbox &bb, const ta_vertex *vtx, int count) const
2656		{
2657		bb.min_x = bb.max_x = vtx->tx();
2658		bb.min_y = bb.max_y = vtx->ty();
2659		for(int i=1; i<count; i++) {
2660		int xx = vtx[i].tx();
2661		int yy = vtx[i].ty();
2662		if(bb.min_x > xx)
2663		bb.min_x = xx;
2664		if(bb.min_y > yy)
2665		bb.min_y = yy;
2666		if(bb.max_x < xx)
2667		bb.max_x = xx;
2668		if(bb.max_y < yy)
2669		bb.max_y = yy;
2670		}
2671
2672		int sx = ta_glob_tile_clip & 0x3f;
2673		int sy = (ta_glob_tile_clip >> 16) & 0xf;
2674		bool clipped = false;
2675		if(bb.min_x <= sx && bb.max_x >= 0) {
2676		if(bb.min_x <= 0)
2677		bb.min_x = 0;
2678		if(bb.max_x > sx)
2679		bb.max_x = sx;
2680		} else {
2681		clipped = true;
2682		if(bb.max_x < 0)
2683		bb.min_x = bb.max_x = 0;
2684		else
2685		bb.min_x = bb.max_x = sx;
2686		}
2687		if(bb.min_y <= sy && bb.max_y >= 0) {
2688		if(bb.min_y <= 0)
2689		bb.min_y = 0;
2690		if(bb.max_y > sy)
2691		bb.max_y = sy;
2692		} else {
2693		clipped = true;
2694		if(bb.max_y < 0)
2695		bb.min_y = bb.max_y = 0;
2696		else
2697		bb.min_y = bb.max_y = sy;
2698		}
2699
2700		return clipped;
2701		}
2702
2703		UINT32 powervr2_device::ta_strip_write(bool single_tile, UINT32 &psize)
2704		{
2705		bool shadow = ta_list_type == L_OPAQUE_SHADOW \|\| ta_list_type == L_TRANS_SHADOW;
2706
2707		UINT32 base_adr = ta_itp_current;
2708		UINT32 adr = base_adr;
2709
2710		psize = 0;
2711		if(ta_cmd_header & H_TEX)
2712		psize += ta_cmd_header & H_COMPACT_UV ? 4 : 8;
2713		if(!shadow)
2714		psize += 4;
2715		if(ta_cmd_header & H_DUAL)
2716		psize *= 2;
2717		psize = (psize + 12)*ta_vertex_count + 12;
2718		if(ta_cmd_header & H_DUAL)
2719		psize += 8;
2720		if(adr+psize > ta_isp_limit)
2721		return 0xffffffff;
2722
2723		mem_write32(adr, ta_cmd_instr \| (single_tile ? 0x00200000 : 0x00000000)); adr += 4;
2724		mem_write32(adr, ta_cmd_tsp[0]); adr += 4;
2725		mem_write32(adr, ta_cmd_tex[0]); adr += 4;
2726
2727		if(ta_cmd_header & H_DUAL) {
2728		mem_write32(adr, ta_cmd_tsp[1]); adr += 4;
2729		mem_write32(adr, ta_cmd_tex[1]); adr += 4;
2730		}
2731
2732		for(int i=0; i<ta_vertex_count; i++) {
2733		mem_write32(adr, ta_vertex_strip[i].coords[0]); adr += 4;
2734		mem_write32(adr, ta_vertex_strip[i].coords[1]); adr += 4;
2735		mem_write32(adr, ta_vertex_strip[i].coords[2]); adr += 4;
2736		if(ta_cmd_header & H_TEX) {
2737		if(ta_cmd_header & H_COMPACT_UV) {
2738		mem_write32(adr, ta_vertex_strip[i].uvc[0]); adr += 4;
2739		} else {
2740		mem_write32(adr, f2u(ta_vertex_strip[i].uv[0][0])); adr += 4;
2741		mem_write32(adr, f2u(ta_vertex_strip[i].uv[0][1])); adr += 4;
2742		}
2743		}
2744		if(!shadow) {
2745		mem_write32(adr, ta_vertex_strip[i].color_base[0]); adr += 4;
2746		}
2747		if(ta_cmd_header & H_OFF) {
2748		mem_write32(adr, ta_vertex_strip[i].color_offset[0]); adr += 4;
2749		}
2750		if(ta_cmd_header & H_DUAL) {
2751		if(ta_cmd_header & H_TEX) {
2752		if(ta_cmd_header & H_COMPACT_UV) {
2753		mem_write32(adr, ta_vertex_strip[i].uvc[1]); adr += 4;
2754		} else {
2755		mem_write32(adr, f2u(ta_vertex_strip[i].uv[1][0])); adr += 4;
2756		mem_write32(adr, f2u(ta_vertex_strip[i].uv[1][1])); adr += 4;
2757		}
2758		}
2759		if(!shadow) {
2760		mem_write32(adr, ta_vertex_strip[i].color_base[1]); adr += 4;
2761		}
2762		if(ta_cmd_header & H_OFF) {
2763		mem_write32(adr, ta_vertex_strip[i].color_offset[1]); adr += 4;
2764		}
2765		}
2766		}
2767		ta_itp_current = adr;
2768		return base_adr - (ta_isp_base & 0xfff00000);
2769		}
2770
2771
2772		void powervr2_device::ta_add_strip(UINT32 adr, UINT32 psize)
2773		{
2774		logerror("%s: add strip %08x\n", tag(), adr);
2775		if(adr & 0x80000000) { // not strip, may concatenate into an array
2776		logerror("%s: tri or quad\n", tag());
2777		if(ta_ol_pointers_1[ta_olist_tile] & 0x40000000) {
2778		UINT32 cache = ta_ol_pointers_2[ta_olist_tile];
2779		bool conc = (adr & 0xc0000000) == 0x80000000; // tri or quad
2780		logerror("%s: a %d %08x\n", tag(), conc, adr);
2781		conc = conc && ((adr & 0xe1e00000) == (cache & 0xe1e00000)); // skip, shadow and tri/quad match
2782		logerror("%s: b %d %08x %08x\n", tag(), conc, adr, cache);
2783		conc = conc && ((cache & 0x1e000000) != 0x1e000000); // Max size not reached
2784		logerror("%s: c %d %08x\n", tag(), conc, cache);
2785		conc = conc && ((adr & 0x1fffff) == (cache & 0x1fffff) + ((((cache >> 25) & 0xf)+1)*psize >> 2)); // Data actually consecutive
2786		logerror("%s: d %d %08x %08x\n", tag(), conc, (adr - cache) & 0x1fffff, (((cache >> 25) & 0xf)+1)*psize >> 2);
2787		if(conc)
2788		ta_ol_pointers_2[ta_olist_tile] += 0x2000000; // Increment the count
2789		else {
2790		ta_add_object(ta_ol_pointers_2[ta_olist_tile], true);
2791		ta_ol_pointers_2[ta_olist_tile] = adr;
2792		}
2793
2794		} else {
2795		ta_ol_pointers_2[ta_olist_tile] = adr;
2796		ta_ol_pointers_1[ta_olist_tile] \|= 0x40000000;
2797		ta_object_list_extend();
2798		}
2799		} else { // strip, no concatenation
2800		if(ta_ol_pointers_1[ta_olist_tile] & 0x40000000) {
2801		ta_add_object(ta_ol_pointers_2[ta_olist_tile], true);
2802		ta_ol_pointers_1[ta_olist_tile] &= ~0x40000000;
2803		}
2804		ta_add_object(adr, false);
2805		}
2806		}
2807
2808		void powervr2_device::ta_vertex_write()
2809		{
2810		ta_bbox prim_bbox[6], full_bbox;
2811		bool prim_clipped[6], full_clipped;
2812		int prims;
2813		UINT32 op_tag;
2814		bool use_mask = false;
2815		switch(ta_cmd_type) {
2816		case SPRITE:
2817		case LINE_SPRITE: {
2818		prims = 1;
2819		full_clipped = prim_clipped[0] = ta_bbox_vertex(prim_bbox[0], ta_vertex_strip, 4);
2820		full_bbox = prim_bbox[0];
2821		UINT32 skip =
2822		ta_cmd_header & H_TEX ?
2823		ta_cmd_header & H_OFF ? 27 : 23
2824		: 19;
2825		op_tag = 0xa0000000 \| (skip << 21);
2826		break;
2827		}
2828
2829		case SHADOW: {
2830		prims = 1;
2831		full_clipped = prim_clipped[0] = ta_bbox_vertex(prim_bbox[0], ta_vertex_strip, 3);
2832
2833		if(!full_clipped && ta_vertex_shadow_first) {
2834		ta_vertex_shadow_bbox = prim_bbox[0];
2835		ta_vertex_shadow_first = false;
2836		} else
2837		ta_bbox_merge(ta_vertex_shadow_bbox, prim_bbox[0]);
2838
2839		if(!ta_vertex_shadow_first && (ta_cmd_instr & 0xe0000000)) {
2840		prim_bbox[0] = ta_vertex_shadow_bbox;
2841		full_clipped = false;
2842		ta_vertex_shadow_first = true;
2843		}
2844		full_bbox = prim_bbox[0];
2845		op_tag = 0x80000000;
2846		break;
2847		}
2848
2849		default: {
2850		if(ta_vertex_count < 3)
2851		return;
2852		prims = ta_vertex_count - 2;
2853		full_clipped = true;
2854		for(int i=0; i<prims; i++) {
2855		prim_clipped[i] = ta_bbox_vertex(prim_bbox[i], ta_vertex_strip+i, 3);
2856		if(!prim_clipped[i])
2857		full_clipped = false;
2858		if(i)
2859		ta_bbox_merge(full_bbox, prim_bbox[i]);
2860		else
2861		full_bbox = prim_bbox[i];
2862		}
2863		UINT32 skip =
2864		ta_cmd_header & H_TEX ?
2865		ta_cmd_header & H_OFF ?
2866		ta_cmd_header & H_COMPACT_UV ? 3 : 4
2867		: ta_cmd_header & H_COMPACT_UV ? 2 : 3
2868		: 1;
2869		op_tag = skip << 21;
2870		if(prims == 1)
2871		op_tag \|= 0x80000000;
2872		else
2873		use_mask = true;
2874		break;
2875		}
2876		}
2877
2878		if(full_clipped)
2879		return;
2880
2881		switch(ta_cmd_user_clip_mode) {
2882		case 2: // inside
2883		if(full_bbox.min_x < ta_clip_min_x \|\|
2884		full_bbox.max_x > ta_clip_max_x \|\|
2885		full_bbox.min_y < ta_clip_min_y \|\|
2886		full_bbox.max_y > ta_clip_max_y)
2887		return;
2888		break;
2889
2890		case 3: // outside
2891		if(full_bbox.min_x >= ta_clip_min_x &&
2892		full_bbox.max_x <= ta_clip_max_x &&
2893		full_bbox.min_y >= ta_clip_min_y &&
2894		full_bbox.max_y <= ta_clip_max_y)
2895		return;
2896		break;
2897		}
2898
2899		bool single_tile = full_bbox.min_x == full_bbox.max_x && full_bbox.min_y == full_bbox.max_y;
2900		int sx = (ta_glob_tile_clip & 0x3f) + 1;
2901		UINT32 params_address = 0xffffffff;
2902		UINT32 lbase = ta_olist_pos_base + full_bbox.min_xta_olist_block_size + full_bbox.min_yta_olist_line_size;
2903		UINT32 tbase = full_bbox.min_x + full_bbox.min_y*sx;
2904		UINT32 psize = 0;
2905
2906		logerror("%s: full_bbox (%d, %d) - (%d, %d)\n", tag(),
2907		full_bbox.min_x, full_bbox.min_y,
2908		full_bbox.max_x, full_bbox.max_y);
2909		for(int y = full_bbox.min_y; y <= full_bbox.max_y; y++) {
2910		bool clip = false;
2911		switch(ta_cmd_user_clip_mode) {
2912		case 2: // inside
2913		clip = y < ta_clip_min_y \|\| y > ta_clip_max_y;
2914		break;
2915
2916		case 3: // outside
2917		clip = y >= ta_clip_min_y && y <= ta_clip_max_y;
2918		break;
2919		}
2920
2921		if(!clip) {
2922		ta_olist_pos = lbase;
2923		ta_olist_tile = tbase;
2924		for(int x = full_bbox.min_x; x <= full_bbox.max_x; x++) {
2925		clip = ta_olist_tile >= OL_POINTERS_COUNT;
2926		switch(ta_cmd_user_clip_mode) {
2927		case 2: // inside
2928		clip = x < ta_clip_min_x \|\| x > ta_clip_max_x;
2929		break;
2930
2931		case 3: // outside
2932		clip = x >= ta_clip_min_x && x <= ta_clip_max_x;
2933		break;
2934		}
2935
2936		if(!clip) {
2937		UINT32 mask = 0;
2938		if(use_mask)
2939		for(int i=0; i<prims; i++)
2940		if(!prim_clipped[i] &&
2941		x >= prim_bbox[i].min_x &&
2942		x <= prim_bbox[i].max_x &&
2943		y >= prim_bbox[i].min_y &&
2944		y <= prim_bbox[i].max_y)
2945		mask \|= 0x40000000 >> i;
2946		if(!use_mask \|\| mask) {
2947		if(params_address == 0xffffffff) {
2948		params_address = ta_strip_write(single_tile, psize);
2949		if(params_address == 0xffffffff)
2950		return;
2951		logerror("%s: params_address = %08x\n", tag(), params_address);
2952		}
2953		UINT32 op = ((params_address >> 2) & 0x1fffff) \| op_tag \| mask;
2954		ta_add_strip(op, psize);
2955		}
2956		}
2957		ta_olist_pos += ta_olist_block_size;
2958		ta_olist_tile++;
2959		}
2960		}
2961		tbase += sx;
2962		lbase += ta_olist_line_size;
2963		}
2964		}
2965
2966		void powervr2_device::ta_vertex_push()
2967		{
2968		int strip_size;
2969		switch(ta_cmd_type) {
2970		case SPRITE:
2971		case LINE_SPRITE:
2972		strip_size = 4;
2973		break;
2974		case SHADOW:
2975		strip_size = 3;
2976		break;
2977		default:
2978		strip_size = ta_cmd_strip_length + 2;
2979		break;
2980		}
2981
2982		ta_vertex_strip[ta_vertex_count++] = ta_vertex_current;
2983
2984		if(ta_vertex_count == strip_size \|\| (ta_vertex_current.header & H_EOSTRIP)) {
2985		ta_vertex_write();
2986		if(!(ta_vertex_current.header & H_EOSTRIP)) {
2987		if(ta_cmd_strip_length == 1) {
2988		if(ta_vertex_odd_tri) {
2989		ta_vertex_strip[0] = ta_vertex_strip[ta_vertex_count-3];
2990		ta_vertex_strip[1] = ta_vertex_strip[ta_vertex_count-1];
2991		} else {
2992		ta_vertex_strip[0] = ta_vertex_strip[ta_vertex_count-1];
2993		ta_vertex_strip[1] = ta_vertex_strip[ta_vertex_count-2];
2994		}
2995		ta_vertex_odd_tri = !ta_vertex_odd_tri;
2996		} else {
2997		ta_vertex_strip[0] = ta_vertex_strip[ta_vertex_count-2];
2998		ta_vertex_strip[1] = ta_vertex_strip[ta_vertex_count-1];
2999		}
3000		ta_vertex_count = 2;
3001		} else {
3002		ta_vertex_count = 0;
3003		ta_vertex_odd_tri = false;
3004		}
3005		}
3006		}
3007
3008		void powervr2_device::ta_handle_vertex()
3009		{
3010		if(ta_cmd_type != SHADOW && ta_cmd_type != SPRITE && ta_cmd_type != LINE_SPRITE) {
3011		ta_vertex_current.header = ta_fifo_buf[0];
3012		ta_vertex_current.coords[0] = ta_fifo_buf[1];
3013		ta_vertex_current.coords[1] = ta_fifo_buf[2];
3014		ta_vertex_current.coords[2] = ta_fifo_buf[3];
3015		}
3016
3017		switch(ta_cmd_type) {
3018		case TRI_G_U8:
3019		ta_vertex_current.color_base[0] = ta_fifo_buf[6];
3020		ta_vertex_push();
3021		break;
3022
3023		case TRI_G_F32:
3024		ta_vertex_current.color_base[0] = ta_color_f32_to_u8(ta_fifo_buf+4);
3025		ta_vertex_push();
3026		break;
3027
3028		case TRI_G_I_GLB:
3029		case TRI_G_I_PREV:
3030		ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
3031		ta_vertex_push();
3032		break;
3033
3034		case TRI_G_U8_DUAL:
3035		ta_vertex_current.color_base[0] = ta_fifo_buf[4];
3036		ta_vertex_current.color_base[1] = ta_fifo_buf[5];
3037		ta_vertex_push();
3038		break;
3039
3040		case TRI_G_I_GLB_DUAL:
3041		case TRI_G_I_PREV_DUAL:
3042		ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[4]);
3043		ta_vertex_current.color_base[1] = ta_intensity(ta_cmd_color_base[1], ta_fifo_buf[5]);
3044		ta_vertex_push();
3045		break;
3046
3047		case TRI_T_U8:
3048		ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
3049		ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
3050		ta_vertex_current.color_base[0] = ta_fifo_buf[6];
3051		ta_vertex_current.color_offset[0] = ta_fifo_buf[7];
3052		ta_vertex_push();
3053		break;
3054
3055		case TRI_T_U8_CUV:
3056		ta_vertex_current.uvc[0] = ta_fifo_buf[4];
3057		ta_vertex_current.color_base[0] = ta_fifo_buf[6];
3058		ta_vertex_current.color_offset[0] = ta_fifo_buf[7];
3059		ta_vertex_push();
3060		break;
3061
3062		case TRI_T_F32:
3063		ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
3064		ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
3065		ta_vertex_current.color_base[0] = ta_color_f32_to_u8(ta_fifo_buf+8);
3066		ta_vertex_current.color_offset[0] = ta_color_f32_to_u8(ta_fifo_buf+12);
3067		ta_vertex_push();
3068		break;
3069
3070		case TRI_T_F32_CUV:
3071		ta_vertex_current.uvc[0] = ta_fifo_buf[4];
3072		ta_vertex_current.color_base[0] = ta_color_f32_to_u8(ta_fifo_buf+8);
3073		ta_vertex_current.color_offset[0] = ta_color_f32_to_u8(ta_fifo_buf+12);
3074		ta_vertex_push();
3075		break;
3076
3077		case TRI_T_I_GLB:
3078		case TRI_T_I_GLB_OFF:
3079		case TRI_T_I_PREV:
3080		ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
3081		ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
3082		ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
3083		ta_vertex_current.color_offset[0] = ta_intensity(ta_cmd_color_offset[0], ta_fifo_buf[7]);
3084		ta_vertex_push();
3085		break;
3086
3087		case TRI_T_I_GLB_CUV:
3088		case TRI_T_I_GLB_OFF_CUV:
3089		case TRI_T_I_PREV_CUV:
3090		ta_vertex_current.uvc[0] = ta_fifo_buf[4];
3091		ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
3092		ta_vertex_current.color_offset[0] = ta_intensity(ta_cmd_color_offset[0], ta_fifo_buf[7]);
3093		ta_vertex_push();
3094		break;
3095
3096		case TRI_T_U8_DUAL:
3097		ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
3098		ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
3099		ta_vertex_current.color_base[0] = ta_fifo_buf[6];
3100		ta_vertex_current.color_offset[0] = ta_fifo_buf[7];
3101		ta_vertex_current.uv[1][0] = ta_fifo_buf[8];
3102		ta_vertex_current.uv[1][1] = ta_fifo_buf[9];
3103		ta_vertex_current.color_base[1] = ta_fifo_buf[10];
3104		ta_vertex_current.color_offset[1] = ta_fifo_buf[11];
3105		ta_vertex_push();
3106		break;
3107
3108		case TRI_T_U8_CUV_DUAL:
3109		ta_vertex_current.uvc[0] = ta_fifo_buf[4];
3110		ta_vertex_current.color_base[0] = ta_fifo_buf[6];
3111		ta_vertex_current.color_offset[0] = ta_fifo_buf[7];
3112		ta_vertex_current.uvc[1] = ta_fifo_buf[8];
3113		ta_vertex_current.color_base[1] = ta_fifo_buf[10];
3114		ta_vertex_current.color_offset[1] = ta_fifo_buf[11];
3115		ta_vertex_push();
3116		break;
3117
3118		case TRI_T_I_GLB_DUAL:
3119		case TRI_T_I_PREV_DUAL:
3120		ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
3121		ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
3122		ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
3123		ta_vertex_current.color_offset[0] = ta_intensity(ta_cmd_color_offset[0], ta_fifo_buf[7]);
3124		ta_vertex_current.uv[1][0] = ta_fifo_buf[8];
3125		ta_vertex_current.uv[1][1] = ta_fifo_buf[9];
3126		ta_vertex_current.color_base[1] = ta_intensity(ta_cmd_color_base[1], ta_fifo_buf[10]);
3127		ta_vertex_current.color_offset[1] = ta_intensity(ta_cmd_color_offset[1], ta_fifo_buf[11]);
3128		ta_vertex_push();
3129		break;
3130
3131		case TRI_T_I_GLB_CUV_DUAL:
3132		case TRI_T_I_PREV_CUV_DUAL:
3133		ta_vertex_current.uvc[0] = ta_fifo_buf[4];
3134		ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
3135		ta_vertex_current.color_offset[0] = ta_intensity(ta_cmd_color_offset[0], ta_fifo_buf[7]);
3136		ta_vertex_current.uvc[1] = ta_fifo_buf[8];
3137		ta_vertex_current.color_base[1] = ta_intensity(ta_cmd_color_base[1], ta_fifo_buf[10]);
3138		ta_vertex_current.color_offset[1] = ta_intensity(ta_cmd_color_offset[1], ta_fifo_buf[11]);
3139		ta_vertex_push();
3140		break;
3141
3142		case SPRITE:
3143		ta_vertex_current.header = 0xe0000000;
3144		ta_vertex_current.color_base[0] = 0;
3145		ta_vertex_current.color_offset[0] = 0;
3146		ta_vertex_current.coords[0] = ta_fifo_buf[1];
3147		ta_vertex_current.coords[1] = ta_fifo_buf[2];
3148		ta_vertex_current.coords[2] = ta_fifo_buf[3];
3149		ta_vertex_current.uvc[0] = ta_fifo_buf[13];
3150		ta_vertex_push();
3151
3152		ta_vertex_current.header = 0xe0000000;
3153		ta_vertex_current.color_base[0] = 0;
3154		ta_vertex_current.color_offset[0] = 0;
3155		ta_vertex_current.coords[0] = ta_fifo_buf[4];
3156		ta_vertex_current.coords[1] = ta_fifo_buf[5];
3157		ta_vertex_current.coords[2] = ta_fifo_buf[6];
3158		ta_vertex_current.uvc[0] = ta_fifo_buf[14];
3159		ta_vertex_push();
3160
3161		ta_vertex_current.header = 0xe0000000;
3162		ta_vertex_current.color_base[0] = ta_cmd_color_sprite_base;
3163		ta_vertex_current.color_offset[0] = ta_cmd_color_sprite_offset;
3164		ta_vertex_current.coords[0] = ta_fifo_buf[7];
3165		ta_vertex_current.coords[1] = ta_fifo_buf[8];
3166		ta_vertex_current.coords[2] = ta_fifo_buf[9];
3167		ta_vertex_current.uvc[0] = ta_fifo_buf[15];
3168		ta_vertex_push();
3169
3170		ta_vertex_current.header = 0xe0000000 \| H_EOSTRIP;
3171		ta_vertex_current.color_base[0] = 0;
3172		ta_vertex_current.color_offset[0] = 0;
3173		ta_vertex_current.coords[0] = ta_fifo_buf[10];
3174		ta_vertex_current.coords[1] = ta_fifo_buf[11];
3175		ta_vertex_current.coords[2] = 0;
3176		ta_vertex_current.uvc[0] = 0;
3177		ta_vertex_push();
3178		break;
3179
3180		case LINE_SPRITE:
3181		ta_vertex_current.header = 0xe0000000;
3182		ta_vertex_current.color_base[0] = 0;
3183		ta_vertex_current.coords[0] = ta_fifo_buf[1];
3184		ta_vertex_current.coords[1] = ta_fifo_buf[2];
3185		ta_vertex_current.coords[2] = ta_fifo_buf[3];
3186		ta_vertex_push();
3187
3188		ta_vertex_current.header = 0xe0000000;
3189		ta_vertex_current.color_base[0] = 0;
3190		ta_vertex_current.coords[0] = ta_fifo_buf[4];
3191		ta_vertex_current.coords[1] = ta_fifo_buf[5];
3192		ta_vertex_current.coords[2] = ta_fifo_buf[6];
3193		ta_vertex_push();
3194
3195		ta_vertex_current.header = 0xe0000000;
3196		ta_vertex_current.color_base[0] = ta_cmd_color_sprite_base;
3197		ta_vertex_current.coords[0] = ta_fifo_buf[7];
3198		ta_vertex_current.coords[1] = ta_fifo_buf[8];
3199		ta_vertex_current.coords[2] = ta_fifo_buf[9];
3200		ta_vertex_push();
3201
3202		ta_vertex_current.header = 0xf0000000;
3203		ta_vertex_current.color_base[0] = 0;
3204		ta_vertex_current.coords[0] = ta_fifo_buf[10];
3205		ta_vertex_current.coords[1] = ta_fifo_buf[11];
3206		ta_vertex_current.coords[2] = 0;
3207		ta_vertex_push();
3208		break;
3209
3210		case SHADOW:
3211		ta_vertex_current.header = 0xe0000000;
3212		ta_vertex_current.coords[0] = ta_fifo_buf[1];
3213		ta_vertex_current.coords[1] = ta_fifo_buf[2];
3214		ta_vertex_current.coords[2] = ta_fifo_buf[3];
3215		ta_vertex_push();
3216
3217		ta_vertex_current.header = 0xe0000000;
3218		ta_vertex_current.coords[0] = ta_fifo_buf[4];
3219		ta_vertex_current.coords[1] = ta_fifo_buf[5];
3220		ta_vertex_current.coords[2] = ta_fifo_buf[6];
3221		ta_vertex_push();
3222
3223		ta_vertex_current.header = 0xf0000000;
3224		ta_vertex_current.coords[0] = ta_fifo_buf[7];
3225		ta_vertex_current.coords[1] = ta_fifo_buf[8];
3226		ta_vertex_current.coords[2] = ta_fifo_buf[9];
3227		ta_vertex_push();
3228		break;
3229		}
3230		}
3231
3232		void powervr2_device::ta_handle_command_end_of_list()
3233		{
3234		int sx = ta_glob_tile_clip & 0x3f;
3235		int sy = (ta_glob_tile_clip >> 16) & 0xf;
3236		ta_olist_tile = 0;
3237		ta_olist_pos = ta_olist_pos_base;
3238		for(int y=0; y<=sy; y++)
3239		for(int x=0; x<=sx; x++) {
3240		if(ta_olist_tile >= OL_POINTERS_COUNT)
3241		break;
3242		UINT32 ptr = ta_ol_pointers_1[ta_olist_tile];
3243		if(ptr & 0x40000000) {
3244		ta_add_object(ta_ol_pointers_2[ta_olist_tile], false);
3245		ptr = ta_ol_pointers_1[ta_olist_tile];
3246		}
3247		if(!(ptr & 0x80000000))
3248		ptr = ta_olist_pos;
3249		else
3250		ptr &= 0x007fffff;
3251		mem_write32(ptr, 0xf0000000);
3252
3253		ta_ol_pointers_1[ta_olist_tile] = 0;
3254
3255		ta_olist_tile++;
3256		ta_olist_pos += ta_olist_block_size;
3257		}
3258		ta_olist_pos_base = ta_olist_pos;
3259		irq_cb(EOXFER_OPLST_IRQ + ta_list_idx);
3260		ta_next_list();
3261		}
3262
3263		void powervr2_device::ta_handle_command_user_tile_clip()
3264		{
3265		ta_clip_min_x = ta_fifo_buf[4];
3266		ta_clip_min_y = ta_fifo_buf[5];
3267		ta_clip_max_x = ta_fifo_buf[6];
3268		ta_clip_max_y = ta_fifo_buf[7];
3269		}
3270
3271		void powervr2_device::ta_handle_command_object_list_set()
3272		{
3273		logerror("%s: object lists unhandled\n", tag());
3274		}
3275
3276
3277		WRITE64_MEMBER( powervr2_device::ta_fifo_poly_w )
3278		{
3279		if (mem_mask != U64(0xffffffffffffffff)) // 64 bit
3280		fatalerror("ta_fifo_poly_w: Only 64 bit writes supported!\n");
3281
3282		logerror("%s: rec ta_fifo_poly_w %08x\n", tag(), UINT32(data));
3283		logerror("%s: rec ta_fifo_poly_w %08x\n", tag(), UINT32(data >> 32));
3284
3285		if(ta_list_idx == 5)
3286		return;
3287
3288		ta_fifo_buf[ta_fifo_pos] = data;
3289		ta_fifo_buf[ta_fifo_pos+1] = data >> 32;
3290
3291		if(!ta_fifo_pos) {
3292		ta_packet_type = ta_get_packet_type();
3293		if(ta_packet_type < VAR_COUNT)
3294		ta_cmd_type = ta_packet_type;
3295		ta_packet_len = ta_packet_len_table[ta_packet_type];
3296		}
3297
3298		ta_fifo_pos += 2;
3299
3300		if (ta_fifo_pos == ta_packet_len) {
3301		if(ta_packet_type == CMD_END_OF_LIST)
3302		ta_handle_command_end_of_list();
3303		else if(ta_packet_type == CMD_USER_TILE_CLIP)
3304		ta_handle_command_user_tile_clip();
3305		else if(ta_packet_type == CMD_OBJECT_LIST_SET)
3306		ta_handle_command_object_list_set();
3307		else if(ta_packet_type >= TRI_G_F32 && ta_packet_type <= LINE_SPRITE)
3308		ta_handle_command_draw();
3309		else if(ta_packet_type >= TRI_G_F32+VAR_COUNT && ta_packet_type <= LINE_SPRITE+VAR_COUNT)
3310		ta_handle_vertex();
3311
3312		ta_fifo_pos = 0;
3313		ta_packet_len = 0;
3314		}
3315		}
3316
3317	2029	TIMER_CALLBACK_MEMBER(powervr2_device::yuv_convert_end)
3318	2030	{
3319	2031	irq_cb(EOXFER_YUV_IRQ);
r243812	r243813
4290	3002
4291	3003	void powervr2_device::pvr_drawframebuffer(bitmap_rgb32 &bitmap,const rectangle &cliprect)
4292	3004	{
4293		#if 0
4294	3005	int x,y,dy,xi;
4295	3006	UINT32 addrp;
4296	3007	UINT32 *fbaddr;
r243812	r243813
4547	3258	}
4548	3259	break;
4549	3260	}
4550		#endif
4551	3261	}
4552	3262
4553	3263
r243812	r243813
4916	3626	fake_accumulationbuffer_bitmap = auto_bitmap_rgb32_alloc(machine(),2048,2048);
4917	3627
4918	3628	softreset = 0;
4919		test_select = 0;
4920	3629	param_base = 0;
4921	3630	region_base = 0;
4922		span_sort_cfg = 0;
4923	3631	vo_border_col = 0;
4924	3632	fb_r_ctrl = 0;
4925	3633	fb_w_ctrl = 0;
r243812	r243813
4931	3639	fb_w_sof2 = 0;
4932	3640	fb_x_clip = 0;
4933	3641	fb_y_clip = 0;
4934		fpu_shad_scale = 0;
4935		fpu_cull_val = 0;
4936	3642	fpu_param_cfg = 0;
4937		half_offset = 0;
4938		fpu_perp_val = 0;
4939		isp_backgnd_d = 0;
4940	3643	isp_backgnd_t = 0;
4941		isp_feed_cfg = 0;
4942		sdram_refresh = 0;
4943		sdram_arb_cfg = 0;
4944		sdram_cfg = 0;
4945		fog_col_ram = 0;
4946		fog_col_vert = 0;
4947		fog_density = 0;
4948		fog_clamp_max = 0;
4949		fog_clamp_min = 0;
4950		spg_trigger_pos = 0;
4951	3644	spg_hblank_int = 0;
4952	3645	spg_vblank_int = 0;
4953	3646	spg_hblank = 0;
r243812	r243813
4955	3648	spg_vblank = 0;
4956	3649	spg_width = 0;
4957	3650	spg_control = 0;
4958		text_control = 0;
4959	3651	vo_control = 0;
4960	3652	vo_startx = 0;
4961	3653	vo_starty = 0;
4962		~~scal~~er_ctl = 0;
	3654	text_control = 0;
4963	3655	pal_ram_ctrl = 0;
4964		fb_burstctrl = 0;
4965		y_coeff = 0;
4966		pt_alpha_ref = 255;
4967	3656	ta_ol_base = 0;
4968	3657	ta_ol_limit = 0;
4969	3658	ta_isp_base = 0;
r243812	r243813
4978	3667	memset(fog_table, 0, sizeof(fog_table));
4979	3668	memset(palette, 0, sizeof(palette));
4980	3669	memset(&m_pvr_dma, 0x00, sizeof(m_pvr_dma));
4981		memset(ta_ol_pointers_1, 0, sizeof(ta_ol_pointers_1));
4982		memset(ta_ol_pointers_2, 0, sizeof(ta_ol_pointers_2));
4983	3670
4984		ta_clip_min_x = 0;
4985		ta_clip_max_x = 0;
4986		ta_clip_min_y = 0;
4987		ta_clip_max_y = 0;
4988
4989	3671	sb_pdstap = 0;
4990	3672	sb_pdstar = 0;
4991	3673	sb_pdlen = 0;
r243812	r243813
4995	3677	sb_pdst = 0;
4996	3678	sb_pdapro = 0;
4997	3679
4998		sdram = auto_alloc_array(machine(), UINT32, 410241024);
4999
5000		save_pointer(NAME(sdram), 410241024);
5001	3680	save_item(NAME(softreset));
5002		save_item(NAME(test_select));
5003	3681	save_item(NAME(param_base));
5004	3682	save_item(NAME(region_base));
5005		save_item(NAME(span_sort_cfg));
5006	3683	save_item(NAME(vo_border_col));
5007	3684	save_item(NAME(fb_r_ctrl));
5008	3685	save_item(NAME(fb_w_ctrl));
r243812	r243813
5014	3691	save_item(NAME(fb_w_sof2));
5015	3692	save_item(NAME(fb_x_clip));
5016	3693	save_item(NAME(fb_y_clip));
5017		save_item(NAME(fpu_shad_scale));
5018		save_item(NAME(fpu_cull_val));
5019	3694	save_item(NAME(fpu_param_cfg));
5020		save_item(NAME(half_offset));
5021		save_item(NAME(fpu_perp_val));
5022		save_item(NAME(isp_backgnd_d));
5023	3695	save_item(NAME(isp_backgnd_t));
5024		save_item(NAME(isp_feed_cfg));
5025		save_item(NAME(sdram_refresh));
5026		save_item(NAME(sdram_arb_cfg));
5027		save_item(NAME(sdram_cfg));
5028		save_item(NAME(fog_col_ram));
5029		save_item(NAME(fog_col_vert));
5030		save_item(NAME(fog_density));
5031		save_item(NAME(fog_clamp_max));
5032		save_item(NAME(fog_clamp_min));
5033		save_item(NAME(spg_trigger_pos));
5034	3696	save_item(NAME(spg_hblank_int));
5035	3697	save_item(NAME(spg_vblank_int));
5036	3698	save_item(NAME(spg_hblank));
5037	3699	save_item(NAME(spg_load));
5038	3700	save_item(NAME(spg_vblank));
5039	3701	save_item(NAME(spg_width));
5040		save_item(NAME(text_control));
5041	3702	save_item(NAME(vo_control));
5042	3703	save_item(NAME(vo_startx));
5043	3704	save_item(NAME(vo_starty));
5044		save_item(NAME(~~scal~~er_ctl));
	3705	save_item(NAME(text_control));
5045	3706	save_item(NAME(pal_ram_ctrl));
5046		save_item(NAME(fb_burstctrl));
5047		save_item(NAME(y_coeff));
5048		save_item(NAME(pt_alpha_ref));
5049	3707	save_item(NAME(ta_ol_base));
5050	3708	save_item(NAME(ta_ol_limit));
5051	3709	save_item(NAME(ta_isp_base));
r243812	r243813
5057	3715	save_item(NAME(ta_yuv_tex_base));
5058	3716	save_item(NAME(ta_yuv_tex_ctrl));
5059	3717	save_item(NAME(ta_yuv_tex_cnt));
5060		save_item(NAME(fog_table));
5061		save_item(NAME(ta_ol_pointers_1));
5062		save_item(NAME(ta_ol_pointers_2));
5063		save_item(NAME(palette));
	3718	save_pointer(NAME(fog_table), 0x80);
	3719	save_pointer(NAME(palette), 0x400);
5064	3720
5065	3721	save_item(NAME(sb_pdstap));
5066	3722	save_item(NAME(sb_pdstar));
r243812	r243813
5071	3727	save_item(NAME(sb_pdst));
5072	3728	save_item(NAME(sb_pdapro));
5073	3729
5074		save_item(NAME(ta_fifo_buf));
5075		save_item(NAME(ta_fifo_pos));
5076		save_item(NAME(ta_packet_len));
5077		save_item(NAME(ta_packet_type));
5078		save_item(NAME(ta_cmd_type));
5079		save_item(NAME(ta_list_idx));
5080		save_item(NAME(ta_list_type));
5081
5082		save_item(NAME(ta_cmd_header));
5083		save_item(NAME(ta_cmd_instr));
5084		save_item(NAME(ta_cmd_tsp));
5085		save_item(NAME(ta_cmd_tex));
5086		save_item(NAME(ta_cmd_color_base));
5087		save_item(NAME(ta_cmd_color_offset));
5088		save_item(NAME(ta_cmd_color_sprite_base));
5089		save_item(NAME(ta_cmd_color_sprite_offset));
5090		save_item(NAME(ta_cmd_strip_length));
5091		save_item(NAME(ta_cmd_user_clip_mode));
5092
5093		save_item(NAME(ta_clip_min_x));
5094		save_item(NAME(ta_clip_max_x));
5095		save_item(NAME(ta_clip_min_y));
5096		save_item(NAME(ta_clip_max_y));
5097
5098		save_item(NAME(ta_vertex_current.header));
5099		save_item(NAME(ta_vertex_current.coords));
5100		save_item(NAME(ta_vertex_current.color_base));
5101		save_item(NAME(ta_vertex_current.color_offset));
5102		save_item(NAME(ta_vertex_current.uv));
5103		save_item(NAME(ta_vertex_current.uvc));
5104		for(int i=0; i<8; i++) {
5105		save_item(NAME(ta_vertex_strip[i].header), i);
5106		save_item(NAME(ta_vertex_strip[i].coords), i);
5107		save_item(NAME(ta_vertex_strip[i].color_base), i);
5108		save_item(NAME(ta_vertex_strip[i].color_offset), i);
5109		save_item(NAME(ta_vertex_strip[i].uv), i);
5110		save_item(NAME(ta_vertex_strip[i].uvc), i);
5111		}
5112		save_item(NAME(ta_vertex_count));
5113		save_item(NAME(ta_vertex_odd_tri));
5114		save_item(NAME(ta_vertex_shadow_first));
5115		save_item(NAME(ta_vertex_shadow_bbox.min_x));
5116		save_item(NAME(ta_vertex_shadow_bbox.min_y));
5117		save_item(NAME(ta_vertex_shadow_bbox.max_x));
5118		save_item(NAME(ta_vertex_shadow_bbox.max_y));
5119
5120		save_item(NAME(ta_olist_pos));
5121		save_item(NAME(ta_olist_pos_base));
5122		save_item(NAME(ta_olist_tile));
5123		save_item(NAME(ta_olist_block_size));
5124
5125	3730	save_item(NAME(m_pvr_dma.pvr_addr));
5126	3731	save_item(NAME(m_pvr_dma.sys_addr));
5127	3732	save_item(NAME(m_pvr_dma.size));
r243812	r243813
5130	3735	save_item(NAME(m_pvr_dma.flag));
5131	3736	save_item(NAME(m_pvr_dma.start));
5132	3737	save_item(NAME(debug_dip_status));
5133
	3738	save_pointer(NAME(tafifo_buff),32);
5134	3739	save_item(NAME(scanline));
5135	3740	save_item(NAME(next_y));
5136	3741	}
5137	3742
5138	3743	void powervr2_device::device_reset()
5139	3744	{
5140		memset(sdram, 0, 410241024*4);
5141
5142	3745	softreset = 0x00000007;
5143	3746	vo_control = 0x00000108;
5144	3747	vo_startx = 0x0000009d;
r243812	r243813
5149	3752	spg_hblank_int = 0x031d0000;
5150	3753	spg_vblank_int = 0x01500104;
5151	3754
5152		ta_fifo_pos = 0;
5153		memset(ta_fifo_buf, 0, sizeof(ta_fifo_buf));
5154		ta_packet_len = 0;
5155		ta_packet_type = VAR_UNKNOWN;
5156		ta_cmd_type = VAR_UNKNOWN;
5157		ta_list_idx = 0;
5158		ta_list_type = -1;
5159
5160		ta_cmd_header = 0;
5161		ta_cmd_instr = 0;
5162		memset(ta_cmd_tsp, 0, sizeof(ta_cmd_tsp));
5163		memset(ta_cmd_tex, 0, sizeof(ta_cmd_tex));
5164		memset(ta_cmd_color_base, 0, sizeof(ta_cmd_color_base));
5165		memset(ta_cmd_color_offset, 0, sizeof(ta_cmd_color_offset));
5166		ta_cmd_color_sprite_base = 0;
5167		ta_cmd_color_sprite_offset = 0;
5168		ta_cmd_strip_length = 0;
5169		ta_cmd_user_clip_mode = 0;
5170
5171		memset(&ta_vertex_current, 0, sizeof(ta_vertex_current));
5172		memset(ta_vertex_strip, 0, sizeof(ta_vertex_strip));
5173		ta_vertex_count = 0;
5174		ta_vertex_odd_tri = false;
5175		ta_vertex_shadow_first = true;
5176		memset(&ta_vertex_shadow_bbox, 0, sizeof(ta_vertex_shadow_bbox));
5177
5178		ta_olist_pos = 0;
5179		ta_olist_pos_base = 0;
5180		ta_olist_tile = 0;
5181		ta_olist_block_size = 0;
5182		ta_olist_line_size = 0;
5183
	3755	tafifo_pos=0;
	3756	tafifo_mask=7;
	3757	tafifo_vertexwords=8;
	3758	tafifo_listtype= -1;
5184	3759	start_render_received=0;
5185	3760	renderselect= -1;
5186	3761	grabsel=0;
r243812	r243813
5197	3772	endofrender_timer_video->adjust(attotime::never);
5198	3773	yuv_timer_end->adjust(attotime::never);
5199	3774
5200		dc_texture_ram = NULL;
5201		dc_framebuffer_ram = NULL;
	3775	dc_state *state = machine().driver_data<dc_state>();
	3776	dc_texture_ram = state->dc_texture_ram.target();
	3777	dc_framebuffer_ram = state->dc_framebuffer_ram.target();
5202	3778	}
5203	3779
5204	3780	/* called by TIMER_ADD_PERIODIC, in driver sections (controlled by SPG, that's a PVR sub-device) */

trunk/src/mame/video/powervr2.h
r243812	r243813
97	97	TEX_FILTER_TRILINEAR_B
98	98	};
99	99
100		int tafifo_vertexwords, tafifo_listtype;
	100	int tafifo_pos, tafifo_mask, tafifo_vertexwords, tafifo_listtype;
101	101	int start_render_received;
102	102	int renderselect;
103	103	int listtype_used;
r243812	r243813
130	130	emu_timer *endofrender_timer_tsp;
131	131	emu_timer *endofrender_timer_video;
132	132	emu_timer *yuv_timer_end;
	133	UINT32 tafifo_buff[32];
133	134	int scanline;
134	135	int next_y;
135	136
136	137	powervr2_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
137	138	template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
138	139
139		DECLARE_READ64_MEMBER( tex64_r );
140		DECLARE_WRITE64_MEMBER( tex64_w );
141		DECLARE_READ32_MEMBER( tex32_r );
142		DECLARE_WRITE32_MEMBER( tex32_w );
143
144	140	DECLARE_READ32_MEMBER( id_r );
145	141	DECLARE_READ32_MEMBER( revision_r );
146	142	DECLARE_READ32_MEMBER( softreset_r );
147	143	DECLARE_WRITE32_MEMBER( softreset_w );
148		DECLARE_READ32_MEMBER( startrender_r );
149	144	DECLARE_WRITE32_MEMBER( startrender_w );
150		DECLARE_READ32_MEMBER( test_select_r );
151		DECLARE_WRITE32_MEMBER( test_select_w );
152	145	DECLARE_READ32_MEMBER( param_base_r );
153	146	DECLARE_WRITE32_MEMBER( param_base_w );
154	147	DECLARE_READ32_MEMBER( region_base_r );
155	148	DECLARE_WRITE32_MEMBER( region_base_w );
156		DECLARE_READ32_MEMBER( span_sort_cfg_r );
157		DECLARE_WRITE32_MEMBER( span_sort_cfg_w );
158	149	DECLARE_READ32_MEMBER( vo_border_col_r );
159	150	DECLARE_WRITE32_MEMBER( vo_border_col_w );
160	151	DECLARE_READ32_MEMBER( fb_r_ctrl_r );
r243812	r243813
177	168	DECLARE_WRITE32_MEMBER( fb_x_clip_w );
178	169	DECLARE_READ32_MEMBER( fb_y_clip_r );
179	170	DECLARE_WRITE32_MEMBER( fb_y_clip_w );
180		DECLARE_READ32_MEMBER( fpu_shad_scale_r );
181		DECLARE_WRITE32_MEMBER( fpu_shad_scale_w );
182		DECLARE_READ32_MEMBER( fpu_cull_val_r );
183		DECLARE_WRITE32_MEMBER( fpu_cull_val_w );
184	171	DECLARE_READ32_MEMBER( fpu_param_cfg_r );
185	172	DECLARE_WRITE32_MEMBER( fpu_param_cfg_w );
186		DECLARE_READ32_MEMBER( half_offset_r );
187		DECLARE_WRITE32_MEMBER( half_offset_w );
188		DECLARE_READ32_MEMBER( fpu_perp_val_r );
189		DECLARE_WRITE32_MEMBER( fpu_perp_val_w );
190		DECLARE_READ32_MEMBER( isp_backgnd_d_r );
191		DECLARE_WRITE32_MEMBER( isp_backgnd_d_w );
192	173	DECLARE_READ32_MEMBER( isp_backgnd_t_r );
193	174	DECLARE_WRITE32_MEMBER( isp_backgnd_t_w );
194		DECLARE_READ32_MEMBER( isp_feed_cfg_r );
195		DECLARE_WRITE32_MEMBER( isp_feed_cfg_w );
196		DECLARE_READ32_MEMBER( sdram_refresh_r );
197		DECLARE_WRITE32_MEMBER( sdram_refresh_w );
198		DECLARE_READ32_MEMBER( sdram_arb_cfg_r );
199		DECLARE_WRITE32_MEMBER( sdram_arb_cfg_w );
200		DECLARE_READ32_MEMBER( sdram_cfg_r );
201		DECLARE_WRITE32_MEMBER( sdram_cfg_w );
202		DECLARE_READ32_MEMBER( fog_col_ram_r );
203		DECLARE_WRITE32_MEMBER( fog_col_ram_w );
204		DECLARE_READ32_MEMBER( fog_col_vert_r );
205		DECLARE_WRITE32_MEMBER( fog_col_vert_w );
206		DECLARE_READ32_MEMBER( fog_density_r );
207		DECLARE_WRITE32_MEMBER( fog_density_w );
208		DECLARE_READ32_MEMBER( fog_clamp_max_r );
209		DECLARE_WRITE32_MEMBER( fog_clamp_max_w );
210		DECLARE_READ32_MEMBER( fog_clamp_min_r );
211		DECLARE_WRITE32_MEMBER( fog_clamp_min_w );
212		DECLARE_READ32_MEMBER( spg_trigger_pos_r );
213		DECLARE_WRITE32_MEMBER( spg_trigger_pos_w );
214	175	DECLARE_READ32_MEMBER( spg_hblank_int_r );
215	176	DECLARE_WRITE32_MEMBER( spg_hblank_int_w );
216	177	DECLARE_READ32_MEMBER( spg_vblank_int_r );
r243812	r243813
233	194	DECLARE_WRITE32_MEMBER( vo_startx_w );
234	195	DECLARE_READ32_MEMBER( vo_starty_r );
235	196	DECLARE_WRITE32_MEMBER( vo_starty_w );
236		DECLARE_READ32_MEMBER( scaler_ctl_r );
237		DECLARE_WRITE32_MEMBER( scaler_ctl_w );
238	197	DECLARE_READ32_MEMBER( pal_ram_ctrl_r );
239	198	DECLARE_WRITE32_MEMBER( pal_ram_ctrl_w );
240	199	DECLARE_READ32_MEMBER( spg_status_r );
241		DECLARE_READ32_MEMBER( fb_burstctrl_r );
242		DECLARE_WRITE32_MEMBER( fb_burstctrl_w );
243		DECLARE_READ32_MEMBER( y_coeff_r );
244		DECLARE_WRITE32_MEMBER( y_coeff_w );
245		DECLARE_READ32_MEMBER( pt_alpha_ref_r );
246		DECLARE_WRITE32_MEMBER( pt_alpha_ref_w );
	200
247	201	DECLARE_READ32_MEMBER( ta_ol_base_r );
248	202	DECLARE_WRITE32_MEMBER( ta_ol_base_w );
249	203	DECLARE_READ32_MEMBER( ta_isp_base_r );
r243812	r243813
254	208	DECLARE_WRITE32_MEMBER( ta_isp_limit_w );
255	209	DECLARE_READ32_MEMBER( ta_next_opb_r );
256	210	DECLARE_READ32_MEMBER( ta_itp_current_r );
257		DECLARE_READ32_MEMBER( ta_glob_tile_clip_r );
258		DECLARE_WRITE32_MEMBER( ta_glob_tile_clip_w );
259	211	DECLARE_READ32_MEMBER( ta_alloc_ctrl_r );
260	212	DECLARE_WRITE32_MEMBER( ta_alloc_ctrl_w );
261	213	DECLARE_READ32_MEMBER( ta_list_init_r );
r243812	r243813
265	217	DECLARE_READ32_MEMBER( ta_yuv_tex_ctrl_r );
266	218	DECLARE_WRITE32_MEMBER( ta_yuv_tex_ctrl_w );
267	219	DECLARE_READ32_MEMBER( ta_yuv_tex_cnt_r );
	220	DECLARE_WRITE32_MEMBER( ta_yuv_tex_cnt_w );
268	221	DECLARE_READ32_MEMBER( ta_list_cont_r );
269	222	DECLARE_WRITE32_MEMBER( ta_list_cont_w );
270	223	DECLARE_READ32_MEMBER( ta_next_opb_init_r );
271	224	DECLARE_WRITE32_MEMBER( ta_next_opb_init_w );
	225
	226
272	227	DECLARE_READ32_MEMBER( fog_table_r );
273	228	DECLARE_WRITE32_MEMBER( fog_table_w );
274		DECLARE_READ32_MEMBER( ta_ol_pointers_1_r );
275		DECLARE_READ32_MEMBER( ta_ol_pointers_2_r );
276	229	DECLARE_READ32_MEMBER( palette_r );
277	230	DECLARE_WRITE32_MEMBER( palette_w );
278	231
r243812	r243813
329	282	virtual void device_reset();
330	283
331	284	private:
332		enum {
333		TRI_G_F32,
334		TRI_G_I_GLB,
335		TRI_G_I_GLB_DUAL,
336		TRI_G_I_PREV,
337		TRI_G_I_PREV_DUAL,
338		TRI_G_U8,
339		TRI_G_U8_DUAL,
340		TRI_T_F32,
341		TRI_T_F32_CUV,
342		TRI_T_I_GLB,
343		TRI_T_I_GLB_CUV,
344		TRI_T_I_GLB_CUV_DUAL,
345		TRI_T_I_GLB_DUAL,
346		TRI_T_I_GLB_OFF,
347		TRI_T_I_GLB_OFF_CUV,
348		TRI_T_I_PREV,
349		TRI_T_I_PREV_CUV,
350		TRI_T_I_PREV_CUV_DUAL,
351		TRI_T_I_PREV_DUAL,
352		TRI_T_U8,
353		TRI_T_U8_CUV,
354		TRI_T_U8_CUV_DUAL,
355		TRI_T_U8_DUAL,
356
357		SHADOW,
358		SPRITE,
359		LINE_SPRITE,
360
361		CMD_END_OF_LIST,
362		CMD_USER_TILE_CLIP,
363		CMD_OBJECT_LIST_SET,
364
365		VAR_UNKNOWN,
366		VAR_COUNT
367		};
368
369		enum {
370		L_OPAQUE,
371		L_OPAQUE_SHADOW,
372		L_TRANS,
373		L_TRANS_SHADOW,
374		L_TRANS_PUNCHTHROUGH
375		};
376
377		enum {
378		H_TYPE = 0xe0000000,
379		H_EOSTRIP = 0x10000000,
380		H_LTYPE = 0x07000000,
381		H_GROUP = 0x00800000,
382		H_SLEN = 0x000c0000,
383		H_UCLIP = 0x00030000,
384		H_DUAL = 0x00000040,
385		H_COLMODE = 0x00000030,
386		H_TEX = 0x00000008,
387		H_OFF = 0x00000004,
388		H_GOURAUD = 0x00000002,
389		H_COMPACT_UV = 0x00000001,
390
391		HI_DEPTH = 0xe0000000,
392		HI_CULL = 0x18000000,
393		HI_ZWRITE = 0x04000000,
394		HI_TEX = 0x02000000,
395		HI_OFF = 0x01000000,
396		HI_GOURAUD = 0x00800000,
397		HI_COMPACT_UV = 0x00400000,
398		HI_CACHE = 0x00200000,
399		HI_DCOEFF = 0x00100000,
400		};
401
402		enum {
403		OL_POINTERS_COUNT = 40*15,
404		TA_SORTER_SIZE = 16
405		};
406
407		static const char *ta_packet_type_name[VAR_COUNT];
408		static const int ta_packet_len_table[VAR_COUNT*2];
409
410	285	devcb_write8 irq_cb;
411	286
412		// SDRAM, 4 pairs of 1M*16 sdrams, total of 16M
413		UINT32 *sdram;
414
415	287	// Core registers
416	288	UINT32 softreset;
417		UINT32 test_select;
418	289	UINT32 param_base, region_base;
419		UINT32 span_sort_cfg;
420	290	UINT32 vo_border_col;
421	291	UINT32 fb_r_ctrl, fb_w_ctrl, fb_w_linestride, fb_r_sof1, fb_r_sof2, fb_r_size, fb_w_sof1, fb_w_sof2, fb_x_clip, fb_y_clip;
422		UINT32 fpu_shad_scale, fpu_cull_val, fpu_param_cfg, half_offset, fpu_perp_val;
423		UINT32 isp_backgnd_d, isp_backgnd_t, isp_feed_cfg;
424		UINT32 sdram_refresh, sdram_arb_cfg, sdram_cfg;
425		UINT32 fog_col_ram, fog_col_vert, fog_density, fog_clamp_max, fog_clamp_min;
426		UINT32 spg_trigger_pos, spg_hblank_int, spg_vblank_int, spg_control, spg_hblank, spg_load, spg_vblank, spg_width;
427		UINT32 text_control;
	292	UINT32 fpu_param_cfg;
	293	UINT32 isp_backgnd_t;
	294	UINT32 spg_hblank_int, spg_vblank_int, spg_control, spg_hblank, spg_load, spg_vblank, spg_width;
428	295	UINT32 vo_control, vo_startx, vo_starty;
429		UINT32 scaler_ctl, pal_ram_ctrl, fb_burstctrl, y_coeff, pt_alpha_ref;
	296	UINT32 text_control;
	297	UINT32 pal_ram_ctrl;
430	298
431	299	// TA registers
432	300	UINT32 ta_ol_base, ta_ol_limit, ta_isp_base, ta_isp_limit;
433		UINT32 ta_next_opb, ta_itp_current, ta_~~glob_tile_clip, ta_~~alloc_ctrl, ta_next_opb_init;
	301	UINT32 ta_next_opb, ta_itp_current, ta_alloc_ctrl, ta_next_opb_init;
434	302	UINT32 ta_yuv_tex_base, ta_yuv_tex_ctrl, ta_yuv_tex_cnt;
435	303	UINT32 ta_yuv_index;
436	304	int ta_yuv_x,ta_yuv_y;
437	305	int ta_yuv_x_size,ta_yuv_y_size;
438	306	UINT8 yuv_fifo[384];
439		UINT32 ta_ol_pointers_1[OL_POINTERS_COUNT];
440		UINT32 ta_ol_pointers_2[OL_POINTERS_COUNT];
441	307
442	308	// Other registers
443	309	UINT32 fog_table[0x80];
r243812	r243813
446	312	// PD DMA registers
447	313	UINT32 sb_pdstap, sb_pdstar, sb_pdlen, sb_pddir, sb_pdtsel, sb_pden, sb_pdst, sb_pdapro;
448	314
449		// TA input fifo
450		int ta_fifo_pos;
451		UINT32 ta_fifo_buf[16];
452
453		// TA lists and packetization
454		int ta_packet_len, ta_packet_type, ta_cmd_type, ta_list_idx, ta_list_type;
455
456		// TA command parsing
457		UINT32 ta_cmd_header, ta_cmd_instr, ta_cmd_tsp[2], ta_cmd_tex[2];
458		float ta_cmd_color_base[2][4], ta_cmd_color_offset[2][4];
459		UINT32 ta_cmd_color_sprite_base, ta_cmd_color_sprite_offset;
460		int ta_cmd_strip_length, ta_cmd_user_clip_mode;
461
462		// TA user clipping
463		UINT32 ta_clip_min_x, ta_clip_max_x, ta_clip_min_y, ta_clip_max_y;
464
465		// TA vertices
466		struct ta_vertex {
467		UINT32 header;
468		UINT32 coords[3];
469		UINT32 color_base[2];
470		UINT32 color_offset[2];
471		UINT32 uv[2][2];
472		UINT32 uvc[2];
473
474		int tx() const { float p = u2f(coords[0]); if(p<0) return -1; return int(p)>>5; }
475		int ty() const { float p = u2f(coords[1]); if(p<0) return -1; return int(p)>>5; }
476		};
477
478		struct ta_bbox {
479		int min_x, max_x, min_y, max_y;
480		};
481
482		ta_vertex ta_vertex_current, ta_vertex_strip[8];
483		int ta_vertex_count;
484		bool ta_vertex_odd_tri;
485		bool ta_vertex_shadow_first;
486		ta_bbox ta_vertex_shadow_bbox;
487
488		// TA output
489		UINT32 ta_olist_pos, ta_olist_pos_base, ta_olist_tile, ta_olist_block_size, ta_olist_line_size;
490
491	315	static UINT32 (*const blend_functions[64])(UINT32 s, UINT32 d);
492	316
493		inline float clampf(UINT32 v) {
494		float v1 = u2f(v);
495		return v1 < 0 ? 0 : v1 > 1 ? 1 : v1;
496		}
497
498		inline float clampf(float v) {
499		return v < 0 ? 0 : v > 1 ? 1 : v;
500		}
501
502		inline void ta_load_color_f32(float dest, const UINT32 src)
503		{
504		for(int i=0; i<4; i++)
505		dest[i] = clampf(src[i]);
506		}
507
508		inline UINT32 ta_color_f32_to_u8(const UINT32 *src)
509		{
510		UINT32 res = 0;
511		for(int i=0; i<4; i++)
512		res \|= UINT8(255clampf(src[i])) << (24-8i);
513		return res;
514		}
515
516		inline UINT32 ta_intensity(const float *src, UINT32 i)
517		{
518		UINT32 ii = UINT32(i*256) & 0x1ff;
519		UINT32 res = UINT8(255*clampf(src[0])) << 24;
520
521		for(int i=1; i<4; i++)
522		res \|= UINT8((iiUINT8(255clampf(src[i]))) >> 8) << (24-8*i);
523		return res;
524		}
525
526	317	static inline INT32 clamp(INT32 in, INT32 min, INT32 max);
527	318	static inline UINT32 bilinear_filter(UINT32 c0, UINT32 c1, UINT32 c2, UINT32 c3, float u, float v);
528	319	static inline UINT32 bla(UINT32 c, UINT32 a);
r243812	r243813
686	477	void fb_convert_8888argb_to_888rgb24(address_space &space, int x, int y);
687	478	void fb_convert_8888argb_to_888rgb32(address_space &space, int x, int y);
688	479
689		void mem_write32(UINT32 adr, UINT32 val);
690
691		void ta_object_list_extend();
692		void ta_add_object(UINT32 adr, bool tail);
693		void ta_add_strip(UINT32 adr, UINT32 psize);
694		bool ta_bbox_vertex(ta_bbox &bb, const ta_vertex *vtx, int count) const;
695		void ta_bbox_merge(ta_bbox &bb, const ta_bbox &src) const;
696		UINT32 ta_strip_write(bool single_tile, UINT32 &psize);
697		void ta_vertex_write_sprite();
698		void ta_vertex_write_shadow();
699		void ta_vertex_write();
700		void ta_vertex_push();
701		void ta_handle_command_draw();
702		void ta_handle_vertex();
703		void ta_handle_command_end_of_list();
704		void ta_handle_command_user_tile_clip();
705		void ta_handle_command_object_list_set();
706
707		int ta_get_packet_type();
708		void ta_next_list();
709		void ta_list_start();
710		void ta_process_lists(UINT32 adr, bool cont);
711	480	};
712	481
713	482	extern const device_type POWERVR2;

trunk/src/mess/drivers/dccons.c
r243812	r243813
391	391	// AM_RANGE(0x03000000, 0x03ffffff) G2 Ext Device #2
392	392
393	393	/* Area 1 */
394		AM_RANGE(0x04000000, 0x04ffffff) AM_DEVREADWRITE ("powervr2", powervr2_device, tex64_r, tex64_w)
395		AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE32("powervr2", powervr2_device, tex32_r, tex32_w, U64(0xffffffffffffffff))
	394	AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
	395	AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
396	396
397	397	/* Area 3 */
398	398	AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE("dc_ram")

trunk/src/mess/drivers/lg.c
r243812	r243813
1		#include "emu.h"
2		#include "debugger.h"
3		#include "cpu/mcs51/mcs51.h"
4
5		class lg_state : public driver_device {
6		public:
7		lg_state(const machine_config &mconfig, device_type type, const char *tag)
8		: driver_device(mconfig, type, tag),
9		maincpu(*this, "maincpu")
10		{ }
11
12		required_device<i80c52_device> maincpu;
13		};
14
15		static INPUT_PORTS_START( lg )
16		INPUT_PORTS_END
17
18		static ADDRESS_MAP_START( lg_map, AS_PROGRAM, 8, lg_state )
19		AM_RANGE(0x0000, 0x7fff) AM_ROM AM_REGION("maincpu", 0)
20		ADDRESS_MAP_END
21
22		static MACHINE_CONFIG_START( lg, lg_state )
23		MCFG_CPU_ADD( "maincpu", I80C52, XTAL_16MHz )
24		MCFG_CPU_PROGRAM_MAP( lg_map )
25		MACHINE_CONFIG_END
26
27		ROM_START( lg )
28		ROM_REGION( 0x100000, "maincpu", 0 )
29		ROM_SYSTEM_BIOS( 0, "bios0", "1.00" )
30		ROMX_LOAD( "firm-1.00.bin", 0x000000, 0x100000, CRC(c7f24f3b) SHA1(c2ce96c02ab419fb7e0b38703cdaeeccb2b7f34b), ROM_BIOS(1) )
31		ROM_SYSTEM_BIOS( 1, "bios1", "1.01" )
32		ROMX_LOAD( "firm-1.01.bin", 0x000000, 0x100000, CRC(28820e0c) SHA1(c5f2c1e14e6cff2e57c5196cabcebfaaff7284ce), ROM_BIOS(2) )
33		ROM_END
34
35		SYST( 2011, lg, 0, 0, lg, lg, driver_device, 0, "LG", "GP40NW10 dvd writer", GAME_NOT_WORKING\|GAME_NO_SOUND_HW )

trunk/src/mess/drivers/mt735.c
r243812	r243813
1		/*
2		Brother MT735 thermal printer
3		*/
4
5
6		#include "emu.h"
7		#include "cpu/m68000/m68000.h"
8
9		class mt735_state : public driver_device
10		{
11		public:
12		mt735_state(const machine_config &mconfig, device_type type, const char *tag);
13
14		required_device<m68000_device> m_cpu;
15
16		DECLARE_READ8_MEMBER(p4_r);
17		DECLARE_READ8_MEMBER(p5_r);
18
19		virtual void machine_start();
20		virtual void machine_reset();
21		};
22
23		mt735_state::mt735_state(const machine_config &mconfig, device_type type, const char *tag) :
24		driver_device(mconfig, type, tag),
25		m_cpu(*this, "maincpu")
26		{
27		}
28
29		void mt735_state::machine_start()
30		{
31		}
32
33		void mt735_state::machine_reset()
34		{
35		}
36
37		READ8_MEMBER(mt735_state::p4_r)
38		{
39		logerror("p4_r (%06x)\n", space.device().safe_pc());
40		return 0xe0;
41		}
42
43		READ8_MEMBER(mt735_state::p5_r)
44		{
45		logerror("p5_r (%06x)\n", space.device().safe_pc());
46		return 0x00;
47		}
48
49		static ADDRESS_MAP_START( mt735_map, AS_PROGRAM, 16, mt735_state )
50		AM_RANGE(0x000000, 0x03ffff) AM_ROM AM_REGION("maincpu", 0)
51		AM_RANGE(0x278000, 0x287fff) AM_RAM
52		AM_RANGE(0x400000, 0x4fffff) AM_RAM
53		AM_RANGE(0xff8004, 0xff8005) AM_READ8(p4_r, 0xff00)
54		AM_RANGE(0xff8004, 0xff8005) AM_READ8(p5_r, 0x00ff)
55		ADDRESS_MAP_END
56
57		static INPUT_PORTS_START( mt735 )
58		INPUT_PORTS_END
59
60		static MACHINE_CONFIG_START( mt735, mt735_state )
61		MCFG_CPU_ADD("maincpu", M68000, XTAL_48MHz/6)
62		MCFG_CPU_PROGRAM_MAP(mt735_map)
63		MACHINE_CONFIG_END
64
65		ROM_START( mt735 )
66		ROM_REGION( 0x40000, "maincpu", 0 )
67		ROM_LOAD16_BYTE( "spg_m_e_ic103.bin", 0, 0x20000, CRC(1ab58bc9) SHA1(c10d50f38819c037d28435b77e09f2b6923e8369) )
68		ROM_LOAD16_BYTE( "spg_m_o_ic102.bin", 1, 0x20000, CRC(84d8446b) SHA1(b1cedd8b09556eb8118f79b012aeec5b61e3ff32) )
69		ROM_END
70
71		COMP( ????, mt735, 0, 0, mt735, mt735, driver_device, 0, "Brother", "MT735", GAME_NOT_WORKING\|GAME_NO_SOUND )

trunk/src/mess/drivers/rmt32.c
r243812	r243813
84	84	*3 - R15229863 HG61H20R36F (QFP100, stamped 'BOSS')
85	85	PCM54HP- Burr-Brown PCM54HP 16-Bit Monolithic Digital-to-Analog Converter (DIP28)
86	86	& Various logic ICs - 4051, 74HC27, 74HC00, 74HC02, 74HC04, 74LS05
87
	87
88	88	ROMs - Filename Device Type
89	89	------------------------------------------------------------------------
90	90	ROM.IC26.106 Mitsubishi M5M27C256 (labeled 1.0.6) read as 27C256
r243812	r243813
92	92	ROM.IC13.200 Mitsubishi M5M27C128 (labeled 2.0.0) read as 27C128
93	93	ROM.IC21 Toshiba TC532000P (-7471) read as TC572000
94	94	ROM.IC22 Toshiba TC532000P (-7472) read as TC572000
95
96	95
97	96
	97
98	98	Newer version
99	99
100	100	PCB Layout
r243812	r243813
149	149	*3 - R15229863 HG61H20R36F (QFP100, stamped 'BOSS')
150	150	PCM54HP- Burr-Brown PCM54HP 16-Bit Monolithic Digital-to-Analog Converter (DIP28)
151	151	& Various logic ICs - 4051, 74HC27, 74HC00, 74HC02, 74HC04, 74LS05
152
	152
153	153	ROMs - Filename Device Type
154	154	----------------------------------------------------
155	155	ROM.IC26 Hitachi HN623258PH26 read as 27C256
r243812	r243813
159	159	*/
160	160
161	161	#include "emu.h"
162		#include "sound/la32.h"
163	162	#include "machine/ram.h"
164	163	#include "video/sed1200.h"
165	164	#include "cpu/mcs96/i8x9x.h"
r243812	r243813
181	180	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_OTHER) PORT_NAME("Master volume") PORT_CODE(KEYCODE_M)
182	181	PORT_BIT(0xe0, IP_ACTIVE_LOW, IPT_UNUSED)
183	182
184		PORT_START("Z")
185		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test Z") PORT_CODE(KEYCODE_Z)
186		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test X") PORT_CODE(KEYCODE_X)
187
188	183	PORT_START("A7")
189	184	PORT_BIT(0x03ff, 0x0000, IPT_DIAL) PORT_NAME("Knob") PORT_SENSITIVITY(50) PORT_KEYDELTA(8) PORT_CODE_DEC(KEYCODE_DOWN) PORT_CODE_INC(KEYCODE_UP)
190	185	INPUT_PORTS_END
r243812	r243813
196	191	required_device<ram_device> ram;
197	192	optional_device<sed1200d0a_device> lcd;
198	193	required_device<timer_device> midi_timer;
199		required_device<la32_device> la32;
200	194
201	195	mt32_state(const machine_config &mconfig, device_type type, const char *tag);
202	196
r243812	r243813
214	208	DECLARE_WRITE8_MEMBER(lcd_ctrl_w);
215	209	DECLARE_WRITE8_MEMBER(lcd_data_w);
216	210	DECLARE_READ16_MEMBER(port0_r);
217		DECLARE_READ16_MEMBER(port2_r);
218	211
219	212	TIMER_DEVICE_CALLBACK_MEMBER(midi_timer_cb);
	213	TIMER_DEVICE_CALLBACK_MEMBER(samples_timer_cb);
220	214
221		DECLARE_WRITE_LINE_MEMBER(la32_irq_w);
222		DECLARE_WRITE_LINE_MEMBER(sample_line_w);
223
224	215	private:
225	216	UINT8 lcd_data_buffer[256];
226	217	int lcd_data_buffer_pos;
227	218	UINT8 midi;
228	219	int midi_pos;
229		UINT8 port0, port2;
	220	UINT8 port0;
	221	required_device<cpu_device> m_maincpu;
230	222	};
231	223
232	224	mt32_state::mt32_state(const machine_config &mconfig, device_type type, const char *tag) :
r243812	r243813
234	226	cpu(*this, "maincpu"),
235	227	ram(*this, "ram"),
236	228	lcd(*this, "lcd"),
237		midi_timer(*this, "midi_timer"),
238		la32(*this, "la32")
239		{
	229	midi_timer(*this, "midi_timer")
	230	,
	231	m_maincpu(*this, "maincpu") {
240	232	}
241	233
242	234
r243812	r243813
250	242	for(int x=0; x<5; x++)
251	243	bitmap.pix16(y == 7 ? 8 : y, c*6+x) = v & (0x10 >> x) ? 1 : 0;
252	244	}
253
254		UINT8 cp = ioport("Z")->read();
255		if(cp & 1) {
256		midi_timer->adjust(attotime::from_hz(1));
257		midi_pos = 0;
258		}
259	245	return 0;
260	246	}
261	247
r243812	r243813
270	256
271	257	void mt32_state::machine_reset()
272	258	{
273		// midi_timer->adjust(attotime::from_hz(1));
	259	midi_timer->adjust(attotime::from_hz(1));
274	260	midi_pos = 0;
275	261	port0 = 0;
276		port2 = 0;
277	262	}
278	263
279	264	WRITE8_MEMBER(mt32_state::lcd_ctrl_w)
r243812	r243813
315	300	midi_timer->adjust(attotime::from_hz(1250));
316	301	}
317	302
318		WRITE_LINE_MEMBER(mt32_state::sample_line_w)
319		{
320		port0 = (port0 & ~0x10) \| (state ? 0x10 : 0);
321		}
322
323		WRITE_LINE_MEMBER(mt32_state::la32_irq_w)
324		{
325		logerror("la32_irq_w(%d)\n", state);
326		port2 = (port2 & ~4) \| (state ? 4 : 0);
327		cpu->set_input_line(mcs96_device::EXINT_LINE, state);
328		}
329
330	303	READ16_MEMBER(mt32_state::port0_r)
331	304	{
332	305	return port0;
333	306	}
334	307
335		REA~~D16~~_MEMBER(mt32_state::p~~ort2~~_r)
	308	TIMER_DEVICE_CALLBACK_MEMBER(mt32_state::samples_timer_cb)
336	309	{
337		~~return~~ port2;
	310	port0 ^= 0x10;
338	311	}
339	312
340	313	WRITE8_MEMBER(mt32_state::so_w)
r243812	r243813
345	318	// bit 5 = boss x1
346	319	// bit 6 = lcd cs, also handled internally by the gate array
347	320	// bit 7 = lcd clk, also handled internally by the gate array
348		// logerror("so: x1=%d bank=%d led=%d\n", (data >> 5) & 1, (data >> 1) & 3, data & 1);
	321	// logerror("so: x1=%d bank=%d led=%d\n", (data >> 5) & 1, (data >> 1) & 3, data & 1);
349	322	}
350	323
351	324	PALETTE_INIT_MEMBER(mt32_state, mt32)
r243812	r243813
361	334	AM_RANGE(0x021c, 0x021c) AM_READ_PORT("SC1")
362	335	AM_RANGE(0x0300, 0x0300) AM_WRITE(lcd_data_w)
363	336	AM_RANGE(0x0380, 0x0380) AM_READWRITE(lcd_ctrl_r, lcd_ctrl_w)
364		AM_RANGE(0x0400, 0x0fff) AM_DEVREADWRITE("la32", la32_device, read, write)
365	337	AM_RANGE(0x1000, 0x7fff) AM_ROM AM_REGION("maincpu", 0x1000)
366	338	AM_RANGE(0x8000, 0xbfff) AM_RAMBANK("bank")
367	339	AM_RANGE(0xc000, 0xffff) AM_RAMBANK("fixed")
r243812	r243813
371	343	AM_RANGE(i8x9x_device::A7, i8x9x_device::A7) AM_READ_PORT("A7")
372	344	AM_RANGE(i8x9x_device::SERIAL, i8x9x_device::SERIAL) AM_WRITE(midi_w)
373	345	AM_RANGE(i8x9x_device::P0, i8x9x_device::P0) AM_READ(port0_r)
374		AM_RANGE(i8x9x_device::P2, i8x9x_device::P2) AM_READ(port2_r)
375	346	ADDRESS_MAP_END
376	347
377	348	static MACHINE_CONFIG_START( mt32, mt32_state )
r243812	r243813
385	356	MCFG_SCREEN_ADD( "screen", LCD )
386	357	MCFG_SCREEN_REFRESH_RATE(50)
387	358	MCFG_SCREEN_UPDATE_DRIVER(mt32_state, screen_update)
388		// MCFG_SCREEN_SIZE(20*6-1, 9)
	359	// MCFG_SCREEN_SIZE(20*6-1, 9)
389	360	MCFG_SCREEN_SIZE(206-1, (206-1)*3/4)
390	361	MCFG_SCREEN_VISIBLE_AREA(0, 206-2, 0, (206-1)*3/4-1)
391	362	MCFG_SCREEN_PALETTE("palette")
r243812	r243813
397	368
398	369	MCFG_TIMER_DRIVER_ADD( "midi_timer", mt32_state, midi_timer_cb )
399	370
400		MCFG_LA32_ADD( "la32" )
401		MCFG_LA32_IRQ_CALLBACK( WRITELINE(mt32_state, la32_irq_w) )
402		MCFG_LA32_SAMPLE_CALLBACK( WRITELINE(mt32_state, sample_line_w) )
	371	MCFG_TIMER_DRIVER_ADD_PERIODIC( "samples_timer", mt32_state, samples_timer_cb, attotime::from_hz(32000*2) )
403	372	MACHINE_CONFIG_END
404	373
405	374	ROM_START( mt32 )

trunk/src/mess/drivers/wicat.c
r243812	r243813
154	154	ADDRESS_MAP_UNMAP_LOW
155	155	ADDRESS_MAP_GLOBAL_MASK(0xffffff)
156	156	AM_RANGE(0x000000, 0x001fff) AM_ROM AM_REGION("c2", 0x0000)
157		AM_RANGE(0x010000, 0x013fff) AM_ROM AM_REGION("c1", 0x0000)
158	157	AM_RANGE(0x020000, 0x1fffff) AM_RAM
159	158	AM_RANGE(0x200000, 0x2fffff) AM_RAM
160	159	AM_RANGE(0x300000, 0xdfffff) AM_READWRITE(invalid_r,invalid_w)

trunk/src/mess/drivers/ymmu100.c
r243812	r243813
276	276	{
277	277	int chan = (offset >> 6) & 0x3f;
278	278	int slot = offset & 0x3f;
279		if(slot == 0x38 && (data == 0xffff \|\| data == 0xff00 \|\| data == 0x00ff))
280		return;
281		if(slot == 0x39 && (data == 0x08ff \|\| data == 0x20ff \|\| data == 0xffff))
282		return;
283		if(slot == 0x3a && data == 0xffff)
284		return;
285	279	logerror("snd_w %02x.%02x, %04x (%06x)\n", chan, slot, data, m_maincpu->pc());
286	280	}
287	281
288	282	READ16_MEMBER(mu100_state::adc0_r)
289	283	{
290		// logerror("adc0_r\n");
	284	logerror("adc0_r\n");
291	285	return 0;
292	286	}
293	287
294	288	READ16_MEMBER(mu100_state::adc2_r)
295	289	{
296		// logerror("adc2_r\n");
	290	logerror("adc2_r\n");
297	291	return 0;
298	292	}
299	293
300	294	// Put the host switch to pure midi
301	295	READ16_MEMBER(mu100_state::adc4_r)
302	296	{
303		return 0~~x3ff~~;
	297	return 0;
304	298	}
305	299
306	300	// Battery level
307	301	READ16_MEMBER(mu100_state::adc6_r)
308	302	{
309		// logerror("adc6_r\n");
	303	logerror("adc6_r\n");
310	304	return 0x3ff;
311	305	}
312	306
r243812	r243813
385	379
386	380	READ16_MEMBER(mu100_state::p6_r)
387	381	{
388		// logerror("plug in detect read\n");
	382	logerror("plug in detect read\n");
389	383	return 0x00;
390	384	}
391	385
r243812	r243813
449	443	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
450	444
451	445	MCFG_MIDI_PORT_ADD("mdin", midiin_slot, "midiin")
452		MCFG_MIDI_RX_HANDLER(DEVWRITELINE("maincpu:sci1", h8_sci_device, rx_w))
	446	MCFG_MIDI_RX_HANDLER(DEVWRITELINE("maincpu:sci0", h8_sci_device, rx_w))
453	447
454	448	MCFG_MIDI_PORT_ADD("mdout", midiout_slot, "midiout")
455	449	MCFG_DEVICE_MODIFY("maincpu:sci0")

trunk/src/mess/machine/nextmo.c
r243812	r243813
182	182	logerror("nextmo: r10_w %d, %02x (%08x)\n", offset, data, space.device().safe_pc());
183	183	}
184	184
185		/* Reed-Solomon(36,32) in GF(2*8), generator polynomial (x-1)(x-2)(x-4)(x-8)
186		GF's polynom is the usual 11d
187		*/
188
189		/* Partial remainders, e.g. t_rem[i] = (ix^4) % ((x-1)(x-2)(x-4)(x-8)) */
190		const UINT32 nextmo_device::t_rem[256] = {
191		0x00000000, 0x0f367840, 0x1e6cf080, 0x115a88c0, 0x3cd8fd1d, 0x33ee855d, 0x22b40d9d, 0x2d8275dd,
192		0x78ade73a, 0x779b9f7a, 0x66c117ba, 0x69f76ffa, 0x44751a27, 0x4b436267, 0x5a19eaa7, 0x552f92e7,
193		0xf047d374, 0xff71ab34, 0xee2b23f4, 0xe11d5bb4, 0xcc9f2e69, 0xc3a95629, 0xd2f3dee9, 0xddc5a6a9,
194		0x88ea344e, 0x87dc4c0e, 0x9686c4ce, 0x99b0bc8e, 0xb432c953, 0xbb04b113, 0xaa5e39d3, 0xa5684193,
195		0xfd8ebbe8, 0xf2b8c3a8, 0xe3e24b68, 0xecd43328, 0xc15646f5, 0xce603eb5, 0xdf3ab675, 0xd00cce35,
196		0x85235cd2, 0x8a152492, 0x9b4fac52, 0x9479d412, 0xb9fba1cf, 0xb6cdd98f, 0xa797514f, 0xa8a1290f,
197		0x0dc9689c, 0x02ff10dc, 0x13a5981c, 0x1c93e05c, 0x31119581, 0x3e27edc1, 0x2f7d6501, 0x204b1d41,
198		0x75648fa6, 0x7a52f7e6, 0x6b087f26, 0x643e0766, 0x49bc72bb, 0x468a0afb, 0x57d0823b, 0x58e6fa7b,
199		0xe7016bcd, 0xe837138d, 0xf96d9b4d, 0xf65be30d, 0xdbd996d0, 0xd4efee90, 0xc5b56650, 0xca831e10,
200		0x9fac8cf7, 0x909af4b7, 0x81c07c77, 0x8ef60437, 0xa37471ea, 0xac4209aa, 0xbd18816a, 0xb22ef92a,
201		0x1746b8b9, 0x1870c0f9, 0x092a4839, 0x061c3079, 0x2b9e45a4, 0x24a83de4, 0x35f2b524, 0x3ac4cd64,
202		0x6feb5f83, 0x60dd27c3, 0x7187af03, 0x7eb1d743, 0x5333a29e, 0x5c05dade, 0x4d5f521e, 0x42692a5e,
203		0x1a8fd025, 0x15b9a865, 0x04e320a5, 0x0bd558e5, 0x26572d38, 0x29615578, 0x383bddb8, 0x370da5f8,
204		0x6222371f, 0x6d144f5f, 0x7c4ec79f, 0x7378bfdf, 0x5efaca02, 0x51ccb242, 0x40963a82, 0x4fa042c2,
205		0xeac80351, 0xe5fe7b11, 0xf4a4f3d1, 0xfb928b91, 0xd610fe4c, 0xd926860c, 0xc87c0ecc, 0xc74a768c,
206		0x9265e46b, 0x9d539c2b, 0x8c0914eb, 0x833f6cab, 0xaebd1976, 0xa18b6136, 0xb0d1e9f6, 0xbfe791b6,
207		0xd302d687, 0xdc34aec7, 0xcd6e2607, 0xc2585e47, 0xefda2b9a, 0xe0ec53da, 0xf1b6db1a, 0xfe80a35a,
208		0xabaf31bd, 0xa49949fd, 0xb5c3c13d, 0xbaf5b97d, 0x9777cca0, 0x9841b4e0, 0x891b3c20, 0x862d4460,
209		0x234505f3, 0x2c737db3, 0x3d29f573, 0x321f8d33, 0x1f9df8ee, 0x10ab80ae, 0x01f1086e, 0x0ec7702e,
210		0x5be8e2c9, 0x54de9a89, 0x45841249, 0x4ab26a09, 0x67301fd4, 0x68066794, 0x795cef54, 0x766a9714,
211		0x2e8c6d6f, 0x21ba152f, 0x30e09def, 0x3fd6e5af, 0x12549072, 0x1d62e832, 0x0c3860f2, 0x030e18b2,
212		0x56218a55, 0x5917f215, 0x484d7ad5, 0x477b0295, 0x6af97748, 0x65cf0f08, 0x749587c8, 0x7ba3ff88,
213		0xdecbbe1b, 0xd1fdc65b, 0xc0a74e9b, 0xcf9136db, 0xe2134306, 0xed253b46, 0xfc7fb386, 0xf349cbc6,
214		0xa6665921, 0xa9502161, 0xb80aa9a1, 0xb73cd1e1, 0x9abea43c, 0x9588dc7c, 0x84d254bc, 0x8be42cfc,
215		0x3403bd4a, 0x3b35c50a, 0x2a6f4dca, 0x2559358a, 0x08db4057, 0x07ed3817, 0x16b7b0d7, 0x1981c897,
216		0x4cae5a70, 0x43982230, 0x52c2aaf0, 0x5df4d2b0, 0x7076a76d, 0x7f40df2d, 0x6e1a57ed, 0x612c2fad,
217		0xc4446e3e, 0xcb72167e, 0xda289ebe, 0xd51ee6fe, 0xf89c9323, 0xf7aaeb63, 0xe6f063a3, 0xe9c61be3,
218		0xbce98904, 0xb3dff144, 0xa2857984, 0xadb301c4, 0x80317419, 0x8f070c59, 0x9e5d8499, 0x916bfcd9,
219		0xc98d06a2, 0xc6bb7ee2, 0xd7e1f622, 0xd8d78e62, 0xf555fbbf, 0xfa6383ff, 0xeb390b3f, 0xe40f737f,
220		0xb120e198, 0xbe1699d8, 0xaf4c1118, 0xa07a6958, 0x8df81c85, 0x82ce64c5, 0x9394ec05, 0x9ca29445,
221		0x39cad5d6, 0x36fcad96, 0x27a62556, 0x28905d16, 0x051228cb, 0x0a24508b, 0x1b7ed84b, 0x1448a00b,
222		0x416732ec, 0x4e514aac, 0x5f0bc26c, 0x503dba2c, 0x7dbfcff1, 0x7289b7b1, 0x63d33f71, 0x6ce54731,
223		};
224
225		const UINT8 nextmo_device::t_exp[768] = {
226		0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26,
227		0x4c, 0x98, 0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x03, 0x06, 0x0c, 0x18, 0x30, 0x60, 0xc0,
228		0x9d, 0x27, 0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23,
229		0x46, 0x8c, 0x05, 0x0a, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1,
230		0x5f, 0xbe, 0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0x0f, 0x1e, 0x3c, 0x78, 0xf0,
231		0xfd, 0xe7, 0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2,
232		0xd9, 0xaf, 0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0x0d, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce,
233		0x81, 0x1f, 0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc,
234		0x85, 0x17, 0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54,
235		0xa8, 0x4d, 0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73,
236		0xe6, 0xd1, 0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff,
237		0xe3, 0xdb, 0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41,
238		0x82, 0x19, 0x32, 0x64, 0xc8, 0x8d, 0x07, 0x0e, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6,
239		0x51, 0xa2, 0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x09,
240		0x12, 0x24, 0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0x0b, 0x16,
241		0x2c, 0x58, 0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x01,
242		0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26, 0x4c,
243		0x98, 0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x03, 0x06, 0x0c, 0x18, 0x30, 0x60, 0xc0, 0x9d,
244		0x27, 0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23, 0x46,
245		0x8c, 0x05, 0x0a, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1, 0x5f,
246		0xbe, 0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0x0f, 0x1e, 0x3c, 0x78, 0xf0, 0xfd,
247		0xe7, 0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2, 0xd9,
248		0xaf, 0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0x0d, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce, 0x81,
249		0x1f, 0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc, 0x85,
250		0x17, 0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54, 0xa8,
251		0x4d, 0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73, 0xe6,
252		0xd1, 0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff, 0xe3,
253		0xdb, 0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41, 0x82,
254		0x19, 0x32, 0x64, 0xc8, 0x8d, 0x07, 0x0e, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6, 0x51,
255		0xa2, 0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x09, 0x12,
256		0x24, 0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0x0b, 0x16, 0x2c,
257		0x58, 0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x01, 0x02,
258		0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26, 0x4c, 0x98,
259		0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x03, 0x06, 0x0c, 0x18, 0x30, 0x60, 0xc0, 0x9d, 0x27,
260		0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23, 0x46, 0x8c,
261		0x05, 0x0a, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1, 0x5f, 0xbe,
262		0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0x0f, 0x1e, 0x3c, 0x78, 0xf0, 0xfd, 0xe7,
263		0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2, 0xd9, 0xaf,
264		0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0x0d, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce, 0x81, 0x1f,
265		0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc, 0x85, 0x17,
266		0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54, 0xa8, 0x4d,
267		0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73, 0xe6, 0xd1,
268		0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff, 0xe3, 0xdb,
269		0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41, 0x82, 0x19,
270		0x32, 0x64, 0xc8, 0x8d, 0x07, 0x0e, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6, 0x51, 0xa2,
271		0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x09, 0x12, 0x24,
272		0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0x0b, 0x16, 0x2c, 0x58,
273		0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x01, 0x02, 0x04,
274		};
275
276		const UINT8 nextmo_device::t_log[256] = {
277		0x00, 0x00, 0x01, 0x19, 0x02, 0x32, 0x1a, 0xc6, 0x03, 0xdf, 0x33, 0xee, 0x1b, 0x68, 0xc7, 0x4b,
278		0x04, 0x64, 0xe0, 0x0e, 0x34, 0x8d, 0xef, 0x81, 0x1c, 0xc1, 0x69, 0xf8, 0xc8, 0x08, 0x4c, 0x71,
279		0x05, 0x8a, 0x65, 0x2f, 0xe1, 0x24, 0x0f, 0x21, 0x35, 0x93, 0x8e, 0xda, 0xf0, 0x12, 0x82, 0x45,
280		0x1d, 0xb5, 0xc2, 0x7d, 0x6a, 0x27, 0xf9, 0xb9, 0xc9, 0x9a, 0x09, 0x78, 0x4d, 0xe4, 0x72, 0xa6,
281		0x06, 0xbf, 0x8b, 0x62, 0x66, 0xdd, 0x30, 0xfd, 0xe2, 0x98, 0x25, 0xb3, 0x10, 0x91, 0x22, 0x88,
282		0x36, 0xd0, 0x94, 0xce, 0x8f, 0x96, 0xdb, 0xbd, 0xf1, 0xd2, 0x13, 0x5c, 0x83, 0x38, 0x46, 0x40,
283		0x1e, 0x42, 0xb6, 0xa3, 0xc3, 0x48, 0x7e, 0x6e, 0x6b, 0x3a, 0x28, 0x54, 0xfa, 0x85, 0xba, 0x3d,
284		0xca, 0x5e, 0x9b, 0x9f, 0x0a, 0x15, 0x79, 0x2b, 0x4e, 0xd4, 0xe5, 0xac, 0x73, 0xf3, 0xa7, 0x57,
285		0x07, 0x70, 0xc0, 0xf7, 0x8c, 0x80, 0x63, 0x0d, 0x67, 0x4a, 0xde, 0xed, 0x31, 0xc5, 0xfe, 0x18,
286		0xe3, 0xa5, 0x99, 0x77, 0x26, 0xb8, 0xb4, 0x7c, 0x11, 0x44, 0x92, 0xd9, 0x23, 0x20, 0x89, 0x2e,
287		0x37, 0x3f, 0xd1, 0x5b, 0x95, 0xbc, 0xcf, 0xcd, 0x90, 0x87, 0x97, 0xb2, 0xdc, 0xfc, 0xbe, 0x61,
288		0xf2, 0x56, 0xd3, 0xab, 0x14, 0x2a, 0x5d, 0x9e, 0x84, 0x3c, 0x39, 0x53, 0x47, 0x6d, 0x41, 0xa2,
289		0x1f, 0x2d, 0x43, 0xd8, 0xb7, 0x7b, 0xa4, 0x76, 0xc4, 0x17, 0x49, 0xec, 0x7f, 0x0c, 0x6f, 0xf6,
290		0x6c, 0xa1, 0x3b, 0x52, 0x29, 0x9d, 0x55, 0xaa, 0xfb, 0x60, 0x86, 0xb1, 0xbb, 0xcc, 0x3e, 0x5a,
291		0xcb, 0x59, 0x5f, 0xb0, 0x9c, 0xa9, 0xa0, 0x51, 0x0b, 0xf5, 0x16, 0xeb, 0x7a, 0x75, 0x2c, 0xd7,
292		0x4f, 0xae, 0xd5, 0xe9, 0xe6, 0xe7, 0xad, 0xe8, 0x74, 0xd6, 0xf4, 0xea, 0xa8, 0x50, 0x58, 0xaf,
293		};
294
295		UINT32 nextmo_device::ecc_block(const UINT8 *s, int ss)
	185	void nextmo_device::check_ecc()
296	186	{
297		UINT32 r = (s[0] << 24) \| (s[ss] << 16) \| (s[2ss] << 8) \| s[3ss];
298
299		s += 4*ss;
300		for(int i=4; i<36; i++) {
301		r = t_rem[r >> 24] ^ (r << 8);
302		if(i < 32) {
303		r ^= *s;
304		s += ss;
305		}
306		}
307		return r;
	187	logerror("nextmo: check_ecc\n");
	188	for(int i=0; i<0x400; i++)
	189	sector[i] = i;
308	190	}
309	191
310		void nextmo_device::compute_one_ecc(int off, int step)
311		{
312		UINT32 ecc = ecc_block(sector+off, step);
313		sector[off+32*step] = ecc >> 24;
314		sector[off+33*step] = ecc >> 16;
315		sector[off+34*step] = ecc >> 8;
316		sector[off+35*step] = ecc;
317		}
318
319	192	void nextmo_device::compute_ecc()
320	193	{
321		for(int i=31; i>0; i--)
322		memmove(sector+36i, sector+32i, 32);
323		for(int i=0; i<32; i++)
324		compute_one_ecc(i, 36);
325		for(int i=0; i<36; i++)
326		compute_one_ecc(36*i, 1);
	194	logerror("nextmo: compute_ecc\n");
	195	memset(sector+0x400, 0, 0x110);
327	196	}
328
329		int nextmo_device::fix_one_ecc(int off, int step)
330		{
331		UINT32 ecc = ecc_block(sector+off, step);
332		UINT32 ref_ecc =
333		(sector[off+32*step] << 24) \|
334		(sector[off+33*step] << 16) \|
335		(sector[off+34*step] << 8) \|
336		sector[off+35*step];
337		if(ref_ecc == ecc)
338		return 0;
339
340		// Syndrome polynomial
341		// syn[i] = value of the codebook polynom at 2**(i-1)
342		UINT8 syn[5];
343		memset(syn, 0, 5);
344		syn[0] = 1;
345		for(int i=0; i<36; i++) {
346		UINT8 v = sector[off+step*(35-i)];
347		if(v) {
348		syn[1] ^= v;
349		int lv = t_log[v];
350		syn[2] ^= t_exp[lv+i];
351		syn[3] ^= t_exp[lv+2*i];
352		syn[4] ^= t_exp[lv+3*i];
353		}
354		}
355
356		// Berlekamp-Massey
357
358		UINT8 sigma[5];
359		UINT8 omega[5];
360		UINT8 tau[5];
361		UINT8 gamma[5];
362		int d;
363		int b;
364
365		memset(sigma, 0, 5);
366		memset(omega, 0, 5);
367		memset(tau, 0, 5);
368		memset(gamma, 0, 5);
369		sigma[0] = 1;
370		omega[0] = 1;
371		tau[0] = 1;
372		d = 0;
373		b = 0;
374
375		for(int l=1; l<5; l++) {
376		// 1- Determine the l-order coefficient syn*sigma
377		UINT8 delta = 0;
378		for(int i=0; i<=l; i++)
379		if(sigma[i] && syn[l-i])
380		delta ^= t_exp[t_log[sigma[i]] + t_log[syn[l-i]]];
381
382		// 2- Select update method a/b
383		int limit = (l+1)/2;
384		int exact = l & 1;
385		if(!delta \|\| d > limit \|\| (d == limit && exact && !b)) {
386		// 2.1- Method a
387		// b and d unchanged
388		// tau and gamma multiplied by x
389		// sigma = sigma - delta * tau
390		// omega = omega - delta * gamma
391
392		for(int i=0; i<l; i++) {
393		tau[l-i] = tau[l-i-1];
394		gamma[l-i] = gamma[l-i-1];
395		}
396		tau[0] = gamma[0] = 0;
397
398		if(delta) {
399		UINT8 ldelta = t_log[delta];
400		for(int i=1; i<=l; i++) {
401		if(tau[i])
402		sigma[i] ^= t_exp[t_log[tau [i]] + ldelta];
403		if(gamma[i])
404		omega[i] ^= t_exp[t_log[gamma[i]] + ldelta];
405		}
406		}
407		} else {
408		// 2.2- Method b
409		d = l-d;
410		b = !b;
411		// tau(n+1) = sigma(n) / delta
412		// gamma(n+1) = omega(n) / delta
413		// sigma(n+1) = sigma(n) - deltaxtau(n)
414		// omega(n+1) = omega(n) - deltaxgamma(n)
415		UINT8 ldelta = t_log[delta];
416		UINT8 ildelta = ldelta ^ 255;
417		for(int i=l; i>0; i--) {
418		if(tau[i-1])
419		sigma[i] = sigma[i] ^ t_exp[t_log[tau [i-1]] + ldelta];
420
421		if(gamma[i-1])
422		omega[i] = omega[i] ^ t_exp[t_log[gamma[i-1]] + ldelta];
423
424		if(sigma[i-1])
425		tau[i-1] = t_exp[t_log[sigma[i-1]] + ildelta];
426		else
427		tau[i-1] = 0x00;
428
429		if(omega[i-1])
430		gamma[i-1] = t_exp[t_log[omega[i-1]] + ildelta];
431		else
432		gamma[i-1] = 0x00;
433		}
434		}
435		}
436
437		// Find the roots of sigma to get the error positions (they're the inverses of 2**position)
438		// Compute the error(s)
439
440		if(sigma[3] \|\| sigma[4]) {
441		// Should not happen
442		return -1;
443		}
444
445		if(sigma[2] && sigma[0]) {
446		int epos1, epos2;
447		UINT8 ls1 = t_log[sigma[1]];
448		UINT8 ls2 = t_log[sigma[2]];
449		for(epos1 = 0; epos1 < 256; epos1++) {
450		UINT8 res = sigma[0];
451		if(sigma[1])
452		res ^= t_exp[255-epos1+ls1];
453		res ^= t_exp[2*(255-epos1)+ls2];
454		if(!res)
455		break;
456		}
457		if(epos1 > 35)
458		return -1;
459
460		// sigma = c.(x-1/r1)(x-1/r2) = c.xx - cx(1/r1+1/r2) + c/(r1r2)
461
462		// s0 = s2/(r1r2) -> r1r2s0 = s2 -> r1 = s2 / (r1s0)
463		// -> r2 = sigma[2]/(r1*sigma[0])
464		epos2 = ls2 - epos1 - t_log[sigma[0]];
465		if(epos2 < 0)
466		epos2 += 255;
467		if(epos2 > 35)
468		return -1;
469
470		UINT8 err1 = omega[0];
471		if(omega[1])
472		err1 ^= t_exp[t_log[omega[1]] + 255 - epos1];
473		if(omega[2])
474		err1 ^= t_exp[t_log[omega[2]] + 2*(255 - epos1)];
475		err1 = t_log[err1] + epos1;
476		UINT8 div = t_log[1 ^ t_exp[255 + epos2 - epos1]];
477		err1 = t_exp[255 + err1 - div];
478
479		UINT8 err2 = omega[0];
480		if(omega[1])
481		err2 ^= t_exp[t_log[omega[1]] + 255 - epos2];
482		if(omega[2])
483		err2 ^= t_exp[t_log[omega[2]] + 2*(255 - epos2)];
484		err2 = t_log[err2] + epos2;
485		div = t_log[1 ^ t_exp[255 + epos1 - epos2]];
486		err2 = t_exp[255 + err2 - div];
487
488		sector[off + step*(35-epos1)] ^= err1;
489		sector[off + step*(35-epos2)] ^= err2;
490		return 2;
491
492		} else if(sigma[1] && sigma[0]) {
493		// sigma = c.(x-1/r1) -> r1=sigma[1]/sigma[0]
494		int epos = t_log[sigma[1]] - t_log[sigma[0]];
495
496		if(epos > 35)
497		return -1;
498
499		UINT8 err = sigma[1]^omega[1];
500		sector[off + step*(35-epos)] ^= err;
501		return 1;
502
503		} else {
504		// Should not happen
505		return -1;
506		}
507		}
508
509		void nextmo_device::check_ecc()
510		{
511		int ecount = 0;
512		bool errors_left, errors_fixed;
513		do {
514		errors_left = false;
515		errors_fixed = false;
516		for(int i=0; i<32; i++) {
517		int ec = fix_one_ecc(i, 36);
518		if(ec == -1)
519		errors_left = true;
520		else if(ec) {
521		ecount += ec;
522		errors_fixed = true;
523		}
524		}
525		if(!errors_left)
526		break;
527		for(int i=0; i<36; i++) {
528		int ec = fix_one_ecc(36*i, 1);
529		if(ec == -1)
530		errors_left = true;
531		else if(ec) {
532		ecount += ec;
533		errors_fixed = true;
534		}
535		}
536		} while(errors_left && errors_fixed);
537
538		if(errors_left)
539		fprintf(stderr, "Fix failed\n");
540
541		for(int i=1; i<32; i++)
542		memmove(sector+i32, sector+i36, 32);
543		}

trunk/src/mess/machine/nextmo.h
r243812	r243813
52	52	void check_dma_end();
53	53	void check_ecc();
54	54	void compute_ecc();
55
56		static const UINT32 t_rem[256];
57		static const UINT8 t_exp[768], t_log[256];
58
59		static UINT32 ecc_block(const UINT8 *s, int ss);
60		void compute_one_ecc(int off, int step);
61		int fix_one_ecc(int off, int step);
62	55	};
63	56
64	57	extern const device_type NEXTMO;

trunk/src/mess/machine/pcd_kbd.c
r243812	r243813
219	219	pcd_keyboard_device::pcd_keyboard_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
220	220	: device_t(mconfig, PCD_KEYBOARD, "PC-D Keyboard", tag, owner, clock, "pcd_kbd", __FILE__),
221	221	m_rows(*this, "ROW"),
222		m_data(0),
223	222	m_p1(0),
224	223	m_out_tx_handler(*this)
225	224	{

trunk/src/mess/machine/pcd_kbd.h
r243812	r243813
28	28	DECLARE_WRITE_LINE_MEMBER( t0_w );
29	29	private:
30	30	required_ioport_array<17> m_rows;
31		UINT8 m_~~data, m_~~p1;
	31	UINT8 m_p1;
32	32	bool m_t0;
33	33	devcb_write_line m_out_tx_handler;
34	34	};

trunk/src/mess/mess.lst
r243812	r243813
2617	2617	edracula
2618	2618	tc4
2619	2619	ebball
2620		mt735
2621		lg

trunk/src/mess/mess.mak
r243812	r243813
260	260	SOUNDS += MOS7360
261	261	SOUNDS += ESQPUMP
262	262	SOUNDS += VRC6
263		SOUNDS += LA32
264	263
265	264	#-------------------------------------------------
266	265	# specify available video cores
r243812	r243813
1987	1986	$(MESS_DRIVERS)/ms0515.o \
1988	1987	$(MESS_DRIVERS)/ms9540.o \
1989	1988	$(MESS_DRIVERS)/mstation.o \
1990		$(MESS_DRIVERS)/mt735.o \
1991	1989	$(MESS_DRIVERS)/mx2178.o \
1992	1990	$(MESS_DRIVERS)/mycom.o \
1993	1991	$(MESS_DRIVERS)/myvision.o \
r243812	r243813
2031	2029	$(MESS_DRIVERS)/xor100.o \
2032	2030	$(MESS_DRIVERS)/xavix.o \
2033	2031	$(MESS_DRIVERS)/zorba.o \
2034		$(MESS_DRIVERS)/lg.o
2035	2032
2036	2033
2037	2034

trunk/src/mess/tools/floptool/main.c
r243812	r243813
124	124	fprintf(stderr, "Usage: \n");
125	125	fprintf(stderr, " floptool.exe identify <inputfile> [<inputfile> ...]\n");
126	126	fprintf(stderr, " floptool.exe convert [input_format\|auto] output_format <inputfile> <outputfile>\n");
127		fprintf(stderr, " floptool.exe stream-to-flux <inputfile> <outputfile> [half\|quarter\|<track> <subtrack> <head>]\n");
128	127	}
129	128
130	129	static void display_formats()
r243812	r243813
266	265
267	266	if (!core_stricmp("identify", argv[1]))
268	267	return identify(argc, argv);
269
270	268	else if (!core_stricmp("convert", argv[1]))
271	269	return convert(argc, argv);
272
273		else if (!core_stricmp("stream-to-flux", argv[1]))
274		return stream_to_flux(argc, argv);
275
276	270	else {
277	271	fprintf(stderr, "Unknown command '%s'\n\n", argv[1]);
278	272	display_usage();

trunk/src/mess/video/atarist.c
r243812	r243813
12	12	*/
13	13
14	14	#include "emu.h"
15		#include "mac~~hine~~/mc68901.h"
	15	#include "cpu/m68000/m68000.h"
16	16	#include "machine/ram.h"
17	17	#include "video/atarist.h"
18	18	#include "includes/atarist.h"

trunk/src/osd/modules/netdev/taptun.c
r243812	r243813
57	57	{
58	58	#ifdef __linux__
59	59	struct ifreq ifr;
	60
60	61	m_fd = -1;
61	62	if((m_fd = open("/dev/net/tun", O_RDWR)) == -1) {
62	63	osd_printf_verbose("tap: open failed %d\n", errno);
r243812	r243813
65	66
66	67	memset(&ifr, 0, sizeof(ifr));
67	68	ifr.ifr_flags = IFF_TAP \| IFF_NO_PI;
68		sprintf(ifr.ifr_name, "mess0");
	69	sprintf(ifr.ifr_name, "tap-mess-%d-0", getuid());
69	70	if(ioctl(m_fd, TUNSETIFF, (void *)&ifr) == -1) {
70	71	osd_printf_verbose("tap: ioctl failed %d\n", errno);
71	72	close(m_fd);

https://github.com/mamedev/mame/commit/cf05cdf6835f5f1f0480f0752220491d9ad62fd9

199869 Revisions