MAME SVN History

199869 Revisions

r35297 Thursday 26th February, 2015 at 15:11:29 UTC by Olivier Galibert
h8: Add watchdog, dma [O. Galibert] h8: Disassembly fix [O. Galibert] tmp68301: Add serial [O. Galibert]

[src/emu/cpu]	cpu.mak
[src/emu/cpu/h8]	h8.c h8.h h83002.c h83002.h h83006.c h83006.h h83008.c h83008.h h83048.c h83048.h h83337.c h83337.h h8_dma.c* h8_dma.h* h8_sci.c h8_watchdog.c* h8_watchdog.h* h8s2245.c h8s2245.h h8s2320.c h8s2320.h h8s2357.c h8s2357.h h8s2655.c h8s2655.h
[src/emu/machine]	tmp68301.c tmp68301.h
[src/mame/drivers]	csplayh5.c niyanpai.c realbrk.c seta2.c

trunk/src/emu/cpu/cpu.mak
r243808	r243809
573	573	$(CPUOBJ)/h8/h83048.o \
574	574	$(CPUOBJ)/h8/h8s2245.o $(CPUOBJ)/h8/h8s2320.o $(CPUOBJ)/h8/h8s2357.o \
575	575	$(CPUOBJ)/h8/h8s2655.o \
576		$(CPUOBJ)/h8/h8_adc.o $(CPUOBJ)/h8/h8_port.o $(CPUOBJ)/h8/h8_intc.o \
577		$(CPUOBJ)/h8/h8_timer8.o $(CPUOBJ)/h8/h8_timer16.o $(CPUOBJ)/h8/h8_sci.o
	576	$(CPUOBJ)/h8/h8_adc.o $(CPUOBJ)/h8/h8_dma.o $(CPUOBJ)/h8/h8_port.o $(CPUOBJ)/h8/h8_intc.o \
	577	$(CPUOBJ)/h8/h8_timer8.o $(CPUOBJ)/h8/h8_timer16.o $(CPUOBJ)/h8/h8_sci.o $(CPUOBJ)/h8/h8_watchdog.o
	578
578	579	DASMOBJS +=
579	580	endif
580	581
r243808	r243809
608	609	$(CPUSRC)/h8/h8_port.h \
609	610	$(CPUSRC)/h8/h8_timer8.h \
610	611	$(CPUSRC)/h8/h8_timer16.h \
611		$(CPUSRC)/h8/h8_sci.h
	612	$(CPUSRC)/h8/h8_sci.h \
	613	$(CPUSRC)/h8/h8_watchdog.h
612	614
613	615	$(CPUOBJ)/h8/h83002.o: $(CPUSRC)/h8/h83002.c \
614	616	$(CPUSRC)/h8/h83002.h \
r243808	r243809
618	620	$(CPUSRC)/h8/h8_adc.h \
619	621	$(CPUSRC)/h8/h8_port.h \
620	622	$(CPUSRC)/h8/h8_timer16.h \
621		$(CPUSRC)/h8/h8_sci.h
	623	$(CPUSRC)/h8/h8_sci.h \
	624	$(CPUSRC)/h8/h8_watchdog.h
622	625
623	626	$(CPUOBJ)/h8/h83006.o: $(CPUSRC)/h8/h83006.c \
624	627	$(CPUSRC)/h8/h83006.h \
r243808	r243809
629	632	$(CPUSRC)/h8/h8_port.h \
630	633	$(CPUSRC)/h8/h8_timer8.h \
631	634	$(CPUSRC)/h8/h8_timer16.h \
632		$(CPUSRC)/h8/h8_sci.h
	635	$(CPUSRC)/h8/h8_sci.h \
	636	$(CPUSRC)/h8/h8_watchdog.h
633	637
634	638	$(CPUOBJ)/h8/h83008.o: $(CPUSRC)/h8/h83008.c \
635	639	$(CPUSRC)/h8/h83008.h \
r243808	r243809
640	644	$(CPUSRC)/h8/h8_port.h \
641	645	$(CPUSRC)/h8/h8_timer8.h \
642	646	$(CPUSRC)/h8/h8_timer16.h \
643		$(CPUSRC)/h8/h8_sci.h
	647	$(CPUSRC)/h8/h8_sci.h \
	648	$(CPUSRC)/h8/h8_watchdog.h
644	649
645	650	$(CPUOBJ)/h8/h83048.o: $(CPUSRC)/h8/h83048.c \
646	651	$(CPUSRC)/h8/h83048.h \
r243808	r243809
650	655	$(CPUSRC)/h8/h8_adc.h \
651	656	$(CPUSRC)/h8/h8_port.h \
652	657	$(CPUSRC)/h8/h8_timer16.h \
653		$(CPUSRC)/h8/h8_sci.h
	658	$(CPUSRC)/h8/h8_sci.h \
	659	$(CPUSRC)/h8/h8_watchdog.h
654	660
655	661	$(CPUOBJ)/h8/h8s2245.o: $(CPUSRC)/h8/h8s2245.c \
656	662	$(CPUSRC)/h8/h8s2245.h \
r243808	r243809
662	668	$(CPUSRC)/h8/h8_port.h \
663	669	$(CPUSRC)/h8/h8_timer8.h \
664	670	$(CPUSRC)/h8/h8_timer16.h \
665		$(CPUSRC)/h8/h8_sci.h
	671	$(CPUSRC)/h8/h8_sci.h \
	672	$(CPUSRC)/h8/h8_watchdog.h
666	673
667	674	$(CPUOBJ)/h8/h8s2320.o: $(CPUSRC)/h8/h8s2320.c \
668	675	$(CPUSRC)/h8/h8s2320.h \
r243808	r243809
671	678	$(CPUSRC)/h8/h8.h \
672	679	$(CPUSRC)/h8/h8_intc.h \
673	680	$(CPUSRC)/h8/h8_adc.h \
	681	$(CPUSRC)/h8/h8_dma.h \
674	682	$(CPUSRC)/h8/h8_port.h \
675	683	$(CPUSRC)/h8/h8_timer8.h \
676	684	$(CPUSRC)/h8/h8_timer16.h \
677		$(CPUSRC)/h8/h8_sci.h
	685	$(CPUSRC)/h8/h8_sci.h \
	686	$(CPUSRC)/h8/h8_watchdog.h
678	687
679	688	$(CPUOBJ)/h8/h8s2357.o: $(CPUSRC)/h8/h8s2357.c \
680	689	$(CPUSRC)/h8/h8s2357.h \
r243808	r243809
686	695	$(CPUSRC)/h8/h8_port.h \
687	696	$(CPUSRC)/h8/h8_timer8.h \
688	697	$(CPUSRC)/h8/h8_timer16.h \
689		$(CPUSRC)/h8/h8_sci.h
	698	$(CPUSRC)/h8/h8_sci.h \
	699	$(CPUSRC)/h8/h8_watchdog.h
690	700
691	701	$(CPUOBJ)/h8/h8s2655.o: $(CPUSRC)/h8/h8s2655.c \
692	702	$(CPUSRC)/h8/h8s2655.h \
r243808	r243809
699	709	$(CPUSRC)/h8/h8_port.h \
700	710	$(CPUSRC)/h8/h8_timer8.h \
701	711	$(CPUSRC)/h8/h8_timer16.h \
702		$(CPUSRC)/h8/h8_sci.h
	712	$(CPUSRC)/h8/h8_sci.h \
	713	$(CPUSRC)/h8/h8_watchdog.h
703	714
704	715	$(CPUOBJ)/h8/h8_intc.o: $(CPUSRC)/h8/h8_intc.c \
705	716	$(CPUSRC)/h8/h8_intc.h \
r243808	r243809
710	721	$(CPUSRC)/h8/h8_intc.h \
711	722	$(CPUSRC)/h8/h8.h
712	723
	724	$(CPUOBJ)/h8/h8_dma.o: $(CPUSRC)/h8/h8_dma.c \
	725	$(CPUSRC)/h8/h8_dma.h \
	726	$(CPUSRC)/h8/h8_intc.h \
	727	$(CPUSRC)/h8/h8.h
	728
713	729	$(CPUOBJ)/h8/h8_port.o: $(CPUSRC)/h8/h8_port.c \
714	730	$(CPUSRC)/h8/h8_port.h \
715	731	$(CPUSRC)/h8/h8.h
716	732
	733	$(CPUOBJ)/h8/h8_timer8.o: $(CPUSRC)/h8/h8_timer8.c \
	734	$(CPUSRC)/h8/h8_timer8.h \
	735	$(CPUSRC)/h8/h8_intc.h \
	736	$(CPUSRC)/h8/h8.h
	737
717	738	$(CPUOBJ)/h8/h8_timer16.o: $(CPUSRC)/h8/h8_timer16.c \
718	739	$(CPUSRC)/h8/h8_timer16.h \
719	740	$(CPUSRC)/h8/h8_intc.h \
r243808	r243809
724	745	$(CPUSRC)/h8/h8_intc.h \
725	746	$(CPUSRC)/h8/h8.h
726	747
	748	$(CPUOBJ)/h8/h8_watchdog.o: $(CPUSRC)/h8/h8_watchdog.c \
	749	$(CPUSRC)/h8/h8_watchdog.h \
	750	$(CPUSRC)/h8/h8_intc.h \
	751	$(CPUSRC)/h8/h8.h
	752
727	753	# rule to generate the C files
728	754	$(CPUOBJ)/h8/h8.inc: $(CPUSRC)/h8/h8make.py $(CPUSRC)/h8/h8.lst
729	755	@echo Generating H8-300 source file...

trunk/src/emu/cpu/h8/h8.c
r243808	r243809
295	295	return 10;
296	296	}
297	297
298		void h8_device::disassemble_am(char &buffer, int am, offs_t pc, const UINT8 oprom, UINT32 opcode, int offset)
	298	void h8_device::disassemble_am(char &buffer, int am, offs_t pc, const UINT8 oprom, UINT32 opcode, int slot, int offset)
299	299	{
300	300	static const char *const r8_names[16] = {
301	301	"r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h",
r243808	r243809
420	420	break;
421	421
422	422	case DASM_abs32:
423		if(~~off~~set >= 8)
	423	if(slot == 3)
424	424	buffer += sprintf(buffer, "@%08x", (oprom[offset-6] << 24) \| (oprom[offset-5] << 16) \| (oprom[offset-4] << 8) \| oprom[offset-3]);
425	425	else
426	426	buffer += sprintf(buffer, "@%08x", (oprom[offset-4] << 24) \| (oprom[offset-3] << 16) \| (oprom[offset-2] << 8) \| oprom[offset-1]);
r243808	r243809
520	520
521	521	if(e.am1 != DASM_none) {
522	522	*buffer++ = ' ';
523		disassemble_am(buffer, e.am1, pc, oprom, slot[e.slot], e.flags & DASMFLAG_LENGTHMASK);
	523	disassemble_am(buffer, e.am1, pc, oprom, slot[e.slot], e.slot, e.flags & DASMFLAG_LENGTHMASK);
524	524	}
525	525	if(e.am2 != DASM_none) {
526	526	*buffer++ = ',';
527	527	*buffer++ = ' ';
528		disassemble_am(buffer, e.am2, pc, oprom, slot[e.slot], e.flags & DASMFLAG_LENGTHMASK);
	528	disassemble_am(buffer, e.am2, pc, oprom, slot[e.slot], e.slot, e.flags & DASMFLAG_LENGTHMASK);
529	529	}
530	530	return e.flags \| DASMFLAG_SUPPORTED;
531	531	}
r243808	r243809
556	556
557	557	void h8_device::write8(UINT32 adr, UINT8 data)
558	558	{
559		// logerror("W %06x %02x\n", adr & 0xffffff, data);
560	559	icount--;
561	560	program->write_byte(adr, data);
562	561	}
r243808	r243809
569	568
570	569	void h8_device::write16(UINT32 adr, UINT16 data)
571	570	{
572		// logerror("W %06x %04x\n", adr & 0xfffffe, data);
573	571	icount--;
574	572	program->write_word(adr & ~1, data);
575	573	}

trunk/src/emu/cpu/h8/h8.h
r243808	r243809
220	220	static const disasm_entry disasm_entries[];
221	221
222	222	offs_t disassemble_generic(char buffer, offs_t pc, const UINT8 oprom, const UINT8 opram, UINT32 options, const disasm_entry table);
223		void disassemble_am(char &buffer, int am, offs_t pc, const UINT8 oprom, UINT32 opcode, int offset);
	223	void disassemble_am(char &buffer, int am, offs_t pc, const UINT8 oprom, UINT32 opcode, int slot, int offset);
224	224
225	225	virtual void do_exec_full();
226	226	virtual void do_exec_partial();

trunk/src/emu/cpu/h8/h83002.c
r243808	r243809
21	21	timer16_3(*this, "timer16:3"),
22	22	timer16_4(*this, "timer16:4"),
23	23	sci0(*this, "sci0"),
24		sci1(*this, "sci1")
	24	sci1(*this, "sci1"),
	25	watchdog(*this, "watchdog")
25	26	{
26	27	}
27	28
r243808	r243809
43	44	MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:4", 2, 2, "intc", 40)
44	45	MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
45	46	MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
	47	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
46	48	MACHINE_CONFIG_END
47	49
48	50	DEVICE_ADDRESS_MAP_START(map, 16, h83002_device)
r243808	r243809
87	89	AM_RANGE(0xffff98, 0xffff9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
88	90	AM_RANGE(0xffff9c, 0xffff9f) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tbr_r, tbr_w )
89	91
	92	AM_RANGE(0xffffa8, 0xffffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
	93	AM_RANGE(0xffffaa, 0xffffab) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
	94
90	95	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
91	96	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
92	97	AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
r243808	r243809
189	194	add_event(event_time, timer16_2->internal_update(current_time));
190	195	add_event(event_time, timer16_3->internal_update(current_time));
191	196	add_event(event_time, timer16_4->internal_update(current_time));
	197	add_event(event_time, watchdog->internal_update(current_time));
192	198
193	199	recompute_bcount(event_time);
194	200	}

trunk/src/emu/cpu/h8/h83002.h
r243808	r243809
46	46	#include "h8_adc.h"
47	47	#include "h8_port.h"
48	48	#include "h8_intc.h"
	49	#include "h8_timer16.h"
49	50	#include "h8_sci.h"
50		#include "h8_t~~imer16~~.h"
	51	#include "h8_watchdog.h"
51	52
52	53	class h83002_device : public h8h_device {
53	54	public:
r243808	r243809
74	75	required_device<h8h_timer16_channel_device> timer16_4;
75	76	required_device<h8_sci_device> sci0;
76	77	required_device<h8_sci_device> sci1;
	78	required_device<h8_watchdog_device> watchdog;
77	79
78	80	UINT8 syscr;
79	81

trunk/src/emu/cpu/h8/h83006.c
r243808	r243809
26	26	timer16_2(*this, "timer16:2"),
27	27	sci0(*this, "sci0"),
28	28	sci1(*this, "sci1"),
29		sci2(*this, "sci2")
	29	sci2(*this, "sci2"),
	30	watchdog(*this, "watchdog")
30	31	{
31	32	}
32	33
r243808	r243809
51	52	timer16_2(*this, "timer16:2"),
52	53	sci0(*this, "sci0"),
53	54	sci1(*this, "sci1"),
54		sci2(*this, "sci2")
	55	sci2(*this, "sci2"),
	56	watchdog(*this, "watchdog")
55	57	{
56	58	ram_start = 0xfff720;
57	59	}
r243808	r243809
84	86	MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
85	87	MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
86	88	MCFG_H8_SCI_ADD("sci2", "intc", 60, 61, 62, 63)
	89	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
87	90	MACHINE_CONFIG_END
88	91
89	92	DEVICE_ADDRESS_MAP_START(map, 16, h83006_device)
r243808	r243809
130	133	AM_RANGE(0xffff84, 0xffff87) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
131	134	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
132	135	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
	136	AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
	137	AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
133	138	AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
134	139	AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_3", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
135	140	AM_RANGE(0xffff92, 0xffff93) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
r243808	r243809
240	245	add_event(event_time, timer16_0->internal_update(current_time));
241	246	add_event(event_time, timer16_1->internal_update(current_time));
242	247	add_event(event_time, timer16_2->internal_update(current_time));
	248	add_event(event_time, watchdog->internal_update(current_time));
243	249
244	250	recompute_bcount(event_time);
245	251	}

trunk/src/emu/cpu/h8/h83006.h
r243808	r243809
46	46	#include "h8_adc.h"
47	47	#include "h8_port.h"
48	48	#include "h8_intc.h"
49		#include "h8_sci.h"
50	49	#include "h8_timer8.h"
51	50	#include "h8_timer16.h"
	51	#include "h8_sci.h"
	52	#include "h8_watchdog.h"
52	53
53	54	class h83006_device : public h8h_device {
54	55	public:
r243808	r243809
79	80	required_device<h8_sci_device> sci0;
80	81	required_device<h8_sci_device> sci1;
81	82	required_device<h8_sci_device> sci2;
	83	required_device<h8_watchdog_device> watchdog;
82	84
83	85	UINT8 syscr;
84	86	UINT32 ram_start;

trunk/src/emu/cpu/h8/h83008.c
r243808	r243809
23	23	timer16_1(*this, "timer16:1"),
24	24	timer16_2(*this, "timer16:2"),
25	25	sci0(*this, "sci0"),
26		sci1(*this, "sci1")
	26	sci1(*this, "sci1"),
	27	watchdog(*this, "watchdog")
27	28	{
28	29	}
29	30
r243808	r243809
47	48	MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:2", 2, 2, "intc", 32)
48	49	MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
49	50	MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
	51	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
50	52	MACHINE_CONFIG_END
51	53
52	54	DEVICE_ADDRESS_MAP_START(map, 16, h83008_device)
r243808	r243809
93	95	AM_RANGE(0xffff84, 0xffff87) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
94	96	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
95	97	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
	98	AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
	99	AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
96	100	AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
97	101	AM_RANGE(0xffff90, 0xffff91) AM_DEVREADWRITE8("timer8_3", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
98	102	AM_RANGE(0xffff92, 0xffff93) AM_DEVREADWRITE8("timer8_2", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
r243808	r243809
195	199	add_event(event_time, timer16_0->internal_update(current_time));
196	200	add_event(event_time, timer16_1->internal_update(current_time));
197	201	add_event(event_time, timer16_2->internal_update(current_time));
	202	add_event(event_time, watchdog->internal_update(current_time));
198	203
199	204	recompute_bcount(event_time);
200	205	}

trunk/src/emu/cpu/h8/h83008.h
r243808	r243809
46	46	#include "h8_adc.h"
47	47	#include "h8_port.h"
48	48	#include "h8_intc.h"
49		#include "h8_sci.h"
50	49	#include "h8_timer8.h"
51	50	#include "h8_timer16.h"
	51	#include "h8_sci.h"
	52	#include "h8_watchdog.h"
52	53
53	54	class h83008_device : public h8h_device {
54	55	public:
r243808	r243809
78	79	required_device<h8h_timer16_channel_device> timer16_2;
79	80	required_device<h8_sci_device> sci0;
80	81	required_device<h8_sci_device> sci1;
	82	required_device<h8_watchdog_device> watchdog;
81	83
82	84	UINT8 syscr;
83	85

trunk/src/emu/cpu/h8/h83048.c
r243808	r243809
28	28	timer16_3(*this, "timer16:3"),
29	29	timer16_4(*this, "timer16:4"),
30	30	sci0(*this, "sci0"),
31		sci1(*this, "sci1")
	31	sci1(*this, "sci1"),
	32	watchdog(*this, "watchdog")
32	33	{
33	34	}
34	35
r243808	r243809
54	55	timer16_3(*this, "timer16:3"),
55	56	timer16_4(*this, "timer16:4"),
56	57	sci0(*this, "sci0"),
57		sci1(*this, "sci1")
	58	sci1(*this, "sci1"),
	59	watchdog(*this, "watchdog")
58	60	{
59	61	ram_start = 0xffef10;
60	62	}
r243808	r243809
99	101	MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:4", 2, 2, "intc", 40)
100	102	MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
101	103	MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
	104	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
102	105	MACHINE_CONFIG_END
103	106
104	107	DEVICE_ADDRESS_MAP_START(map, 16, h83048_device)
r243808	r243809
143	146	AM_RANGE(0xffff98, 0xffff9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
144	147	AM_RANGE(0xffff9c, 0xffff9f) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tbr_r, tbr_w )
145	148
	149	AM_RANGE(0xffffa8, 0xffffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
	150	AM_RANGE(0xffffaa, 0xffffab) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
	151
146	152	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
147	153	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
148	154	AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
r243808	r243809
256	262	add_event(event_time, timer16_2->internal_update(current_time));
257	263	add_event(event_time, timer16_3->internal_update(current_time));
258	264	add_event(event_time, timer16_4->internal_update(current_time));
	265	add_event(event_time, watchdog->internal_update(current_time));
259	266
260	267	recompute_bcount(event_time);
261	268	}

trunk/src/emu/cpu/h8/h83048.h
r243808	r243809
54	54	#include "h8_adc.h"
55	55	#include "h8_port.h"
56	56	#include "h8_intc.h"
	57	#include "h8_timer16.h"
57	58	#include "h8_sci.h"
58		#include "h8_t~~imer16~~.h"
	59	#include "h8_watchdog.h"
59	60
60	61	class h83048_device : public h8h_device {
61	62	public:
r243808	r243809
87	88	required_device<h8h_timer16_channel_device> timer16_4;
88	89	required_device<h8_sci_device> sci0;
89	90	required_device<h8_sci_device> sci1;
	91	required_device<h8_watchdog_device> watchdog;
90	92
91	93	UINT32 ram_start;
92	94	UINT8 syscr;

trunk/src/emu/cpu/h8/h83337.c
r243808	r243809
24	24	timer16(*this, "timer16"),
25	25	timer16_0(*this, "timer16:0"),
26	26	sci0(*this, "sci0"),
27		sci1(*this, "sci1")
	27	sci1(*this, "sci1"),
	28	watchdog(*this, "watchdog")
28	29	{
29	30	}
30	31
r243808	r243809
46	47	timer16(*this, "timer16"),
47	48	timer16_0(*this, "timer16:0"),
48	49	sci0(*this, "sci0"),
49		sci1(*this, "sci1")
	50	sci1(*this, "sci1"),
	51	watchdog(*this, "watchdog")
50	52	{
51	53	ram_start = 0xf780;
52	54	}
r243808	r243809
81	83	MCFG_H8_TIMER16_CHANNEL_ADD("timer16:0", 4, 0, "intc", 32)
82	84	MCFG_H8_SCI_ADD("sci0", "intc", 27, 28, 29, 30)
83	85	MCFG_H8_SCI_ADD("sci1", "intc", 31, 32, 33, 34)
	86	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 36, h8_watchdog_device::B)
84	87	MACHINE_CONFIG_END
85	88
86	89	DEVICE_ADDRESS_MAP_START(map, 16, h83337_device)
r243808	r243809
100	103	// AM_RANGE(0xff96, 0xff97) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tocr_r, tocr_w, 0x00ff)
101	104	AM_RANGE(0xff98, 0xff9f) AM_DEVREAD( "timer16:0", h8_timer16_channel_device, tgr_r )
102	105
	106	AM_RANGE(0xffa8, 0xffa9) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
103	107	AM_RANGE(0xffac, 0xffad) AM_DEVREADWRITE8("port1", h8_port_device, pcr_r, pcr_w, 0xff00)
104	108	AM_RANGE(0xffac, 0xffad) AM_DEVREADWRITE8("port2", h8_port_device, pcr_r, pcr_w, 0x00ff)
105	109	AM_RANGE(0xffae, 0xffaf) AM_DEVREADWRITE8("port3", h8_port_device, pcr_r, pcr_w, 0xff00)
r243808	r243809
186	190	add_event(event_time, timer8_0->internal_update(current_time));
187	191	add_event(event_time, timer8_1->internal_update(current_time));
188	192	add_event(event_time, timer16_0->internal_update(current_time));
	193	add_event(event_time, watchdog->internal_update(current_time));
189	194
190	195	recompute_bcount(event_time);
191	196	}

trunk/src/emu/cpu/h8/h83337.h
r243808	r243809
50	50	#define __H83337_H__
51	51
52	52	#include "h8.h"
	53	#include "h8_intc.h"
53	54	#include "h8_adc.h"
54	55	#include "h8_port.h"
55		#include "h8_intc.h"
56	56	#include "h8_timer8.h"
57	57	#include "h8_timer16.h"
58	58	#include "h8_sci.h"
	59	#include "h8_watchdog.h"
59	60
60	61	class h83337_device : public h8_device {
61	62	public:
r243808	r243809
89	90	required_device<h8_timer16_channel_device> timer16_0;
90	91	required_device<h8_sci_device> sci0;
91	92	required_device<h8_sci_device> sci1;
	93	required_device<h8_watchdog_device> watchdog;
92	94
93	95	UINT8 syscr;
94	96	UINT32 ram_start;

trunk/src/emu/cpu/h8/h8_dma.c
r0	r243809
	1	#include "emu.h"
	2	#include "h8_dma.h"
	3
	4	const device_type H8_DMA = &device_creator<h8_dma_device>;
	5	const device_type H8_DMA_CHANNEL = &device_creator<h8_dma_channel_device>;
	6
	7	h8_dma_device::h8_dma_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	8	device_t(mconfig, H8_DMA, "H8 DMA controller", tag, owner, clock, "h8_dma", __FILE__)
	9	{
	10	}
	11
	12	void h8_dma_device::device_start()
	13	{
	14	}
	15
	16	void h8_dma_device::device_reset()
	17	{
	18	dmabcr = 0x0000;
	19	dmawer = 0x00;
	20	}
	21
	22	READ8_MEMBER(h8_dma_device::dmawer_r)
	23	{
	24	logerror("%s: dmawer_r\n", tag());
	25	return dmawer;
	26	}
	27
	28	WRITE8_MEMBER(h8_dma_device::dmawer_w)
	29	{
	30	dmawer = data;
	31	logerror("%s: dmawer_w %02x\n", tag(), data);
	32	}
	33
	34	READ8_MEMBER(h8_dma_device::dmatcr_r)
	35	{
	36	logerror("%s: dmatcr_r\n", tag());
	37	return dmatcr;
	38	}
	39
	40	WRITE8_MEMBER(h8_dma_device::dmatcr_w)
	41	{
	42	dmatcr = data;
	43	logerror("%s: dmatcr_w %02x\n", tag(), data);
	44	}
	45
	46	READ16_MEMBER(h8_dma_device::dmabcr_r)
	47	{
	48	logerror("%s: dmabcr_r\n", tag());
	49	return dmabcr;
	50	}
	51
	52	WRITE16_MEMBER(h8_dma_device::dmabcr_w)
	53	{
	54	COMBINE_DATA(&dmabcr);
	55	logerror("%s: dmabcr_w %04x\n", tag(), dmabcr);
	56	if(dmabcr & 0x40)
	57	dmabcr &= ~0x40;
	58	}
	59
	60
	61
	62	h8_dma_channel_device::h8_dma_channel_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	63	device_t(mconfig, H8_DMA_CHANNEL, "H8 DMA channel", tag, owner, clock, "h8_dma_channel", __FILE__)
	64	{
	65	}
	66
	67	void h8_dma_channel_device::set_info(const char *intc, int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf)
	68	{
	69	}
	70
	71	void h8_dma_channel_device::device_start()
	72	{
	73	}
	74
	75	void h8_dma_channel_device::device_reset()
	76	{
	77	}
	78
	79	READ16_MEMBER(h8_dma_channel_device::marah_r)
	80	{
	81	logerror("%s: marah_r\n", tag());
	82	return 0x0000;
	83	}
	84
	85	WRITE16_MEMBER(h8_dma_channel_device::marah_w)
	86	{
	87	logerror("%s: marah_w %04x\n", tag(), data);
	88	}
	89
	90	READ16_MEMBER(h8_dma_channel_device::maral_r)
	91	{
	92	logerror("%s: maral_r\n", tag());
	93	return 0x0000;
	94	}
	95
	96	WRITE16_MEMBER(h8_dma_channel_device::maral_w)
	97	{
	98	logerror("%s: maral_w %04x\n", tag(), data);
	99	}
	100
	101	READ16_MEMBER(h8_dma_channel_device::ioara_r)
	102	{
	103	logerror("%s: iorar_r\n", tag());
	104	return 0x0000;
	105	}
	106
	107	WRITE16_MEMBER(h8_dma_channel_device::ioara_w)
	108	{
	109	logerror("%s: ioara_w %04x\n", tag(), data);
	110	}
	111
	112	READ16_MEMBER(h8_dma_channel_device::etcra_r)
	113	{
	114	logerror("%s: etcra_r\n", tag());
	115	return 0x0000;
	116	}
	117
	118	WRITE16_MEMBER(h8_dma_channel_device::etcra_w)
	119	{
	120	logerror("%s: etcra_w %04x\n", tag(), data);
	121	}
	122
	123	READ16_MEMBER(h8_dma_channel_device::marbh_r)
	124	{
	125	logerror("%s: marbh_r\n", tag());
	126	return 0x0000;
	127	}
	128
	129	WRITE16_MEMBER(h8_dma_channel_device::marbh_w)
	130	{
	131	logerror("%s: marbh_w %04x\n", tag(), data);
	132	}
	133
	134	READ16_MEMBER(h8_dma_channel_device::marbl_r)
	135	{
	136	logerror("%s: marbl_r\n", tag());
	137	return 0x0000;
	138	}
	139
	140	WRITE16_MEMBER(h8_dma_channel_device::marbl_w)
	141	{
	142	logerror("%s: marbl_w %04x\n", tag(), data);
	143	}
	144
	145	READ16_MEMBER(h8_dma_channel_device::ioarb_r)
	146	{
	147	logerror("%s: ioarb_r\n", tag());
	148	return 0x0000;
	149	}
	150
	151	WRITE16_MEMBER(h8_dma_channel_device::ioarb_w)
	152	{
	153	logerror("%s: ioarb_w %04x\n", tag(), data);
	154	}
	155
	156	READ16_MEMBER(h8_dma_channel_device::etcrb_r)
	157	{
	158	logerror("%s: etcrb_r\n", tag());
	159	return 0x0000;
	160	}
	161
	162	WRITE16_MEMBER(h8_dma_channel_device::etcrb_w)
	163	{
	164	logerror("%s: etcrb_w %04x\n", tag(), data);
	165	}
	166
	167	READ8_MEMBER(h8_dma_channel_device::dmacr_r)
	168	{
	169	logerror("%s: dmacr_r %d\n", tag(), offset);
	170	return 0x00;
	171	}
	172
	173	WRITE8_MEMBER(h8_dma_channel_device::dmacr_w)
	174	{
	175	logerror("%s: dmacr_w %d, %02x\n", tag(), offset, data);
	176	}

trunk/src/emu/cpu/h8/h8_dma.h
r0	r243809
	1	/***************************************************************************
	2
	3	h8_dma.h
	4
	5	H8 DMA
	6
	7	****************************************************************************
	8
	9	Copyright Olivier Galibert
	10	All rights reserved.
	11
	12	Redistribution and use in source and binary forms, with or without
	13	modification, are permitted provided that the following conditions are
	14	met:
	15
	16	* Redistributions of source code must retain the above copyright
	17	notice, this list of conditions and the following disclaimer.
	18	* Redistributions in binary form must reproduce the above copyright
	19	notice, this list of conditions and the following disclaimer in
	20	the documentation and/or other materials provided with the
	21	distribution.
	22	* Neither the name 'MAME' nor the names of its contributors may be
	23	used to endorse or promote products derived from this software
	24	without specific prior written permission.
	25
	26	THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR
	27	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	28	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	29	DISCLAIMED. IN NO EVENT SHALL OLIVIER GALIBERT BE LIABLE FOR ANY DIRECT,
	30	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	31	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	32	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	33	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	34	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	35	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	36	POSSIBILITY OF SUCH DAMAGE.
	37
	38	***************************************************************************/
	39
	40	#ifndef __H8_DMA_H__
	41	#define __H8_DMA_H__
	42
	43	#include "h8.h"
	44	#include "h8_intc.h"
	45
	46	#define MCFG_H8_DMA_ADD( _tag ) \
	47	MCFG_DEVICE_ADD( _tag, H8_DMA, 0 )
	48
	49	#define MCFG_H8_DMA_CHANNEL_ADD( _tag, intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf ) \
	50	MCFG_DEVICE_ADD( _tag, H8_DMA_CHANNEL, 0 ) \
	51	downcast<h8_dma_channel_device *>(device)->set_info(intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf);
	52
	53	class h8_dma_device : public device_t {
	54	public:
	55	h8_dma_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	56
	57	DECLARE_READ8_MEMBER(dmawer_r);
	58	DECLARE_WRITE8_MEMBER(dmawer_w);
	59	DECLARE_READ8_MEMBER(dmatcr_r);
	60	DECLARE_WRITE8_MEMBER(dmatcr_w);
	61	DECLARE_READ16_MEMBER(dmabcr_r);
	62	DECLARE_WRITE16_MEMBER(dmabcr_w);
	63
	64	protected:
	65	virtual void device_start();
	66	virtual void device_reset();
	67
	68	UINT8 dmawer, dmatcr;
	69	UINT16 dmabcr;
	70	};
	71
	72	class h8_dma_channel_device : public device_t {
	73	public:
	74	enum {
	75	NONE = -1,
	76	DREQ_LEVEL = -2,
	77	DREQ_EDGE = -3
	78	};
	79
	80	enum {
	81	MODE8_MEM_MEM,
	82	MODE8_DACK_MEM,
	83	MODE8_MEM_DACK,
	84	MODE16_MEM_MEM,
	85	MODE16_DACK_MEM,
	86	MODE16_MEM_DACK
	87	};
	88
	89	h8_dma_channel_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	90
	91	void set_info(const char *intc, int irq_base, int v0, int v1, int v2, int v3, int v4, int v5, int v6, int v7, int v8, int v9, int va, int vb, int vc, int vd, int ve, int vf);
	92
	93	DECLARE_READ16_MEMBER(marah_r);
	94	DECLARE_WRITE16_MEMBER(marah_w);
	95	DECLARE_READ16_MEMBER(maral_r);
	96	DECLARE_WRITE16_MEMBER(maral_w);
	97	DECLARE_READ16_MEMBER(ioara_r);
	98	DECLARE_WRITE16_MEMBER(ioara_w);
	99	DECLARE_READ16_MEMBER(etcra_r);
	100	DECLARE_WRITE16_MEMBER(etcra_w);
	101	DECLARE_READ16_MEMBER(marbh_r);
	102	DECLARE_WRITE16_MEMBER(marbh_w);
	103	DECLARE_READ16_MEMBER(marbl_r);
	104	DECLARE_WRITE16_MEMBER(marbl_w);
	105	DECLARE_READ16_MEMBER(ioarb_r);
	106	DECLARE_WRITE16_MEMBER(ioarb_w);
	107	DECLARE_READ16_MEMBER(etcrb_r);
	108	DECLARE_WRITE16_MEMBER(etcrb_w);
	109	DECLARE_READ8_MEMBER(dmacr_r);
	110	DECLARE_WRITE8_MEMBER(dmacr_w);
	111
	112	protected:
	113	virtual void device_start();
	114	virtual void device_reset();
	115	};
	116
	117	extern const device_type H8_DMA;
	118	extern const device_type H8_DMA_CHANNEL;
	119
	120	#endif

trunk/src/emu/cpu/h8/h8_sci.c
r243808	r243809
14	14	external_clock_period = attotime::never;
15	15	}
16	16
17		void h8_sci_device::set_info(const char *_intc_tag,int eri, int rxi, int txi, int tei)
	17	void h8_sci_device::set_info(const char *_intc_tag, int eri, int rxi, int txi, int tei)
18	18	{
19	19	intc_tag = _intc_tag;
20	20	eri_int = eri;

trunk/src/emu/cpu/h8/h8_watchdog.c
r0	r243809
	1	#include "emu.h"
	2	#include "h8_watchdog.h"
	3
	4	const device_type H8_WATCHDOG = &device_creator<h8_watchdog_device>;
	5
	6	const int h8_watchdog_device::div_bh[8] = { 1, 6, 7, 9, 11, 13, 15, 17 };
	7	const int h8_watchdog_device::div_s [8] = { 1, 5, 6, 7, 8, 9, 11, 12 };
	8
	9	h8_watchdog_device::h8_watchdog_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	10	device_t(mconfig, H8_WATCHDOG, "H8 watchdog", tag, owner, clock, "h8_watchdog", __FILE__),
	11	cpu(*this, DEVICE_SELF_OWNER)
	12	{
	13	}
	14
	15	void h8_watchdog_device::set_info(const char *_intc_tag, int _irq, int _type)
	16	{
	17	intc_tag = _intc_tag;
	18	irq = _irq;
	19	type = _type;
	20	}
	21
	22
	23	UINT64 h8_watchdog_device::internal_update(UINT64 current_time)
	24	{
	25	tcnt_update(current_time);
	26	if(tcsr & TCSR_TME) {
	27	int shift = (type == S ? div_s : div_bh)[tcsr & TCSR_CKS];
	28	UINT64 spos = tcnt_cycle_base >> shift;
	29	return (spos + 0x100 - tcnt) << shift;
	30
	31	} else
	32	return 0;
	33	}
	34
	35	void h8_watchdog_device::tcnt_update(UINT64 cur_time)
	36	{
	37	if(tcsr & TCSR_TME) {
	38	int shift = (type == S ? div_s : div_bh)[tcsr & TCSR_CKS];
	39	if(!cur_time)
	40	cur_time = cpu->total_cycles();
	41	UINT64 spos = tcnt_cycle_base >> shift;
	42	UINT64 epos = cur_time >> shift;
	43
	44	int next_tcnt = tcnt + int(epos - spos);
	45	tcnt = next_tcnt;
	46	tcnt_cycle_base = cur_time;
	47	// logerror("%s: %10lld tcnt %02x -> %03x shift=%d\n", tag(), cur_time, tcnt, next_tcnt, shift);
	48
	49	if(next_tcnt >= 0x100) {
	50	if(tcsr & TCSR_WT) {
	51	logerror("%s: watchdog triggered\n", tag());
	52	if(type == B && !(tcsr & TCSR_NMI))
	53	intc->internal_interrupt(3);
	54	else
	55	cpu->reset();
	56
	57	} else {
	58	if(!(tcsr & TCSR_OVF)) {
	59	tcsr \|= TCSR_OVF;
	60	intc->internal_interrupt(irq);
	61	}
	62	}
	63	}
	64	} else
	65	tcnt = 0;
	66
	67	}
	68
	69	READ16_MEMBER(h8_watchdog_device::wd_r)
	70	{
	71	tcnt_update();
	72
	73	logerror("%s: read\n", tag());
	74	return 0;
	75	}
	76
	77	WRITE16_MEMBER(h8_watchdog_device::wd_w)
	78	{
	79	if(mem_mask != 0xffff)
	80	return;
	81
	82	if((data & 0xff00) == 0xa500) {
	83	tcnt_update();
	84	tcsr = data & 0xff;
	85	tcsr \|= type == B ? 0x10 : 0x18;
	86	cpu->internal_update();
	87	}
	88
	89	if((data & 0xff00) == 0x5a00) {
	90	if(tcsr & TCSR_TME) {
	91	tcnt = data & 0xff;
	92	tcnt_cycle_base = cpu->total_cycles();
	93	// logerror("%s: %10lld tcnt = %02x\n", tag(), tcnt_cycle_base, tcnt);
	94	}
	95	cpu->internal_update();
	96	}
	97	}
	98
	99	READ16_MEMBER(h8_watchdog_device::rst_r)
	100	{
	101	logerror("%s: rst_r\n", tag());
	102	return 0;
	103	}
	104
	105	WRITE16_MEMBER(h8_watchdog_device::rst_w)
	106	{
	107	if((data & 0xff00) == 0xa500)
	108	logerror("%s: wowf_w %02x\n", tag(), data & 0xff);
	109	if((data & 0xff00) == 0x5a00)
	110	logerror("%s: rtse_w %02x\n", tag(), data & 0xff);
	111	}
	112
	113	void h8_watchdog_device::device_start()
	114	{
	115	intc = siblingdevice<h8_intc_device>(intc_tag);
	116	}
	117
	118	void h8_watchdog_device::device_reset()
	119	{
	120	tcnt = 0x00;
	121	tcnt_cycle_base = cpu->total_cycles();
	122	tcsr = type == B ? 0x10 : 0x18;
	123	rst = type == S ? 0x1f : 0x3f;
	124	}

trunk/src/emu/cpu/h8/h8_watchdog.h
r0	r243809
	1	/***************************************************************************
	2
	3	h8_watchdog.h
	4
	5	H8 watchdog/timer
	6
	7	****************************************************************************
	8
	9	Copyright Olivier Galibert
	10	All rights reserved.
	11
	12	Redistribution and use in source and binary forms, with or without
	13	modification, are permitted provided that the following conditions are
	14	met:
	15
	16	* Redistributions of source code must retain the above copyright
	17	notice, this list of conditions and the following disclaimer.
	18	* Redistributions in binary form must reproduce the above copyright
	19	notice, this list of conditions and the following disclaimer in
	20	the documentation and/or other materials provided with the
	21	distribution.
	22	* Neither the name 'MAME' nor the names of its contributors may be
	23	used to endorse or promote products derived from this software
	24	without specific prior written permission.
	25
	26	THIS SOFTWARE IS PROVIDED BY OLIVIER GALIBERT ''AS IS'' AND ANY EXPRESS OR
	27	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	28	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	29	DISCLAIMED. IN NO EVENT SHALL OLIVIER GALIBERT BE LIABLE FOR ANY DIRECT,
	30	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	31	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	32	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	33	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	34	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	35	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	36	POSSIBILITY OF SUCH DAMAGE.
	37
	38	***************************************************************************/
	39
	40	#ifndef __H8_WATCHDOG_H__
	41	#define __H8_WATCHDOG_H__
	42
	43	#include "h8.h"
	44	#include "h8_intc.h"
	45
	46	#define MCFG_H8_WATCHDOG_ADD( _tag, intc, irq, type ) \
	47	MCFG_DEVICE_ADD( _tag, H8_WATCHDOG, 0 ) \
	48	downcast<h8_watchdog_device *>(device)->set_info(intc, irq, type);
	49
	50	class h8_watchdog_device : public device_t {
	51	public:
	52	enum { B, H, S };
	53
	54	h8_watchdog_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	55
	56	void set_info(const char *intc, int irq, int type);
	57
	58	UINT64 internal_update(UINT64 current_time);
	59
	60	DECLARE_READ16_MEMBER(wd_r);
	61	DECLARE_WRITE16_MEMBER(wd_w);
	62	DECLARE_READ16_MEMBER(rst_r);
	63	DECLARE_WRITE16_MEMBER(rst_w);
	64
	65	protected:
	66	virtual void device_start();
	67	virtual void device_reset();
	68
	69	private:
	70	enum {
	71	TCSR_CKS = 0x07,
	72	TCSR_NMI = 0x08,
	73	TCSR_TME = 0x20,
	74	TCSR_WT = 0x40,
	75	TCSR_OVF = 0x80,
	76
	77	RST_RSTS = 0x20,
	78	RST_RSTE = 0x40,
	79	RST_RSTEO = 0x40,
	80	RST_WRST = 0x80
	81	};
	82
	83	static const int div_bh[8];
	84	static const int div_s[8];
	85
	86	required_device<h8_device> cpu;
	87	h8_intc_device *intc;
	88	const char *intc_tag;
	89	int irq;
	90	int type;
	91	UINT8 tcnt, tcsr, rst;
	92	UINT64 tcnt_cycle_base;
	93
	94	void tcnt_update(UINT64 current_time = 0);
	95	};
	96
	97	extern const device_type H8_WATCHDOG;
	98
	99	#endif

trunk/src/emu/cpu/h8/h8s2245.c
r243808	r243809
31	31	timer16_2(*this, "timer16:2"),
32	32	sci0(*this, "sci0"),
33	33	sci1(*this, "sci1"),
34		sci2(*this, "sci2")
	34	sci2(*this, "sci2"),
	35	watchdog(*this, "watchdog")
35	36	{
36	37	}
37	38
r243808	r243809
59	60	timer16_2(*this, "timer16:2"),
60	61	sci0(*this, "sci0"),
61	62	sci1(*this, "sci1"),
62		sci2(*this, "sci2")
	63	sci2(*this, "sci2"),
	64	watchdog(*this, "watchdog")
63	65	{
64	66	ram_start = 0xffec00;
65	67	}
r243808	r243809
131	133	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
132	134	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
133	135	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
	136	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
134	137	MACHINE_CONFIG_END
135	138
136	139	DEVICE_ADDRESS_MAP_START(map, 16, h8s2245_device)
r243808	r243809
217	220	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
218	221	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
219	222	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
	223	AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
	224	AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
220	225	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
221	226	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
222	227	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
r243808	r243809
240	245	AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
241	246	AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
242	247	AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
243
244	248	ADDRESS_MAP_END
245	249
246	250	machine_config_constructor h8s2245_device::device_mconfig_additions() const
r243808	r243809
317	321	add_event(event_time, timer16_0->internal_update(current_time));
318	322	add_event(event_time, timer16_1->internal_update(current_time));
319	323	add_event(event_time, timer16_2->internal_update(current_time));
	324	add_event(event_time, watchdog->internal_update(current_time));
320	325
321	326	recompute_bcount(event_time);
322	327	}

trunk/src/emu/cpu/h8/h8s2245.h
r243808	r243809
50	50	#define __H8S2245_H__
51	51
52	52	#include "h8s2000.h"
	53	#include "h8_intc.h"
53	54	#include "h8_adc.h"
54	55	#include "h8_port.h"
55		#include "h8_intc.h"
56		#include "h8_sci.h"
57	56	#include "h8_timer8.h"
58	57	#include "h8_timer16.h"
	58	#include "h8_sci.h"
	59	#include "h8_watchdog.h"
59	60
60	61	class h8s2245_device : public h8s2000_device {
61	62	public:
r243808	r243809
89	90	required_device<h8_sci_device> sci0;
90	91	required_device<h8_sci_device> sci1;
91	92	required_device<h8_sci_device> sci2;
	93	required_device<h8_watchdog_device> watchdog;
92	94
93	95	UINT32 ram_start;
94	96	UINT8 syscr;

trunk/src/emu/cpu/h8/h8s2320.c
r243808	r243809
16	16	h8s2000_device(mconfig, type, name, tag, owner, clock, shortname, source, address_map_delegate(FUNC(h8s2320_device::map), this)),
17	17	intc(*this, "intc"),
18	18	adc(*this, "adc"),
	19	dma(*this, "dma"),
	20	dma0(*this, "dma:0"),
	21	dma1(*this, "dma:1"),
19	22	port1(*this, "port1"),
20	23	port2(*this, "port2"),
21	24	port3(*this, "port3"),
r243808	r243809
40	43	timer16_5(*this, "timer16:5"),
41	44	sci0(*this, "sci0"),
42	45	sci1(*this, "sci1"),
43		sci2(*this, "sci2")
	46	sci2(*this, "sci2"),
	47	watchdog(*this, "watchdog")
44	48	{
45	49	}
46	50
r243808	r243809
48	52	h8s2000_device(mconfig, H8S2320, "H8S/2320", tag, owner, clock, "h8s2320", __FILE__, address_map_delegate(FUNC(h8s2320_device::map), this)),
49	53	intc(*this, "intc"),
50	54	adc(*this, "adc"),
	55	dma(*this, "dma"),
	56	dma0(*this, "dma:0"),
	57	dma1(*this, "dma:1"),
51	58	port1(*this, "port1"),
52	59	port2(*this, "port2"),
53	60	port3(*this, "port3"),
r243808	r243809
72	79	timer16_5(*this, "timer16:5"),
73	80	sci0(*this, "sci0"),
74	81	sci1(*this, "sci1"),
75		sci2(*this, "sci2")
	82	sci2(*this, "sci2"),
	83	watchdog(*this, "watchdog")
76	84	{
77	85	ram_start = 0xffec00;
78	86	}
r243808	r243809
128	136	static MACHINE_CONFIG_FRAGMENT(h8s2320)
129	137	MCFG_H8S_INTC_ADD("intc")
130	138	MCFG_H8_ADC_2320_ADD("adc", "intc", 28)
	139	MCFG_H8_DMA_ADD("dma")
	140	MCFG_H8_DMA_CHANNEL_ADD("dma:0", "intc", 72, h8_dma_channel_device::NONE, 28, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 82, 81, 86, 85, 32, 40, 44, 48, 56, 60, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
	141	MCFG_H8_DMA_CHANNEL_ADD("dma:1", "intc", 74, h8_dma_channel_device::NONE, 28, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 82, 81, 86, 85, 32, 40, 44, 48, 56, 60, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
131	142	MCFG_H8_PORT_ADD("port1", h8_device::PORT_1, 0x00, 0x00)
132	143	MCFG_H8_PORT_ADD("port2", h8_device::PORT_2, 0x00, 0x00)
133	144	MCFG_H8_PORT_ADD("port3", h8_device::PORT_3, 0xc0, 0xc0)
r243808	r243809
203	214	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
204	215	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
205	216	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
	217	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
206	218	MACHINE_CONFIG_END
207	219
208	220	DEVICE_ADDRESS_MAP_START(map, 16, h8s2320_device)
209	221	AM_RANGE(ram_start, 0xfffbff) AM_RAM
210	222
211		AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
212		AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
213		AM_RANGE(0xfffe82, 0xfffe83) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
214		AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
215		AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
216		AM_RANGE(0xfffe86, 0xfffe87) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tcnt_r, tcnt_w )
217		AM_RANGE(0xfffe88, 0xfffe8f) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tgr_r, tgr_w )
218		AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
219		AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
220		AM_RANGE(0xfffe92, 0xfffe93) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
221		AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
222		AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
223		AM_RANGE(0xfffe96, 0xfffe97) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tcnt_r, tcnt_w )
224		AM_RANGE(0xfffe98, 0xfffe9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
225		AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
226		AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
227		AM_RANGE(0xfffea2, 0xfffea3) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
228		AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
229		AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
230		AM_RANGE(0xfffea6, 0xfffea7) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tcnt_r, tcnt_w )
231		AM_RANGE(0xfffea8, 0xfffeab) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tgr_r, tgr_w )
232		AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port1", h8_port_device, ddr_w, 0xff00)
233		AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port2", h8_port_device, ddr_w, 0x00ff)
234		AM_RANGE(0xfffeb2, 0xfffeb3) AM_DEVWRITE8( "port3", h8_port_device, ddr_w, 0xff00)
235		AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port5", h8_port_device, ddr_w, 0xff00)
236		AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port6", h8_port_device, ddr_w, 0x00ff)
237		AM_RANGE(0xfffeb8, 0xfffeb9) AM_DEVWRITE8( "porta", h8_port_device, ddr_w, 0x00ff)
238		AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portb", h8_port_device, ddr_w, 0xff00)
239		AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portc", h8_port_device, ddr_w, 0x00ff)
240		AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "portd", h8_port_device, ddr_w, 0xff00)
241		AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "porte", h8_port_device, ddr_w, 0x00ff)
242		AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portf", h8_port_device, ddr_w, 0xff00)
243		AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portg", h8_port_device, ddr_w, 0x00ff)
244		AM_RANGE(0xfffec0, 0xfffec1) AM_DEVREADWRITE8("intc", h8s_intc_device, icr_r, icr_w, 0xffff)
245		AM_RANGE(0xfffec2, 0xfffec3) AM_DEVREADWRITE8("intc", h8s_intc_device, icrc_r, icrc_w, 0xff00)
246		AM_RANGE(0xfffec4, 0xfffecd) AM_DEVREADWRITE8("intc", h8s_intc_device, ipr_r, ipr_w, 0xffff)
247		AM_RANGE(0xfffece, 0xfffecf) AM_DEVREADWRITE8("intc", h8s_intc_device, iprk_r, iprk_w, 0xff00)
248		AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrh_r, iscrh_w, 0xff00)
249		AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrl_r, iscrl_w, 0x00ff)
250		AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, ier_r, ier_w, 0xff00)
251		AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, isr_r, isr_w, 0x00ff)
252		AM_RANGE(0xffff38, 0xffff39) AM_READWRITE8( syscr_r, syscr_w, 0x00ff)
	223	AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	224	AM_RANGE(0xfffe80, 0xfffe81) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	225	AM_RANGE(0xfffe82, 0xfffe83) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
	226	AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	227	AM_RANGE(0xfffe84, 0xfffe85) AM_DEVREADWRITE8("timer16:3", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	228	AM_RANGE(0xfffe86, 0xfffe87) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tcnt_r, tcnt_w )
	229	AM_RANGE(0xfffe88, 0xfffe8f) AM_DEVREADWRITE( "timer16:3", h8_timer16_channel_device, tgr_r, tgr_w )
	230	AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	231	AM_RANGE(0xfffe90, 0xfffe91) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	232	AM_RANGE(0xfffe92, 0xfffe93) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
	233	AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	234	AM_RANGE(0xfffe94, 0xfffe95) AM_DEVREADWRITE8("timer16:4", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	235	AM_RANGE(0xfffe96, 0xfffe97) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tcnt_r, tcnt_w )
	236	AM_RANGE(0xfffe98, 0xfffe9b) AM_DEVREADWRITE( "timer16:4", h8_timer16_channel_device, tgr_r, tgr_w )
	237	AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	238	AM_RANGE(0xfffea0, 0xfffea1) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	239	AM_RANGE(0xfffea2, 0xfffea3) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
	240	AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	241	AM_RANGE(0xfffea4, 0xfffea5) AM_DEVREADWRITE8("timer16:5", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	242	AM_RANGE(0xfffea6, 0xfffea7) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tcnt_r, tcnt_w )
	243	AM_RANGE(0xfffea8, 0xfffeab) AM_DEVREADWRITE( "timer16:5", h8_timer16_channel_device, tgr_r, tgr_w )
	244	AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port1", h8_port_device, ddr_w, 0xff00)
	245	AM_RANGE(0xfffeb0, 0xfffeb1) AM_DEVWRITE8( "port2", h8_port_device, ddr_w, 0x00ff)
	246	AM_RANGE(0xfffeb2, 0xfffeb3) AM_DEVWRITE8( "port3", h8_port_device, ddr_w, 0xff00)
	247	AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port5", h8_port_device, ddr_w, 0xff00)
	248	AM_RANGE(0xfffeb4, 0xfffeb5) AM_DEVWRITE8( "port6", h8_port_device, ddr_w, 0x00ff)
	249	AM_RANGE(0xfffeb8, 0xfffeb9) AM_DEVWRITE8( "porta", h8_port_device, ddr_w, 0x00ff)
	250	AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portb", h8_port_device, ddr_w, 0xff00)
	251	AM_RANGE(0xfffeba, 0xfffebb) AM_DEVWRITE8( "portc", h8_port_device, ddr_w, 0x00ff)
	252	AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "portd", h8_port_device, ddr_w, 0xff00)
	253	AM_RANGE(0xfffebc, 0xfffebd) AM_DEVWRITE8( "porte", h8_port_device, ddr_w, 0x00ff)
	254	AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portf", h8_port_device, ddr_w, 0xff00)
	255	AM_RANGE(0xfffebe, 0xfffebf) AM_DEVWRITE8( "portg", h8_port_device, ddr_w, 0x00ff)
	256	AM_RANGE(0xfffec0, 0xfffec1) AM_DEVREADWRITE8("intc", h8s_intc_device, icr_r, icr_w, 0xffff)
	257	AM_RANGE(0xfffec2, 0xfffec3) AM_DEVREADWRITE8("intc", h8s_intc_device, icrc_r, icrc_w, 0xff00)
	258	AM_RANGE(0xfffec4, 0xfffecd) AM_DEVREADWRITE8("intc", h8s_intc_device, ipr_r, ipr_w, 0xffff)
	259	AM_RANGE(0xfffece, 0xfffecf) AM_DEVREADWRITE8("intc", h8s_intc_device, iprk_r, iprk_w, 0xff00)
253	260
254		AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port1", h8_port_device, port_r, 0xff00)
255		AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port2", h8_port_device, port_r, 0x00ff)
256		AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port3", h8_port_device, port_r, 0xff00)
257		AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port4", h8_port_device, port_r, 0x00ff)
258		AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port5", h8_port_device, port_r, 0xff00)
259		AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port6", h8_port_device, port_r, 0x00ff)
260		AM_RANGE(0xffff58, 0xffff59) AM_DEVREAD8( "porta", h8_port_device, port_r, 0x00ff)
261		AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portb", h8_port_device, port_r, 0xff00)
262		AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portc", h8_port_device, port_r, 0x00ff)
263		AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "portd", h8_port_device, port_r, 0xff00)
264		AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "porte", h8_port_device, port_r, 0x00ff)
265		AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portf", h8_port_device, port_r, 0xff00)
266		AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portg", h8_port_device, port_r, 0x00ff)
267		AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port1", h8_port_device, dr_r, dr_w, 0xff00)
268		AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port2", h8_port_device, dr_r, dr_w, 0x00ff)
269		AM_RANGE(0xffff62, 0xffff63) AM_DEVREADWRITE8("port3", h8_port_device, dr_r, dr_w, 0xff00)
270		AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port5", h8_port_device, dr_r, dr_w, 0xff00)
271		AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port6", h8_port_device, dr_r, dr_w, 0x00ff)
272		AM_RANGE(0xffff68, 0xffff69) AM_DEVREADWRITE8("porta", h8_port_device, dr_r, dr_w, 0x00ff)
273		AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portb", h8_port_device, dr_r, dr_w, 0xff00)
274		AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portc", h8_port_device, dr_r, dr_w, 0x00ff)
275		AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("portd", h8_port_device, dr_r, dr_w, 0xff00)
276		AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("porte", h8_port_device, dr_r, dr_w, 0x00ff)
277		AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portf", h8_port_device, dr_r, dr_w, 0xff00)
278		AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portg", h8_port_device, dr_r, dr_w, 0x00ff)
279		AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("porta", h8_port_device, pcr_r, pcr_w, 0xff00)
280		AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("portb", h8_port_device, pcr_r, pcr_w, 0x00ff)
281		AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portc", h8_port_device, pcr_r, pcr_w, 0xff00)
282		AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portd", h8_port_device, pcr_r, pcr_w, 0x00ff)
283		AM_RANGE(0xffff74, 0xffff75) AM_DEVREADWRITE8("porte", h8_port_device, pcr_r, pcr_w, 0xff00)
284		AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("port3", h8_port_device, odr_r, odr_w, 0xff00)
285		AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("porta", h8_port_device, odr_r, odr_w, 0x00ff)
286		AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
287		AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
288		AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
289		AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, tdr_r, tdr_w, 0x00ff)
290		AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREADWRITE8("sci0", h8_sci_device, ssr_r, ssr_w, 0xff00)
291		AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREAD8( "sci0", h8_sci_device, rdr_r, 0x00ff)
292		AM_RANGE(0xffff7e, 0xffff7f) AM_DEVREADWRITE8("sci0", h8_sci_device, scmr_r, scmr_w, 0xff00)
293		AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, smr_r, smr_w, 0xff00)
294		AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, brr_r, brr_w, 0x00ff)
295		AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, scr_r, scr_w, 0xff00)
296		AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, tdr_r, tdr_w, 0x00ff)
297		AM_RANGE(0xffff84, 0xffff85) AM_DEVREADWRITE8("sci1", h8_sci_device, ssr_r, ssr_w, 0xff00)
298		AM_RANGE(0xffff84, 0xffff85) AM_DEVREAD8( "sci1", h8_sci_device, rdr_r, 0x00ff)
299		AM_RANGE(0xffff86, 0xffff87) AM_DEVREADWRITE8("sci1", h8_sci_device, scmr_r, scmr_w, 0xff00)
300		AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, smr_r, smr_w, 0xff00)
301		AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, brr_r, brr_w, 0x00ff)
302		AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, scr_r, scr_w, 0xff00)
303		AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, tdr_r, tdr_w, 0x00ff)
304		AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE8("sci2", h8_sci_device, ssr_r, ssr_w, 0xff00)
305		AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREAD8( "sci2", h8_sci_device, rdr_r, 0x00ff)
306		AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE8("sci2", h8_sci_device, scmr_r, scmr_w, 0xff00)
307		AM_RANGE(0xffff90, 0xffff97) AM_DEVREAD8( "adc", h8_adc_device, addr8_r, 0xffff)
308		AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcsr_r, adcsr_w, 0xff00)
309		AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcr_r, adcr_w, 0x00ff)
	261	AM_RANGE(0xfffee0, 0xfffee1) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marah_r, marah_w )
	262	AM_RANGE(0xfffee2, 0xfffee3) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, maral_r, maral_w )
	263	AM_RANGE(0xfffee4, 0xfffee5) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, ioara_r, ioara_w )
	264	AM_RANGE(0xfffee6, 0xfffee7) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, etcra_r, etcra_w )
	265	AM_RANGE(0xfffee8, 0xfffee9) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marbh_r, marbh_w )
	266	AM_RANGE(0xfffeea, 0xfffeeb) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, marbl_r, marbl_w )
	267	AM_RANGE(0xfffeec, 0xfffeed) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, ioarb_r, ioarb_w )
	268	AM_RANGE(0xfffeee, 0xfffeef) AM_DEVREADWRITE( "dma:0", h8_dma_channel_device, etcrb_r, etcrb_w )
	269	AM_RANGE(0xfffef0, 0xfffef1) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marah_r, marah_w )
	270	AM_RANGE(0xfffef2, 0xfffef3) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, maral_r, maral_w )
	271	AM_RANGE(0xfffef4, 0xfffef5) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, ioara_r, ioara_w )
	272	AM_RANGE(0xfffef6, 0xfffef7) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, etcra_r, etcra_w )
	273	AM_RANGE(0xfffef8, 0xfffef9) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marbh_r, marbh_w )
	274	AM_RANGE(0xfffefa, 0xfffefb) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, marbl_r, marbl_w )
	275	AM_RANGE(0xfffefc, 0xfffefd) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, ioarb_r, ioarb_w )
	276	AM_RANGE(0xfffefe, 0xfffeff) AM_DEVREADWRITE( "dma:1", h8_dma_channel_device, etcrb_r, etcrb_w )
	277	AM_RANGE(0xffff00, 0xffff01) AM_DEVREADWRITE8("dma", h8_dma_device, dmawer_r, dmawer_w, 0xff00)
	278	AM_RANGE(0xffff00, 0xffff01) AM_DEVREADWRITE8("dma", h8_dma_device, dmatcr_r, dmatcr_w, 0x00ff)
	279	AM_RANGE(0xffff02, 0xffff03) AM_DEVREADWRITE8("dma:0", h8_dma_channel_device, dmacr_r, dmacr_w, 0xffff)
	280	AM_RANGE(0xffff04, 0xffff05) AM_DEVREADWRITE8("dma:1", h8_dma_channel_device, dmacr_r, dmacr_w, 0xffff)
	281	AM_RANGE(0xffff06, 0xffff07) AM_DEVREADWRITE( "dma", h8_dma_device, dmabcr_r, dmabcr_w )
	282	AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrh_r, iscrh_w, 0xff00)
	283	AM_RANGE(0xffff2c, 0xffff2d) AM_DEVREADWRITE8("intc", h8s_intc_device, iscrl_r, iscrl_w, 0x00ff)
	284	AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, ier_r, ier_w, 0xff00)
	285	AM_RANGE(0xffff2e, 0xffff2f) AM_DEVREADWRITE8("intc", h8s_intc_device, isr_r, isr_w, 0x00ff)
	286	AM_RANGE(0xffff38, 0xffff39) AM_READWRITE8( syscr_r, syscr_w, 0x00ff)
310	287
311		AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
312		AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
313		AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
314		AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcsr_r, tcsr_w, 0x00ff)
315		AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcor_r, tcor_w, 0xff00)
316		AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
317		AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
318		AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
	288	AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port1", h8_port_device, port_r, 0xff00)
	289	AM_RANGE(0xffff50, 0xffff51) AM_DEVREAD8( "port2", h8_port_device, port_r, 0x00ff)
	290	AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port3", h8_port_device, port_r, 0xff00)
	291	AM_RANGE(0xffff52, 0xffff53) AM_DEVREAD8( "port4", h8_port_device, port_r, 0x00ff)
	292	AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port5", h8_port_device, port_r, 0xff00)
	293	AM_RANGE(0xffff54, 0xffff55) AM_DEVREAD8( "port6", h8_port_device, port_r, 0x00ff)
	294	AM_RANGE(0xffff58, 0xffff59) AM_DEVREAD8( "porta", h8_port_device, port_r, 0x00ff)
	295	AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portb", h8_port_device, port_r, 0xff00)
	296	AM_RANGE(0xffff5a, 0xffff5b) AM_DEVREAD8( "portc", h8_port_device, port_r, 0x00ff)
	297	AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "portd", h8_port_device, port_r, 0xff00)
	298	AM_RANGE(0xffff5c, 0xffff5d) AM_DEVREAD8( "porte", h8_port_device, port_r, 0x00ff)
	299	AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portf", h8_port_device, port_r, 0xff00)
	300	AM_RANGE(0xffff5e, 0xffff5f) AM_DEVREAD8( "portg", h8_port_device, port_r, 0x00ff)
	301	AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port1", h8_port_device, dr_r, dr_w, 0xff00)
	302	AM_RANGE(0xffff60, 0xffff61) AM_DEVREADWRITE8("port2", h8_port_device, dr_r, dr_w, 0x00ff)
	303	AM_RANGE(0xffff62, 0xffff63) AM_DEVREADWRITE8("port3", h8_port_device, dr_r, dr_w, 0xff00)
	304	AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port5", h8_port_device, dr_r, dr_w, 0xff00)
	305	AM_RANGE(0xffff64, 0xffff65) AM_DEVREADWRITE8("port6", h8_port_device, dr_r, dr_w, 0x00ff)
	306	AM_RANGE(0xffff68, 0xffff69) AM_DEVREADWRITE8("porta", h8_port_device, dr_r, dr_w, 0x00ff)
	307	AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portb", h8_port_device, dr_r, dr_w, 0xff00)
	308	AM_RANGE(0xffff6a, 0xffff6b) AM_DEVREADWRITE8("portc", h8_port_device, dr_r, dr_w, 0x00ff)
	309	AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("portd", h8_port_device, dr_r, dr_w, 0xff00)
	310	AM_RANGE(0xffff6c, 0xffff6d) AM_DEVREADWRITE8("porte", h8_port_device, dr_r, dr_w, 0x00ff)
	311	AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portf", h8_port_device, dr_r, dr_w, 0xff00)
	312	AM_RANGE(0xffff6e, 0xffff6f) AM_DEVREADWRITE8("portg", h8_port_device, dr_r, dr_w, 0x00ff)
	313	AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("porta", h8_port_device, pcr_r, pcr_w, 0xff00)
	314	AM_RANGE(0xffff70, 0xffff71) AM_DEVREADWRITE8("portb", h8_port_device, pcr_r, pcr_w, 0x00ff)
	315	AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portc", h8_port_device, pcr_r, pcr_w, 0xff00)
	316	AM_RANGE(0xffff72, 0xffff73) AM_DEVREADWRITE8("portd", h8_port_device, pcr_r, pcr_w, 0x00ff)
	317	AM_RANGE(0xffff74, 0xffff75) AM_DEVREADWRITE8("porte", h8_port_device, pcr_r, pcr_w, 0xff00)
	318	AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("port3", h8_port_device, odr_r, odr_w, 0xff00)
	319	AM_RANGE(0xffff76, 0xffff77) AM_DEVREADWRITE8("porta", h8_port_device, odr_r, odr_w, 0x00ff)
	320	AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, smr_r, smr_w, 0xff00)
	321	AM_RANGE(0xffff78, 0xffff79) AM_DEVREADWRITE8("sci0", h8_sci_device, brr_r, brr_w, 0x00ff)
	322	AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, scr_r, scr_w, 0xff00)
	323	AM_RANGE(0xffff7a, 0xffff7b) AM_DEVREADWRITE8("sci0", h8_sci_device, tdr_r, tdr_w, 0x00ff)
	324	AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREADWRITE8("sci0", h8_sci_device, ssr_r, ssr_w, 0xff00)
	325	AM_RANGE(0xffff7c, 0xffff7d) AM_DEVREAD8( "sci0", h8_sci_device, rdr_r, 0x00ff)
	326	AM_RANGE(0xffff7e, 0xffff7f) AM_DEVREADWRITE8("sci0", h8_sci_device, scmr_r, scmr_w, 0xff00)
	327	AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, smr_r, smr_w, 0xff00)
	328	AM_RANGE(0xffff80, 0xffff81) AM_DEVREADWRITE8("sci1", h8_sci_device, brr_r, brr_w, 0x00ff)
	329	AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, scr_r, scr_w, 0xff00)
	330	AM_RANGE(0xffff82, 0xffff83) AM_DEVREADWRITE8("sci1", h8_sci_device, tdr_r, tdr_w, 0x00ff)
	331	AM_RANGE(0xffff84, 0xffff85) AM_DEVREADWRITE8("sci1", h8_sci_device, ssr_r, ssr_w, 0xff00)
	332	AM_RANGE(0xffff84, 0xffff85) AM_DEVREAD8( "sci1", h8_sci_device, rdr_r, 0x00ff)
	333	AM_RANGE(0xffff86, 0xffff87) AM_DEVREADWRITE8("sci1", h8_sci_device, scmr_r, scmr_w, 0xff00)
	334	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, smr_r, smr_w, 0xff00)
	335	AM_RANGE(0xffff88, 0xffff89) AM_DEVREADWRITE8("sci2", h8_sci_device, brr_r, brr_w, 0x00ff)
	336	AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, scr_r, scr_w, 0xff00)
	337	AM_RANGE(0xffff8a, 0xffff8b) AM_DEVREADWRITE8("sci2", h8_sci_device, tdr_r, tdr_w, 0x00ff)
	338	AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREADWRITE8("sci2", h8_sci_device, ssr_r, ssr_w, 0xff00)
	339	AM_RANGE(0xffff8c, 0xffff8d) AM_DEVREAD8( "sci2", h8_sci_device, rdr_r, 0x00ff)
	340	AM_RANGE(0xffff8e, 0xffff8f) AM_DEVREADWRITE8("sci2", h8_sci_device, scmr_r, scmr_w, 0xff00)
	341	AM_RANGE(0xffff90, 0xffff97) AM_DEVREAD8( "adc", h8_adc_device, addr8_r, 0xffff)
	342	AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcsr_r, adcsr_w, 0xff00)
	343	AM_RANGE(0xffff98, 0xffff99) AM_DEVREADWRITE8("adc", h8_adc_device, adcr_r, adcr_w, 0x00ff)
319	344
320		AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
321		AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
	345	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcr_r, tcr_w, 0xff00)
	346	AM_RANGE(0xffffb0, 0xffffb1) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcr_r, tcr_w, 0x00ff)
	347	AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcsr_r, tcsr_w, 0xff00)
	348	AM_RANGE(0xffffb2, 0xffffb3) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcsr_r, tcsr_w, 0x00ff)
	349	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcor_r, tcor_w, 0xff00)
	350	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
	351	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
	352	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
	353	AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
	354	AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
	355	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
	356	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
322	357
323		AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
324		AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
325		AM_RANGE(0xffffd2, 0xffffd3) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
326		AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
327		AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
328		AM_RANGE(0xffffd6, 0xffffd7) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
329		AM_RANGE(0xffffd8, 0xffffdf) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tgr_r, tgr_w )
330		AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
331		AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
332		AM_RANGE(0xffffe2, 0xffffe3) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
333		AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
334		AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
335		AM_RANGE(0xffffe6, 0xffffe7) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tcnt_r, tcnt_w )
336		AM_RANGE(0xffffe8, 0xffffeb) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tgr_r, tgr_w )
337		AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
338		AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
339		AM_RANGE(0xfffff2, 0xfffff3) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
340		AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
341		AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
342		AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
343		AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
	358	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	359	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	360	AM_RANGE(0xffffd2, 0xffffd3) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tior_r, tior_w, 0xffff)
	361	AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	362	AM_RANGE(0xffffd4, 0xffffd5) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	363	AM_RANGE(0xffffd6, 0xffffd7) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tcnt_r, tcnt_w )
	364	AM_RANGE(0xffffd8, 0xffffdf) AM_DEVREADWRITE( "timer16:0", h8_timer16_channel_device, tgr_r, tgr_w )
	365	AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	366	AM_RANGE(0xffffe0, 0xffffe1) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	367	AM_RANGE(0xffffe2, 0xffffe3) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
	368	AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	369	AM_RANGE(0xffffe4, 0xffffe5) AM_DEVREADWRITE8("timer16:1", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	370	AM_RANGE(0xffffe6, 0xffffe7) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tcnt_r, tcnt_w )
	371	AM_RANGE(0xffffe8, 0xffffeb) AM_DEVREADWRITE( "timer16:1", h8_timer16_channel_device, tgr_r, tgr_w )
	372	AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
	373	AM_RANGE(0xfffff0, 0xfffff1) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tmdr_r, tmdr_w, 0x00ff)
	374	AM_RANGE(0xfffff2, 0xfffff3) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tior_r, tior_w, 0xff00)
	375	AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tier_r, tier_w, 0xff00)
	376	AM_RANGE(0xfffff4, 0xfffff5) AM_DEVREADWRITE8("timer16:2", h8_timer16_channel_device, tsr_r, tsr_w, 0x00ff)
	377	AM_RANGE(0xfffff6, 0xfffff7) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tcnt_r, tcnt_w )
	378	AM_RANGE(0xfffff8, 0xfffffb) AM_DEVREADWRITE( "timer16:2", h8_timer16_channel_device, tgr_r, tgr_w )
344	379	ADDRESS_MAP_END
345	380
346	381	machine_config_constructor h8s2320_device::device_mconfig_additions() const
r243808	r243809
425	460	add_event(event_time, timer16_3->internal_update(current_time));
426	461	add_event(event_time, timer16_4->internal_update(current_time));
427	462	add_event(event_time, timer16_5->internal_update(current_time));
	463	add_event(event_time, watchdog->internal_update(current_time));
428	464
429	465	recompute_bcount(event_time);
430	466	}

trunk/src/emu/cpu/h8/h8s2320.h
r243808	r243809
55	55	#define __H8S2320_H__
56	56
57	57	#include "h8s2000.h"
	58	#include "h8_intc.h"
58	59	#include "h8_adc.h"
	60	#include "h8_dma.h"
59	61	#include "h8_port.h"
60		#include "h8_intc.h"
61		#include "h8_sci.h"
62	62	#include "h8_timer8.h"
63	63	#include "h8_timer16.h"
	64	#include "h8_sci.h"
	65	#include "h8_watchdog.h"
64	66
65	67	class h8s2320_device : public h8s2000_device {
66	68	public:
r243808	r243809
73	75	protected:
74	76	required_device<h8s_intc_device> intc;
75	77	required_device<h8_adc_device> adc;
	78	optional_device<h8_dma_device> dma;
	79	optional_device<h8_dma_channel_device> dma0;
	80	optional_device<h8_dma_channel_device> dma1;
76	81	required_device<h8_port_device> port1;
77	82	required_device<h8_port_device> port2;
78	83	required_device<h8_port_device> port3;
r243808	r243809
98	103	required_device<h8_sci_device> sci0;
99	104	required_device<h8_sci_device> sci1;
100	105	required_device<h8_sci_device> sci2;
	106	required_device<h8_watchdog_device> watchdog;
101	107
102	108	UINT32 ram_start;
103	109	UINT8 syscr;

trunk/src/emu/cpu/h8/h8s2357.c
r243808	r243809
36	36	timer16_5(*this, "timer16:5"),
37	37	sci0(*this, "sci0"),
38	38	sci1(*this, "sci1"),
39		sci2(*this, "sci2")
	39	sci2(*this, "sci2"),
	40	watchdog(*this, "watchdog")
40	41	{
41	42	}
42	43
r243808	r243809
68	69	timer16_5(*this, "timer16:5"),
69	70	sci0(*this, "sci0"),
70	71	sci1(*this, "sci1"),
71		sci2(*this, "sci2")
	72	sci2(*this, "sci2"),
	73	watchdog(*this, "watchdog")
72	74	{
73	75	ram_start = 0xffdc00;
74	76	}
r243808	r243809
181	183	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
182	184	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
183	185	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
	186	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
184	187	MACHINE_CONFIG_END
185	188
186	189	DEVICE_ADDRESS_MAP_START(map, 16, h8s2357_device)
r243808	r243809
290	293	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
291	294	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
292	295	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
	296	AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
	297	AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
293	298	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
294	299	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
295	300	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
r243808	r243809
397	402	add_event(event_time, timer16_3->internal_update(current_time));
398	403	add_event(event_time, timer16_4->internal_update(current_time));
399	404	add_event(event_time, timer16_5->internal_update(current_time));
	405	add_event(event_time, watchdog->internal_update(current_time));
400	406
401	407	recompute_bcount(event_time);
402	408	}

trunk/src/emu/cpu/h8/h8s2357.h
r243808	r243809
52	52	#define __H8S2357_H__
53	53
54	54	#include "h8s2000.h"
	55	#include "h8_intc.h"
55	56	#include "h8_adc.h"
56	57	#include "h8_port.h"
57		#include "h8_intc.h"
58		#include "h8_sci.h"
59	58	#include "h8_timer8.h"
60	59	#include "h8_timer16.h"
	60	#include "h8_sci.h"
	61	#include "h8_watchdog.h"
61	62
62	63	class h8s2357_device : public h8s2000_device {
63	64	public:
r243808	r243809
95	96	required_device<h8_sci_device> sci0;
96	97	required_device<h8_sci_device> sci1;
97	98	required_device<h8_sci_device> sci2;
	99	required_device<h8_watchdog_device> watchdog;
98	100
99	101	UINT32 ram_start;
100	102	unsigned char syscr;

trunk/src/emu/cpu/h8/h8s2655.c
r243808	r243809
32	32	timer16_5(*this, "timer16:5"),
33	33	sci0(*this, "sci0"),
34	34	sci1(*this, "sci1"),
35		sci2(*this, "sci2")
	35	sci2(*this, "sci2"),
	36	watchdog(*this, "watchdog")
36	37	{
37	38	has_trace = true;
38	39	}
r243808	r243809
65	66	timer16_5(*this, "timer16:5"),
66	67	sci0(*this, "sci0"),
67	68	sci1(*this, "sci1"),
68		sci2(*this, "sci2")
	69	sci2(*this, "sci2"),
	70	watchdog(*this, "watchdog")
69	71
70	72	{
71	73	has_trace = true;
r243808	r243809
154	156	MCFG_H8_SCI_ADD("sci0", "intc", 80, 81, 82, 83)
155	157	MCFG_H8_SCI_ADD("sci1", "intc", 84, 85, 86, 87)
156	158	MCFG_H8_SCI_ADD("sci2", "intc", 88, 89, 90, 91)
	159	MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 25, h8_watchdog_device::S)
157	160	MACHINE_CONFIG_END
158	161
159	162	DEVICE_ADDRESS_MAP_START(map, 16, h8s2655_device)
r243808	r243809
264	267	AM_RANGE(0xffffb4, 0xffffb7) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcor_r, tcor_w, 0x00ff)
265	268	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_0", h8_timer8_channel_device, tcnt_r, tcnt_w, 0xff00)
266	269	AM_RANGE(0xffffb8, 0xffffb9) AM_DEVREADWRITE8("timer8_1", h8_timer8_channel_device, tcnt_r, tcnt_w, 0x00ff)
	270	AM_RANGE(0xffffbc, 0xffffbd) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, wd_r, wd_w )
	271	AM_RANGE(0xffffbe, 0xffffbf) AM_DEVREADWRITE( "watchdog", h8_watchdog_device, rst_r, rst_w )
267	272	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tstr_r, tstr_w, 0xff00)
268	273	AM_RANGE(0xffffc0, 0xffffc1) AM_DEVREADWRITE8("timer16", h8_timer16_device, tsyr_r, tsyr_w, 0x00ff)
269	274	AM_RANGE(0xffffd0, 0xffffd1) AM_DEVREADWRITE8("timer16:0", h8_timer16_channel_device, tcr_r, tcr_w, 0xff00)
r243808	r243809
404	409	add_event(event_time, timer16_3->internal_update(current_time));
405	410	add_event(event_time, timer16_4->internal_update(current_time));
406	411	add_event(event_time, timer16_5->internal_update(current_time));
	412	add_event(event_time, watchdog->internal_update(current_time));
407	413
408	414	recompute_bcount(event_time);
409	415	}

trunk/src/emu/cpu/h8/h8s2655.h
r243808	r243809
44	44	#define __H8S2655_H__
45	45
46	46	#include "h8s2600.h"
	47	#include "h8_intc.h"
47	48	#include "h8_adc.h"
48	49	#include "h8_port.h"
49		#include "h8_intc.h"
50	50	#include "h8_timer8.h"
51	51	#include "h8_timer16.h"
52	52	#include "h8_sci.h"
	53	#include "h8_watchdog.h"
53	54
54	55	class h8s2655_device : public h8s2600_device {
55	56	public:
r243808	r243809
87	88	required_device<h8_sci_device> sci0;
88	89	required_device<h8_sci_device> sci1;
89	90	required_device<h8_sci_device> sci2;
	91	required_device<h8_watchdog_device> watchdog;
90	92
91	93	UINT8 syscr;
92	94

trunk/src/emu/machine/tmp68301.c
r243808	r243809
18	18	#include "machine/tmp68301.h"
19	19
20	20	const device_type TMP68301 = &device_creator<tmp68301_device>;
	21	const device_type TMP68301_SERIAL = &device_creator<tmp68301_serial_device>;
	22	const device_type TMP68301_RS232 = &device_creator<tmp68301_rs232_device>;
21	23
22	24	static ADDRESS_MAP_START( tmp68301_regs, AS_0, 16, tmp68301_device )
23	25	// AM_RANGE(0x000,0x3ff) AM_RAM
24		AM_RANGE(0x094,0x095) AM_READWRITE(imr_r,imr_w)
25		AM_RANGE(0x098,0x099) AM_READWRITE(iisr_r,iisr_w)
	26	AM_RANGE(0x094,0x095) AM_READWRITE (imr_r, imr_w)
	27	AM_RANGE(0x098,0x099) AM_READWRITE (iisr_r, iisr_w)
26	28
27	29	/* Parallel Port */
28		AM_RANGE(0x100,0x101) AM_READWRITE(pdir_r,pdir_w)
29		AM_RANGE(0x10a,0x10b) AM_READWRITE(pdr_r,pdr_w)
	30	AM_RANGE(0x100,0x101) AM_READWRITE (pdir_r, pdir_w)
	31	AM_RANGE(0x10a,0x10b) AM_READWRITE (pdr_r, pdr_w)
30	32
31	33	/* Serial Port */
32		AM_RANGE(0x18e,0x18f) AM_READWRITE(scr_r,scr_w)
	34	AM_RANGE(0x180,0x181) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, smr_r, smr_w, 0x00ff)
	35	AM_RANGE(0x182,0x183) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, scmr_r, scmr_w, 0x00ff)
	36	AM_RANGE(0x184,0x185) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, sbrr_r, sbrr_w, 0x00ff)
	37	AM_RANGE(0x186,0x187) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, ssr_r, ssr_w, 0x00ff)
	38	AM_RANGE(0x188,0x189) AM_DEVREADWRITE8("ser0", tmp68301_serial_device, sdr_r, sdr_w, 0x00ff)
	39
	40	AM_RANGE(0x18c,0x18d) AM_READWRITE8(spr_r, spr_w, 0x00ff)
	41	AM_RANGE(0x18e,0x18f) AM_READWRITE8(scr_r, scr_w, 0x00ff)
	42
	43	AM_RANGE(0x190,0x191) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, smr_r, smr_w, 0x00ff)
	44	AM_RANGE(0x192,0x193) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, scmr_r, scmr_w, 0x00ff)
	45	AM_RANGE(0x194,0x195) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, sbrr_r, sbrr_w, 0x00ff)
	46	AM_RANGE(0x196,0x197) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, ssr_r, ssr_w, 0x00ff)
	47	AM_RANGE(0x198,0x199) AM_DEVREADWRITE8("ser1", tmp68301_serial_device, sdr_r, sdr_w, 0x00ff)
	48
	49	AM_RANGE(0x1a0,0x1a1) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, smr_r, smr_w, 0x00ff)
	50	AM_RANGE(0x1a2,0x1a3) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, scmr_r, scmr_w, 0x00ff)
	51	AM_RANGE(0x1a4,0x1a5) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, sbrr_r, sbrr_w, 0x00ff)
	52	AM_RANGE(0x1a6,0x1a7) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, ssr_r, ssr_w, 0x00ff)
	53	AM_RANGE(0x1a8,0x1a9) AM_DEVREADWRITE8("ser2", tmp68301_serial_device, sdr_r, sdr_w, 0x00ff)
33	54	ADDRESS_MAP_END
34	55
	56	static MACHINE_CONFIG_FRAGMENT( tmp68301 )
	57	MCFG_TMP68301_RS232_ADD ("ser0")
	58	MCFG_TMP68301_SERIAL_ADD("ser1")
	59	MCFG_TMP68301_SERIAL_ADD("ser2")
	60	MACHINE_CONFIG_END
	61
35	62	// IRQ Mask register, 0x94
36	63	READ16_MEMBER(tmp68301_device::imr_r)
37	64	{
r243808	r243809
54	81	COMBINE_DATA(&m_iisr);
55	82	}
56	83
57		// Serial Control Register (TODO: 8-bit wide)
58		READ16_MEMBER(tmp68301_device::scr_r)
59		{
60		return m_scr;
61		}
62
63		WRITE16_MEMBER(tmp68301_device::scr_w)
64		{
65		/*
66		*--- ---- CKSE
67		--*- ---- RES
68		---- ---* INTM
69		*/
70
71		COMBINE_DATA(&m_scr);
72		m_scr &= 0xa1;
73		}
74
75	84	/* Parallel direction: 1 = output, 0 = input */
76	85	READ16_MEMBER(tmp68301_device::pdir_r)
77	86	{
r243808	r243809
99	108	device_memory_interface(mconfig, *this),
100	109	m_in_parallel_cb(*this),
101	110	m_out_parallel_cb(*this),
	111	m_ser0(*this, "ser0"),
	112	m_ser1(*this, "ser1"),
	113	m_ser2(*this, "ser2"),
102	114	m_space_config("regs", ENDIANNESS_LITTLE, 16, 10, 0, NULL, *ADDRESS_MAP_NAME(tmp68301_regs))
103	115	{
104	116	}
105	117
	118	void tmp68301_device::set_cpu_tag(const char *tag)
	119	{
	120	m_cpu_tag = tag;
	121	}
106	122
107	123	//-------------------------------------------------
108	124	// device_start - device-specific startup
r243808	r243809
116	132
117	133	m_in_parallel_cb.resolve_safe(0);
118	134	m_out_parallel_cb.resolve_safe();
	135
	136	m_cpu = machine().device<m68000_device>(m_cpu_tag);
119	137	}
120	138
121	139	//-------------------------------------------------
r243808	r243809
130	148	m_IE[i] = 0;
131	149
132	150	m_imr = 0x7f7; // mask all irqs
	151	m_scr = 0x00;
	152	m_spr = 0x00;
	153
	154	double prescaled_clock = double(m_cpu->unscaled_clock())/256;
	155	m_ser0->set_prescaled_clock(prescaled_clock);
	156	m_ser1->set_prescaled_clock(prescaled_clock);
	157	m_ser2->set_prescaled_clock(prescaled_clock);
133	158	}
134	159
135	160	//-------------------------------------------------
r243808	r243809
142	167	return (spacenum == AS_0) ? &m_space_config : NULL;
143	168	}
144	169
	170	machine_config_constructor tmp68301_device::device_mconfig_additions() const
	171	{
	172	return MACHINE_CONFIG_NAME(tmp68301);
	173	}
	174
145	175	//**************************************************************************
146	176	// INLINE HELPERS
147	177	//**************************************************************************
r243808	r243809
190	220	m_irq_vector[level] = IVNR & 0x00e0;
191	221	m_irq_vector[level] += 4+i;
192	222
193		m~~achine().first~~cpu->set_input_line(level,HOLD_LINE);
	223	m_cpu->set_input_line(level,HOLD_LINE);
194	224	}
195	225
196	226	if (TCR & 0x0080) // N/1
r243808	r243809
233	263	{
234	264	int scale = (TCR & 0x3c00)>>10; // P4..1
235	265	if (scale > 8) scale = 8;
236		duration = attotime::from_hz(m~~achine().first~~cpu->unscaled_clock()) * ((1 << scale) * max);
	266	duration = attotime::from_hz(m_cpu->unscaled_clock()) * ((1 << scale) * max);
237	267	}
238	268	break;
239	269	}
r243808	r243809
275	305
276	306	m_IE[i] = 0; // Interrupts are edge triggerred
277	307
278		m~~achine().first~~cpu->set_input_line(level,HOLD_LINE);
	308	m_cpu->set_input_line(level,HOLD_LINE);
279	309	}
280	310	}
281	311	}
r243808	r243809
313	343	void tmp68301_device::external_interrupt_0() { m_IE[0] = 1; update_irq_state(); }
314	344	void tmp68301_device::external_interrupt_1() { m_IE[1] = 1; update_irq_state(); }
315	345	void tmp68301_device::external_interrupt_2() { m_IE[2] = 1; update_irq_state(); }
	346
	347
	348	// Serial subsystem
	349
	350	tmp68301_serial_device::tmp68301_serial_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	351	device_t(mconfig, TMP68301_SERIAL, "TMP68301 Serial", tag, owner, clock, "tmp68301_serial", __FILE__),
	352	tx_cb(*this)
	353	{
	354	}
	355
	356	tmp68301_serial_device::tmp68301_serial_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source) :
	357	device_t(mconfig, type, name, tag, owner, clock, shortname, source),
	358	tx_cb(*this)
	359	{
	360	}
	361
	362	tmp68301_rs232_device::tmp68301_rs232_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
	363	tmp68301_serial_device(mconfig, TMP68301_SERIAL, "TMP68301 RS232", tag, owner, clock, "tmp68301_rs232", __FILE__),
	364	rts_cb(*this),
	365	dtr_cb(*this)
	366	{
	367	}
	368
	369	void tmp68301_serial_device::device_start()
	370	{
	371	prescaled_clock = 0;
	372	clock_interval = attotime::never;
	373	}
	374
	375	void tmp68301_serial_device::device_reset()
	376	{
	377	smr = 0xc2;
	378	scmr = 0x10;
	379	ssr = 0x04;
	380	sbrr = 0x00;
	381	clock_interval = attotime::never;
	382	}
	383
	384	void tmp68301_rs232_device::device_start()
	385	{
	386	tmp68301_serial_device::device_start();
	387	}
	388
	389	void tmp68301_rs232_device::device_reset()
	390	{
	391	tmp68301_serial_device::device_reset();
	392	}
	393
	394	READ8_MEMBER(tmp68301_device::scr_r)
	395	{
	396	return m_scr;
	397	}
	398
	399	WRITE8_MEMBER(tmp68301_device::scr_w)
	400	{
	401	logerror("%s: scr_w %02x clokc=%s reset=%s serial_int=%s (%06x)\n", tag(), data,
	402	data & 0x80 ? "internal" : "external",
	403	data & 0x40 ? "on" : "off",
	404	data & 0x01 ? "off" : "on",
	405	space.device().safe_pc());
	406
	407	/*
	408	*--- ---- CKSE
	409	--*- ---- RES
	410	---- ---* INTM
	411	*/
	412
	413	m_scr = data & 0xa1;
	414	recalc_serial_clock();
	415	}
	416
	417	READ8_MEMBER(tmp68301_device::spr_r)
	418	{
	419	logerror("%s: spr_r (%06x)\n", tag(), space.device().safe_pc());
	420	return m_spr;
	421	}
	422
	423	WRITE8_MEMBER(tmp68301_device::spr_w)
	424	{
	425	logerror("%s: spr_w %02x (%06x)\n", tag(), data, space.device().safe_pc());
	426	m_spr = data;
	427	recalc_serial_clock();
	428	}
	429
	430	void tmp68301_device::recalc_serial_clock()
	431	{
	432	double prescaled_clock = m_scr & 0x20 ? 0 : m_spr ? double(m_cpu->unscaled_clock())/m_spr : double(clock())/256;
	433	m_ser0->set_prescaled_clock(prescaled_clock);
	434	m_ser1->set_prescaled_clock(prescaled_clock);
	435	m_ser2->set_prescaled_clock(prescaled_clock);
	436	}
	437
	438	READ8_MEMBER(tmp68301_serial_device::smr_r)
	439	{
	440	logerror("%s: smr_r (%06x)\n", tag(), space.device().safe_pc());
	441	return smr;
	442	}
	443
	444	WRITE8_MEMBER(tmp68301_serial_device::smr_w)
	445	{
	446	logerror("%s: smr_w %02x rx_int=%s tx_int=%s er_int=%s mode=%d%c%c (%06x)\n",
	447	tag(), data,
	448	data & 0x80 ? "off" : "on",
	449	data & 0x02 ? "off" : "on",
	450	data & 0x40 ? "off" : "on",
	451	5 + ((data >> 2) & 3),
	452	data & 0x10 ? data & 0x20 ? 'o' : 'e' : 'n',
	453	data & 0x01 ? '2' : '1',
	454	space.device().safe_pc());
	455	smr = data;
	456	}
	457
	458	READ8_MEMBER(tmp68301_serial_device::scmr_r)
	459	{
	460	logerror("%s: scmr_r (%06x)\n", tag(), space.device().safe_pc());
	461	return scmr;
	462	}
	463
	464	WRITE8_MEMBER(tmp68301_serial_device::scmr_w)
	465	{
	466	logerror("%s: scmr_w %02x ers=%s break=%s rx=%s tx=%s rts=%s dtr=%s (%06x)\n", tag(), data,
	467	data & 0x10 ? "reset" : "off",
	468	data & 0x08 ? "on" : "off",
	469	data & 0x04 ? "on" : "off",
	470	data & 0x01 ? "on" : "off",
	471	data & 0x20 ? "low" : "high",
	472	data & 0x02 ? "low" : "high",
	473	space.device().safe_pc());
	474	scmr = data;
	475	}
	476
	477	READ8_MEMBER(tmp68301_serial_device::sbrr_r)
	478	{
	479	logerror("%s: sbrr_r (%06x)\n", tag(), space.device().safe_pc());
	480	return sbrr;
	481	}
	482
	483	WRITE8_MEMBER(tmp68301_serial_device::sbrr_w)
	484	{
	485	logerror("%s: sbrr_w %02x (%06x)\n", tag(), data, space.device().safe_pc());
	486	sbrr = data;
	487	clock_update();
	488	}
	489
	490	READ8_MEMBER(tmp68301_serial_device::ssr_r)
	491	{
	492	logerror("%s: ssr_r (%06x)\n", tag(), space.device().safe_pc());
	493	return ssr;
	494	}
	495
	496	WRITE8_MEMBER(tmp68301_serial_device::ssr_w)
	497	{
	498	logerror("%s: ssr_w %02x (%06x)\n", tag(), data, space.device().safe_pc());
	499	ssr = data;
	500	}
	501
	502	READ8_MEMBER(tmp68301_serial_device::sdr_r)
	503	{
	504	logerror("%s: sdr_r (%06x)\n", tag(), space.device().safe_pc());
	505	return 0x00;
	506	}
	507
	508	WRITE8_MEMBER(tmp68301_serial_device::sdr_w)
	509	{
	510	logerror("%s: sdr_w %02x (%06x)\n", tag(), data, space.device().safe_pc());
	511	}
	512
	513	void tmp68301_serial_device::set_prescaled_clock(double clock)
	514	{
	515	prescaled_clock = clock;
	516	clock_update();
	517	}
	518
	519	void tmp68301_serial_device::clock_update()
	520	{
	521	if(!prescaled_clock \|\| !sbrr \|\| (sbrr & (sbrr - 1))) {
	522	clock_interval = attotime::never;
	523	return;
	524	}
	525
	526	double base_rate = prescaled_clock / sbrr;
	527	clock_interval = attotime::from_seconds(1/base_rate);
	528	logerror("%s: Baud rate %gHz\n", tag(), base_rate/8);
	529	}

trunk/src/emu/machine/tmp68301.h
r243808	r243809
1	1	#ifndef TMP68301_H
2	2	#define TMP68301_H
3	3
	4	#include "cpu/m68000/m68000.h"
	5
4	6	//**************************************************************************
5	7	// INTERFACE CONFIGURATION MACROS
6	8	//**************************************************************************
7	9
	10	#define MCFG_TMP68301_ADD(_tag, _cpu) \
	11	MCFG_DEVICE_ADD( _tag, TMP68301, 0 ) \
	12	downcast<tmp68301_device *>(device)->set_cpu_tag(_cpu);
	13
8	14	/* TODO: serial ports, frequency & hook it up with m68k */
9	15	#define MCFG_TMP68301_IN_PARALLEL_CB(_devcb) \
10	16	devcb = &tmp68301_device::set_in_parallel_callback(*device, DEVCB_##_devcb);
r243808	r243809
12	18	#define MCFG_TMP68301_OUT_PARALLEL_CB(_devcb) \
13	19	devcb = &tmp68301_device::set_out_parallel_callback(*device, DEVCB_##_devcb);
14	20
	21	#define MCFG_TMP68301_SERIAL_ADD( _tag ) \
	22	MCFG_DEVICE_ADD( _tag, TMP68301_SERIAL, 0 )
15	23
	24	#define MCFG_TMP68301_RS232_ADD( _tag ) \
	25	MCFG_DEVICE_ADD( _tag, TMP68301_RS232, 0 )
	26
	27	#define MCFG_TMP68301_SERIAL_TX_CALLBACK(_devcb) \
	28	devcb = &tmp68301_serial_device::set_tx_cb(*device, DEVCB_##_devcb);
	29
	30	#define MCFG_TMP68301_SERIAL_RTS_CALLBACK(_devcb) \
	31	devcb = &tmp68301_rs232_device::set_rts_cb(*device, DEVCB_##_devcb);
	32
	33	#define MCFG_TMP68301_SERIAL_DTR_CALLBACK(_devcb) \
	34	devcb = &tmp68301_rs232_device::set_str_cb(*device, DEVCB_##_devcb);
	35
16	36	//**************************************************************************
17	37	// TYPE DEFINITIONS
18	38	//**************************************************************************
19	39
	40	class tmp68301_serial_device : public device_t
	41	{
	42	public:
	43	tmp68301_serial_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	44	tmp68301_serial_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
20	45
	46	DECLARE_READ8_MEMBER(smr_r);
	47	DECLARE_WRITE8_MEMBER(smr_w);
	48	DECLARE_READ8_MEMBER(scmr_r);
	49	DECLARE_WRITE8_MEMBER(scmr_w);
	50	DECLARE_READ8_MEMBER(sbrr_r);
	51	DECLARE_WRITE8_MEMBER(sbrr_w);
	52	DECLARE_READ8_MEMBER(ssr_r);
	53	DECLARE_WRITE8_MEMBER(ssr_w);
	54	DECLARE_READ8_MEMBER(sdr_r);
	55	DECLARE_WRITE8_MEMBER(sdr_w);
21	56
	57	DECLARE_WRITE_LINE_MEMBER(rx_w);
	58
	59	template<class _Object> static devcb_base &set_tx_cb(device_t &device, _Object object) { return downcast<tmp68301_serial_device &>(device).tx_cb.set_callback(object); }
	60
	61	void set_prescaled_clock(double clock);
	62
	63	protected:
	64	devcb_write_line tx_cb;
	65	attotime clock_interval;
	66	double prescaled_clock;
	67
	68	UINT8 smr, scmr, ssr, sbrr;
	69
	70	virtual void device_start();
	71	virtual void device_reset();
	72
	73	void clock_update();
	74	};
	75
	76	class tmp68301_rs232_device : public tmp68301_serial_device {
	77	public:
	78	tmp68301_rs232_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	79
	80	DECLARE_WRITE_LINE_MEMBER(cts_w);
	81	DECLARE_WRITE_LINE_MEMBER(dsr_w);
	82
	83	template<class _Object> static devcb_base &set_rts_cb(device_t &device, _Object object) { return downcast<tmp68301_rs232_device &>(device).rts_cb.set_callback(object); }
	84	template<class _Object> static devcb_base &set_dtr_cb(device_t &device, _Object object) { return downcast<tmp68301_rs232_device &>(device).dtr_cb.set_callback(object); }
	85
	86	protected:
	87	devcb_write_line rts_cb, dtr_cb;
	88
	89	virtual void device_start();
	90	virtual void device_reset();
	91	};
	92
22	93	class tmp68301_device : public device_t,
23	94	public device_memory_interface
24	95	{
r243808	r243809
29	100	template<class _Object> static devcb_base &set_in_parallel_callback(device_t &device, _Object object) { return downcast<tmp68301_device &>(device).m_in_parallel_cb.set_callback(object); }
30	101	template<class _Object> static devcb_base &set_out_parallel_callback(device_t &device, _Object object) { return downcast<tmp68301_device &>(device).m_out_parallel_cb.set_callback(object); }
31	102
	103	void set_cpu_tag(const char *tag);
	104
32	105	// Hardware Registers
33	106	DECLARE_READ16_MEMBER( regs_r );
34	107	DECLARE_WRITE16_MEMBER( regs_w );
r243808	r243809
42	115	DECLARE_WRITE16_MEMBER(imr_w);
43	116	DECLARE_READ16_MEMBER(iisr_r);
44	117	DECLARE_WRITE16_MEMBER(iisr_w);
45		DECLARE_READ16_MEMBER(scr_r);
46		DECLARE_WRITE16_MEMBER(scr_w);
47	118	DECLARE_READ16_MEMBER(pdr_r);
48	119	DECLARE_WRITE16_MEMBER(pdr_w);
49	120	DECLARE_READ16_MEMBER(pdir_r);
50	121	DECLARE_WRITE16_MEMBER(pdir_w);
51	122
	123	DECLARE_READ8_MEMBER(spr_r);
	124	DECLARE_WRITE8_MEMBER(spr_w);
	125	DECLARE_READ8_MEMBER(scr_r);
	126	DECLARE_WRITE8_MEMBER(scr_w);
	127
52	128	IRQ_CALLBACK_MEMBER(irq_callback);
53	129	protected:
54	130	// device-level overrides
55	131	virtual void device_start();
56	132	virtual void device_reset();
57	133	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
	134	virtual machine_config_constructor device_mconfig_additions() const;
58	135
59	136	private:
60	137	devcb_read16 m_in_parallel_cb;
61	138	devcb_write16 m_out_parallel_cb;
62	139
	140	required_device<tmp68301_rs232_device> m_ser0;
	141	required_device<tmp68301_serial_device> m_ser1;
	142	required_device<tmp68301_serial_device> m_ser2;
	143
	144	const char *m_cpu_tag;
	145	m68000_device *m_cpu;
	146
63	147	// internal state
64	148	UINT16 m_regs[0x400];
65	149
r243808	r243809
74	158
75	159	UINT16 m_imr;
76	160	UINT16 m_iisr;
77		UINT16 m_scr;
78	161	UINT16 m_pdir;
79	162
	163	UINT8 m_scr, m_spr;
	164
80	165	inline UINT16 read_word(offs_t address);
81	166	inline void write_word(offs_t address, UINT16 data);
82	167	const address_space_config m_space_config;
	168
	169	void recalc_serial_clock();
83	170	};
84	171
85	172	extern const device_type TMP68301;
	173	extern const device_type TMP68301_SERIAL;
	174	extern const device_type TMP68301_RS232;
86	175
87	176	#endif

trunk/src/mame/drivers/csplayh5.c
r243808	r243809
21	21	After returning a correct status code, tmp68301 sends "FSDVD04.MPG00001<CR>" to serial, probably tries
22	22	to playback the file ...
23	23
	24	serial: prescaler (spr) = a0
	25	baud rate (sbrr0) = 2
	26
	27	H8 typing:
	28	- at least h8h
	29	- watchdog at ffffffaa/ffffffa8 = a500 5a00 ok 3002 3044
	30	- ffffffaf/ad/ac = 05 18 23 ok 3002 3044 (refresh controller)
	31	- p6ddr \|= 06
	32	- p6dr \|= 02
	33	- p8ddr = fe
	34	- p8dr = ff
	35	- p9ddr = c3
	36	- p9dr = cf
	37	- paddr = ff
	38	- padr = 1f
	39	- pbddr = 3f
	40	- pbdr = 19
	41	- abwcr = 06
	42	- ipra = 1f a4/a3/a2/a1/a0
	43	- iprb = e8 b7/b6/b5/b3
	44	- ier = 00
	45	- iscr = 10
	46	- tstr = e0
	47	- tsnc = e0
	48	- tmdr = 80
	49	(etc)
	50
	51
24	52	***********************************************************************************************************/
25	53
26	54	#include "emu.h"
r243808	r243809
60	88	DECLARE_READ16_MEMBER(test_r);
61	89	DECLARE_READ8_MEMBER(csplayh5_sound_r);
62	90	DECLARE_WRITE8_MEMBER(csplayh5_soundclr_w);
63
	91	DECLARE_READ8_MEMBER(r40020_r);
	92	DECLARE_WRITE8_MEMBER(r40020_w);
64	93	DECLARE_READ8_MEMBER(soundcpu_portd_r);
65	94	DECLARE_WRITE8_MEMBER(soundcpu_porta_w);
66	95	DECLARE_WRITE8_MEMBER(soundcpu_dac2_w);
67	96	DECLARE_WRITE8_MEMBER(soundcpu_dac1_w);
68	97	DECLARE_WRITE8_MEMBER(soundcpu_porte_w);
69	98
	99	DECLARE_READ8_MEMBER(ext_r);
	100	DECLARE_WRITE8_MEMBER(ext_w);
	101
70	102	DECLARE_DRIVER_INIT(mjmania);
71	103	DECLARE_DRIVER_INIT(csplayh5);
72	104	DECLARE_DRIVER_INIT(fuudol);
r243808	r243809
84	116
85	117
86	118
87		#define USE_H8 0
88
89	119	// from MSX2 driver, may be not accurate for this HW
90	120	#define MSX2_XBORDER_PIXELS 16
91	121	#define MSX2_YBORDER_PIXELS 28
r243808	r243809
141	171	AM_RANGE(0xc00000, 0xc7ffff) AM_RAM AM_SHARE("nvram") AM_MIRROR(0x380000) // work RAM
142	172	ADDRESS_MAP_END
143	173
144		#if USE_H8
145	174	READ16_MEMBER(csplayh5_state::test_r)
146	175	{
147	176	return machine().rand();
148	177	}
149	178
	179	READ8_MEMBER(csplayh5_state::r40020_r)
	180	{
	181	logerror("read %05x (%06x)\n", 0x40020+offset, int(space.device().safe_pc()));
	182	if(space.device().safe_pc() == 0x7a54)
	183	return 0x08;
	184	if(space.device().safe_pc() == 0x7a3c)
	185	return 0x01;
	186	return 0x00;
	187	}
	188
	189	WRITE8_MEMBER(csplayh5_state::r40020_w)
	190	{
	191	logerror("%05x = %02x (%06x)\n", 0x40020+offset, data, int(space.device().safe_pc()));
	192	}
	193
150	194	static ADDRESS_MAP_START( csplayh5_sub_map, AS_PROGRAM, 16, csplayh5_state )
151	195	AM_RANGE(0x000000, 0x01ffff) AM_ROM
152	196
153		AM_RANGE(0x04002a, 0x04002b) AM_READ(test_r)
154		AM_RANGE(0x040036, 0x040037) AM_READ(test_r)
	197	AM_RANGE(0x020008, 0x02000f) AM_READWRITE8(ext_r, ext_w, 0xff00)
155	198
	199	AM_RANGE(0x040020, 0x04002f) AM_READWRITE8(r40020_r, r40020_w, 0xffff)
	200
156	201	AM_RANGE(0x078000, 0x07ffff) AM_RAM AM_SHARE("nvram")
157	202	AM_RANGE(0x080000, 0x0fffff) AM_RAM
158	203	ADDRESS_MAP_END
r243808	r243809
161	206	static ADDRESS_MAP_START( csplayh5_sub_io_map, AS_IO, 16, csplayh5_state )
162	207
163	208	ADDRESS_MAP_END
164		#endif
165	209
166	210
	211	READ8_MEMBER(csplayh5_state::ext_r)
	212	{
	213	return 0x08;
	214	}
	215
	216	WRITE8_MEMBER(csplayh5_state::ext_w)
	217	{
	218	// logerror("ext_w %d, %02x\n", offset, data);
	219	}
	220
167	221	/*
168	222	sound HW is identical to Niyanpai
169	223	*/
r243808	r243809
221	275	}
222	276
223	277
224
225
226
227
228	278	static ADDRESS_MAP_START( csplayh5_sound_map, AS_PROGRAM, 8, csplayh5_state )
229	279	AM_RANGE(0x0000, 0x77ff) AM_ROM
230	280	AM_RANGE(0x7800, 0x7fff) AM_RAM
r243808	r243809
457	507	static MACHINE_CONFIG_START( csplayh5, csplayh5_state )
458	508
459	509	/* basic machine hardware */
460		MCFG_CPU_ADD("maincpu",M68000,16000000) /* TMP68301-16 */
	510	MCFG_CPU_ADD("maincpu",M68000,16000000) /* TMP68301-16, gives a 6250bps serial */
461	511	MCFG_CPU_PROGRAM_MAP(csplayh5_map)
462	512	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
463	513
464	514	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", csplayh5_state, csplayh5_irq, "screen", 0, 1)
465	515
466		MCFG_~~DEVICE~~_ADD("tmp68301", ~~TMP68301, 0~~)
	516	MCFG_TMP68301_ADD("tmp68301", "maincpu")
467	517
468		#if USE_H8
469		MCFG_CPU_ADD("subcpu", H83002, 16000000) /* unknown clock */
	518	MCFG_CPU_ADD("subcpu", H83002, 17600000) /* unknown clock, 17.6MHz gives a 6250bps serial too */
470	519	MCFG_CPU_PROGRAM_MAP(csplayh5_sub_map)
471	520	MCFG_CPU_IO_MAP(csplayh5_sub_io_map)
472		#endif
473	521
474	522	MCFG_CPU_ADD("audiocpu", TMPZ84C011, 8000000) /* TMPZ84C011, unknown clock */
475	523	MCFG_CPU_CONFIG(daisy_chain_sound)

trunk/src/mame/drivers/niyanpai.c
r243808	r243809
774	774	MCFG_CPU_VBLANK_INT_DRIVER("screen", niyanpai_state, niyanpai_interrupt)
775	775	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
776	776
777		MCFG_~~DEVICE~~_ADD("tmp68301", ~~TMP68301, 0~~)
	777	MCFG_TMP68301_ADD("tmp68301", "maincpu")
778	778	MCFG_TMP68301_OUT_PARALLEL_CB(WRITE16(niyanpai_state, tmp68301_parallel_port_w))
779	779
780	780	MCFG_CPU_ADD("audiocpu", TMPZ84C011, 8000000) /* TMPZ84C011, 8.00 MHz */

trunk/src/mame/drivers/realbrk.c
r243808	r243809
758	758	MCFG_CPU_VBLANK_INT_DRIVER("screen", realbrk_state, realbrk_interrupt)
759	759	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
760	760
761		MCFG_~~DEVICE~~_ADD("tmp68301", ~~TMP68301, 0~~)
	761	MCFG_TMP68301_ADD("tmp68301", "maincpu")
762	762	MCFG_TMP68301_OUT_PARALLEL_CB(WRITE16(realbrk_state,realbrk_flipscreen_w))
763	763
764	764	/* video hardware */

trunk/src/mame/drivers/seta2.c
r243808	r243809
2093	2093	MCFG_CPU_VBLANK_INT_DRIVER("screen", seta2_state, seta2_interrupt)
2094	2094	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
2095	2095
2096		MCFG_~~DEVICE~~_ADD("tmp68301", ~~TMP68301, 0~~)
	2096	MCFG_TMP68301_ADD("tmp68301", "maincpu")
2097	2097
2098	2098	// video hardware
2099	2099	MCFG_SCREEN_ADD("screen", RASTER)
r243808	r243809
2325	2325	MCFG_CPU_VBLANK_INT_DRIVER("screen", seta2_state, seta2_interrupt)
2326	2326	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("tmp68301",tmp68301_device,irq_callback)
2327	2327
2328		MCFG_~~DEVICE~~_ADD("tmp68301", ~~TMP68301, 0~~) // does this have a ticket dispenser?
	2328	MCFG_TMP68301_ADD("tmp68301", "maincpu") // does this have a ticket dispenser?
2329	2329
2330	2330	// video hardware
2331	2331	MCFG_SCREEN_ADD("screen", RASTER)

https://github.com/mamedev/mame/commit/554d9cf4cca0096baa4536a98b8bd9ee5cd147b6

199869 Revisions