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r35293 Thursday 26th February, 2015 at 15:11:29 UTC by Olivier Galibert
powervr2: Rewrite [O. Galibert]

[src/mame/drivers]	naomi.c
[src/mame/includes]	dc.h
[src/mame/video]	powervr2.c powervr2.h
[src/mess/drivers]	dccons.c

trunk/src/mame/drivers/naomi.c

r243804	r243805
1634	1634	AM_RANGE(0x0103ff00, 0x0103ffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
1635	1635
1636	1636	/* Area 1 */
1637		AM_RANGE(0x04000000, 0x04ffffff) AM_MIRROR(0x02000000) AM_RAM AM_SHARE("dc_texture_ram")      // texture memory 64 bit access
1638		AM_RANGE(0x05000000, 0x05ffffff) AM_MIRROR(0x02000000) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
	1637	AM_RANGE(0x04000000, 0x04ffffff) AM_DEVREADWRITE  ("powervr2", powervr2_device, tex64_r, tex64_w)
	1638	AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE32("powervr2", powervr2_device, tex32_r, tex32_w, U64(0xffffffffffffffff))
1639	1639
1640	1640	/* Area 2*/
1641	1641	AM_RANGE(0x08000000, 0x09ffffff) AM_MIRROR(0x02000000) AM_NOP // 'Unassigned'
r243804	r243805
1690	1690	AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
1691	1691
1692	1692	/* Area 1 */
1693		AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram")      // texture memory 64 bit access
1694		AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
1695		AM_RANGE(0x06000000, 0x06ffffff) AM_RAM AM_SHARE("textureram2")   // 64 bit access 2nd PVR RAM
1696		AM_RANGE(0x07000000, 0x07ffffff) AM_RAM AM_SHARE("frameram2")// 32 bit access 2nd PVR RAM
	1693	AM_RANGE(0x04000000, 0x04ffffff) AM_DEVREADWRITE  ("powervr2", powervr2_device, tex64_r, tex64_w)
	1694	AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE32("powervr2", powervr2_device, tex32_r, tex32_w, U64(0xffffffffffffffff))
	1695	//   AM_RANGE(0x06000000, 0x06ffffff) AM_RAM AM_SHARE("textureram2")   // 64 bit access 2nd PVR RAM
	1696	//   AM_RANGE(0x07000000, 0x07ffffff) AM_RAM AM_SHARE("frameram2")// 32 bit access 2nd PVR RAM
1697	1697
1698	1698	/* Area 2*/
1699	1699	AM_RANGE(0x085f6800, 0x085f69ff) AM_WRITE(dc_sysctrl_w ) // writes to BOTH PVRs
r243804	r243805
1854	1854	AM_RANGE(0x0103ff00, 0x0103ffff) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
1855	1855
1856	1856	/* Area 1 - half the texture memory, like dreamcast, not naomi */
1857		AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_MIRROR(0x00800000) AM_SHARE("dc_texture_ram")      // texture memory 64 bit access
1858		AM_RANGE(0x05000000, 0x057fffff) AM_RAM AM_MIRROR(0x00800000) AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
	1857	AM_RANGE(0x04000000, 0x04ffffff) AM_DEVREADWRITE  ("powervr2", powervr2_device, tex64_r, tex64_w)
	1858	AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE32("powervr2", powervr2_device, tex32_r, tex32_w, U64(0xffffffffffffffff))
1859	1859
1860	1860	/* Area 2*/
1861	1861	AM_RANGE(0x08000000, 0x0bffffff) AM_NOP // 'Unassigned'

trunk/src/mame/includes/dc.h

r243804	r243805
17	17	public:
18	18	dc_state(const machine_config &mconfig, device_type type, const char *tag)
19	19	: driver_device(mconfig, type, tag),
20		dc_framebuffer_ram(*this, "frameram"),
21		dc_texture_ram(*this, "dc_texture_ram"),
22	20	dc_sound_ram(*this, "dc_sound_ram"),
23	21	dc_ram(*this, "dc_ram"),
24	22	m_maincpu(*this, "maincpu"),
r243804	r243805
28	26	m_naomig1(*this, "rom_board"),
29	27	m_aica(*this, "aica") { }
30	28
31		required_shared_ptr<UINT64> dc_framebuffer_ram; // '32-bit access area'
32		required_shared_ptr<UINT64> dc_texture_ram; // '64-bit access area'
33
34	29	required_shared_ptr<UINT32> dc_sound_ram;
35	30	required_shared_ptr<UINT64> dc_ram;
36	31

trunk/src/mame/video/powervr2.c

r243804	r243805
15	15	DEVICE_ADDRESS_MAP_START(ta_map, 32, powervr2_device)
16	16	AM_RANGE(0x0000, 0x0003) AM_READ(     id_r)
17	17	AM_RANGE(0x0004, 0x0007) AM_READ(     revision_r)
18		AM_RANGE(0x0008, 0x000b) AM_READWRITE(softreset_r,        softreset_w)
19		AM_RANGE(0x0014, 0x0017) AM_WRITE(    startrender_w)
20		// 18 = test select
21		AM_RANGE(0x0020, 0x0023) AM_READWRITE(param_base_r,       param_base_w)
22		AM_RANGE(0x002c, 0x002f) AM_READWRITE(region_base_r,      region_base_w)
23		// 30 = span sort cfg
24		AM_RANGE(0x0040, 0x0043) AM_READWRITE(vo_border_col_r,    vo_border_col_w)
25		AM_RANGE(0x0044, 0x0047) AM_READWRITE(fb_r_ctrl_r,        fb_r_ctrl_w)
26		AM_RANGE(0x0048, 0x004b) AM_READWRITE(fb_w_ctrl_r,        fb_w_ctrl_w)
27		AM_RANGE(0x004c, 0x004f) AM_READWRITE(fb_w_linestride_r,  fb_w_linestride_w)
28		AM_RANGE(0x0050, 0x0053) AM_READWRITE(fb_r_sof1_r,        fb_r_sof1_w)
29		AM_RANGE(0x0054, 0x0057) AM_READWRITE(fb_r_sof2_r,        fb_r_sof2_w)
30		AM_RANGE(0x005c, 0x005f) AM_READWRITE(fb_r_size_r,        fb_r_size_w)
31		AM_RANGE(0x0060, 0x0063) AM_READWRITE(fb_w_sof1_r,        fb_w_sof1_w)
32		AM_RANGE(0x0064, 0x0067) AM_READWRITE(fb_w_sof2_r,        fb_w_sof2_w)
33		AM_RANGE(0x0068, 0x006b) AM_READWRITE(fb_x_clip_r,        fb_x_clip_w)
34		AM_RANGE(0x006c, 0x006f) AM_READWRITE(fb_y_clip_r,        fb_y_clip_w)
35		// 74 = fpu_shad_scale
36		// 78 = fpu_cull_val
37		AM_RANGE(0x007c, 0x007f) AM_READWRITE(fpu_param_cfg_r,    fpu_param_cfg_w)
38		// 80 = half_offset
39		// 84 = fpu_perp_val
40		// 88 = isp_backgnd_d
41		AM_RANGE(0x008c, 0x008f) AM_READWRITE(isp_backgnd_t_r,    isp_backgnd_t_w)
42		// 98 = isp_feed_cfg
43		// a0 = sdram_refresh
44		// a4 = sdram_arb_cfg
45		// a8 = sdram_cfg
46		// b0 = fog_col_ram
47		// b4 = fog_col_vert
48		// b8 = fog_density
49		// bc = fog_clamp_max
50		// c0 = fog_clamp_min
51		// c4 = spg_trigger_pos
52		AM_RANGE(0x00c8, 0x00cb) AM_READWRITE(spg_hblank_int_r,   spg_hblank_int_w)
53		AM_RANGE(0x00cc, 0x00cf) AM_READWRITE(spg_vblank_int_r,   spg_vblank_int_w)
54		AM_RANGE(0x00d0, 0x00d3) AM_READWRITE(spg_control_r,      spg_control_w)
55		AM_RANGE(0x00d4, 0x00d7) AM_READWRITE(spg_hblank_r,       spg_hblank_w)
56		AM_RANGE(0x00d8, 0x00db) AM_READWRITE(spg_load_r,         spg_load_w)
57		AM_RANGE(0x00dc, 0x00df) AM_READWRITE(spg_vblank_r,       spg_vblank_w)
58		AM_RANGE(0x00e0, 0x00e3) AM_READWRITE(spg_width_r,        spg_width_w)
59		AM_RANGE(0x00e4, 0x00e7) AM_READWRITE(text_control_r,     text_control_w)
60		AM_RANGE(0x00e8, 0x00eb) AM_READWRITE(vo_control_r,       vo_control_w)
61		AM_RANGE(0x00ec, 0x00ef) AM_READWRITE(vo_startx_r,        vo_startx_w)
62		AM_RANGE(0x00f0, 0x00f3) AM_READWRITE(vo_starty_r,        vo_starty_w)
63		// f4 = scaler_ctl
64		AM_RANGE(0x0108, 0x010b) AM_READWRITE(pal_ram_ctrl_r,     pal_ram_ctrl_w)
	18	AM_RANGE(0x0008, 0x000b) AM_READWRITE(softreset_r,         softreset_w)
	19	AM_RANGE(0x0014, 0x0017) AM_READWRITE(startrender_r,       startrender_w)
	20	AM_RANGE(0x0018, 0x001f) AM_READWRITE(test_select_r,       test_select_w)
	21	AM_RANGE(0x0020, 0x0023) AM_READWRITE(param_base_r,        param_base_w)
	22	AM_RANGE(0x002c, 0x002f) AM_READWRITE(region_base_r,       region_base_w)
	23	AM_RANGE(0x0030, 0x0034) AM_READWRITE(span_sort_cfg_r,     span_sort_cfg_w)
	24	AM_RANGE(0x0040, 0x0043) AM_READWRITE(vo_border_col_r,     vo_border_col_w)
	25	AM_RANGE(0x0044, 0x0047) AM_READWRITE(fb_r_ctrl_r,         fb_r_ctrl_w)
	26	AM_RANGE(0x0048, 0x004b) AM_READWRITE(fb_w_ctrl_r,         fb_w_ctrl_w)
	27	AM_RANGE(0x004c, 0x004f) AM_READWRITE(fb_w_linestride_r,   fb_w_linestride_w)
	28	AM_RANGE(0x0050, 0x0053) AM_READWRITE(fb_r_sof1_r,         fb_r_sof1_w)
	29	AM_RANGE(0x0054, 0x0057) AM_READWRITE(fb_r_sof2_r,         fb_r_sof2_w)
	30	AM_RANGE(0x005c, 0x005f) AM_READWRITE(fb_r_size_r,         fb_r_size_w)
	31	AM_RANGE(0x0060, 0x0063) AM_READWRITE(fb_w_sof1_r,         fb_w_sof1_w)
	32	AM_RANGE(0x0064, 0x0067) AM_READWRITE(fb_w_sof2_r,         fb_w_sof2_w)
	33	AM_RANGE(0x0068, 0x006b) AM_READWRITE(fb_x_clip_r,         fb_x_clip_w)
	34	AM_RANGE(0x006c, 0x006f) AM_READWRITE(fb_y_clip_r,         fb_y_clip_w)
	35	AM_RANGE(0x0074, 0x0077) AM_READWRITE(fpu_shad_scale_r,    fpu_shad_scale_w)
	36	AM_RANGE(0x0078, 0x007b) AM_READWRITE(fpu_cull_val_r,      fpu_cull_val_w)
	37	AM_RANGE(0x007c, 0x007f) AM_READWRITE(fpu_param_cfg_r,     fpu_param_cfg_w)
	38	AM_RANGE(0x0080, 0x0083) AM_READWRITE(half_offset_r,       half_offset_w)
	39	AM_RANGE(0x0084, 0x0087) AM_READWRITE(fpu_perp_val_r,      fpu_perp_val_w)
	40	AM_RANGE(0x0088, 0x008b) AM_READWRITE(isp_backgnd_d_r,     isp_backgnd_d_w)
	41	AM_RANGE(0x008c, 0x008f) AM_READWRITE(isp_backgnd_t_r,     isp_backgnd_t_w)
	42	AM_RANGE(0x0098, 0x009b) AM_READWRITE(isp_feed_cfg_r,      isp_feed_cfg_w)
	43	AM_RANGE(0x00a0, 0x00a3) AM_READWRITE(sdram_refresh_r,     sdram_refresh_w)
	44	AM_RANGE(0x00a4, 0x00a7) AM_READWRITE(sdram_arb_cfg_r,     sdram_arb_cfg_w)
	45	AM_RANGE(0x00a8, 0x00ab) AM_READWRITE(sdram_cfg_r,         sdram_cfg_w)
	46	AM_RANGE(0x00b0, 0x00b3) AM_READWRITE(fog_col_ram_r,       fog_col_ram_w)
	47	AM_RANGE(0x00b4, 0x00b7) AM_READWRITE(fog_col_vert_r,      fog_col_vert_w)
	48	AM_RANGE(0x00b8, 0x00bb) AM_READWRITE(fog_density_r,       fog_density_w)
	49	AM_RANGE(0x00bc, 0x00bf) AM_READWRITE(fog_clamp_max_r,     fog_clamp_max_w)
	50	AM_RANGE(0x00c0, 0x00c3) AM_READWRITE(fog_clamp_min_r,     fog_clamp_min_w)
	51	AM_RANGE(0x00c4, 0x00c7) AM_READWRITE(spg_trigger_pos_r,   spg_trigger_pos_w)
	52	AM_RANGE(0x00c8, 0x00cb) AM_READWRITE(spg_hblank_int_r,    spg_hblank_int_w)
	53	AM_RANGE(0x00cc, 0x00cf) AM_READWRITE(spg_vblank_int_r,    spg_vblank_int_w)
	54	AM_RANGE(0x00d0, 0x00d3) AM_READWRITE(spg_control_r,       spg_control_w)
	55	AM_RANGE(0x00d4, 0x00d7) AM_READWRITE(spg_hblank_r,        spg_hblank_w)
	56	AM_RANGE(0x00d8, 0x00db) AM_READWRITE(spg_load_r,          spg_load_w)
	57	AM_RANGE(0x00dc, 0x00df) AM_READWRITE(spg_vblank_r,        spg_vblank_w)
	58	AM_RANGE(0x00e0, 0x00e3) AM_READWRITE(spg_width_r,         spg_width_w)
	59	AM_RANGE(0x00e4, 0x00e7) AM_READWRITE(text_control_r,      text_control_w)
	60	AM_RANGE(0x00e8, 0x00eb) AM_READWRITE(vo_control_r,        vo_control_w)
	61	AM_RANGE(0x00ec, 0x00ef) AM_READWRITE(vo_startx_r,         vo_startx_w)
	62	AM_RANGE(0x00f0, 0x00f3) AM_READWRITE(vo_starty_r,         vo_starty_w)
	63	AM_RANGE(0x00f4, 0x00f7) AM_READWRITE(scaler_ctl_r,        scaler_ctl_w)
	64	AM_RANGE(0x0108, 0x010b) AM_READWRITE(pal_ram_ctrl_r,      pal_ram_ctrl_w)
65	65	AM_RANGE(0x010c, 0x010f) AM_READ(     spg_status_r)
66		// 110 = fb_burstctrl
67		// 118 = y_coeff
68		// 11c = pt_alpha_ref
69
70		AM_RANGE(0x0124, 0x0127) AM_READWRITE(ta_ol_base_r,       ta_ol_base_w)
71		AM_RANGE(0x0128, 0x012b) AM_READWRITE(ta_isp_base_r,      ta_isp_base_w)
72		AM_RANGE(0x012c, 0x012f) AM_READWRITE(ta_ol_limit_r,      ta_ol_limit_w)
73		AM_RANGE(0x0130, 0x0133) AM_READWRITE(ta_isp_limit_r,     ta_isp_limit_w)
	66	AM_RANGE(0x0110, 0x0113) AM_READWRITE(fb_burstctrl_r,      fb_burstctrl_w)
	67	AM_RANGE(0x0118, 0x011b) AM_READWRITE(y_coeff_r,           y_coeff_w)
	68	AM_RANGE(0x011c, 0x011f) AM_READWRITE(pt_alpha_ref_r,      pt_alpha_ref_w)
	69	AM_RANGE(0x0124, 0x0127) AM_READWRITE(ta_ol_base_r,        ta_ol_base_w)
	70	AM_RANGE(0x0128, 0x012b) AM_READWRITE(ta_isp_base_r,       ta_isp_base_w)
	71	AM_RANGE(0x012c, 0x012f) AM_READWRITE(ta_ol_limit_r,       ta_ol_limit_w)
	72	AM_RANGE(0x0130, 0x0133) AM_READWRITE(ta_isp_limit_r,      ta_isp_limit_w)
74	73	AM_RANGE(0x0134, 0x0137) AM_READ(     ta_next_opb_r)
75	74	AM_RANGE(0x0138, 0x013b) AM_READ(     ta_itp_current_r)
76		// 13c = ta_glob_tile_clip
77		AM_RANGE(0x0140, 0x0143) AM_READWRITE(ta_alloc_ctrl_r,    ta_alloc_ctrl_w)
78		AM_RANGE(0x0144, 0x0147) AM_READWRITE(ta_list_init_r,     ta_list_init_w)
79		AM_RANGE(0x0148, 0x014b) AM_READWRITE(ta_yuv_tex_base_r,  ta_yuv_tex_base_w)
80		AM_RANGE(0x014c, 0x014f) AM_READWRITE(ta_yuv_tex_ctrl_r,  ta_yuv_tex_ctrl_w)
81		AM_RANGE(0x0150, 0x0153) AM_READWRITE(ta_yuv_tex_cnt_r,   ta_yuv_tex_cnt_w)
82		AM_RANGE(0x0160, 0x0163) AM_WRITE(    ta_list_cont_w)
83		AM_RANGE(0x0164, 0x0167) AM_READWRITE(ta_next_opb_init_r, ta_next_opb_init_w)
	75	AM_RANGE(0x013c, 0x013f) AM_READWRITE(ta_glob_tile_clip_r, ta_glob_tile_clip_w)
	76	AM_RANGE(0x0140, 0x0143) AM_READWRITE(ta_alloc_ctrl_r,     ta_alloc_ctrl_w)
	77	AM_RANGE(0x0144, 0x0147) AM_READWRITE(ta_list_init_r,      ta_list_init_w)
	78	AM_RANGE(0x0148, 0x014b) AM_READWRITE(ta_yuv_tex_base_r,   ta_yuv_tex_base_w)
	79	AM_RANGE(0x014c, 0x014f) AM_READWRITE(ta_yuv_tex_ctrl_r,   ta_yuv_tex_ctrl_w)
	80	AM_RANGE(0x0150, 0x0153) AM_READ(     ta_yuv_tex_cnt_r)
	81	AM_RANGE(0x0160, 0x0163) AM_READWRITE(ta_list_cont_r,      ta_list_cont_w)
	82	AM_RANGE(0x0164, 0x0167) AM_READWRITE(ta_next_opb_init_r,  ta_next_opb_init_w)
84	83
85		AM_RANGE(0x0200, 0x03ff) AM_READWRITE(fog_table_r,        fog_table_w)
86		AM_RANGE(0x1000, 0x1fff) AM_READWRITE(palette_r,          palette_w)
	84	AM_RANGE(0x0200, 0x03ff) AM_READWRITE(fog_table_r,         fog_table_w)
	85	AM_RANGE(0x0600, 0x0f5f) AM_READ     (ta_ol_pointers_1_r)
	86	AM_RANGE(0x1000, 0x1fff) AM_READWRITE(palette_r,           palette_w)
	87	AM_RANGE(0x2000, 0x295f) AM_READ     (ta_ol_pointers_2_r)
87	88	ADDRESS_MAP_END
88	89
89	90	DEVICE_ADDRESS_MAP_START(pd_dma_map, 32, powervr2_device)
90		AM_RANGE(0x00,   0x03)   AM_READWRITE(sb_pdstap_r,        sb_pdstap_w)
91		AM_RANGE(0x04,   0x07)   AM_READWRITE(sb_pdstar_r,        sb_pdstar_w)
92		AM_RANGE(0x08,   0x0b)   AM_READWRITE(sb_pdlen_r,         sb_pdlen_w)
93		AM_RANGE(0x0c,   0x0f)   AM_READWRITE(sb_pddir_r,         sb_pddir_w)
94		AM_RANGE(0x10,   0x13)   AM_READWRITE(sb_pdtsel_r,        sb_pdtsel_w)
95		AM_RANGE(0x14,   0x17)   AM_READWRITE(sb_pden_r,          sb_pden_w)
96		AM_RANGE(0x18,   0x1b)   AM_READWRITE(sb_pdst_r,          sb_pdst_w)
97		AM_RANGE(0x80,   0x83)   AM_READWRITE(sb_pdapro_r,        sb_pdapro_w)
	91	AM_RANGE(0x00,   0x03)   AM_READWRITE(sb_pdstap_r,         sb_pdstap_w)
	92	AM_RANGE(0x04,   0x07)   AM_READWRITE(sb_pdstar_r,         sb_pdstar_w)
	93	AM_RANGE(0x08,   0x0b)   AM_READWRITE(sb_pdlen_r,          sb_pdlen_w)
	94	AM_RANGE(0x0c,   0x0f)   AM_READWRITE(sb_pddir_r,          sb_pddir_w)
	95	AM_RANGE(0x10,   0x13)   AM_READWRITE(sb_pdtsel_r,         sb_pdtsel_w)
	96	AM_RANGE(0x14,   0x17)   AM_READWRITE(sb_pden_r,           sb_pden_w)
	97	AM_RANGE(0x18,   0x1b)   AM_READWRITE(sb_pdst_r,           sb_pdst_w)
	98	AM_RANGE(0x80,   0x83)   AM_READWRITE(sb_pdapro_r,         sb_pdapro_w)
98	99	ADDRESS_MAP_END
99	100
100	101	const int powervr2_device::pvr_parconfseq[] = {1,2,3,2,3,4,5,6,5,6,7,8,9,10,11,12,13,14,13,14,15,16,17,16,17,0,0,0,0,0,18,19,20,19,20,21,22,23,22,23};
r243804	r243805
891	892
892	893	}
893	894
	895	READ64_MEMBER(  powervr2_device::tex64_r )
	896	{
	897	if(offset & 0x100000)
	898	offset ^= 0x300000;
	899	return (UINT64(tex32_r(space, offset | 0x100000, mem_mask >> 32)) << 32) | tex32_r(space, offset, mem_mask);
	900	}
	901
	902	WRITE64_MEMBER( powervr2_device::tex64_w )
	903	{
	904	if(offset & 0x100000)
	905	offset ^= 0x300000;
	906	if(ACCESSING_BITS_0_31)
	907	tex32_w(space, offset           , data      , mem_mask      );
	908	if(ACCESSING_BITS_32_63)
	909	tex32_w(space, offset | 0x100000, data >> 32, mem_mask >> 32);
	910	}
	911
	912	READ32_MEMBER(  powervr2_device::tex32_r )
	913	{
	914	return sdram[offset];
	915	}
	916
	917	WRITE32_MEMBER( powervr2_device::tex32_w )
	918	{
	919	COMBINE_DATA(sdram+offset);
	920	//   logerror("%s: rec tex32_w %06x %08x\n", tag(), offset, sdram[offset]);
	921	}
	922
894	923	READ32_MEMBER( powervr2_device::id_r )
895	924	{
896	925	return 0x17fd11db;
r243804	r243805
933	962	}
934	963	}
935	964
	965	READ32_MEMBER( powervr2_device::startrender_r )
	966	{
	967	return 0;
	968	}
	969
936	970	WRITE32_MEMBER( powervr2_device::startrender_w )
937	971	{
	972	static const int list_order[5] = { 0, 4, 1, 2, 3 };
	973	logerror("%s: rec startrender_w %08x\n", tag(), data);
	974
	975	UINT32 region_data = (region_base >> 2) & 0x3fffff;
	976	bool alt_mode = !(fpu_param_cfg & 0x00200000);
	977	int num_list = alt_mode ? 4 : 5;
	978	for(;;) {
	979	UINT32 head = sdram[region_data];
	980	int xtile = (head & 0xfc) >> 2;
	981	int ytile = (head & 0x3f00) >> 8;
	982	bool zclear = alt_mode ? false : head & 0x40000000;
	983	bool presort = alt_mode ? isp_feed_cfg & 0x00000001 : head & 0x20000000;
	984	bool flushacc = alt_mode ? false : head & 0x10000000;
	985
	986	logerror("%s: xt %d yt %d zc %d ps %d fa %d %s\n",
	987	tag(), xtile, ytile, zclear, presort, flushacc, head & 0x80000000 ? "end" : "next");
	988
	989	region_data++;
	990	for(int list_idx = 0; list_idx < num_list; list_idx++) {
	991	int list_id = alt_mode ? list_idx : list_order[list_idx];
	992	logerror("%s:  %d: %08x\n", tag(), list_id, sdram[region_data + list_id]);
	993	}
	994	region_data += num_list;
	995
	996	if(head & 0x80000000)
	997	break;
	998	}
	999
	1000	exit(0);
	1001	#if 0
938	1002	dc_state *state = machine().driver_data<dc_state>();
939	1003	g_profiler.start(PROFILER_USER1);
940	1004	#if DEBUG_PVRTA
r243804	r243805
1006	1070	}
1007	1071	//          printf("ISP START %d %d\n",sanitycount,m_screen->vpos());
1008	1072	/* Fire ISP irq after a set amount of time TODO: timing of this */
1009		endofrender_timer_isp->adjust(state->m_maincpu->cycles_to_attotime(sanitycount*25));
1010	1073	break;
1011	1074	}
1012	1075	}
	1076	#endif
	1077	endofrender_timer_isp->adjust(machine().driver_data<dc_state>()->m_maincpu->cycles_to_attotime(2500));
1013	1078	}
1014	1079
	1080	READ32_MEMBER( powervr2_device::test_select_r )
	1081	{
	1082	return test_select;
	1083	}
1015	1084
	1085	WRITE32_MEMBER( powervr2_device::test_select_w )
	1086	{
	1087	logerror("%s: rec test_select_w %08x\n", tag(), data);
	1088	COMBINE_DATA(&test_select);
	1089	}
	1090
1016	1091	READ32_MEMBER( powervr2_device::param_base_r )
1017	1092	{
1018	1093	return param_base;
r243804	r243805
1020	1095
1021	1096	WRITE32_MEMBER( powervr2_device::param_base_w )
1022	1097	{
	1098	logerror("%s: rec param_base_w %08x\n", tag(), data);
1023	1099	COMBINE_DATA(&param_base);
1024	1100	}
1025	1101
r243804	r243805
1030	1106
1031	1107	WRITE32_MEMBER( powervr2_device::region_base_w )
1032	1108	{
	1109	logerror("%s: rec region_base_w %08x\n", tag(), data);
1033	1110	COMBINE_DATA(&region_base);
1034	1111	}
1035	1112
	1113	READ32_MEMBER( powervr2_device::span_sort_cfg_r )
	1114	{
	1115	return span_sort_cfg;
	1116	}
	1117
	1118	WRITE32_MEMBER( powervr2_device::span_sort_cfg_w )
	1119	{
	1120	logerror("%s: rec span_sort_cfg_w %08x\n", tag(), data);
	1121	COMBINE_DATA(&span_sort_cfg);
	1122	}
	1123
1036	1124	READ32_MEMBER( powervr2_device::vo_border_col_r )
1037	1125	{
1038	1126	return vo_border_col;
r243804	r243805
1040	1128
1041	1129	WRITE32_MEMBER( powervr2_device::vo_border_col_w )
1042	1130	{
	1131	logerror("%s: rec vo_border_col_w %08x\n", tag(), data);
1043	1132	COMBINE_DATA(&vo_border_col);
1044	1133	}
1045	1134
r243804	r243805
1050	1139
1051	1140	WRITE32_MEMBER( powervr2_device::fb_r_ctrl_w )
1052	1141	{
	1142	logerror("%s: rec fb_r_ctrl_w %08x\n", tag(), data);
1053	1143	COMBINE_DATA(&fb_r_ctrl);
1054	1144	}
1055	1145
r243804	r243805
1060	1150
1061	1151	WRITE32_MEMBER( powervr2_device::fb_w_ctrl_w )
1062	1152	{
	1153	logerror("%s: rec fb_w_ctrl_w %08x\n", tag(), data);
1063	1154	COMBINE_DATA(&fb_w_ctrl);
1064	1155	}
1065	1156
r243804	r243805
1070	1161
1071	1162	WRITE32_MEMBER( powervr2_device::fb_w_linestride_w )
1072	1163	{
	1164	logerror("%s: rec fb_w_linestride_w %08x\n", tag(), data);
1073	1165	COMBINE_DATA(&fb_w_linestride);
1074	1166	}
1075	1167
r243804	r243805
1080	1172
1081	1173	WRITE32_MEMBER( powervr2_device::fb_r_sof1_w )
1082	1174	{
	1175	logerror("%s: rec fb_r_sof1_w %08x\n", tag(), data);
1083	1176	COMBINE_DATA(&fb_r_sof1);
1084	1177	}
1085	1178
r243804	r243805
1090	1183
1091	1184	WRITE32_MEMBER( powervr2_device::fb_r_sof2_w )
1092	1185	{
	1186	logerror("%s: rec fb_r_sof2_w %08x\n", tag(), data);
1093	1187	COMBINE_DATA(&fb_r_sof2);
1094	1188	}
1095	1189
r243804	r243805
1100	1194
1101	1195	WRITE32_MEMBER( powervr2_device::fb_r_size_w )
1102	1196	{
	1197	logerror("%s: rec fb_r_size_w %08x\n", tag(), data);
1103	1198	COMBINE_DATA(&fb_r_size);
1104	1199	}
1105	1200
r243804	r243805
1110	1205
1111	1206	WRITE32_MEMBER( powervr2_device::fb_w_sof1_w )
1112	1207	{
	1208	logerror("%s: rec fb_w_sof1_w %08x\n", tag(), data);
1113	1209	COMBINE_DATA(&fb_w_sof1);
1114	1210	}
1115	1211
r243804	r243805
1120	1216
1121	1217	WRITE32_MEMBER( powervr2_device::fb_w_sof2_w )
1122	1218	{
	1219	logerror("%s: rec fb_w_sof2_w %08x\n", tag(), data);
1123	1220	COMBINE_DATA(&fb_w_sof2);
1124	1221	}
1125	1222
r243804	r243805
1130	1227
1131	1228	WRITE32_MEMBER( powervr2_device::fb_x_clip_w )
1132	1229	{
	1230	logerror("%s: rec fb_x_clip_w %08x\n", tag(), data);
1133	1231	COMBINE_DATA(&fb_x_clip);
1134	1232	}
1135	1233
r243804	r243805
1140	1238
1141	1239	WRITE32_MEMBER( powervr2_device::fb_y_clip_w )
1142	1240	{
	1241	logerror("%s: rec fb_y_clip_w %08x\n", tag(), data);
1143	1242	COMBINE_DATA(&fb_y_clip);
1144	1243	}
1145	1244
	1245	READ32_MEMBER( powervr2_device::fpu_shad_scale_r )
	1246	{
	1247	return fpu_shad_scale;
	1248	}
	1249
	1250	WRITE32_MEMBER( powervr2_device::fpu_shad_scale_w )
	1251	{
	1252	logerror("%s: rec fpu_shad_scale_w %08x\n", tag(), data);
	1253	COMBINE_DATA(&fpu_shad_scale);
	1254	}
	1255
	1256	READ32_MEMBER( powervr2_device::fpu_cull_val_r )
	1257	{
	1258	return fpu_cull_val;
	1259	}
	1260
	1261	WRITE32_MEMBER( powervr2_device::fpu_cull_val_w )
	1262	{
	1263	logerror("%s: rec fpu_cull_val_w %08x\n", tag(), data);
	1264	COMBINE_DATA(&fpu_cull_val);
	1265	}
	1266
1146	1267	READ32_MEMBER( powervr2_device::fpu_param_cfg_r )
1147	1268	{
1148	1269	return fpu_param_cfg;
r243804	r243805
1150	1271
1151	1272	WRITE32_MEMBER( powervr2_device::fpu_param_cfg_w )
1152	1273	{
	1274	logerror("%s: rec fpu_param_cfg_w %08x\n", tag(), data);
1153	1275	COMBINE_DATA(&fpu_param_cfg);
1154	1276	}
1155	1277
	1278	READ32_MEMBER( powervr2_device::half_offset_r )
	1279	{
	1280	return half_offset;
	1281	}
	1282
	1283	WRITE32_MEMBER( powervr2_device::half_offset_w )
	1284	{
	1285	logerror("%s: rec half_offset_w %08x\n", tag(), data);
	1286	COMBINE_DATA(&half_offset);
	1287	}
	1288
	1289	READ32_MEMBER( powervr2_device::fpu_perp_val_r )
	1290	{
	1291	return fpu_perp_val;
	1292	}
	1293
	1294	WRITE32_MEMBER( powervr2_device::fpu_perp_val_w )
	1295	{
	1296	logerror("%s: rec fpu_perp_val_w %08x\n", tag(), data);
	1297	COMBINE_DATA(&fpu_perp_val);
	1298	}
	1299
	1300	READ32_MEMBER( powervr2_device::isp_backgnd_d_r )
	1301	{
	1302	return isp_backgnd_d;
	1303	}
	1304
	1305	WRITE32_MEMBER( powervr2_device::isp_backgnd_d_w )
	1306	{
	1307	logerror("%s: rec isp_backgnd_d_w %08x\n", tag(), data);
	1308	COMBINE_DATA(&isp_backgnd_d);
	1309	}
	1310
1156	1311	READ32_MEMBER( powervr2_device::isp_backgnd_t_r )
1157	1312	{
1158	1313	return isp_backgnd_t;
r243804	r243805
1160	1315
1161	1316	WRITE32_MEMBER( powervr2_device::isp_backgnd_t_w )
1162	1317	{
	1318	logerror("%s: rec isp_backgnd_t_w %08x\n", tag(), data);
1163	1319	COMBINE_DATA(&isp_backgnd_t);
1164	1320	}
1165	1321
	1322	READ32_MEMBER( powervr2_device::isp_feed_cfg_r )
	1323	{
	1324	return isp_feed_cfg;
	1325	}
	1326
	1327	WRITE32_MEMBER( powervr2_device::isp_feed_cfg_w )
	1328	{
	1329	logerror("%s: rec isp_feed_cfg_w %08x\n", tag(), data);
	1330	COMBINE_DATA(&isp_feed_cfg);
	1331	}
	1332
	1333	READ32_MEMBER( powervr2_device::sdram_refresh_r )
	1334	{
	1335	return sdram_refresh;
	1336	}
	1337
	1338	WRITE32_MEMBER( powervr2_device::sdram_refresh_w )
	1339	{
	1340	logerror("%s: rec sdram_refresh_w %08x\n", tag(), data);
	1341	COMBINE_DATA(&sdram_refresh);
	1342	}
	1343
	1344	READ32_MEMBER( powervr2_device::sdram_arb_cfg_r )
	1345	{
	1346	return sdram_arb_cfg;
	1347	}
	1348
	1349	WRITE32_MEMBER( powervr2_device::sdram_arb_cfg_w )
	1350	{
	1351	logerror("%s: rec sdram_arb_cfg_w %08x\n", tag(), data);
	1352	COMBINE_DATA(&sdram_arb_cfg);
	1353	}
	1354
	1355	READ32_MEMBER( powervr2_device::sdram_cfg_r )
	1356	{
	1357	return sdram_cfg;
	1358	}
	1359
	1360	WRITE32_MEMBER( powervr2_device::sdram_cfg_w )
	1361	{
	1362	logerror("%s: rec sdram_cfg_w %08x\n", tag(), data);
	1363	COMBINE_DATA(&sdram_cfg);
	1364	}
	1365
	1366	READ32_MEMBER( powervr2_device::fog_col_ram_r )
	1367	{
	1368	return fog_col_ram;
	1369	}
	1370
	1371	WRITE32_MEMBER( powervr2_device::fog_col_ram_w )
	1372	{
	1373	logerror("%s: rec fog_col_ram_w %08x\n", tag(), data);
	1374	COMBINE_DATA(&fog_col_ram);
	1375	}
	1376
	1377	READ32_MEMBER( powervr2_device::fog_col_vert_r )
	1378	{
	1379	return fog_col_vert;
	1380	}
	1381
	1382	WRITE32_MEMBER( powervr2_device::fog_col_vert_w )
	1383	{
	1384	logerror("%s: rec fog_col_vert_w %08x\n", tag(), data);
	1385	COMBINE_DATA(&fog_col_vert);
	1386	}
	1387
	1388	READ32_MEMBER( powervr2_device::fog_density_r )
	1389	{
	1390	return fog_density;
	1391	}
	1392
	1393	WRITE32_MEMBER( powervr2_device::fog_density_w )
	1394	{
	1395	logerror("%s: rec fog_density_w %08x\n", tag(), data);
	1396	COMBINE_DATA(&fog_density);
	1397	}
	1398
	1399	READ32_MEMBER( powervr2_device::fog_clamp_max_r )
	1400	{
	1401	return fog_clamp_max;
	1402	}
	1403
	1404	WRITE32_MEMBER( powervr2_device::fog_clamp_max_w )
	1405	{
	1406	logerror("%s: rec fog_clamp_max_w %08x\n", tag(), data);
	1407	COMBINE_DATA(&fog_clamp_max);
	1408	}
	1409
	1410	READ32_MEMBER( powervr2_device::fog_clamp_min_r )
	1411	{
	1412	return fog_clamp_min;
	1413	}
	1414
	1415	WRITE32_MEMBER( powervr2_device::fog_clamp_min_w )
	1416	{
	1417	logerror("%s: rec fog_clamp_min_w %08x\n", tag(), data);
	1418	COMBINE_DATA(&fog_clamp_min);
	1419	}
	1420
	1421	READ32_MEMBER( powervr2_device::spg_trigger_pos_r )
	1422	{
	1423	return spg_trigger_pos;
	1424	}
	1425
	1426	WRITE32_MEMBER( powervr2_device::spg_trigger_pos_w )
	1427	{
	1428	logerror("%s: rec spg_trigger_pos_w %08x\n", tag(), data);
	1429	COMBINE_DATA(&spg_trigger_pos);
	1430	}
	1431
1166	1432	READ32_MEMBER( powervr2_device::spg_hblank_int_r )
1167	1433	{
1168	1434	return spg_hblank_int;
r243804	r243805
1170	1436
1171	1437	WRITE32_MEMBER( powervr2_device::spg_hblank_int_w )
1172	1438	{
	1439	logerror("%s: rec spg_hblank_int_w %08x\n", tag(), data);
1173	1440	COMBINE_DATA(&spg_hblank_int);
1174	1441	/* TODO: timer adjust */
1175	1442	}
r243804	r243805
1181	1448
1182	1449	WRITE32_MEMBER( powervr2_device::spg_vblank_int_w )
1183	1450	{
	1451	logerror("%s: rec spg_vblank_int_w %08x\n", tag(), data);
1184	1452	COMBINE_DATA(&spg_vblank_int);
1185	1453
1186	1454	/* clear pending irqs and modify them with the updated ones */
r243804	r243805
1198	1466
1199	1467	WRITE32_MEMBER( powervr2_device::spg_control_w )
1200	1468	{
	1469	logerror("%s: rec spg_control_w %08x\n", tag(), data);
1201	1470	COMBINE_DATA(&spg_control);
1202	1471	update_screen_format();
1203	1472
r243804	r243805
1215	1484
1216	1485	WRITE32_MEMBER( powervr2_device::spg_hblank_w )
1217	1486	{
	1487	logerror("%s: rec spg_hblank_w %08x\n", tag(), data);
1218	1488	COMBINE_DATA(&spg_hblank);
1219	1489	update_screen_format();
1220	1490	}
r243804	r243805
1226	1496
1227	1497	WRITE32_MEMBER( powervr2_device::spg_load_w )
1228	1498	{
	1499	logerror("%s: rec spg_load_w %08x\n", tag(), data);
1229	1500	COMBINE_DATA(&spg_load);
1230	1501	update_screen_format();
1231	1502	}
r243804	r243805
1237	1508
1238	1509	WRITE32_MEMBER( powervr2_device::spg_vblank_w )
1239	1510	{
	1511	logerror("%s: rec spg_vblank_w %08x\n", tag(), data);
1240	1512	COMBINE_DATA(&spg_vblank);
1241	1513	update_screen_format();
1242	1514	}
r243804	r243805
1248	1520
1249	1521	WRITE32_MEMBER( powervr2_device::spg_width_w )
1250	1522	{
	1523	logerror("%s: rec spg_width_w %08x\n", tag(), data);
1251	1524	COMBINE_DATA(&spg_width);
1252	1525	update_screen_format();
1253	1526	}
r243804	r243805
1259	1532
1260	1533	WRITE32_MEMBER( powervr2_device::text_control_w )
1261	1534	{
	1535	logerror("%s: rec text_control_w %08x\n", tag(), data);
1262	1536	COMBINE_DATA(&text_control);
1263	1537	}
1264	1538
r243804	r243805
1269	1543
1270	1544	WRITE32_MEMBER( powervr2_device::vo_control_w )
1271	1545	{
	1546	logerror("%s: rec vo_control_w %08x\n", tag(), data);
1272	1547	COMBINE_DATA(&vo_control);
1273	1548	}
1274	1549
r243804	r243805
1279	1554
1280	1555	WRITE32_MEMBER( powervr2_device::vo_startx_w )
1281	1556	{
	1557	logerror("%s: rec vo_startx_w %08x\n", tag(), data);
1282	1558	COMBINE_DATA(&vo_startx);
1283	1559	update_screen_format();
1284	1560	}
r243804	r243805
1290	1566
1291	1567	WRITE32_MEMBER( powervr2_device::vo_starty_w )
1292	1568	{
	1569	logerror("%s: rec vo_starty_w %08x\n", tag(), data);
1293	1570	COMBINE_DATA(&vo_starty);
1294	1571	update_screen_format();
1295	1572	}
1296	1573
	1574	READ32_MEMBER( powervr2_device::scaler_ctl_r )
	1575	{
	1576	return scaler_ctl;
	1577	}
	1578
	1579	WRITE32_MEMBER( powervr2_device::scaler_ctl_w )
	1580	{
	1581	logerror("%s: rec scaler_ctl_w %08x\n", tag(), data);
	1582	COMBINE_DATA(&scaler_ctl);
	1583	}
	1584
1297	1585	READ32_MEMBER( powervr2_device::pal_ram_ctrl_r )
1298	1586	{
1299	1587	return pal_ram_ctrl;
r243804	r243805
1301	1589
1302	1590	WRITE32_MEMBER( powervr2_device::pal_ram_ctrl_w )
1303	1591	{
	1592	logerror("%s: rec pal_ram_ctrl_w %08x\n", tag(), data);
1304	1593	COMBINE_DATA(&pal_ram_ctrl);
1305	1594	}
1306	1595
r243804	r243805
1324	1613	return (vsync << 13) | (hsync << 12) | (blank << 11) | (fieldnum << 10) | (m_screen->vpos() & 0x3ff);
1325	1614	}
1326	1615
	1616	READ32_MEMBER( powervr2_device::fb_burstctrl_r )
	1617	{
	1618	return fb_burstctrl;
	1619	}
1327	1620
	1621	WRITE32_MEMBER( powervr2_device::fb_burstctrl_w )
	1622	{
	1623	logerror("%s: rec fb_burstctrl_w %08x\n", tag(), data);
	1624	COMBINE_DATA(&fb_burstctrl);
	1625	}
	1626
	1627	READ32_MEMBER( powervr2_device::y_coeff_r )
	1628	{
	1629	return y_coeff;
	1630	}
	1631
	1632	WRITE32_MEMBER( powervr2_device::y_coeff_w )
	1633	{
	1634	logerror("%s: rec y_coeff_w %08x\n", tag(), data);
	1635	COMBINE_DATA(&y_coeff);
	1636	}
	1637
	1638	READ32_MEMBER( powervr2_device::pt_alpha_ref_r )
	1639	{
	1640	return pt_alpha_ref;
	1641	}
	1642
	1643	WRITE32_MEMBER( powervr2_device::pt_alpha_ref_w )
	1644	{
	1645	logerror("%s: rec pt_alpha_ref_w %08x\n", tag(), data);
	1646	COMBINE_DATA(&pt_alpha_ref);
	1647	}
	1648
1328	1649	READ32_MEMBER( powervr2_device::ta_ol_base_r )
1329	1650	{
1330	1651	return ta_ol_base;
r243804	r243805
1332	1653
1333	1654	WRITE32_MEMBER( powervr2_device::ta_ol_base_w )
1334	1655	{
	1656	logerror("%s: rec ta_ol_base_w %08x\n", tag(), data);
1335	1657	COMBINE_DATA(&ta_ol_base);
1336	1658	}
1337	1659
r243804	r243805
1342	1664
1343	1665	WRITE32_MEMBER( powervr2_device::ta_isp_base_w )
1344	1666	{
	1667	logerror("%s: rec ta_isp_base_w %08x\n", tag(), data);
1345	1668	COMBINE_DATA(&ta_isp_base);
1346	1669	}
1347	1670
r243804	r243805
1352	1675
1353	1676	WRITE32_MEMBER( powervr2_device::ta_ol_limit_w )
1354	1677	{
	1678	logerror("%s: rec ta_ol_limit_w %08x\n", tag(), data);
1355	1679	COMBINE_DATA(&ta_ol_limit);
1356	1680	}
1357	1681
r243804	r243805
1362	1686
1363	1687	WRITE32_MEMBER( powervr2_device::ta_isp_limit_w )
1364	1688	{
	1689	logerror("%s: rec ta_isp_limit_w %08x\n", tag(), data);
1365	1690	COMBINE_DATA(&ta_isp_limit);
1366	1691	}
1367	1692
r243804	r243805
1375	1700	return ta_itp_current;
1376	1701	}
1377	1702
	1703	READ32_MEMBER( powervr2_device::ta_glob_tile_clip_r )
	1704	{
	1705	return ta_glob_tile_clip;
	1706	}
	1707
	1708	WRITE32_MEMBER( powervr2_device::ta_glob_tile_clip_w )
	1709	{
	1710	logerror("%s: rec ta_glob_tile_clip_w %08x\n", tag(), data);
	1711	COMBINE_DATA(&ta_glob_tile_clip);
	1712	}
	1713
1378	1714	READ32_MEMBER( powervr2_device::ta_alloc_ctrl_r )
1379	1715	{
1380	1716	return ta_alloc_ctrl;
r243804	r243805
1382	1718
1383	1719	WRITE32_MEMBER( powervr2_device::ta_alloc_ctrl_w )
1384	1720	{
	1721	logerror("%s: rec ta_alloc_ctrl_w %08x\n", tag(), data);
1385	1722	COMBINE_DATA(&ta_alloc_ctrl);
1386	1723	}
1387	1724
	1725	// Dummy read required after write for internal powervr reasons says the manual
1388	1726	READ32_MEMBER( powervr2_device::ta_list_init_r )
1389	1727	{
1390		return 0; //bit 31 always return 0, a probable left-over in Crazy Taxi reads this and discards the read (?)
	1728	return 0;
1391	1729	}
1392	1730
	1731	void powervr2_device::ta_list_start()
	1732	{
	1733	ta_list_idx = -1;
	1734	ta_next_list();
	1735	ta_olist_pos_base = ta_olist_pos = ta_ol_base;
	1736	memset(ta_ol_pointers_1, 0, sizeof(ta_ol_pointers_1));
	1737	}
	1738
1393	1739	WRITE32_MEMBER( powervr2_device::ta_list_init_w )
1394	1740	{
	1741	logerror("%s: rec ta_list_init_w %08x\n", tag(), data);
1395	1742	if(data & 0x80000000) {
	1743	ta_next_opb = ta_next_opb_init;
	1744	ta_itp_current = ta_isp_base;
	1745	ta_list_start();
	1746	}
	1747
	1748	#if 0
	1749	if(data & 0x80000000) {
1396	1750	tafifo_pos=0;
1397	1751	tafifo_mask=7;
1398	1752	tafifo_vertexwords=8;
r243804	r243805
1446	1800
1447	1801	g_profiler.stop();
1448	1802	}
	1803	#endif
1449	1804	}
1450	1805
1451	1806
r243804	r243805
1456	1811
1457	1812	WRITE32_MEMBER( powervr2_device::ta_yuv_tex_base_w )
1458	1813	{
	1814	logerror("%s: rec ta_yuv_tex_base_w %08x\n", tag(), data);
1459	1815	COMBINE_DATA(&ta_yuv_tex_base);
1460		logerror("%s: ta_yuv_tex_base = %08x\n", tag(), ta_yuv_tex_base);
1461	1816
1462	1817	ta_yuv_index = 0;
1463	1818	ta_yuv_x = 0;
r243804	r243805
1472	1827
1473	1828	WRITE32_MEMBER( powervr2_device::ta_yuv_tex_ctrl_w )
1474	1829	{
	1830	logerror("%s: rec ta_yuv_tex_ctrl_w %08x\n", tag(), data);
1475	1831	COMBINE_DATA(&ta_yuv_tex_ctrl);
1476	1832	ta_yuv_x_size = ((ta_yuv_tex_ctrl & 0x3f)+1)*16;
1477	1833	ta_yuv_y_size = (((ta_yuv_tex_ctrl>>8) & 0x3f)+1)*16;
1478		logerror("%s: ta_yuv_tex_ctrl = %08x\n", tag(), ta_yuv_tex_ctrl);
1479	1834	if(ta_yuv_tex_ctrl & 0x01010000)
1480	1835	fatalerror("YUV with setting %08x",ta_yuv_tex_ctrl);
1481	1836	}
r243804	r243805
1488	1843	return ta_yuv_tex_cnt;
1489	1844	}
1490	1845
1491		WRITE32_MEMBER( powervr2_device::ta_yuv_tex_cnt_w )
	1846	// Dummy read required after write for internal powervr reasons says the manual
	1847	READ32_MEMBER( powervr2_device::ta_list_cont_r )
1492	1848	{
1493		debugger_break(machine());
1494		COMBINE_DATA(&ta_yuv_tex_cnt);
	1849	return 0;
1495	1850	}
1496	1851
1497	1852	WRITE32_MEMBER( powervr2_device::ta_list_cont_w )
1498	1853	{
	1854	logerror("%s: rec ta_list_cont_w %08x\n", tag(), data);
1499	1855	if(data & 0x80000000) {
1500	1856	tafifo_listtype= -1; // no list being received
1501	1857	listtype_used |= (1+4);
r243804	r243805
1509	1865
1510	1866	WRITE32_MEMBER( powervr2_device::ta_next_opb_init_w )
1511	1867	{
	1868	logerror("%s: rec ta_next_opb_init_w %08x\n", tag(), data);
1512	1869	COMBINE_DATA(&ta_next_opb_init);
1513	1870	}
1514	1871
r243804	r243805
1523	1880	COMBINE_DATA(fog_table+offset);
1524	1881	}
1525	1882
	1883	READ32_MEMBER( powervr2_device::ta_ol_pointers_1_r )
	1884	{
	1885	return ta_ol_pointers_1[offset];
	1886	}
	1887
	1888	READ32_MEMBER( powervr2_device::ta_ol_pointers_2_r )
	1889	{
	1890	return ta_ol_pointers_2[offset];
	1891	}
	1892
1526	1893	READ32_MEMBER( powervr2_device::palette_r )
1527	1894	{
1528	1895	return palette[offset];
r243804	r243805
1700	2067
1701	2068	void powervr2_device::process_ta_fifo()
1702	2069	{
	2070	#if 0
1703	2071	/* first byte in the buffer is the Parameter Control Word
1704	2072
1705	2073	pppp pppp gggg gggg oooo oooo oooo oooo
r243804	r243805
1713	2081	receiveddata *rd = &grab[grabsel];
1714	2082
1715	2083	// Para Control
1716		paracontrol=(tafifo_buff[0] >> 24) & 0xff;
	2084	paracontrol=(ta_fifo_buf[0] >> 24) & 0xff;
1717	2085	// 0 end of list
1718	2086	// 1 user tile clip
1719	2087	// 2 object list set
r243804	r243805
1729	2097	{
1730	2098	global_paratype = paratype;
1731	2099	// Group Control
1732		groupcontrol=(tafifo_buff[0] >> 16) & 0xff;
	2100	groupcontrol=(ta_fifo_buf[0] >> 16) & 0xff;
1733	2101	groupen=(groupcontrol >> 7) & 1;
1734	2102	striplen=(groupcontrol >> 2) & 3;
1735	2103	userclip=(groupcontrol >> 0) & 3;
1736	2104	// Obj Control
1737		objcontrol=(tafifo_buff[0] >> 0) & 0xffff;
	2105	objcontrol=(ta_fifo_buf[0] >> 0) & 0xffff;
1738	2106	shadow=(objcontrol >> 7) & 1;
1739	2107	volume=(objcontrol >> 6) & 1;
1740	2108	coltype=(objcontrol >> 4) & 3;
r243804	r243805
1798	2166	{ // user tile clip
1799	2167	#if DEBUG_PVRDLIST
1800	2168	osd_printf_verbose("Para Type 1 User Tile Clip\n");
1801		osd_printf_verbose(" (%d , %d)-(%d , %d)\n", tafifo_buff[4], tafifo_buff[5], tafifo_buff[6], tafifo_buff[7]);
	2169	osd_printf_verbose(" (%d , %d)-(%d , %d)\n", ta_fifo_buf[4], ta_fifo_buf[5], ta_fifo_buf[6], ta_fifo_buf[7]);
1802	2170	#endif
1803	2171	}
1804	2172	else if (paratype == 2)
1805	2173	{ // object list set
1806	2174	#if DEBUG_PVRDLIST
1807		osd_printf_verbose("Para Type 2 Object List Set at %08x\n", tafifo_buff[1]);
1808		osd_printf_verbose(" (%d , %d)-(%d , %d)\n", tafifo_buff[4], tafifo_buff[5], tafifo_buff[6], tafifo_buff[7]);
	2175	osd_printf_verbose("Para Type 2 Object List Set at %08x\n", ta_fifo_buf[1]);
	2176	osd_printf_verbose(" (%d , %d)-(%d , %d)\n", ta_fifo_buf[4], ta_fifo_buf[5], ta_fifo_buf[6], ta_fifo_buf[7]);
1809	2177	#endif
1810	2178	}
1811	2179	else if (paratype == 3)
1812	2180	{
1813	2181	#if DEBUG_PVRDLIST
1814		osd_printf_verbose("Para Type %x Unknown!\n", tafifo_buff[0]);
	2182	osd_printf_verbose("Para Type %x Unknown!\n", ta_fifo_buf[0]);
1815	2183	#endif
1816	2184	}
1817	2185	else
r243804	r243805
1837	2205
1838	2206	if ((paratype == 4) || (paratype == 5))
1839	2207	{ // quad or polygon
1840		depthcomparemode=(tafifo_buff[1] >> 29) & 7;
1841		cullingmode=(tafifo_buff[1] >> 27) & 3;
1842		zwritedisable=(tafifo_buff[1] >> 26) & 1;
1843		cachebypass=(tafifo_buff[1] >> 21) & 1;
1844		dcalcctrl=(tafifo_buff[1] >> 20) & 1;
1845		volumeinstruction=(tafifo_buff[1] >> 29) & 7;
	2208	depthcomparemode=(ta_fifo_buf[1] >> 29) & 7;
	2209	cullingmode=(ta_fifo_buf[1] >> 27) & 3;
	2210	zwritedisable=(ta_fifo_buf[1] >> 26) & 1;
	2211	cachebypass=(ta_fifo_buf[1] >> 21) & 1;
	2212	dcalcctrl=(ta_fifo_buf[1] >> 20) & 1;
	2213	volumeinstruction=(ta_fifo_buf[1] >> 29) & 7;
1846	2214
1847		//textureusize=1 << (3+((tafifo_buff[2] >> 3) & 7));
1848		//texturevsize=1 << (3+(tafifo_buff[2] & 7));
1849		texturesizes=tafifo_buff[2] & 0x3f;
1850		blend_mode = tafifo_buff[2] >> 26;
1851		srcselect=(tafifo_buff[2] >> 25) & 1;
1852		dstselect=(tafifo_buff[2] >> 24) & 1;
1853		fogcontrol=(tafifo_buff[2] >> 22) & 3;
1854		colorclamp=(tafifo_buff[2] >> 21) & 1;
1855		use_alpha = (tafifo_buff[2] >> 20) & 1;
1856		ignoretexalpha=(tafifo_buff[2] >> 19) & 1;
1857		flipuv=(tafifo_buff[2] >> 17) & 3;
1858		clampuv=(tafifo_buff[2] >> 15) & 3;
1859		filtermode=(tafifo_buff[2] >> 13) & 3;
1860		sstexture=(tafifo_buff[2] >> 12) & 1;
1861		mmdadjust=(tafifo_buff[2] >> 8) & 1;
1862		tsinstruction=(tafifo_buff[2] >> 6) & 3;
	2215	//textureusize=1 << (3+((ta_fifo_buf[2] >> 3) & 7));
	2216	//texturevsize=1 << (3+(ta_fifo_buf[2] & 7));
	2217	texturesizes=ta_fifo_buf[2] & 0x3f;
	2218	blend_mode = ta_fifo_buf[2] >> 26;
	2219	srcselect=(ta_fifo_buf[2] >> 25) & 1;
	2220	dstselect=(ta_fifo_buf[2] >> 24) & 1;
	2221	fogcontrol=(ta_fifo_buf[2] >> 22) & 3;
	2222	colorclamp=(ta_fifo_buf[2] >> 21) & 1;
	2223	use_alpha = (ta_fifo_buf[2] >> 20) & 1;
	2224	ignoretexalpha=(ta_fifo_buf[2] >> 19) & 1;
	2225	flipuv=(ta_fifo_buf[2] >> 17) & 3;
	2226	clampuv=(ta_fifo_buf[2] >> 15) & 3;
	2227	filtermode=(ta_fifo_buf[2] >> 13) & 3;
	2228	sstexture=(ta_fifo_buf[2] >> 12) & 1;
	2229	mmdadjust=(ta_fifo_buf[2] >> 8) & 1;
	2230	tsinstruction=(ta_fifo_buf[2] >> 6) & 3;
1863	2231	if (texture == 1)
1864	2232	{
1865		textureaddress=(tafifo_buff[3] & 0x1FFFFF) << 3;
1866		scanorder=(tafifo_buff[3] >> 26) & 1;
1867		pixelformat=(tafifo_buff[3] >> 27) & 7;
1868		mipmapped=(tafifo_buff[3] >> 31) & 1;
1869		vqcompressed=(tafifo_buff[3] >> 30) & 1;
1870		strideselect=(tafifo_buff[3] >> 25) & 1;
1871		paletteselector=(tafifo_buff[3] >> 21) & 0x3F;
	2233	textureaddress=(ta_fifo_buf[3] & 0x1FFFFF) << 3;
	2234	scanorder=(ta_fifo_buf[3] >> 26) & 1;
	2235	pixelformat=(ta_fifo_buf[3] >> 27) & 7;
	2236	mipmapped=(ta_fifo_buf[3] >> 31) & 1;
	2237	vqcompressed=(ta_fifo_buf[3] >> 30) & 1;
	2238	strideselect=(ta_fifo_buf[3] >> 25) & 1;
	2239	paletteselector=(ta_fifo_buf[3] >> 21) & 0x3F;
1872	2240	#if DEBUG_PVRDLIST
1873		osd_printf_verbose(" Texture at %08x format %d\n", (tafifo_buff[3] & 0x1FFFFF) << 3, pixelformat);
	2241	osd_printf_verbose(" Texture at %08x format %d\n", (ta_fifo_buf[3] & 0x1FFFFF) << 3, pixelformat);
1874	2242	#endif
1875	2243	}
1876	2244	if (paratype == 4)
r243804	r243805
1902	2270	{
1903	2271	#if DEBUG_PVRDLIST
1904	2272	osd_printf_verbose(" Vertex modifier volume");
1905		osd_printf_verbose(" A(%f,%f,%f) B(%f,%f,%f) C(%f,%f,%f)", u2f(tafifo_buff[1]), u2f(tafifo_buff[2]),
1906		u2f(tafifo_buff[3]), u2f(tafifo_buff[4]), u2f(tafifo_buff[5]), u2f(tafifo_buff[6]), u2f(tafifo_buff[7]),
1907		u2f(tafifo_buff[8]), u2f(tafifo_buff[9]));
	2273	osd_printf_verbose(" A(%f,%f,%f) B(%f,%f,%f) C(%f,%f,%f)", u2f(ta_fifo_buf[1]), u2f(ta_fifo_buf[2]),
	2274	u2f(ta_fifo_buf[3]), u2f(ta_fifo_buf[4]), u2f(ta_fifo_buf[5]), u2f(ta_fifo_buf[6]), u2f(ta_fifo_buf[7]),
	2275	u2f(ta_fifo_buf[8]), u2f(ta_fifo_buf[9]));
1908	2276	osd_printf_verbose("\n");
1909	2277	#endif
1910	2278	}
r243804	r243805
1912	2280	{
1913	2281	#if DEBUG_PVRDLIST
1914	2282	osd_printf_verbose(" Vertex sprite");
1915		osd_printf_verbose(" A(%f,%f,%f) B(%f,%f,%f) C(%f,%f,%f) D(%f,%f,)", u2f(tafifo_buff[1]), u2f(tafifo_buff[2]),
1916		u2f(tafifo_buff[3]), u2f(tafifo_buff[4]), u2f(tafifo_buff[5]), u2f(tafifo_buff[6]), u2f(tafifo_buff[7]),
1917		u2f(tafifo_buff[8]), u2f(tafifo_buff[9]), u2f(tafifo_buff[10]), u2f(tafifo_buff[11]));
	2283	osd_printf_verbose(" A(%f,%f,%f) B(%f,%f,%f) C(%f,%f,%f) D(%f,%f,)", u2f(ta_fifo_buf[1]), u2f(ta_fifo_buf[2]),
	2284	u2f(ta_fifo_buf[3]), u2f(ta_fifo_buf[4]), u2f(ta_fifo_buf[5]), u2f(ta_fifo_buf[6]), u2f(ta_fifo_buf[7]),
	2285	u2f(ta_fifo_buf[8]), u2f(ta_fifo_buf[9]), u2f(ta_fifo_buf[10]), u2f(ta_fifo_buf[11]));
1918	2286	osd_printf_verbose("\n");
1919	2287	#endif
1920	2288	if (texture == 1)
r243804	r243805
1923	2291	{
1924	2292	strip *ts;
1925	2293	vert *tv = &rd->verts[rd->verts_size];
1926		tv[0].x = u2f(tafifo_buff[0x1]);
1927		tv[0].y = u2f(tafifo_buff[0x2]);
1928		tv[0].w = u2f(tafifo_buff[0x3]);
1929		tv[1].x = u2f(tafifo_buff[0x4]);
1930		tv[1].y = u2f(tafifo_buff[0x5]);
1931		tv[1].w = u2f(tafifo_buff[0x6]);
1932		tv[3].x = u2f(tafifo_buff[0x7]);
1933		tv[3].y = u2f(tafifo_buff[0x8]);
1934		tv[3].w = u2f(tafifo_buff[0x9]);
1935		tv[2].x = u2f(tafifo_buff[0xa]);
1936		tv[2].y = u2f(tafifo_buff[0xb]);
	2294	tv[0].x = u2f(ta_fifo_buf[0x1]);
	2295	tv[0].y = u2f(ta_fifo_buf[0x2]);
	2296	tv[0].w = u2f(ta_fifo_buf[0x3]);
	2297	tv[1].x = u2f(ta_fifo_buf[0x4]);
	2298	tv[1].y = u2f(ta_fifo_buf[0x5]);
	2299	tv[1].w = u2f(ta_fifo_buf[0x6]);
	2300	tv[3].x = u2f(ta_fifo_buf[0x7]);
	2301	tv[3].y = u2f(ta_fifo_buf[0x8]);
	2302	tv[3].w = u2f(ta_fifo_buf[0x9]);
	2303	tv[2].x = u2f(ta_fifo_buf[0xa]);
	2304	tv[2].y = u2f(ta_fifo_buf[0xb]);
1937	2305	tv[2].w = tv[0].w+tv[3].w-tv[1].w;
1938		tv[0].u = u2f(tafifo_buff[0xd] & 0xffff0000);
1939		tv[0].v = u2f(tafifo_buff[0xd] << 16);
1940		tv[1].u = u2f(tafifo_buff[0xe] & 0xffff0000);
1941		tv[1].v = u2f(tafifo_buff[0xe] << 16);
1942		tv[3].u = u2f(tafifo_buff[0xf] & 0xffff0000);
1943		tv[3].v = u2f(tafifo_buff[0xf] << 16);
	2306	tv[0].u = u2f(ta_fifo_buf[0xd] & 0xffff0000);
	2307	tv[0].v = u2f(ta_fifo_buf[0xd] << 16);
	2308	tv[1].u = u2f(ta_fifo_buf[0xe] & 0xffff0000);
	2309	tv[1].v = u2f(ta_fifo_buf[0xe] << 16);
	2310	tv[3].u = u2f(ta_fifo_buf[0xf] & 0xffff0000);
	2311	tv[3].v = u2f(ta_fifo_buf[0xf] << 16);
1944	2312	tv[2].u = tv[0].u+tv[3].u-tv[1].u;
1945	2313	tv[2].v = tv[0].v+tv[3].v-tv[1].v;
1946	2314
r243804	r243805
1957	2325	{
1958	2326	#if DEBUG_PVRDLIST
1959	2327	osd_printf_verbose(" Vertex polygon");
1960		osd_printf_verbose(" V(%f,%f,%f) T(%f,%f)", u2f(tafifo_buff[1]), u2f(tafifo_buff[2]), u2f(tafifo_buff[3]), u2f(tafifo_buff[4]), u2f(tafifo_buff[5]));
	2328	osd_printf_verbose(" V(%f,%f,%f) T(%f,%f)", u2f(ta_fifo_buf[1]), u2f(ta_fifo_buf[2]), u2f(ta_fifo_buf[3]), u2f(ta_fifo_buf[4]), u2f(ta_fifo_buf[5]));
1961	2329	osd_printf_verbose("\n");
1962	2330	#endif
1963	2331	if (rd->verts_size <= 65530)
r243804	r243805
1967	2335	/* -- this is also wildly inaccurate! */
1968	2336	vert *tv = &rd->verts[rd->verts_size];
1969	2337
1970		tv->x=u2f(tafifo_buff[1]);
1971		tv->y=u2f(tafifo_buff[2]);
1972		tv->w=u2f(tafifo_buff[3]);
1973		tv->u=u2f(tafifo_buff[4]);
1974		tv->v=u2f(tafifo_buff[5]);
	2338	tv->x=u2f(ta_fifo_buf[1]);
	2339	tv->y=u2f(ta_fifo_buf[2]);
	2340	tv->w=u2f(ta_fifo_buf[3]);
	2341	tv->u=u2f(ta_fifo_buf[4]);
	2342	tv->v=u2f(ta_fifo_buf[5]);
1975	2343	if (texture == 0)
1976	2344	{
1977	2345	if(coltype == 0)
1978		nontextured_pal_int=tafifo_buff[6];
	2346	nontextured_pal_int=ta_fifo_buf[6];
1979	2347	else if(coltype == 1)
1980	2348	{
1981		nontextured_fpal_a=u2f(tafifo_buff[4]);
1982		nontextured_fpal_r=u2f(tafifo_buff[5]);
1983		nontextured_fpal_g=u2f(tafifo_buff[6]);
1984		nontextured_fpal_b=u2f(tafifo_buff[7]);
	2349	nontextured_fpal_a=u2f(ta_fifo_buf[4]);
	2350	nontextured_fpal_r=u2f(ta_fifo_buf[5]);
	2351	nontextured_fpal_g=u2f(ta_fifo_buf[6]);
	2352	nontextured_fpal_b=u2f(ta_fifo_buf[7]);
1985	2353	}
1986	2354	}
1987	2355
r243804	r243805
2000	2368	}
2001	2369	}
2002	2370	}
	2371	#endif
2003	2372	}
2004	2373
2005		WRITE64_MEMBER( powervr2_device::ta_fifo_poly_w )
	2374	const int powervr2_device::ta_packet_len_table[VAR_COUNT*2] = {
	2375	// Command packets
	2376	8, 8, 16, 8, 8, 8,  8,  8,  8, 8, 8,  8,  8, 16, 16, 8, 8,  8,  8, 8, 8,  8,  8,  8,  8,  8, 8, 8, 8, 8,
	2377	// Vertex packets
	2378	8, 8,  8, 8, 8, 8, 16, 16, 16, 8, 8, 16, 16,  8,  8, 8, 8, 16, 16, 8, 8, 16, 16, 16, 16, 16, 8, 8, 8, 8
	2379	};
	2380
	2381	int powervr2_device::ta_get_packet_type()
2006	2382	{
2007		if (mem_mask == U64(0xffffffffffffffff))    // 64 bit
2008		{
2009		tafifo_buff[tafifo_pos]=(UINT32)data;
2010		tafifo_buff[tafifo_pos+1]=(UINT32)(data >> 32);
2011		#if DEBUG_FIFO_POLY
2012		osd_printf_debug("ta_fifo_poly_w:  Unmapped write64 %08x = %" I64FMT "x -> %08x %08x\n", 0x10000000+offset*8, data, tafifo_buff[tafifo_pos], tafifo_buff[tafifo_pos+1]);
2013		#endif
2014		tafifo_pos += 2;
	2383	UINT32 h = ta_fifo_buf[0];
	2384	switch(h >> 29) {
	2385	case 0: return CMD_END_OF_LIST;
	2386	case 1: return CMD_USER_TILE_CLIP;
	2387	case 2: return CMD_OBJECT_LIST_SET;
	2388	case 4: case 5: {
	2389	if(ta_list_type == -1) {
	2390	ta_list_type = (h >> 24) & 7;
	2391	if(ta_list_type >= 5) {
	2392	ta_list_type = -1;
	2393	return VAR_UNKNOWN;
	2394	}
	2395	}
	2396	if(ta_list_type == L_OPAQUE_SHADOW || ta_list_type == L_TRANS_SHADOW)
	2397	return SHADOW;
	2398
	2399	bool vol = h & H_DUAL;
	2400	int  col = (h & H_COLMODE) >> 4;
	2401	bool tex = h & H_TEX;
	2402	bool off = h & H_OFF;
	2403	bool cuv = h & H_COMPACT_UV;
	2404
	2405	if((h >> 29) == 5)
	2406	return tex ? SPRITE : LINE_SPRITE;
	2407
	2408	if(vol)
	2409	if(tex)
	2410	if(cuv)
	2411	switch(col) {
	2412	case 0: return TRI_T_U8_CUV_DUAL;
	2413	case 2: return TRI_T_I_GLB_CUV_DUAL;
	2414	case 3: return TRI_T_I_PREV_CUV_DUAL;
	2415	}
	2416	else
	2417	switch(col) {
	2418	case 0: return TRI_T_U8_DUAL;
	2419	case 2: return TRI_T_I_GLB_DUAL;
	2420	case 3: return TRI_T_I_PREV_DUAL;
	2421	}
	2422	else
	2423	switch(col) {
	2424	case 0: return TRI_G_U8_DUAL;
	2425	case 2: return TRI_G_I_GLB_DUAL;
	2426	case 3: return TRI_G_I_PREV_DUAL;
	2427	}
	2428	else
	2429	if(tex)
	2430	if(cuv)
	2431	switch(col) {
	2432	case 0: return TRI_T_U8_CUV;
	2433	case 1: return TRI_T_F32_CUV;
	2434	case 2: return off ? TRI_T_I_GLB_OFF_CUV : TRI_T_I_GLB_CUV;
	2435	case 3: return TRI_T_I_PREV_CUV;
	2436	}
	2437	else
	2438	switch(col) {
	2439	case 0: return TRI_T_U8;
	2440	case 1: return TRI_T_F32;
	2441	case 2: return off ? TRI_T_I_GLB_OFF : TRI_T_I_GLB;
	2442	case 3: return TRI_T_I_PREV;
	2443	}
	2444	else
	2445	switch(col) {
	2446	case 0: return TRI_G_U8;
	2447	case 1: return TRI_G_F32;
	2448	case 2: return TRI_G_I_GLB;
	2449	case 3: return TRI_G_I_PREV;
	2450	}
	2451	return VAR_UNKNOWN;
2015	2452	}
2016		else
2017		{
2018		fatalerror("ta_fifo_poly_w:  Only 64 bit writes supported!\n");
	2453	case 7: return ta_cmd_type + VAR_COUNT;
2019	2454	}
	2455	return VAR_UNKNOWN;
	2456	}
2020	2457
2021		tafifo_pos &= tafifo_mask;
	2458	const char *powervr2_device::ta_packet_type_name[VAR_COUNT] = {
	2459	"tri_g_f32",
	2460	"tri_g_i_glb",
	2461	"tri_g_i_glb_dual",
	2462	"tri_g_i_prev",
	2463	"tri_g_i_prev_dual",
	2464	"tri_g_u8",
	2465	"tri_g_u8_dual",
	2466	"tri_t_f32",
	2467	"tri_t_f32_cuv",
	2468	"tri_t_i_glb",
	2469	"tri_t_i_glb_cuv",
	2470	"tri_t_i_glb_cuv_dual",
	2471	"tri_t_i_glb_dual",
	2472	"tri_t_i_glb_off",
	2473	"tri_t_i_glb_off_cuv",
	2474	"tri_t_i_prev",
	2475	"tri_t_i_prev_cuv",
	2476	"tri_t_i_prev_cuv_dual",
	2477	"tri_t_i_prev_dual",
	2478	"tri_t_u8",
	2479	"tri_t_u8_cuv",
	2480	"tri_t_u8_cuv_dual",
	2481	"tri_t_u8_dual",
2022	2482
2023		// if the command is complete, process it
2024		if (tafifo_pos == 0)
2025		process_ta_fifo();
	2483	"shadow",
	2484	"sprite",
	2485	"line_sprite",
2026	2486
	2487	"cmd_end_of_list",
	2488	"cmd_user_tile_clip",
	2489	"cmd_object_list_set",
	2490
	2491	"var_unknown"
	2492	};
	2493
	2494	void powervr2_device::mem_write32(UINT32 adr, UINT32 val)
	2495	{
	2496	logerror("%s: write32 %08x, %08x (%g)\n", tag(), adr/4, val, u2f(val));
2027	2497	}
2028	2498
	2499	void powervr2_device::ta_object_list_extend()
	2500	{
	2501	UINT32 ptr = ta_ol_pointers_1[ta_olist_tile];
	2502	switch(ta_olist_block_size) {
	2503	case 32:  if((ptr & 0x1c) != 0x1c) return; break;
	2504	case 64:  if((ptr & 0x3c) != 0x3c) return; break;
	2505	case 128: if((ptr & 0x7c) != 0x7c) return; break;
	2506	}
	2507
	2508	logerror("%s: list extend\n", tag());
	2509	exit(0);
	2510	}
	2511
	2512	void powervr2_device::ta_add_object(UINT32 adr, bool tail)
	2513	{
	2514	UINT32 ptr = ta_ol_pointers_1[ta_olist_tile];
	2515	if(ptr & 0x80000000) {
	2516	if(!tail) {
	2517	ta_object_list_extend();
	2518	ptr = ta_ol_pointers_1[ta_olist_tile];
	2519	}
	2520	mem_write32(ptr & 0x7fffff, adr);
	2521	ta_ol_pointers_1[ta_olist_tile] = (ptr & 0xff800000) | ((ptr + 4) & 0x7fffff);
	2522
	2523	if(tail)
	2524	ta_object_list_extend();
	2525
	2526	} else {
	2527	mem_write32(ta_olist_pos, adr);
	2528	ta_ol_pointers_1[ta_olist_tile] = ((ta_olist_pos + 4) & 0x7fffff) | (ptr & 0x7f800000) | 0x80000000;
	2529	}
	2530	//   logerror("%s: ta_ol_pointers_1[%d] = %08x\n", tag(), ta_olist_tile, ta_ol_pointers_1[ta_olist_tile]);
	2531	}
	2532
	2533	void powervr2_device::ta_handle_command_draw()
	2534	{
	2535	logerror("%s: command %s %08x %08x\n",
	2536	tag(),
	2537	ta_packet_type_name[ta_packet_type],
	2538	ta_fifo_buf[0],
	2539	ta_fifo_buf[1]
	2540	);
	2541
	2542	ta_cmd_header = ta_fifo_buf[0];
	2543	ta_cmd_instr  = ta_fifo_buf[1];
	2544
	2545	if(ta_packet_type == SPRITE) {
	2546	ta_cmd_header = (ta_cmd_header & ~(H_DUAL|H_COLMODE|H_GOURAUD)) | (H_TEX|H_COMPACT_UV);
	2547	ta_cmd_instr  = (ta_cmd_instr  & ~HI_GOURAUD) | (HI_TEX|HI_COMPACT_UV);
	2548
	2549	} else if(ta_packet_type == LINE_SPRITE) {
	2550	ta_cmd_header = ta_cmd_header & ~(H_DUAL|H_COLMODE|H_GOURAUD|H_TEX|H_OFF|H_COMPACT_UV);
	2551	ta_cmd_instr  = ta_cmd_instr  & ~(HI_GOURAUD|HI_TEX|HI_COMPACT_UV);
	2552
	2553	} else if(ta_packet_type == SHADOW)
	2554	ta_cmd_header = ta_cmd_header & ~(H_DUAL|H_TEX|H_OFF|H_COMPACT_UV);
	2555
	2556	if(!(ta_cmd_header & H_TEX)) {
	2557	ta_cmd_header &= ~H_OFF;
	2558	ta_cmd_instr  &= ~HI_OFF;
	2559	}
	2560
	2561	if(ta_cmd_header & H_GROUP) {
	2562	switch((ta_cmd_header & H_GROUP) >> 18) {
	2563	case 0: ta_cmd_strip_length = 1; break;
	2564	case 1: ta_cmd_strip_length = 2; break;
	2565	case 2: ta_cmd_strip_length = 4; break;
	2566	case 3: ta_cmd_strip_length = 6; break;
	2567	}
	2568	}
	2569
	2570	ta_cmd_user_clip_mode = (ta_cmd_header & H_UCLIP) >> 16;
	2571
	2572	if(ta_packet_type == SHADOW) {
	2573	ta_cmd_tsp[0] = 0;
	2574	ta_cmd_tex[0] = 0;
	2575	} else {
	2576	ta_cmd_tsp[0] = ta_fifo_buf[2];
	2577	ta_cmd_tex[0] = ta_fifo_buf[3];
	2578	}
	2579
	2580	if(ta_packet_type == TRI_G_I_GLB_DUAL ||
	2581	ta_packet_type == TRI_G_I_PREV_DUAL ||
	2582	ta_packet_type == TRI_G_U8_DUAL ||
	2583	ta_packet_type == TRI_T_I_GLB_CUV_DUAL ||
	2584	ta_packet_type == TRI_T_I_GLB_DUAL ||
	2585	ta_packet_type == TRI_T_I_PREV_CUV_DUAL ||
	2586	ta_packet_type == TRI_T_I_PREV_DUAL ||
	2587	ta_packet_type == TRI_T_U8_CUV_DUAL ||
	2588	ta_packet_type == TRI_T_U8_DUAL) {
	2589
	2590	ta_cmd_tsp[1] = ta_fifo_buf[4];
	2591	ta_cmd_tex[1] = ta_fifo_buf[5];
	2592
	2593	} else {
	2594	ta_cmd_tsp[1] = 0;
	2595	ta_cmd_tex[1] = 0;
	2596	}
	2597
	2598	if(!(ta_cmd_header & H_TEX) && (ta_packet_type != SPRITE) && (ta_packet_type != LINE_SPRITE)) {
	2599	ta_cmd_tex[0] = 0;
	2600	ta_cmd_tex[1] = 0;
	2601	}
	2602
	2603	switch(ta_packet_type) {
	2604	case TRI_G_I_GLB:
	2605	case TRI_T_I_GLB:
	2606	case TRI_T_I_GLB_CUV:
	2607	ta_load_color_f32(ta_cmd_color_base[0], ta_fifo_buf+4);
	2608	break;
	2609	case TRI_T_I_GLB_OFF:
	2610	case TRI_T_I_GLB_OFF_CUV:
	2611	ta_load_color_f32(ta_cmd_color_base[0], ta_fifo_buf+8);
	2612	ta_load_color_f32(ta_cmd_color_offset[0], ta_fifo_buf+12);
	2613	break;
	2614	case TRI_G_I_GLB_DUAL:
	2615	case TRI_T_I_GLB_DUAL:
	2616	case TRI_T_I_GLB_CUV_DUAL:
	2617	ta_load_color_f32(ta_cmd_color_base[0], ta_fifo_buf+8);
	2618	ta_load_color_f32(ta_cmd_color_base[1], ta_fifo_buf+12);
	2619	break;
	2620	case SPRITE:
	2621	case LINE_SPRITE:
	2622	ta_cmd_color_sprite_base   = ta_fifo_buf[4];
	2623	ta_cmd_color_sprite_offset = ta_fifo_buf[5];
	2624	break;
	2625	}
	2626	}
	2627
	2628	void powervr2_device::ta_next_list()
	2629	{
	2630	for(ta_list_idx++; ta_list_idx < 5; ta_list_idx++)
	2631	if((ta_alloc_ctrl >> (4*ta_list_idx)) & 3) {
	2632	ta_olist_block_size = 16 << ((ta_alloc_ctrl >> (4*ta_list_idx)) & 3);
	2633	ta_olist_line_size = ta_olist_block_size*((ta_glob_tile_clip & 0x3f)+1);
	2634	return;
	2635	}
	2636	ta_olist_block_size = 0;
	2637	ta_vertex_count = 0;
	2638	ta_vertex_odd_tri = false;
	2639	ta_list_type = -1;
	2640	ta_vertex_shadow_first = true;
	2641	}
	2642
	2643	void powervr2_device::ta_bbox_merge(ta_bbox &bb, const ta_bbox &src) const
	2644	{
	2645	if(bb.min_x > src.min_x)
	2646	bb.min_x = src.min_x;
	2647	if(bb.min_y > src.min_y)
	2648	bb.min_y = src.min_y;
	2649	if(bb.max_x < src.max_x)
	2650	bb.max_x = src.max_x;
	2651	if(bb.max_y < src.max_y)
	2652	bb.max_y = src.max_y;
	2653	}
	2654
	2655	bool powervr2_device::ta_bbox_vertex(ta_bbox &bb, const ta_vertex *vtx, int count) const
	2656	{
	2657	bb.min_x = bb.max_x = vtx->tx();
	2658	bb.min_y = bb.max_y = vtx->ty();
	2659	for(int i=1; i<count; i++) {
	2660	int xx = vtx[i].tx();
	2661	int yy = vtx[i].ty();
	2662	if(bb.min_x > xx)
	2663	bb.min_x = xx;
	2664	if(bb.min_y > yy)
	2665	bb.min_y = yy;
	2666	if(bb.max_x < xx)
	2667	bb.max_x = xx;
	2668	if(bb.max_y < yy)
	2669	bb.max_y = yy;
	2670	}
	2671
	2672	int sx = ta_glob_tile_clip & 0x3f;
	2673	int sy = (ta_glob_tile_clip >> 16) & 0xf;
	2674	bool clipped = false;
	2675	if(bb.min_x <= sx && bb.max_x >= 0) {
	2676	if(bb.min_x <= 0)
	2677	bb.min_x = 0;
	2678	if(bb.max_x > sx)
	2679	bb.max_x = sx;
	2680	} else {
	2681	clipped = true;
	2682	if(bb.max_x < 0)
	2683	bb.min_x = bb.max_x = 0;
	2684	else
	2685	bb.min_x = bb.max_x = sx;
	2686	}
	2687	if(bb.min_y <= sy && bb.max_y >= 0) {
	2688	if(bb.min_y <= 0)
	2689	bb.min_y = 0;
	2690	if(bb.max_y > sy)
	2691	bb.max_y = sy;
	2692	} else {
	2693	clipped = true;
	2694	if(bb.max_y < 0)
	2695	bb.min_y = bb.max_y = 0;
	2696	else
	2697	bb.min_y = bb.max_y = sy;
	2698	}
	2699
	2700	return clipped;
	2701	}
	2702
	2703	UINT32 powervr2_device::ta_strip_write(bool single_tile, UINT32 &psize)
	2704	{
	2705	bool shadow = ta_list_type == L_OPAQUE_SHADOW || ta_list_type == L_TRANS_SHADOW;
	2706
	2707	UINT32 base_adr = ta_itp_current;
	2708	UINT32 adr = base_adr;
	2709
	2710	psize = 0;
	2711	if(ta_cmd_header & H_TEX)
	2712	psize += ta_cmd_header & H_COMPACT_UV ? 4 : 8;
	2713	if(!shadow)
	2714	psize += 4;
	2715	if(ta_cmd_header & H_DUAL)
	2716	psize *= 2;
	2717	psize = (psize + 12)*ta_vertex_count + 12;
	2718	if(ta_cmd_header & H_DUAL)
	2719	psize += 8;
	2720	if(adr+psize > ta_isp_limit)
	2721	return 0xffffffff;
	2722
	2723	mem_write32(adr, ta_cmd_instr | (single_tile ? 0x00200000 : 0x00000000)); adr += 4;
	2724	mem_write32(adr, ta_cmd_tsp[0]); adr += 4;
	2725	mem_write32(adr, ta_cmd_tex[0]); adr += 4;
	2726
	2727	if(ta_cmd_header & H_DUAL) {
	2728	mem_write32(adr, ta_cmd_tsp[1]); adr += 4;
	2729	mem_write32(adr, ta_cmd_tex[1]); adr += 4;
	2730	}
	2731
	2732	for(int i=0; i<ta_vertex_count; i++) {
	2733	mem_write32(adr, ta_vertex_strip[i].coords[0]); adr += 4;
	2734	mem_write32(adr, ta_vertex_strip[i].coords[1]); adr += 4;
	2735	mem_write32(adr, ta_vertex_strip[i].coords[2]); adr += 4;
	2736	if(ta_cmd_header & H_TEX) {
	2737	if(ta_cmd_header & H_COMPACT_UV) {
	2738	mem_write32(adr, ta_vertex_strip[i].uvc[0]); adr += 4;
	2739	} else {
	2740	mem_write32(adr, f2u(ta_vertex_strip[i].uv[0][0])); adr += 4;
	2741	mem_write32(adr, f2u(ta_vertex_strip[i].uv[0][1])); adr += 4;
	2742	}
	2743	}
	2744	if(!shadow) {
	2745	mem_write32(adr, ta_vertex_strip[i].color_base[0]); adr += 4;
	2746	}
	2747	if(ta_cmd_header & H_OFF) {
	2748	mem_write32(adr, ta_vertex_strip[i].color_offset[0]); adr += 4;
	2749	}
	2750	if(ta_cmd_header & H_DUAL) {
	2751	if(ta_cmd_header & H_TEX) {
	2752	if(ta_cmd_header & H_COMPACT_UV) {
	2753	mem_write32(adr, ta_vertex_strip[i].uvc[1]); adr += 4;
	2754	} else {
	2755	mem_write32(adr, f2u(ta_vertex_strip[i].uv[1][0])); adr += 4;
	2756	mem_write32(adr, f2u(ta_vertex_strip[i].uv[1][1])); adr += 4;
	2757	}
	2758	}
	2759	if(!shadow) {
	2760	mem_write32(adr, ta_vertex_strip[i].color_base[1]); adr += 4;
	2761	}
	2762	if(ta_cmd_header & H_OFF) {
	2763	mem_write32(adr, ta_vertex_strip[i].color_offset[1]); adr += 4;
	2764	}
	2765	}
	2766	}
	2767	ta_itp_current = adr;
	2768	return base_adr - (ta_isp_base & 0xfff00000);
	2769	}
	2770
	2771
	2772	void powervr2_device::ta_add_strip(UINT32 adr, UINT32 psize)
	2773	{
	2774	logerror("%s: add strip %08x\n", tag(), adr);
	2775	if(adr & 0x80000000) { // not strip, may concatenate into an array
	2776	logerror("%s: tri or quad\n", tag());
	2777	if(ta_ol_pointers_1[ta_olist_tile] & 0x40000000) {
	2778	UINT32 cache = ta_ol_pointers_2[ta_olist_tile];
	2779	bool conc = (adr & 0xc0000000) == 0x80000000; // tri or quad
	2780	logerror("%s: a %d %08x\n", tag(), conc, adr);
	2781	conc = conc && ((adr & 0xe1e00000) == (cache & 0xe1e00000)); // skip, shadow and tri/quad match
	2782	logerror("%s: b %d %08x %08x\n", tag(), conc, adr, cache);
	2783	conc = conc && ((cache & 0x1e000000) != 0x1e000000); // Max size not reached
	2784	logerror("%s: c %d %08x\n", tag(), conc, cache);
	2785	conc = conc && ((adr & 0x1fffff) == (cache & 0x1fffff) + ((((cache >> 25) & 0xf)+1)*psize >> 2)); // Data actually consecutive
	2786	logerror("%s: d %d %08x %08x\n", tag(), conc, (adr - cache) & 0x1fffff, (((cache >> 25) & 0xf)+1)*psize >> 2);
	2787	if(conc)
	2788	ta_ol_pointers_2[ta_olist_tile] += 0x2000000; // Increment the count
	2789	else {
	2790	ta_add_object(ta_ol_pointers_2[ta_olist_tile], true);
	2791	ta_ol_pointers_2[ta_olist_tile] = adr;
	2792	}
	2793
	2794	} else {
	2795	ta_ol_pointers_2[ta_olist_tile] = adr;
	2796	ta_ol_pointers_1[ta_olist_tile] |= 0x40000000;
	2797	ta_object_list_extend();
	2798	}
	2799	} else { // strip, no concatenation
	2800	if(ta_ol_pointers_1[ta_olist_tile] & 0x40000000) {
	2801	ta_add_object(ta_ol_pointers_2[ta_olist_tile], true);
	2802	ta_ol_pointers_1[ta_olist_tile] &= ~0x40000000;
	2803	}
	2804	ta_add_object(adr, false);
	2805	}
	2806	}
	2807
	2808	void powervr2_device::ta_vertex_write()
	2809	{
	2810	ta_bbox prim_bbox[6], full_bbox;
	2811	bool prim_clipped[6], full_clipped;
	2812	int prims;
	2813	UINT32 op_tag;
	2814	bool use_mask = false;
	2815	switch(ta_cmd_type) {
	2816	case SPRITE:
	2817	case LINE_SPRITE: {
	2818	prims = 1;
	2819	full_clipped = prim_clipped[0] = ta_bbox_vertex(prim_bbox[0], ta_vertex_strip, 4);
	2820	full_bbox = prim_bbox[0];
	2821	UINT32 skip =
	2822	ta_cmd_header & H_TEX ?
	2823	ta_cmd_header & H_OFF ? 27 : 23
	2824	: 19;
	2825	op_tag = 0xa0000000 | (skip << 21);
	2826	break;
	2827	}
	2828
	2829	case SHADOW: {
	2830	prims = 1;
	2831	full_clipped = prim_clipped[0] = ta_bbox_vertex(prim_bbox[0], ta_vertex_strip, 3);
	2832
	2833	if(!full_clipped && ta_vertex_shadow_first) {
	2834	ta_vertex_shadow_bbox = prim_bbox[0];
	2835	ta_vertex_shadow_first = false;
	2836	} else
	2837	ta_bbox_merge(ta_vertex_shadow_bbox, prim_bbox[0]);
	2838
	2839	if(!ta_vertex_shadow_first && (ta_cmd_instr & 0xe0000000)) {
	2840	prim_bbox[0] = ta_vertex_shadow_bbox;
	2841	full_clipped = false;
	2842	ta_vertex_shadow_first = true;
	2843	}
	2844	full_bbox = prim_bbox[0];
	2845	op_tag = 0x80000000;
	2846	break;
	2847	}
	2848
	2849	default: {
	2850	if(ta_vertex_count < 3)
	2851	return;
	2852	prims = ta_vertex_count - 2;
	2853	full_clipped = true;
	2854	for(int i=0; i<prims; i++) {
	2855	prim_clipped[i] = ta_bbox_vertex(prim_bbox[i], ta_vertex_strip+i, 3);
	2856	if(!prim_clipped[i])
	2857	full_clipped = false;
	2858	if(i)
	2859	ta_bbox_merge(full_bbox, prim_bbox[i]);
	2860	else
	2861	full_bbox = prim_bbox[i];
	2862	}
	2863	UINT32 skip =
	2864	ta_cmd_header & H_TEX ?
	2865	ta_cmd_header & H_OFF ?
	2866	ta_cmd_header & H_COMPACT_UV ? 3 : 4
	2867	: ta_cmd_header & H_COMPACT_UV ? 2 : 3
	2868	: 1;
	2869	op_tag = skip << 21;
	2870	if(prims == 1)
	2871	op_tag |= 0x80000000;
	2872	else
	2873	use_mask = true;
	2874	break;
	2875	}
	2876	}
	2877
	2878	if(full_clipped)
	2879	return;
	2880
	2881	switch(ta_cmd_user_clip_mode) {
	2882	case 2: // inside
	2883	if(full_bbox.min_x < ta_clip_min_x ||
	2884	full_bbox.max_x > ta_clip_max_x ||
	2885	full_bbox.min_y < ta_clip_min_y ||
	2886	full_bbox.max_y > ta_clip_max_y)
	2887	return;
	2888	break;
	2889
	2890	case 3: // outside
	2891	if(full_bbox.min_x >= ta_clip_min_x &&
	2892	full_bbox.max_x <= ta_clip_max_x &&
	2893	full_bbox.min_y >= ta_clip_min_y &&
	2894	full_bbox.max_y <= ta_clip_max_y)
	2895	return;
	2896	break;
	2897	}
	2898
	2899	bool single_tile = full_bbox.min_x == full_bbox.max_x && full_bbox.min_y == full_bbox.max_y;
	2900	int sx = (ta_glob_tile_clip & 0x3f) + 1;
	2901	UINT32 params_address = 0xffffffff;
	2902	UINT32 lbase =  ta_olist_pos_base + full_bbox.min_x*ta_olist_block_size + full_bbox.min_y*ta_olist_line_size;
	2903	UINT32 tbase = full_bbox.min_x + full_bbox.min_y*sx;
	2904	UINT32 psize = 0;
	2905
	2906	logerror("%s: full_bbox (%d, %d) - (%d, %d)\n", tag(),
	2907	full_bbox.min_x, full_bbox.min_y,
	2908	full_bbox.max_x, full_bbox.max_y);
	2909	for(int y = full_bbox.min_y; y <= full_bbox.max_y; y++) {
	2910	bool clip = false;
	2911	switch(ta_cmd_user_clip_mode) {
	2912	case 2: // inside
	2913	clip = y < ta_clip_min_y || y > ta_clip_max_y;
	2914	break;
	2915
	2916	case 3: // outside
	2917	clip = y >= ta_clip_min_y && y <= ta_clip_max_y;
	2918	break;
	2919	}
	2920
	2921	if(!clip) {
	2922	ta_olist_pos = lbase;
	2923	ta_olist_tile = tbase;
	2924	for(int x = full_bbox.min_x; x <= full_bbox.max_x; x++) {
	2925	clip = ta_olist_tile >= OL_POINTERS_COUNT;
	2926	switch(ta_cmd_user_clip_mode) {
	2927	case 2: // inside
	2928	clip = x < ta_clip_min_x || x > ta_clip_max_x;
	2929	break;
	2930
	2931	case 3: // outside
	2932	clip = x >= ta_clip_min_x && x <= ta_clip_max_x;
	2933	break;
	2934	}
	2935
	2936	if(!clip) {
	2937	UINT32 mask = 0;
	2938	if(use_mask)
	2939	for(int i=0; i<prims; i++)
	2940	if(!prim_clipped[i] &&
	2941	x >= prim_bbox[i].min_x &&
	2942	x <= prim_bbox[i].max_x &&
	2943	y >= prim_bbox[i].min_y &&
	2944	y <= prim_bbox[i].max_y)
	2945	mask |= 0x40000000 >> i;
	2946	if(!use_mask || mask) {
	2947	if(params_address == 0xffffffff) {
	2948	params_address = ta_strip_write(single_tile, psize);
	2949	if(params_address == 0xffffffff)
	2950	return;
	2951	logerror("%s: params_address = %08x\n", tag(), params_address);
	2952	}
	2953	UINT32 op = ((params_address >> 2) & 0x1fffff) | op_tag | mask;
	2954	ta_add_strip(op, psize);
	2955	}
	2956	}
	2957	ta_olist_pos += ta_olist_block_size;
	2958	ta_olist_tile++;
	2959	}
	2960	}
	2961	tbase += sx;
	2962	lbase += ta_olist_line_size;
	2963	}
	2964	}
	2965
	2966	void powervr2_device::ta_vertex_push()
	2967	{
	2968	int strip_size;
	2969	switch(ta_cmd_type) {
	2970	case SPRITE:
	2971	case LINE_SPRITE:
	2972	strip_size = 4;
	2973	break;
	2974	case SHADOW:
	2975	strip_size = 3;
	2976	break;
	2977	default:
	2978	strip_size = ta_cmd_strip_length + 2;
	2979	break;
	2980	}
	2981
	2982	ta_vertex_strip[ta_vertex_count++] = ta_vertex_current;
	2983
	2984	if(ta_vertex_count == strip_size || (ta_vertex_current.header & H_EOSTRIP)) {
	2985	ta_vertex_write();
	2986	if(!(ta_vertex_current.header & H_EOSTRIP)) {
	2987	if(ta_cmd_strip_length == 1) {
	2988	if(ta_vertex_odd_tri) {
	2989	ta_vertex_strip[0] = ta_vertex_strip[ta_vertex_count-3];
	2990	ta_vertex_strip[1] = ta_vertex_strip[ta_vertex_count-1];
	2991	} else {
	2992	ta_vertex_strip[0] = ta_vertex_strip[ta_vertex_count-1];
	2993	ta_vertex_strip[1] = ta_vertex_strip[ta_vertex_count-2];
	2994	}
	2995	ta_vertex_odd_tri = !ta_vertex_odd_tri;
	2996	} else {
	2997	ta_vertex_strip[0] = ta_vertex_strip[ta_vertex_count-2];
	2998	ta_vertex_strip[1] = ta_vertex_strip[ta_vertex_count-1];
	2999	}
	3000	ta_vertex_count = 2;
	3001	} else {
	3002	ta_vertex_count = 0;
	3003	ta_vertex_odd_tri = false;
	3004	}
	3005	}
	3006	}
	3007
	3008	void powervr2_device::ta_handle_vertex()
	3009	{
	3010	if(ta_cmd_type != SHADOW && ta_cmd_type != SPRITE && ta_cmd_type != LINE_SPRITE) {
	3011	ta_vertex_current.header = ta_fifo_buf[0];
	3012	ta_vertex_current.coords[0] = ta_fifo_buf[1];
	3013	ta_vertex_current.coords[1] = ta_fifo_buf[2];
	3014	ta_vertex_current.coords[2] = ta_fifo_buf[3];
	3015	}
	3016
	3017	switch(ta_cmd_type) {
	3018	case TRI_G_U8:
	3019	ta_vertex_current.color_base[0] = ta_fifo_buf[6];
	3020	ta_vertex_push();
	3021	break;
	3022
	3023	case TRI_G_F32:
	3024	ta_vertex_current.color_base[0] = ta_color_f32_to_u8(ta_fifo_buf+4);
	3025	ta_vertex_push();
	3026	break;
	3027
	3028	case TRI_G_I_GLB:
	3029	case TRI_G_I_PREV:
	3030	ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
	3031	ta_vertex_push();
	3032	break;
	3033
	3034	case TRI_G_U8_DUAL:
	3035	ta_vertex_current.color_base[0] = ta_fifo_buf[4];
	3036	ta_vertex_current.color_base[1] = ta_fifo_buf[5];
	3037	ta_vertex_push();
	3038	break;
	3039
	3040	case TRI_G_I_GLB_DUAL:
	3041	case TRI_G_I_PREV_DUAL:
	3042	ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[4]);
	3043	ta_vertex_current.color_base[1] = ta_intensity(ta_cmd_color_base[1], ta_fifo_buf[5]);
	3044	ta_vertex_push();
	3045	break;
	3046
	3047	case TRI_T_U8:
	3048	ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
	3049	ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
	3050	ta_vertex_current.color_base[0] = ta_fifo_buf[6];
	3051	ta_vertex_current.color_offset[0] = ta_fifo_buf[7];
	3052	ta_vertex_push();
	3053	break;
	3054
	3055	case TRI_T_U8_CUV:
	3056	ta_vertex_current.uvc[0] = ta_fifo_buf[4];
	3057	ta_vertex_current.color_base[0] = ta_fifo_buf[6];
	3058	ta_vertex_current.color_offset[0] = ta_fifo_buf[7];
	3059	ta_vertex_push();
	3060	break;
	3061
	3062	case TRI_T_F32:
	3063	ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
	3064	ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
	3065	ta_vertex_current.color_base[0] = ta_color_f32_to_u8(ta_fifo_buf+8);
	3066	ta_vertex_current.color_offset[0] = ta_color_f32_to_u8(ta_fifo_buf+12);
	3067	ta_vertex_push();
	3068	break;
	3069
	3070	case TRI_T_F32_CUV:
	3071	ta_vertex_current.uvc[0] = ta_fifo_buf[4];
	3072	ta_vertex_current.color_base[0] = ta_color_f32_to_u8(ta_fifo_buf+8);
	3073	ta_vertex_current.color_offset[0] = ta_color_f32_to_u8(ta_fifo_buf+12);
	3074	ta_vertex_push();
	3075	break;
	3076
	3077	case TRI_T_I_GLB:
	3078	case TRI_T_I_GLB_OFF:
	3079	case TRI_T_I_PREV:
	3080	ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
	3081	ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
	3082	ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
	3083	ta_vertex_current.color_offset[0] = ta_intensity(ta_cmd_color_offset[0], ta_fifo_buf[7]);
	3084	ta_vertex_push();
	3085	break;
	3086
	3087	case TRI_T_I_GLB_CUV:
	3088	case TRI_T_I_GLB_OFF_CUV:
	3089	case TRI_T_I_PREV_CUV:
	3090	ta_vertex_current.uvc[0] = ta_fifo_buf[4];
	3091	ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
	3092	ta_vertex_current.color_offset[0] = ta_intensity(ta_cmd_color_offset[0], ta_fifo_buf[7]);
	3093	ta_vertex_push();
	3094	break;
	3095
	3096	case TRI_T_U8_DUAL:
	3097	ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
	3098	ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
	3099	ta_vertex_current.color_base[0] = ta_fifo_buf[6];
	3100	ta_vertex_current.color_offset[0] = ta_fifo_buf[7];
	3101	ta_vertex_current.uv[1][0] = ta_fifo_buf[8];
	3102	ta_vertex_current.uv[1][1] = ta_fifo_buf[9];
	3103	ta_vertex_current.color_base[1] = ta_fifo_buf[10];
	3104	ta_vertex_current.color_offset[1] = ta_fifo_buf[11];
	3105	ta_vertex_push();
	3106	break;
	3107
	3108	case TRI_T_U8_CUV_DUAL:
	3109	ta_vertex_current.uvc[0] = ta_fifo_buf[4];
	3110	ta_vertex_current.color_base[0] = ta_fifo_buf[6];
	3111	ta_vertex_current.color_offset[0] = ta_fifo_buf[7];
	3112	ta_vertex_current.uvc[1] = ta_fifo_buf[8];
	3113	ta_vertex_current.color_base[1] = ta_fifo_buf[10];
	3114	ta_vertex_current.color_offset[1] = ta_fifo_buf[11];
	3115	ta_vertex_push();
	3116	break;
	3117
	3118	case TRI_T_I_GLB_DUAL:
	3119	case TRI_T_I_PREV_DUAL:
	3120	ta_vertex_current.uv[0][0] = ta_fifo_buf[4];
	3121	ta_vertex_current.uv[0][1] = ta_fifo_buf[5];
	3122	ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
	3123	ta_vertex_current.color_offset[0] = ta_intensity(ta_cmd_color_offset[0], ta_fifo_buf[7]);
	3124	ta_vertex_current.uv[1][0] = ta_fifo_buf[8];
	3125	ta_vertex_current.uv[1][1] = ta_fifo_buf[9];
	3126	ta_vertex_current.color_base[1] = ta_intensity(ta_cmd_color_base[1], ta_fifo_buf[10]);
	3127	ta_vertex_current.color_offset[1] = ta_intensity(ta_cmd_color_offset[1], ta_fifo_buf[11]);
	3128	ta_vertex_push();
	3129	break;
	3130
	3131	case TRI_T_I_GLB_CUV_DUAL:
	3132	case TRI_T_I_PREV_CUV_DUAL:
	3133	ta_vertex_current.uvc[0] = ta_fifo_buf[4];
	3134	ta_vertex_current.color_base[0] = ta_intensity(ta_cmd_color_base[0], ta_fifo_buf[6]);
	3135	ta_vertex_current.color_offset[0] = ta_intensity(ta_cmd_color_offset[0], ta_fifo_buf[7]);
	3136	ta_vertex_current.uvc[1] = ta_fifo_buf[8];
	3137	ta_vertex_current.color_base[1] = ta_intensity(ta_cmd_color_base[1], ta_fifo_buf[10]);
	3138	ta_vertex_current.color_offset[1] = ta_intensity(ta_cmd_color_offset[1], ta_fifo_buf[11]);
	3139	ta_vertex_push();
	3140	break;
	3141
	3142	case SPRITE:
	3143	ta_vertex_current.header = 0xe0000000;
	3144	ta_vertex_current.color_base[0] = 0;
	3145	ta_vertex_current.color_offset[0] = 0;
	3146	ta_vertex_current.coords[0] = ta_fifo_buf[1];
	3147	ta_vertex_current.coords[1] = ta_fifo_buf[2];
	3148	ta_vertex_current.coords[2] = ta_fifo_buf[3];
	3149	ta_vertex_current.uvc[0] = ta_fifo_buf[13];
	3150	ta_vertex_push();
	3151
	3152	ta_vertex_current.header = 0xe0000000;
	3153	ta_vertex_current.color_base[0] = 0;
	3154	ta_vertex_current.color_offset[0] = 0;
	3155	ta_vertex_current.coords[0] = ta_fifo_buf[4];
	3156	ta_vertex_current.coords[1] = ta_fifo_buf[5];
	3157	ta_vertex_current.coords[2] = ta_fifo_buf[6];
	3158	ta_vertex_current.uvc[0] = ta_fifo_buf[14];
	3159	ta_vertex_push();
	3160
	3161	ta_vertex_current.header = 0xe0000000;
	3162	ta_vertex_current.color_base[0] = ta_cmd_color_sprite_base;
	3163	ta_vertex_current.color_offset[0] = ta_cmd_color_sprite_offset;
	3164	ta_vertex_current.coords[0] = ta_fifo_buf[7];
	3165	ta_vertex_current.coords[1] = ta_fifo_buf[8];
	3166	ta_vertex_current.coords[2] = ta_fifo_buf[9];
	3167	ta_vertex_current.uvc[0] = ta_fifo_buf[15];
	3168	ta_vertex_push();
	3169
	3170	ta_vertex_current.header = 0xe0000000 | H_EOSTRIP;
	3171	ta_vertex_current.color_base[0] = 0;
	3172	ta_vertex_current.color_offset[0] = 0;
	3173	ta_vertex_current.coords[0] = ta_fifo_buf[10];
	3174	ta_vertex_current.coords[1] = ta_fifo_buf[11];
	3175	ta_vertex_current.coords[2] = 0;
	3176	ta_vertex_current.uvc[0] = 0;
	3177	ta_vertex_push();
	3178	break;
	3179
	3180	case LINE_SPRITE:
	3181	ta_vertex_current.header = 0xe0000000;
	3182	ta_vertex_current.color_base[0] = 0;
	3183	ta_vertex_current.coords[0] = ta_fifo_buf[1];
	3184	ta_vertex_current.coords[1] = ta_fifo_buf[2];
	3185	ta_vertex_current.coords[2] = ta_fifo_buf[3];
	3186	ta_vertex_push();
	3187
	3188	ta_vertex_current.header = 0xe0000000;
	3189	ta_vertex_current.color_base[0] = 0;
	3190	ta_vertex_current.coords[0] = ta_fifo_buf[4];
	3191	ta_vertex_current.coords[1] = ta_fifo_buf[5];
	3192	ta_vertex_current.coords[2] = ta_fifo_buf[6];
	3193	ta_vertex_push();
	3194
	3195	ta_vertex_current.header = 0xe0000000;
	3196	ta_vertex_current.color_base[0] = ta_cmd_color_sprite_base;
	3197	ta_vertex_current.coords[0] = ta_fifo_buf[7];
	3198	ta_vertex_current.coords[1] = ta_fifo_buf[8];
	3199	ta_vertex_current.coords[2] = ta_fifo_buf[9];
	3200	ta_vertex_push();
	3201
	3202	ta_vertex_current.header = 0xf0000000;
	3203	ta_vertex_current.color_base[0] = 0;
	3204	ta_vertex_current.coords[0] = ta_fifo_buf[10];
	3205	ta_vertex_current.coords[1] = ta_fifo_buf[11];
	3206	ta_vertex_current.coords[2] = 0;
	3207	ta_vertex_push();
	3208	break;
	3209
	3210	case SHADOW:
	3211	ta_vertex_current.header = 0xe0000000;
	3212	ta_vertex_current.coords[0] = ta_fifo_buf[1];
	3213	ta_vertex_current.coords[1] = ta_fifo_buf[2];
	3214	ta_vertex_current.coords[2] = ta_fifo_buf[3];
	3215	ta_vertex_push();
	3216
	3217	ta_vertex_current.header = 0xe0000000;
	3218	ta_vertex_current.coords[0] = ta_fifo_buf[4];
	3219	ta_vertex_current.coords[1] = ta_fifo_buf[5];
	3220	ta_vertex_current.coords[2] = ta_fifo_buf[6];
	3221	ta_vertex_push();
	3222
	3223	ta_vertex_current.header = 0xf0000000;
	3224	ta_vertex_current.coords[0] = ta_fifo_buf[7];
	3225	ta_vertex_current.coords[1] = ta_fifo_buf[8];
	3226	ta_vertex_current.coords[2] = ta_fifo_buf[9];
	3227	ta_vertex_push();
	3228	break;
	3229	}
	3230	}
	3231
	3232	void powervr2_device::ta_handle_command_end_of_list()
	3233	{
	3234	int sx = ta_glob_tile_clip & 0x3f;
	3235	int sy = (ta_glob_tile_clip >> 16) & 0xf;
	3236	ta_olist_tile = 0;
	3237	ta_olist_pos = ta_olist_pos_base;
	3238	for(int y=0; y<=sy; y++)
	3239	for(int x=0; x<=sx; x++) {
	3240	if(ta_olist_tile >= OL_POINTERS_COUNT)
	3241	break;
	3242	UINT32 ptr = ta_ol_pointers_1[ta_olist_tile];
	3243	if(ptr & 0x40000000) {
	3244	ta_add_object(ta_ol_pointers_2[ta_olist_tile], false);
	3245	ptr = ta_ol_pointers_1[ta_olist_tile];
	3246	}
	3247	if(!(ptr & 0x80000000))
	3248	ptr = ta_olist_pos;
	3249	else
	3250	ptr &= 0x007fffff;
	3251	mem_write32(ptr, 0xf0000000);
	3252
	3253	ta_ol_pointers_1[ta_olist_tile] = 0;
	3254
	3255	ta_olist_tile++;
	3256	ta_olist_pos += ta_olist_block_size;
	3257	}
	3258	ta_olist_pos_base = ta_olist_pos;
	3259	irq_cb(EOXFER_OPLST_IRQ + ta_list_idx);
	3260	ta_next_list();
	3261	}
	3262
	3263	void powervr2_device::ta_handle_command_user_tile_clip()
	3264	{
	3265	ta_clip_min_x = ta_fifo_buf[4];
	3266	ta_clip_min_y = ta_fifo_buf[5];
	3267	ta_clip_max_x = ta_fifo_buf[6];
	3268	ta_clip_max_y = ta_fifo_buf[7];
	3269	}
	3270
	3271	void powervr2_device::ta_handle_command_object_list_set()
	3272	{
	3273	logerror("%s: object lists unhandled\n", tag());
	3274	}
	3275
	3276
	3277	WRITE64_MEMBER( powervr2_device::ta_fifo_poly_w )
	3278	{
	3279	if (mem_mask != U64(0xffffffffffffffff))    // 64 bit
	3280	fatalerror("ta_fifo_poly_w:  Only 64 bit writes supported!\n");
	3281
	3282	logerror("%s: rec ta_fifo_poly_w %08x\n", tag(), UINT32(data));
	3283	logerror("%s: rec ta_fifo_poly_w %08x\n", tag(), UINT32(data >> 32));
	3284
	3285	if(ta_list_idx == 5)
	3286	return;
	3287
	3288	ta_fifo_buf[ta_fifo_pos]   = data;
	3289	ta_fifo_buf[ta_fifo_pos+1] = data >> 32;
	3290
	3291	if(!ta_fifo_pos) {
	3292	ta_packet_type = ta_get_packet_type();
	3293	if(ta_packet_type < VAR_COUNT)
	3294	ta_cmd_type = ta_packet_type;
	3295	ta_packet_len = ta_packet_len_table[ta_packet_type];
	3296	}
	3297
	3298	ta_fifo_pos += 2;
	3299
	3300	if (ta_fifo_pos == ta_packet_len) {
	3301	if(ta_packet_type == CMD_END_OF_LIST)
	3302	ta_handle_command_end_of_list();
	3303	else if(ta_packet_type == CMD_USER_TILE_CLIP)
	3304	ta_handle_command_user_tile_clip();
	3305	else if(ta_packet_type == CMD_OBJECT_LIST_SET)
	3306	ta_handle_command_object_list_set();
	3307	else if(ta_packet_type >= TRI_G_F32 && ta_packet_type <= LINE_SPRITE)
	3308	ta_handle_command_draw();
	3309	else if(ta_packet_type >= TRI_G_F32+VAR_COUNT && ta_packet_type <= LINE_SPRITE+VAR_COUNT)
	3310	ta_handle_vertex();
	3311
	3312	ta_fifo_pos = 0;
	3313	ta_packet_len = 0;
	3314	}
	3315	}
	3316
2029	3317	TIMER_CALLBACK_MEMBER(powervr2_device::yuv_convert_end)
2030	3318	{
2031	3319	irq_cb(EOXFER_YUV_IRQ);
r243804	r243805
3002	4290
3003	4291	void powervr2_device::pvr_drawframebuffer(bitmap_rgb32 &bitmap,const rectangle &cliprect)
3004	4292	{
	4293	#if 0
3005	4294	int x,y,dy,xi;
3006	4295	UINT32 addrp;
3007	4296	UINT32 *fbaddr;
r243804	r243805
3258	4547	}
3259	4548	break;
3260	4549	}
	4550	#endif
3261	4551	}
3262	4552
3263	4553
r243804	r243805
3626	4916	fake_accumulationbuffer_bitmap = auto_bitmap_rgb32_alloc(machine(),2048,2048);
3627	4917
3628	4918	softreset = 0;
	4919	test_select = 0;
3629	4920	param_base = 0;
3630	4921	region_base = 0;
	4922	span_sort_cfg = 0;
3631	4923	vo_border_col = 0;
3632	4924	fb_r_ctrl = 0;
3633	4925	fb_w_ctrl = 0;
r243804	r243805
3639	4931	fb_w_sof2 = 0;
3640	4932	fb_x_clip = 0;
3641	4933	fb_y_clip = 0;
	4934	fpu_shad_scale = 0;
	4935	fpu_cull_val = 0;
3642	4936	fpu_param_cfg = 0;
	4937	half_offset = 0;
	4938	fpu_perp_val = 0;
	4939	isp_backgnd_d = 0;
3643	4940	isp_backgnd_t = 0;
	4941	isp_feed_cfg = 0;
	4942	sdram_refresh = 0;
	4943	sdram_arb_cfg = 0;
	4944	sdram_cfg = 0;
	4945	fog_col_ram = 0;
	4946	fog_col_vert = 0;
	4947	fog_density = 0;
	4948	fog_clamp_max = 0;
	4949	fog_clamp_min = 0;
	4950	spg_trigger_pos = 0;
3644	4951	spg_hblank_int = 0;
3645	4952	spg_vblank_int = 0;
3646	4953	spg_hblank = 0;
r243804	r243805
3648	4955	spg_vblank = 0;
3649	4956	spg_width = 0;
3650	4957	spg_control = 0;
	4958	text_control = 0;
3651	4959	vo_control = 0;
3652	4960	vo_startx = 0;
3653	4961	vo_starty = 0;
3654		text_control = 0;
	4962	scaler_ctl = 0;
3655	4963	pal_ram_ctrl = 0;
	4964	fb_burstctrl = 0;
	4965	y_coeff = 0;
	4966	pt_alpha_ref = 255;
3656	4967	ta_ol_base = 0;
3657	4968	ta_ol_limit = 0;
3658	4969	ta_isp_base = 0;
r243804	r243805
3667	4978	memset(fog_table, 0, sizeof(fog_table));
3668	4979	memset(palette, 0, sizeof(palette));
3669	4980	memset(&m_pvr_dma, 0x00, sizeof(m_pvr_dma));
	4981	memset(ta_ol_pointers_1, 0, sizeof(ta_ol_pointers_1));
	4982	memset(ta_ol_pointers_2, 0, sizeof(ta_ol_pointers_2));
3670	4983
	4984	ta_clip_min_x = 0;
	4985	ta_clip_max_x = 0;
	4986	ta_clip_min_y = 0;
	4987	ta_clip_max_y = 0;
	4988
3671	4989	sb_pdstap = 0;
3672	4990	sb_pdstar = 0;
3673	4991	sb_pdlen = 0;
r243804	r243805
3677	4995	sb_pdst = 0;
3678	4996	sb_pdapro = 0;
3679	4997
	4998	sdram = auto_alloc_array(machine(), UINT32, 4*1024*1024);
	4999
	5000	save_pointer(NAME(sdram), 4*1024*1024);
3680	5001	save_item(NAME(softreset));
	5002	save_item(NAME(test_select));
3681	5003	save_item(NAME(param_base));
3682	5004	save_item(NAME(region_base));
	5005	save_item(NAME(span_sort_cfg));
3683	5006	save_item(NAME(vo_border_col));
3684	5007	save_item(NAME(fb_r_ctrl));
3685	5008	save_item(NAME(fb_w_ctrl));
r243804	r243805
3691	5014	save_item(NAME(fb_w_sof2));
3692	5015	save_item(NAME(fb_x_clip));
3693	5016	save_item(NAME(fb_y_clip));
	5017	save_item(NAME(fpu_shad_scale));
	5018	save_item(NAME(fpu_cull_val));
3694	5019	save_item(NAME(fpu_param_cfg));
	5020	save_item(NAME(half_offset));
	5021	save_item(NAME(fpu_perp_val));
	5022	save_item(NAME(isp_backgnd_d));
3695	5023	save_item(NAME(isp_backgnd_t));
	5024	save_item(NAME(isp_feed_cfg));
	5025	save_item(NAME(sdram_refresh));
	5026	save_item(NAME(sdram_arb_cfg));
	5027	save_item(NAME(sdram_cfg));
	5028	save_item(NAME(fog_col_ram));
	5029	save_item(NAME(fog_col_vert));
	5030	save_item(NAME(fog_density));
	5031	save_item(NAME(fog_clamp_max));
	5032	save_item(NAME(fog_clamp_min));
	5033	save_item(NAME(spg_trigger_pos));
3696	5034	save_item(NAME(spg_hblank_int));
3697	5035	save_item(NAME(spg_vblank_int));
3698	5036	save_item(NAME(spg_hblank));
3699	5037	save_item(NAME(spg_load));
3700	5038	save_item(NAME(spg_vblank));
3701	5039	save_item(NAME(spg_width));
	5040	save_item(NAME(text_control));
3702	5041	save_item(NAME(vo_control));
3703	5042	save_item(NAME(vo_startx));
3704	5043	save_item(NAME(vo_starty));
3705		save_item(NAME(text_control));
	5044	save_item(NAME(scaler_ctl));
3706	5045	save_item(NAME(pal_ram_ctrl));
	5046	save_item(NAME(fb_burstctrl));
	5047	save_item(NAME(y_coeff));
	5048	save_item(NAME(pt_alpha_ref));
3707	5049	save_item(NAME(ta_ol_base));
3708	5050	save_item(NAME(ta_ol_limit));
3709	5051	save_item(NAME(ta_isp_base));
r243804	r243805
3715	5057	save_item(NAME(ta_yuv_tex_base));
3716	5058	save_item(NAME(ta_yuv_tex_ctrl));
3717	5059	save_item(NAME(ta_yuv_tex_cnt));
3718		save_pointer(NAME(fog_table), 0x80);
3719		save_pointer(NAME(palette), 0x400);
	5060	save_item(NAME(fog_table));
	5061	save_item(NAME(ta_ol_pointers_1));
	5062	save_item(NAME(ta_ol_pointers_2));
	5063	save_item(NAME(palette));
3720	5064
3721	5065	save_item(NAME(sb_pdstap));
3722	5066	save_item(NAME(sb_pdstar));
r243804	r243805
3727	5071	save_item(NAME(sb_pdst));
3728	5072	save_item(NAME(sb_pdapro));
3729	5073
	5074	save_item(NAME(ta_fifo_buf));
	5075	save_item(NAME(ta_fifo_pos));
	5076	save_item(NAME(ta_packet_len));
	5077	save_item(NAME(ta_packet_type));
	5078	save_item(NAME(ta_cmd_type));
	5079	save_item(NAME(ta_list_idx));
	5080	save_item(NAME(ta_list_type));
	5081
	5082	save_item(NAME(ta_cmd_header));
	5083	save_item(NAME(ta_cmd_instr));
	5084	save_item(NAME(ta_cmd_tsp));
	5085	save_item(NAME(ta_cmd_tex));
	5086	save_item(NAME(ta_cmd_color_base));
	5087	save_item(NAME(ta_cmd_color_offset));
	5088	save_item(NAME(ta_cmd_color_sprite_base));
	5089	save_item(NAME(ta_cmd_color_sprite_offset));
	5090	save_item(NAME(ta_cmd_strip_length));
	5091	save_item(NAME(ta_cmd_user_clip_mode));
	5092
	5093	save_item(NAME(ta_clip_min_x));
	5094	save_item(NAME(ta_clip_max_x));
	5095	save_item(NAME(ta_clip_min_y));
	5096	save_item(NAME(ta_clip_max_y));
	5097
	5098	save_item(NAME(ta_vertex_current.header));
	5099	save_item(NAME(ta_vertex_current.coords));
	5100	save_item(NAME(ta_vertex_current.color_base));
	5101	save_item(NAME(ta_vertex_current.color_offset));
	5102	save_item(NAME(ta_vertex_current.uv));
	5103	save_item(NAME(ta_vertex_current.uvc));
	5104	for(int i=0; i<8; i++) {
	5105	save_item(NAME(ta_vertex_strip[i].header), i);
	5106	save_item(NAME(ta_vertex_strip[i].coords), i);
	5107	save_item(NAME(ta_vertex_strip[i].color_base), i);
	5108	save_item(NAME(ta_vertex_strip[i].color_offset), i);
	5109	save_item(NAME(ta_vertex_strip[i].uv), i);
	5110	save_item(NAME(ta_vertex_strip[i].uvc), i);
	5111	}
	5112	save_item(NAME(ta_vertex_count));
	5113	save_item(NAME(ta_vertex_odd_tri));
	5114	save_item(NAME(ta_vertex_shadow_first));
	5115	save_item(NAME(ta_vertex_shadow_bbox.min_x));
	5116	save_item(NAME(ta_vertex_shadow_bbox.min_y));
	5117	save_item(NAME(ta_vertex_shadow_bbox.max_x));
	5118	save_item(NAME(ta_vertex_shadow_bbox.max_y));
	5119
	5120	save_item(NAME(ta_olist_pos));
	5121	save_item(NAME(ta_olist_pos_base));
	5122	save_item(NAME(ta_olist_tile));
	5123	save_item(NAME(ta_olist_block_size));
	5124
3730	5125	save_item(NAME(m_pvr_dma.pvr_addr));
3731	5126	save_item(NAME(m_pvr_dma.sys_addr));
3732	5127	save_item(NAME(m_pvr_dma.size));
r243804	r243805
3735	5130	save_item(NAME(m_pvr_dma.flag));
3736	5131	save_item(NAME(m_pvr_dma.start));
3737	5132	save_item(NAME(debug_dip_status));
3738		save_pointer(NAME(tafifo_buff),32);
	5133
3739	5134	save_item(NAME(scanline));
3740	5135	save_item(NAME(next_y));
3741	5136	}
3742	5137
3743	5138	void powervr2_device::device_reset()
3744	5139	{
	5140	memset(sdram, 0, 4*1024*1024*4);
	5141
3745	5142	softreset =                 0x00000007;
3746	5143	vo_control =                0x00000108;
3747	5144	vo_startx =                 0x0000009d;
r243804	r243805
3752	5149	spg_hblank_int =            0x031d0000;
3753	5150	spg_vblank_int =            0x01500104;
3754	5151
3755		tafifo_pos=0;
3756		tafifo_mask=7;
3757		tafifo_vertexwords=8;
3758		tafifo_listtype= -1;
	5152	ta_fifo_pos = 0;
	5153	memset(ta_fifo_buf, 0, sizeof(ta_fifo_buf));
	5154	ta_packet_len = 0;
	5155	ta_packet_type = VAR_UNKNOWN;
	5156	ta_cmd_type = VAR_UNKNOWN;
	5157	ta_list_idx = 0;
	5158	ta_list_type = -1;
	5159
	5160	ta_cmd_header = 0;
	5161	ta_cmd_instr = 0;
	5162	memset(ta_cmd_tsp, 0, sizeof(ta_cmd_tsp));
	5163	memset(ta_cmd_tex, 0, sizeof(ta_cmd_tex));
	5164	memset(ta_cmd_color_base, 0, sizeof(ta_cmd_color_base));
	5165	memset(ta_cmd_color_offset, 0, sizeof(ta_cmd_color_offset));
	5166	ta_cmd_color_sprite_base = 0;
	5167	ta_cmd_color_sprite_offset = 0;
	5168	ta_cmd_strip_length = 0;
	5169	ta_cmd_user_clip_mode = 0;
	5170
	5171	memset(&ta_vertex_current, 0, sizeof(ta_vertex_current));
	5172	memset(ta_vertex_strip, 0, sizeof(ta_vertex_strip));
	5173	ta_vertex_count = 0;
	5174	ta_vertex_odd_tri = false;
	5175	ta_vertex_shadow_first = true;
	5176	memset(&ta_vertex_shadow_bbox, 0, sizeof(ta_vertex_shadow_bbox));
	5177
	5178	ta_olist_pos = 0;
	5179	ta_olist_pos_base = 0;
	5180	ta_olist_tile = 0;
	5181	ta_olist_block_size = 0;
	5182	ta_olist_line_size = 0;
	5183
3759	5184	start_render_received=0;
3760	5185	renderselect= -1;
3761	5186	grabsel=0;
r243804	r243805
3772	5197	endofrender_timer_video->adjust(attotime::never);
3773	5198	yuv_timer_end->adjust(attotime::never);
3774	5199
3775		dc_state *state = machine().driver_data<dc_state>();
3776		dc_texture_ram = state->dc_texture_ram.target();
3777		dc_framebuffer_ram = state->dc_framebuffer_ram.target();
	5200	dc_texture_ram = NULL;
	5201	dc_framebuffer_ram = NULL;
3778	5202	}
3779	5203
3780	5204	/* called by TIMER_ADD_PERIODIC, in driver sections (controlled by SPG, that's a PVR sub-device) */

trunk/src/mame/video/powervr2.h

r243804	r243805
97	97	TEX_FILTER_TRILINEAR_B
98	98	};
99	99
100		int tafifo_pos, tafifo_mask, tafifo_vertexwords, tafifo_listtype;
	100	int tafifo_vertexwords, tafifo_listtype;
101	101	int start_render_received;
102	102	int renderselect;
103	103	int listtype_used;
r243804	r243805
130	130	emu_timer *endofrender_timer_tsp;
131	131	emu_timer *endofrender_timer_video;
132	132	emu_timer *yuv_timer_end;
133		UINT32 tafifo_buff[32];
134	133	int scanline;
135	134	int next_y;
136	135
137	136	powervr2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
138	137	template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
139	138
	139	DECLARE_READ64_MEMBER(  tex64_r );
	140	DECLARE_WRITE64_MEMBER( tex64_w );
	141	DECLARE_READ32_MEMBER(  tex32_r );
	142	DECLARE_WRITE32_MEMBER( tex32_w );
	143
140	144	DECLARE_READ32_MEMBER(  id_r );
141	145	DECLARE_READ32_MEMBER(  revision_r );
142	146	DECLARE_READ32_MEMBER(  softreset_r );
143	147	DECLARE_WRITE32_MEMBER( softreset_w );
	148	DECLARE_READ32_MEMBER(  startrender_r );
144	149	DECLARE_WRITE32_MEMBER( startrender_w );
	150	DECLARE_READ32_MEMBER(  test_select_r );
	151	DECLARE_WRITE32_MEMBER( test_select_w );
145	152	DECLARE_READ32_MEMBER(  param_base_r );
146	153	DECLARE_WRITE32_MEMBER( param_base_w );
147	154	DECLARE_READ32_MEMBER(  region_base_r );
148	155	DECLARE_WRITE32_MEMBER( region_base_w );
	156	DECLARE_READ32_MEMBER(  span_sort_cfg_r );
	157	DECLARE_WRITE32_MEMBER( span_sort_cfg_w );
149	158	DECLARE_READ32_MEMBER(  vo_border_col_r );
150	159	DECLARE_WRITE32_MEMBER( vo_border_col_w );
151	160	DECLARE_READ32_MEMBER(  fb_r_ctrl_r );
r243804	r243805
168	177	DECLARE_WRITE32_MEMBER( fb_x_clip_w );
169	178	DECLARE_READ32_MEMBER(  fb_y_clip_r );
170	179	DECLARE_WRITE32_MEMBER( fb_y_clip_w );
	180	DECLARE_READ32_MEMBER(  fpu_shad_scale_r );
	181	DECLARE_WRITE32_MEMBER( fpu_shad_scale_w );
	182	DECLARE_READ32_MEMBER(  fpu_cull_val_r );
	183	DECLARE_WRITE32_MEMBER( fpu_cull_val_w );
171	184	DECLARE_READ32_MEMBER(  fpu_param_cfg_r );
172	185	DECLARE_WRITE32_MEMBER( fpu_param_cfg_w );
	186	DECLARE_READ32_MEMBER(  half_offset_r );
	187	DECLARE_WRITE32_MEMBER( half_offset_w );
	188	DECLARE_READ32_MEMBER(  fpu_perp_val_r );
	189	DECLARE_WRITE32_MEMBER( fpu_perp_val_w );
	190	DECLARE_READ32_MEMBER(  isp_backgnd_d_r );
	191	DECLARE_WRITE32_MEMBER( isp_backgnd_d_w );
173	192	DECLARE_READ32_MEMBER(  isp_backgnd_t_r );
174	193	DECLARE_WRITE32_MEMBER( isp_backgnd_t_w );
	194	DECLARE_READ32_MEMBER(  isp_feed_cfg_r );
	195	DECLARE_WRITE32_MEMBER( isp_feed_cfg_w );
	196	DECLARE_READ32_MEMBER(  sdram_refresh_r );
	197	DECLARE_WRITE32_MEMBER( sdram_refresh_w );
	198	DECLARE_READ32_MEMBER(  sdram_arb_cfg_r );
	199	DECLARE_WRITE32_MEMBER( sdram_arb_cfg_w );
	200	DECLARE_READ32_MEMBER(  sdram_cfg_r );
	201	DECLARE_WRITE32_MEMBER( sdram_cfg_w );
	202	DECLARE_READ32_MEMBER(  fog_col_ram_r );
	203	DECLARE_WRITE32_MEMBER( fog_col_ram_w );
	204	DECLARE_READ32_MEMBER(  fog_col_vert_r );
	205	DECLARE_WRITE32_MEMBER( fog_col_vert_w );
	206	DECLARE_READ32_MEMBER(  fog_density_r );
	207	DECLARE_WRITE32_MEMBER( fog_density_w );
	208	DECLARE_READ32_MEMBER(  fog_clamp_max_r );
	209	DECLARE_WRITE32_MEMBER( fog_clamp_max_w );
	210	DECLARE_READ32_MEMBER(  fog_clamp_min_r );
	211	DECLARE_WRITE32_MEMBER( fog_clamp_min_w );
	212	DECLARE_READ32_MEMBER(  spg_trigger_pos_r );
	213	DECLARE_WRITE32_MEMBER( spg_trigger_pos_w );
175	214	DECLARE_READ32_MEMBER(  spg_hblank_int_r );
176	215	DECLARE_WRITE32_MEMBER( spg_hblank_int_w );
177	216	DECLARE_READ32_MEMBER(  spg_vblank_int_r );
r243804	r243805
194	233	DECLARE_WRITE32_MEMBER( vo_startx_w );
195	234	DECLARE_READ32_MEMBER(  vo_starty_r );
196	235	DECLARE_WRITE32_MEMBER( vo_starty_w );
	236	DECLARE_READ32_MEMBER(  scaler_ctl_r );
	237	DECLARE_WRITE32_MEMBER( scaler_ctl_w );
197	238	DECLARE_READ32_MEMBER(  pal_ram_ctrl_r );
198	239	DECLARE_WRITE32_MEMBER( pal_ram_ctrl_w );
199	240	DECLARE_READ32_MEMBER(  spg_status_r );
200
	241	DECLARE_READ32_MEMBER(  fb_burstctrl_r );
	242	DECLARE_WRITE32_MEMBER( fb_burstctrl_w );
	243	DECLARE_READ32_MEMBER(  y_coeff_r );
	244	DECLARE_WRITE32_MEMBER( y_coeff_w );
	245	DECLARE_READ32_MEMBER(  pt_alpha_ref_r );
	246	DECLARE_WRITE32_MEMBER( pt_alpha_ref_w );
201	247	DECLARE_READ32_MEMBER(  ta_ol_base_r );
202	248	DECLARE_WRITE32_MEMBER( ta_ol_base_w );
203	249	DECLARE_READ32_MEMBER(  ta_isp_base_r );
r243804	r243805
208	254	DECLARE_WRITE32_MEMBER( ta_isp_limit_w );
209	255	DECLARE_READ32_MEMBER(  ta_next_opb_r );
210	256	DECLARE_READ32_MEMBER(  ta_itp_current_r );
	257	DECLARE_READ32_MEMBER(  ta_glob_tile_clip_r );
	258	DECLARE_WRITE32_MEMBER( ta_glob_tile_clip_w );
211	259	DECLARE_READ32_MEMBER(  ta_alloc_ctrl_r );
212	260	DECLARE_WRITE32_MEMBER( ta_alloc_ctrl_w );
213	261	DECLARE_READ32_MEMBER(  ta_list_init_r );
r243804	r243805
217	265	DECLARE_READ32_MEMBER(  ta_yuv_tex_ctrl_r );
218	266	DECLARE_WRITE32_MEMBER( ta_yuv_tex_ctrl_w );
219	267	DECLARE_READ32_MEMBER(  ta_yuv_tex_cnt_r );
220		DECLARE_WRITE32_MEMBER( ta_yuv_tex_cnt_w );
221	268	DECLARE_READ32_MEMBER(  ta_list_cont_r );
222	269	DECLARE_WRITE32_MEMBER( ta_list_cont_w );
223	270	DECLARE_READ32_MEMBER(  ta_next_opb_init_r );
224	271	DECLARE_WRITE32_MEMBER( ta_next_opb_init_w );
225
226
227	272	DECLARE_READ32_MEMBER(  fog_table_r );
228	273	DECLARE_WRITE32_MEMBER( fog_table_w );
	274	DECLARE_READ32_MEMBER(  ta_ol_pointers_1_r );
	275	DECLARE_READ32_MEMBER(  ta_ol_pointers_2_r );
229	276	DECLARE_READ32_MEMBER(  palette_r );
230	277	DECLARE_WRITE32_MEMBER( palette_w );
231	278
r243804	r243805
282	329	virtual void device_reset();
283	330
284	331	private:
	332	enum {
	333	TRI_G_F32,
	334	TRI_G_I_GLB,
	335	TRI_G_I_GLB_DUAL,
	336	TRI_G_I_PREV,
	337	TRI_G_I_PREV_DUAL,
	338	TRI_G_U8,
	339	TRI_G_U8_DUAL,
	340	TRI_T_F32,
	341	TRI_T_F32_CUV,
	342	TRI_T_I_GLB,
	343	TRI_T_I_GLB_CUV,
	344	TRI_T_I_GLB_CUV_DUAL,
	345	TRI_T_I_GLB_DUAL,
	346	TRI_T_I_GLB_OFF,
	347	TRI_T_I_GLB_OFF_CUV,
	348	TRI_T_I_PREV,
	349	TRI_T_I_PREV_CUV,
	350	TRI_T_I_PREV_CUV_DUAL,
	351	TRI_T_I_PREV_DUAL,
	352	TRI_T_U8,
	353	TRI_T_U8_CUV,
	354	TRI_T_U8_CUV_DUAL,
	355	TRI_T_U8_DUAL,
	356
	357	SHADOW,
	358	SPRITE,
	359	LINE_SPRITE,
	360
	361	CMD_END_OF_LIST,
	362	CMD_USER_TILE_CLIP,
	363	CMD_OBJECT_LIST_SET,
	364
	365	VAR_UNKNOWN,
	366	VAR_COUNT
	367	};
	368
	369	enum {
	370	L_OPAQUE,
	371	L_OPAQUE_SHADOW,
	372	L_TRANS,
	373	L_TRANS_SHADOW,
	374	L_TRANS_PUNCHTHROUGH
	375	};
	376
	377	enum {
	378	H_TYPE        = 0xe0000000,
	379	H_EOSTRIP     = 0x10000000,
	380	H_LTYPE       = 0x07000000,
	381	H_GROUP       = 0x00800000,
	382	H_SLEN        = 0x000c0000,
	383	H_UCLIP       = 0x00030000,
	384	H_DUAL        = 0x00000040,
	385	H_COLMODE     = 0x00000030,
	386	H_TEX         = 0x00000008,
	387	H_OFF         = 0x00000004,
	388	H_GOURAUD     = 0x00000002,
	389	H_COMPACT_UV  = 0x00000001,
	390
	391	HI_DEPTH      = 0xe0000000,
	392	HI_CULL       = 0x18000000,
	393	HI_ZWRITE     = 0x04000000,
	394	HI_TEX        = 0x02000000,
	395	HI_OFF        = 0x01000000,
	396	HI_GOURAUD    = 0x00800000,
	397	HI_COMPACT_UV = 0x00400000,
	398	HI_CACHE      = 0x00200000,
	399	HI_DCOEFF     = 0x00100000,
	400	};
	401
	402	enum {
	403	OL_POINTERS_COUNT = 40*15,
	404	TA_SORTER_SIZE    = 16
	405	};
	406
	407	static const char *ta_packet_type_name[VAR_COUNT];
	408	static const int ta_packet_len_table[VAR_COUNT*2];
	409
285	410	devcb_write8 irq_cb;
286	411
	412	// SDRAM, 4 pairs of 1M*16 sdrams, total of 16M
	413	UINT32 *sdram;
	414
287	415	// Core registers
288	416	UINT32 softreset;
	417	UINT32 test_select;
289	418	UINT32 param_base, region_base;
	419	UINT32 span_sort_cfg;
290	420	UINT32 vo_border_col;
291	421	UINT32 fb_r_ctrl, fb_w_ctrl, fb_w_linestride, fb_r_sof1, fb_r_sof2, fb_r_size, fb_w_sof1, fb_w_sof2, fb_x_clip, fb_y_clip;
292		UINT32 fpu_param_cfg;
293		UINT32 isp_backgnd_t;
294		UINT32 spg_hblank_int, spg_vblank_int, spg_control, spg_hblank, spg_load, spg_vblank, spg_width;
	422	UINT32 fpu_shad_scale, fpu_cull_val, fpu_param_cfg, half_offset, fpu_perp_val;
	423	UINT32 isp_backgnd_d, isp_backgnd_t, isp_feed_cfg;
	424	UINT32 sdram_refresh, sdram_arb_cfg, sdram_cfg;
	425	UINT32 fog_col_ram, fog_col_vert, fog_density, fog_clamp_max, fog_clamp_min;
	426	UINT32 spg_trigger_pos, spg_hblank_int, spg_vblank_int, spg_control, spg_hblank, spg_load, spg_vblank, spg_width;
	427	UINT32 text_control;
295	428	UINT32 vo_control, vo_startx, vo_starty;
296		UINT32 text_control;
297		UINT32 pal_ram_ctrl;
	429	UINT32 scaler_ctl, pal_ram_ctrl, fb_burstctrl, y_coeff, pt_alpha_ref;
298	430
299	431	// TA registers
300	432	UINT32 ta_ol_base, ta_ol_limit, ta_isp_base, ta_isp_limit;
301		UINT32 ta_next_opb, ta_itp_current, ta_alloc_ctrl, ta_next_opb_init;
	433	UINT32 ta_next_opb, ta_itp_current, ta_glob_tile_clip, ta_alloc_ctrl, ta_next_opb_init;
302	434	UINT32 ta_yuv_tex_base, ta_yuv_tex_ctrl, ta_yuv_tex_cnt;
303	435	UINT32 ta_yuv_index;
304	436	int ta_yuv_x,ta_yuv_y;
305	437	int ta_yuv_x_size,ta_yuv_y_size;
306	438	UINT8 yuv_fifo[384];
	439	UINT32 ta_ol_pointers_1[OL_POINTERS_COUNT];
	440	UINT32 ta_ol_pointers_2[OL_POINTERS_COUNT];
307	441
308	442	// Other registers
309	443	UINT32 fog_table[0x80];
r243804	r243805
312	446	// PD DMA registers
313	447	UINT32 sb_pdstap, sb_pdstar, sb_pdlen, sb_pddir, sb_pdtsel, sb_pden, sb_pdst, sb_pdapro;
314	448
	449	// TA input fifo
	450	int ta_fifo_pos;
	451	UINT32 ta_fifo_buf[16];
	452
	453	// TA lists and packetization
	454	int ta_packet_len, ta_packet_type, ta_cmd_type, ta_list_idx, ta_list_type;
	455
	456	// TA command parsing
	457	UINT32 ta_cmd_header, ta_cmd_instr, ta_cmd_tsp[2], ta_cmd_tex[2];
	458	float ta_cmd_color_base[2][4], ta_cmd_color_offset[2][4];
	459	UINT32 ta_cmd_color_sprite_base, ta_cmd_color_sprite_offset;
	460	int ta_cmd_strip_length, ta_cmd_user_clip_mode;
	461
	462	// TA user clipping
	463	UINT32 ta_clip_min_x, ta_clip_max_x, ta_clip_min_y, ta_clip_max_y;
	464
	465	// TA vertices
	466	struct ta_vertex {
	467	UINT32 header;
	468	UINT32 coords[3];
	469	UINT32 color_base[2];
	470	UINT32 color_offset[2];
	471	UINT32 uv[2][2];
	472	UINT32 uvc[2];
	473
	474	int tx() const { float p = u2f(coords[0]); if(p<0) return -1; return int(p)>>5; }
	475	int ty() const { float p = u2f(coords[1]); if(p<0) return -1; return int(p)>>5; }
	476	};
	477
	478	struct ta_bbox {
	479	int min_x, max_x, min_y, max_y;
	480	};
	481
	482	ta_vertex ta_vertex_current, ta_vertex_strip[8];
	483	int ta_vertex_count;
	484	bool ta_vertex_odd_tri;
	485	bool ta_vertex_shadow_first;
	486	ta_bbox ta_vertex_shadow_bbox;
	487
	488	// TA output
	489	UINT32 ta_olist_pos, ta_olist_pos_base, ta_olist_tile, ta_olist_block_size, ta_olist_line_size;
	490
315	491	static UINT32 (*const blend_functions[64])(UINT32 s, UINT32 d);
316	492
	493	inline float clampf(UINT32 v) {
	494	float v1 = u2f(v);
	495	return v1 < 0 ? 0 : v1 > 1 ? 1 : v1;
	496	}
	497
	498	inline float clampf(float v) {
	499	return v < 0 ? 0 : v > 1 ? 1 : v;
	500	}
	501
	502	inline void ta_load_color_f32(float *dest, const UINT32 *src)
	503	{
	504	for(int i=0; i<4; i++)
	505	dest[i] = clampf(src[i]);
	506	}
	507
	508	inline UINT32 ta_color_f32_to_u8(const UINT32 *src)
	509	{
	510	UINT32 res = 0;
	511	for(int i=0; i<4; i++)
	512	res |= UINT8(255*clampf(src[i])) << (24-8*i);
	513	return res;
	514	}
	515
	516	inline UINT32 ta_intensity(const float *src, UINT32 i)
	517	{
	518	UINT32 ii = UINT32(i*256) & 0x1ff;
	519	UINT32 res = UINT8(255*clampf(src[0])) << 24;
	520
	521	for(int i=1; i<4; i++)
	522	res |= UINT8((ii*UINT8(255*clampf(src[i]))) >> 8) << (24-8*i);
	523	return res;
	524	}
	525
317	526	static inline INT32 clamp(INT32 in, INT32 min, INT32 max);
318	527	static inline UINT32 bilinear_filter(UINT32 c0, UINT32 c1, UINT32 c2, UINT32 c3, float u, float v);
319	528	static inline UINT32 bla(UINT32 c, UINT32 a);
r243804	r243805
477	686	void fb_convert_8888argb_to_888rgb24(address_space &space, int x, int y);
478	687	void fb_convert_8888argb_to_888rgb32(address_space &space, int x, int y);
479	688
	689	void mem_write32(UINT32 adr, UINT32 val);
	690
	691	void ta_object_list_extend();
	692	void ta_add_object(UINT32 adr, bool tail);
	693	void ta_add_strip(UINT32 adr, UINT32 psize);
	694	bool ta_bbox_vertex(ta_bbox &bb, const ta_vertex *vtx, int count) const;
	695	void ta_bbox_merge(ta_bbox &bb, const ta_bbox &src) const;
	696	UINT32 ta_strip_write(bool single_tile, UINT32 &psize);
	697	void ta_vertex_write_sprite();
	698	void ta_vertex_write_shadow();
	699	void ta_vertex_write();
	700	void ta_vertex_push();
	701	void ta_handle_command_draw();
	702	void ta_handle_vertex();
	703	void ta_handle_command_end_of_list();
	704	void ta_handle_command_user_tile_clip();
	705	void ta_handle_command_object_list_set();
	706
	707	int ta_get_packet_type();
	708	void ta_next_list();
	709	void ta_list_start();
	710	void ta_process_lists(UINT32 adr, bool cont);
480	711	};
481	712
482	713	extern const device_type POWERVR2;

trunk/src/mess/drivers/dccons.c

r243804	r243805
391	391	//  AM_RANGE(0x03000000, 0x03ffffff) G2 Ext Device #2
392	392
393	393	/* Area 1 */
394		AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram")      // texture memory 64 bit access
395		AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
	394	AM_RANGE(0x04000000, 0x04ffffff) AM_DEVREADWRITE  ("powervr2", powervr2_device, tex64_r, tex64_w)
	395	AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE32("powervr2", powervr2_device, tex32_r, tex32_w, U64(0xffffffffffffffff))
396	396
397	397	/* Area 3 */
398	398	AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE("dc_ram")

https://github.com/mamedev/mame/commit/594851607fafe4fbd7b547a0ca1dfc714d66a98e

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