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r35068 Sunday 15th February, 2015 at 14:28:10 UTC by Parry
sdl: Add BASELIBS for MACOSX_USE_LIBSDL

[3rdparty/bgfx/3rdparty/ib-compress]	readbitstream.h
[3rdparty/bgfx/examples/common/font]	font_manager.cpp
[3rdparty/bgfx/src]	image.cpp
[3rdparty/bx/include/bx]	macros.h
[3rdparty/mongoose]	mongoose.c
[src/emu/cpu/amis2000]	amis2000.c amis2000.h amis2000op.inc
[src/emu/cpu/ucom4]	ucom4.c ucom4.h
[src/emu/video]	scn2674.c scn2674.h video.mak
[src/mame]	mame.mak
[src/mame/drivers]	mpu4vid.c wc90.c wwfsstar.c xxmissio.c
[src/mame/includes]	wc90.h wwfsstar.h xxmissio.h
[src/mame/video]	scn2674.c* scn2674.h* wc90.c wwfsstar.c xxmissio.c
[src/mess]	mess.mak
[src/mess/drivers]	alnchase.c edracula.c ngen.c pcd.c tmtennis.c wildfire.c
[src/mess/machine]	ngen_kb.c ngen_kb.h
[src/osd/sdl]	sdl.mak

trunk/3rdparty/bgfx/3rdparty/ib-compress/readbitstream.h

r243579	r243580
95	95	}
96	96	}
97	97
	98	#if defined(__GNUC__) || defined(_MSC_VER)
	99	#define U64(val) val##ULL
	100	#else
	101	#define U64(val) val
	102	#endif
	103
98	104	RBS_INLINE uint32_t ReadBitstream::Read( uint32_t bitCount )
99	105	{
100	106	uint64_t mask   = ( uint64_t( 1 ) << bitCount ) - 1;
101		uint32_t result = static_cast< uint32_t >( ( m_bitBuffer >> ( 64 - m_bitsLeft ) & ( m_bitsLeft == 0 ? 0 : UINT64_C(0xFFFFFFFFFFFFFFFF) ) ) & mask );
	107	uint32_t result = static_cast< uint32_t >( ( m_bitBuffer >> ( 64 - m_bitsLeft ) & ( m_bitsLeft == 0 ? 0 : U64(0xFFFFFFFFFFFFFFFF) ) ) & mask );
102	108
103	109	if ( m_bitsLeft < bitCount )
104	110	{

trunk/3rdparty/bgfx/examples/common/font/font_manager.cpp

r243579	r243580
13	13
14	14	BX_PRAGMA_DIAGNOSTIC_PUSH();
15	15	BX_PRAGMA_DIAGNOSTIC_IGNORED_MSVC(4245) // error C4245: '=' : conversion from 'int' to 'FT_UInt', signed/unsigned mismatch
16		#if BX_COMPILER_MSVC || BX_COMPILER_GCC >= 40300
	16	#if defined(_MSC_VER) || (defined(__GNUC__) && (__GNUC__ == 4) && (__GNUC_MINOR__ >= 3))
17	17	#pragma push_macro("interface")
18	18	#endif
19	19	#undef interface
20	20	#include <freetype/freetype.h>
21		#if BX_COMPILER_MSVC || BX_COMPILER_GCC >= 40300
	21	#if defined(_MSC_VER) || (defined(__GNUC__) && (__GNUC__ == 4) && (__GNUC_MINOR__ >= 3))
22	22	#pragma pop_macro("interface")
23	23	#endif
24	24	BX_PRAGMA_DIAGNOSTIC_POP();

trunk/3rdparty/bgfx/src/image.cpp

r243579	r243580
1391	1391
1392	1392	static TranslateDdsPixelFormat s_translateDdsPixelFormat[] =
1393	1393	{
1394		{  8, { 0x000000ff, 0x00000000, 0x00000000, 0x00000000 }, TextureFormat::R8      },
1395		{ 16, { 0x0000ffff, 0x00000000, 0x00000000, 0x00000000 }, TextureFormat::R16     },
1396		{ 16, { 0x00000f00, 0x000000f0, 0x0000000f, 0x0000f000 }, TextureFormat::RGBA4   },
1397		{ 16, { 0x0000f800, 0x000007e0, 0x0000001f, 0x00000000 }, TextureFormat::R5G6B5  },
1398		{ 16, { 0x00007c00, 0x000003e0, 0x0000001f, 0x00008000 }, TextureFormat::RGB5A1  },
1399	1394	{ 32, { 0x00ff0000, 0x0000ff00, 0x000000ff, 0xff000000 }, TextureFormat::BGRA8   },
1400	1395	{ 32, { 0x00ff0000, 0x0000ff00, 0x000000ff, 0x00000000 }, TextureFormat::BGRA8   },
1401	1396	{ 32, { 0x000003ff, 0x000ffc00, 0x3ff00000, 0xc0000000 }, TextureFormat::RGB10A2 },

trunk/3rdparty/bx/include/bx/macros.h

r243579	r243580
138	138	#   define BX_PRAGMA_DIAGNOSTIC_IGNORED_CLANG(_x)
139	139	#endif // BX_COMPILER_CLANG
140	140
141		#if BX_COMPILER_GCC && BX_COMPILER_GCC >= 40600
	141	#if BX_COMPILER_GCC && (__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)
142	142	#   define BX_PRAGMA_DIAGNOSTIC_PUSH_GCC()        _Pragma("GCC diagnostic push")
143	143	#   define BX_PRAGMA_DIAGNOSTIC_POP_GCC()         _Pragma("GCC diagnostic pop")
144	144	#   define BX_PRAGMA_DIAGNOSTIC_IGNORED_GCC(_x)   _Pragma(BX_STRINGIZE(GCC diagnostic ignored _x) )
r243579	r243580
173	173	#endif // BX_COMPILER_
174	174
175	175	///
176		#if BX_COMPILER_GCC && defined(__is_pod)
	176	#if defined(__GNUC__) && defined(__is_pod)
177	177	#   define BX_TYPE_IS_POD(t) __is_pod(t)
178		#elif BX_COMPILER_MSVC
	178	#elif defined(_MSC_VER)
179	179	#   define BX_TYPE_IS_POD(t) (!__is_class(t) || __is_pod(t))
180	180	#else
181	181	#   define BX_TYPE_IS_POD(t) false

trunk/3rdparty/mongoose/mongoose.c

r243579	r243580
48	48	#define _INTEGRAL_MAX_BITS 64   // Enable _stati64() on Windows
49	49	#define _CRT_SECURE_NO_WARNINGS // Disable deprecation warning in VS2005+
50	50	#undef WIN32_LEAN_AND_MEAN      // Let windows.h always include winsock2.h
51		#ifdef __Linux__
52	51	#define _XOPEN_SOURCE 600       // For flockfile() on Linux
53		#endif
54	52	#define __STDC_FORMAT_MACROS    // <inttypes.h> wants this for C++
55	53	#define __STDC_LIMIT_MACROS     // C++ wants that for INT64_MAX
56	54	#ifndef _LARGEFILE_SOURCE

trunk/src/emu/cpu/amis2000/amis2000.c

r243579	r243580
6	6	Overall functionality is similar to (and probably derived from) NEC uCOM-4.
7	7
8	8	References:
9		- AMI MOS Products Catalog 1979/1980
	9	- AMI MOS Products Catalog Winter 1979
10	10	- AMI S2000 Programming Manual (rev. 2)
11	11
12	12	TODO:
13	13	- unemulated opcodes (need more testing material)
14		- is K/I input handling correct?
15	14	- support external program map
	15	- STATUS pin(wildfire.c sound?)
16	16	- add 50/60hz timer
17	17	- add S2200/S2400
18	18
r243579	r243580
27	27	// S2000 is the most basic one, 64 nibbles internal RAM and 1KB internal ROM
28	28	// S2150 increased RAM to 80 nibbles and ROM to 1.5KB
29	29	// high-voltage output versions of these chips (S2000A and S2150A) are identical overall
30		const device_type AMI_S2000 = &device_creator<amis2000_cpu_device>;
31		const device_type AMI_S2150 = &device_creator<amis2150_cpu_device>;
	30	const device_type AMI_S2000 = &device_creator<amis2000_device>;
	31	const device_type AMI_S2150 = &device_creator<amis2150_device>;
32	32
33		// S2152 is an extension to S2150, removing the K pins and adding a better timer
34		const device_type AMI_S2152 = &device_creator<amis2152_cpu_device>;
35	33
36
37	34	// internal memory maps
38		static ADDRESS_MAP_START(program_1k, AS_PROGRAM, 8, amis2000_base_device)
	35	static ADDRESS_MAP_START(program_1k, AS_PROGRAM, 8, amis2000_device)
39	36	AM_RANGE(0x0000, 0x03ff) AM_ROM
40	37	ADDRESS_MAP_END
41	38
42		static ADDRESS_MAP_START(program_1_5k, AS_PROGRAM, 8, amis2000_base_device)
	39	static ADDRESS_MAP_START(program_1_5k, AS_PROGRAM, 8, amis2000_device)
43	40	AM_RANGE(0x0000, 0x03ff) AM_ROM
44	41	AM_RANGE(0x0400, 0x05ff) AM_NOP // 0x00
45	42	AM_RANGE(0x0600, 0x07ff) AM_ROM
46	43	ADDRESS_MAP_END
47	44
48	45
49		static ADDRESS_MAP_START(data_64x4, AS_DATA, 8, amis2000_base_device)
	46	static ADDRESS_MAP_START(data_64x4, AS_DATA, 8, amis2000_device)
50	47	AM_RANGE(0x00, 0x3f) AM_RAM
51	48	ADDRESS_MAP_END
52	49
53		static ADDRESS_MAP_START(data_80x4, AS_DATA, 8, amis2000_base_device)
	50	static ADDRESS_MAP_START(data_80x4, AS_DATA, 8, amis2000_device)
54	51	AM_RANGE(0x00, 0x3f) AM_RAM
55	52	AM_RANGE(0x40, 0x4f) AM_RAM
56	53	ADDRESS_MAP_END
57	54
58	55
59	56	// device definitions
60		amis2000_cpu_device::amis2000_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
61		: amis2000_base_device(mconfig, AMI_S2000, "AMI S2000", tag, owner, clock, 2, 10, 3, 13, ADDRESS_MAP_NAME(program_1k), 6, ADDRESS_MAP_NAME(data_64x4), "amis2000", __FILE__)
62		{ }
	57	amis2000_device::amis2000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	58	: cpu_device(mconfig, AMI_S2000, "AMI S2000", tag, owner, clock, "amis2000", __FILE__),
	59	m_program_config("program", ENDIANNESS_BIG, 8, 13, 0, ADDRESS_MAP_NAME(program_1k)),
	60	m_data_config("data", ENDIANNESS_BIG, 8, 6, 0, ADDRESS_MAP_NAME(data_64x4)),
	61	m_bu_bits(2),
	62	m_callstack_bits(10),
	63	m_callstack_depth(3),
	64	m_read_k(*this),
	65	m_read_i(*this),
	66	m_read_d(*this),
	67	m_write_d(*this),
	68	m_write_a(*this)
	69	{
	70	}
63	71
64		amis2150_cpu_device::amis2150_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
65		: amis2000_base_device(mconfig, AMI_S2150, "AMI S2150", tag, owner, clock, 3, 11, 3, 13, ADDRESS_MAP_NAME(program_1_5k), 7, ADDRESS_MAP_NAME(data_80x4), "amis2150", __FILE__)
66		{ }
	72	amis2000_device::amis2000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT8 bu_bits, UINT8 callstack_bits, UINT8 callstack_depth, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source)
	73	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source),
	74	m_program_config("program", ENDIANNESS_BIG, 8, prgwidth, 0, program),
	75	m_data_config("data", ENDIANNESS_BIG, 8, datawidth, 0, data),
	76	m_bu_bits(bu_bits),
	77	m_callstack_bits(callstack_bits),
	78	m_callstack_depth(callstack_depth),
	79	m_read_k(*this),
	80	m_read_i(*this),
	81	m_read_d(*this),
	82	m_write_d(*this),
	83	m_write_a(*this)
	84	{
	85	}
67	86
68		amis2152_cpu_device::amis2152_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
69		: amis2000_base_device(mconfig, AMI_S2152, "AMI S2152", tag, owner, clock, 3, 11, 3, 13, ADDRESS_MAP_NAME(program_1_5k), 7, ADDRESS_MAP_NAME(data_80x4), "amis2152", __FILE__)
70		{ }
	87	amis2150_device::amis2150_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	88	: amis2000_device(mconfig, AMI_S2150, "AMI S2150", tag, owner, clock, 3, 11, 3, 13, ADDRESS_MAP_NAME(program_1_5k), 7, ADDRESS_MAP_NAME(data_80x4), "amis2150", __FILE__)
	89	{
	90	}
71	91
72	92
73
74	93	// disasm
75		void amis2000_base_device::state_string_export(const device_state_entry &entry, astring &string)
	94	void amis2000_device::state_string_export(const device_state_entry &entry, astring &string)
76	95	{
77	96	switch (entry.index())
78	97	{
r243579	r243580
91	110	}
92	111	}
93	112
94		offs_t amis2000_base_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	113	offs_t amis2000_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
95	114	{
96	115	extern CPU_DISASSEMBLE(amis2000);
97	116	return CPU_DISASSEMBLE_NAME(amis2000)(this, buffer, pc, oprom, opram, options);
r243579	r243580
109	128	S2000_ACC, S2000_E, S2000_CY
110	129	};
111	130
112		void amis2000_base_device::device_start()
	131	void amis2000_device::device_start()
113	132	{
114	133	m_program = &space(AS_PROGRAM);
115	134	m_data = &space(AS_DATA);
r243579	r243580
119	138	m_read_d.resolve_safe(0);
120	139	m_write_d.resolve_safe();
121	140	m_write_a.resolve_safe();
122		m_write_f.resolve_safe();
123	141
124	142	m_bu_mask = (1 << m_bu_bits) - 1;
125	143	m_callstack_mask = (1 << m_callstack_bits) - 1;
r243579	r243580
138	156	m_bu = 0;
139	157	m_acc = 0;
140	158	m_e = 0;
141		m_ki_mask = 0;
	159	m_i = 0;
	160	m_k = 0;
142	161	m_d = 0;
143	162	m_d_active = false;
144	163	m_d_polarity = 0;
r243579	r243580
158	177	save_item(NAME(m_bu));
159	178	save_item(NAME(m_acc));
160	179	save_item(NAME(m_e));
161		save_item(NAME(m_ki_mask));
	180	save_item(NAME(m_i));
	181	save_item(NAME(m_k));
162	182	save_item(NAME(m_d));
163	183	save_item(NAME(m_d_active));
164	184	save_item(NAME(m_d_polarity));
r243579	r243580
184	204	//  device_reset - device-specific reset
185	205	//-------------------------------------------------
186	206
187		void amis2000_base_device::device_reset()
	207	void amis2000_device::device_reset()
188	208	{
189	209	m_pc = 0;
190	210	m_op = 0;
r243579	r243580
194	214	m_d_polarity = 0;
195	215	m_d = 0; d_latch_out(false);
196	216	m_a = 0; m_write_a(0, 0, 0xffff);
	217	m_i = 0xf;
	218	m_k = 0xf;
197	219	}
198	220
199	221
r243579	r243580
202	224	//  execute
203	225	//-------------------------------------------------
204	226
205		void amis2000_base_device::execute_run()
	227	void amis2000_device::execute_run()
206	228	{
207	229	while (m_icount > 0)
208	230	{

trunk/src/emu/cpu/amis2000/amis2000.h

r243579	r243580
14	14
15	15	// generic input pins (4 bits each)
16	16	#define MCFG_AMI_S2000_READ_K_CB(_devcb) \
17		amis2000_base_device::set_read_k_callback(*device, DEVCB_##_devcb);
	17	amis2000_device::set_read_k_callback(*device, DEVCB_##_devcb);
18	18
19	19	#define MCFG_AMI_S2000_READ_I_CB(_devcb) \
20		amis2000_base_device::set_read_i_callback(*device, DEVCB_##_devcb);
	20	amis2000_device::set_read_i_callback(*device, DEVCB_##_devcb);
21	21
22	22	// 8-bit external databus coupled as input/output pins
23	23	#define MCFG_AMI_S2000_READ_D_CB(_devcb) \
24		amis2000_base_device::set_read_d_callback(*device, DEVCB_##_devcb);
	24	amis2000_device::set_read_d_callback(*device, DEVCB_##_devcb);
25	25
26	26	#define MCFG_AMI_S2000_WRITE_D_CB(_devcb) \
27		amis2000_base_device::set_write_d_callback(*device, DEVCB_##_devcb);
	27	amis2000_device::set_write_d_callback(*device, DEVCB_##_devcb);
28	28
29	29	// 13-bit external addressbus coupled as output pins
30	30	#define MCFG_AMI_S2000_WRITE_A_CB(_devcb) \
31		amis2000_base_device::set_write_a_callback(*device, DEVCB_##_devcb);
	31	amis2000_device::set_write_a_callback(*device, DEVCB_##_devcb);
32	32
33		// F_out pin (only for S2152)
34		#define MCFG_AMI_S2152_FOUT_CB(_devcb) \
35		amis2000_base_device::set_write_f_callback(*device, DEVCB_##_devcb);
36	33
37
38		class amis2000_base_device : public cpu_device
	34	class amis2000_device : public cpu_device
39	35	{
40	36	public:
41	37	// construction/destruction
42		amis2000_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT8 bu_bits, UINT8 callstack_bits, UINT8 callstack_depth, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source)
43		: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
44		, m_program_config("program", ENDIANNESS_BIG, 8, prgwidth, 0, program)
45		, m_data_config("data", ENDIANNESS_BIG, 8, datawidth, 0, data)
46		, m_bu_bits(bu_bits)
47		, m_callstack_bits(callstack_bits)
48		, m_callstack_depth(callstack_depth)
49		, m_read_k(*this)
50		, m_read_i(*this)
51		, m_read_d(*this)
52		, m_write_d(*this)
53		, m_write_a(*this)
54		, m_write_f(*this)
55		{ }
	38	amis2000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	39	amis2000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT8 bu_bits, UINT8 callstack_bits, UINT8 callstack_depth, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source);
56	40
57	41	// static configuration helpers
58		template<class _Object> static devcb_base &set_read_k_callback(device_t &device, _Object object) { return downcast<amis2000_base_device &>(device).m_read_k.set_callback(object); }
59		template<class _Object> static devcb_base &set_read_i_callback(device_t &device, _Object object) { return downcast<amis2000_base_device &>(device).m_read_i.set_callback(object); }
60		template<class _Object> static devcb_base &set_read_d_callback(device_t &device, _Object object) { return downcast<amis2000_base_device &>(device).m_read_d.set_callback(object); }
61		template<class _Object> static devcb_base &set_write_d_callback(device_t &device, _Object object) { return downcast<amis2000_base_device &>(device).m_write_d.set_callback(object); }
62		template<class _Object> static devcb_base &set_write_a_callback(device_t &device, _Object object) { return downcast<amis2000_base_device &>(device).m_write_a.set_callback(object); }
63		template<class _Object> static devcb_base &set_write_f_callback(device_t &device, _Object object) { return downcast<amis2000_base_device &>(device).m_write_f.set_callback(object); }
	42	template<class _Object> static devcb_base &set_read_k_callback(device_t &device, _Object object) { return downcast<amis2000_device &>(device).m_read_k.set_callback(object); }
	43	template<class _Object> static devcb_base &set_read_i_callback(device_t &device, _Object object) { return downcast<amis2000_device &>(device).m_read_i.set_callback(object); }
	44	template<class _Object> static devcb_base &set_read_d_callback(device_t &device, _Object object) { return downcast<amis2000_device &>(device).m_read_d.set_callback(object); }
	45	template<class _Object> static devcb_base &set_write_d_callback(device_t &device, _Object object) { return downcast<amis2000_device &>(device).m_write_d.set_callback(object); }
	46	template<class _Object> static devcb_base &set_write_a_callback(device_t &device, _Object object) { return downcast<amis2000_device &>(device).m_write_a.set_callback(object); }
64	47
65	48	protected:
66	49	// device-level overrides
r243579	r243580
108	91	UINT8 m_bu;                 // 2/3-bit ram index y
109	92	UINT8 m_acc;                // 4-bit accumulator
110	93	UINT8 m_e;                  // 4-bit generic register
111		UINT8 m_ki_mask;            // 4-bit k/i-pins select latch
	94	UINT8 m_i;                  // 4-bit i-pins latch
	95	UINT8 m_k;                  // 4-bit k-pins latch
112	96	UINT8 m_d;                  // 8-bit d-pins latch
113	97	bool m_d_active;            // d-pins available for direct i/o(floating), or outputting d-latch
114	98	UINT8 m_d_polarity;         // invert d-latch output
r243579	r243580
120	104	devcb_read8 m_read_d;
121	105	devcb_write8 m_write_d;
122	106	devcb_write16 m_write_a;
123		devcb_write_line m_write_f;
124	107
125	108	// misc internal helpers
126	109	UINT8 ram_r();
r243579	r243580
130	113	void d_latch_out(bool active);
131	114
132	115	// opcode handlers
133		virtual void op_lai();
134		virtual void op_lab();
135		virtual void op_lae();
136		virtual void op_xab();
137		virtual void op_xabu();
138		virtual void op_xae();
139		virtual void op_lbe();
140		virtual void op_lbep();
141		virtual void op_lbz();
142		virtual void op_lbf();
	116	void op_lai();
	117	void op_lab();
	118	void op_lae();
	119	void op_xab();
	120	void op_xabu();
	121	void op_xae();
	122	void op_lbe();
	123	void op_lbep();
	124	void op_lbz();
	125	void op_lbf();
143	126
144		virtual void op_lam();
145		virtual void op_xc();
146		virtual void op_xci();
147		virtual void op_xcd();
148		virtual void op_stm();
149		virtual void op_rsm();
	127	void op_lam();
	128	void op_xc();
	129	void op_xci();
	130	void op_xcd();
	131	void op_stm();
	132	void op_rsm();
150	133
151		virtual void op_inp();
152		virtual void op_out();
153		virtual void op_disb();
154		virtual void op_disn();
155		virtual void op_mvs();
156		virtual void op_psh();
157		virtual void op_psl();
158		virtual void op_eur();
	134	void op_inp();
	135	void op_out();
	136	void op_disb();
	137	void op_disn();
	138	void op_mvs();
	139	void op_psh();
	140	void op_psl();
	141	void op_eur();
159	142
160		virtual void op_pp();
161		virtual void op_jmp();
162		virtual void op_jms();
163		virtual void op_rt();
164		virtual void op_rts();
165		virtual void op_nop();
166		virtual void op_halt();
	143	void op_pp();
	144	void op_jmp();
	145	void op_jms();
	146	void op_rt();
	147	void op_rts();
	148	void op_nop();
	149	void op_halt();
167	150
168		virtual void op_szc();
169		virtual void op_szm();
170		virtual void op_szi();
171		virtual void op_szk();
172		virtual void op_sbe();
173		virtual void op_sam();
174		virtual void op_sos();
175		virtual void op_tf1();
176		virtual void op_tf2();
	151	void op_szc();
	152	void op_szm();
	153	void op_szi();
	154	void op_szk();
	155	void op_sbe();
	156	void op_sam();
	157	void op_sos();
	158	void op_tf1();
	159	void op_tf2();
177	160
178		virtual void op_adcs();
179		virtual void op_adis();
180		virtual void op_add();
181		virtual void op_and();
182		virtual void op_xor();
183		virtual void op_stc();
184		virtual void op_rsc();
185		virtual void op_cma();
186		virtual void op_sf1();
187		virtual void op_rf1();
188		virtual void op_sf2();
189		virtual void op_rf2();
	161	void op_adcs();
	162	void op_adis();
	163	void op_add();
	164	void op_and();
	165	void op_xor();
	166	void op_stc();
	167	void op_rsc();
	168	void op_cma();
	169	void op_sf1();
	170	void op_rf1();
	171	void op_sf2();
	172	void op_rf2();
190	173	};
191	174
192	175
193		class amis2000_cpu_device : public amis2000_base_device
	176	class amis2150_device : public amis2000_device
194	177	{
195	178	public:
196		amis2000_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	179	amis2150_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
197	180	};
198	181
199	182
200		class amis2150_cpu_device : public amis2000_base_device
201		{
202		public:
203		amis2150_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
204		};
205	183
206
207		class amis2152_cpu_device : public amis2000_base_device
208		{
209		public:
210		amis2152_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
211		};
212
213
214
215	184	extern const device_type AMI_S2000;
216	185	extern const device_type AMI_S2150;
217		extern const device_type AMI_S2152;
218	186
219	187
220	188	#endif /* _AMIS2000_H_ */

trunk/src/emu/cpu/amis2000/amis2000op.inc

r243579	r243580
2	2
3	3	// internal helpers
4	4
5		inline UINT8 amis2000_base_device::ram_r()
	5	inline UINT8 amis2000_device::ram_r()
6	6	{
7	7	UINT16 address = m_bu << 4 | m_bl;
8	8	return m_data->read_byte(address) & 0xf;
9	9	}
10	10
11		inline void amis2000_base_device::ram_w(UINT8 data)
	11	inline void amis2000_device::ram_w(UINT8 data)
12	12	{
13	13	UINT16 address = m_bu << 4 | m_bl;
14	14	m_data->write_byte(address, data & 0xf);
15	15	}
16	16
17		void amis2000_base_device::pop_callstack()
	17	void amis2000_device::pop_callstack()
18	18	{
19	19	m_pc = (m_pc & ~m_callstack_mask) | (m_callstack[0] & m_callstack_mask);
20	20	for (int i = 0; i < m_callstack_depth-1; i++)
21	21	m_callstack[i] = m_callstack[i+1];
22	22	}
23	23
24		void amis2000_base_device::push_callstack()
	24	void amis2000_device::push_callstack()
25	25	{
26	26	for (int i = m_callstack_depth-1; i >= 1; i--)
27	27	m_callstack[i] = m_callstack[i-1];
28	28	m_callstack[0] = m_pc & m_callstack_mask;
29	29	}
30	30
31		void amis2000_base_device::d_latch_out(bool active)
	31	void amis2000_device::d_latch_out(bool active)
32	32	{
33	33	m_write_d(0, active ? (m_d ^ m_d_polarity) : 0, 0xff);
34	34	m_d_active = active;
r243579	r243580
37	37
38	38	// Register Instructions
39	39
40		void amis2000_base_device::op_lai()
	40	void amis2000_device::op_lai()
41	41	{
42	42	// LAI X: load ACC with X, select I and K inputs
43	43	// note: only execute the first one in a sequence of LAI
r243579	r243580
45	45	{
46	46	UINT8 param = m_op & 0x0f;
47	47	m_acc = param;
48		m_ki_mask = param;
	48	m_i = m_read_i(0, 0xff) & param;
	49	m_k = m_read_k(0, 0xff) & param;
49	50	}
50	51	}
51	52
52		void amis2000_base_device::op_lab()
	53	void amis2000_device::op_lab()
53	54	{
54	55	// LAB: load ACC with BL
55	56	m_acc = m_bl;
56	57	}
57	58
58		void amis2000_base_device::op_lae()
	59	void amis2000_device::op_lae()
59	60	{
60	61	// LAE: load ACC with E
61	62	m_acc = m_e;
62	63	}
63	64
64		void amis2000_base_device::op_xab()
	65	void amis2000_device::op_xab()
65	66	{
66	67	// XAB: exchange ACC with BL
67	68	UINT8 old_acc = m_acc;
r243579	r243580
69	70	m_bl = old_acc;
70	71	}
71	72
72		void amis2000_base_device::op_xabu()
	73	void amis2000_device::op_xabu()
73	74	{
74	75	// XABU: exchange ACC with BU
75	76	UINT8 old_acc = m_acc;
r243579	r243580
77	78	m_bu = old_acc & m_bu_mask;
78	79	}
79	80
80		void amis2000_base_device::op_xae()
	81	void amis2000_device::op_xae()
81	82	{
82	83	// XAE: exchange ACC with E
83	84	UINT8 old_acc = m_acc;
r243579	r243580
85	86	m_e = old_acc;
86	87	}
87	88
88		void amis2000_base_device::op_lbe()
	89	void amis2000_device::op_lbe()
89	90	{
90	91	// LBE Y: load BU with Y, load BL with E
91	92	// note: only execute the first one in a sequence of LB*
r243579	r243580
97	98	}
98	99	}
99	100
100		void amis2000_base_device::op_lbep()
	101	void amis2000_device::op_lbep()
101	102	{
102	103	// LBEP Y: load BU with Y, load BL with E+1
103	104	// note: only execute the first one in a sequence of LB*
r243579	r243580
109	110	}
110	111	}
111	112
112		void amis2000_base_device::op_lbz()
	113	void amis2000_device::op_lbz()
113	114	{
114	115	// LBZ Y: load BU with Y, load BL with 0
115	116	// note: only execute the first one in a sequence of LB*
r243579	r243580
121	122	}
122	123	}
123	124
124		void amis2000_base_device::op_lbf()
	125	void amis2000_device::op_lbf()
125	126	{
126	127	// LBF Y: load BU with Y, load BL with 15
127	128	// note: only execute the first one in a sequence of LB*
r243579	r243580
136	137
137	138	// RAM Instructions
138	139
139		void amis2000_base_device::op_lam()
	140	void amis2000_device::op_lam()
140	141	{
141	142	// LAM _Y: load ACC with RAM, xor BU with _Y
142	143	m_acc = ram_r();
r243579	r243580
144	145	m_bu ^= (param & m_bu_mask);
145	146	}
146	147
147		void amis2000_base_device::op_xc()
	148	void amis2000_device::op_xc()
148	149	{
149	150	// XC _Y: exchange ACC with RAM, xor BU with _Y
150	151	UINT8 old_acc = m_acc;
r243579	r243580
154	155	m_bu ^= (param & m_bu_mask);
155	156	}
156	157
157		void amis2000_base_device::op_xci()
	158	void amis2000_device::op_xci()
158	159	{
159	160	// XCI _Y: exchange ACC with RAM, increment BL(skip next on carry), xor BU with _Y
160	161	op_xc();
r243579	r243580
162	163	m_skip = (m_bl == 0);
163	164	}
164	165
165		void amis2000_base_device::op_xcd()
	166	void amis2000_device::op_xcd()
166	167	{
167	168	// XCD _Y: exchange ACC with RAM, decrement BL(skip next on carry), xor BU with _Y
168	169	op_xc();
r243579	r243580
170	171	m_skip = (m_bl == 0xf);
171	172	}
172	173
173		void amis2000_base_device::op_stm()
	174	void amis2000_device::op_stm()
174	175	{
175	176	// STM Z: set RAM bit Z
176	177	UINT8 param = 1 << (m_op & 0x03);
177	178	ram_w(ram_r() | param);
178	179	}
179	180
180		void amis2000_base_device::op_rsm()
	181	void amis2000_device::op_rsm()
181	182	{
182	183	// RSM Z: reset RAM bit Z
183	184	UINT8 param = 1 << (m_op & 0x03);
r243579	r243580
187	188
188	189	// Input/Output Instructions
189	190
190		void amis2000_base_device::op_inp()
	191	void amis2000_device::op_inp()
191	192	{
192	193	// INP: input D-pins to ACC and RAM
193	194	UINT8 in = m_d_active ? m_d : m_read_d(0, 0xff);
r243579	r243580
195	196	ram_w(in >> 4 & 0xf);
196	197	}
197	198
198		void amis2000_base_device::op_out()
	199	void amis2000_device::op_out()
199	200	{
200	201	// OUT: pulse output ACC and RAM to D-pins
201	202	logerror("%s unknown opcode $%02X at $%04X\n", tag(), m_op, m_pc);
202	203	}
203	204
204		void amis2000_base_device::op_disb()
	205	void amis2000_device::op_disb()
205	206	{
206	207	// DISB: set D-latch to ACC and RAM directly
207	208	m_d = m_acc | ram_r() << 4;
208	209	d_latch_out(true);
209	210	}
210	211
211		void amis2000_base_device::op_disn()
	212	void amis2000_device::op_disn()
212	213	{
213	214	// DISN: set D-latch to ACC+carry via on-die segment decoder
214	215	static const UINT8 lut_segment_decoder[0x10] =
r243579	r243580
220	221	d_latch_out(true);
221	222	}
222	223
223		void amis2000_base_device::op_mvs()
	224	void amis2000_device::op_mvs()
224	225	{
225	226	// MVS: output master strobe latch to A-pins
226	227	d_latch_out(false);
227	228	m_write_a(0, m_a, 0xffff);
228	229	}
229	230
230		void amis2000_base_device::op_psh()
	231	void amis2000_device::op_psh()
231	232	{
232	233	// PSH: preset high(BL) master strobe latch
233	234	switch (m_bl)
r243579	r243580
254	255	}
255	256	}
256	257
257		void amis2000_base_device::op_psl()
	258	void amis2000_device::op_psl()
258	259	{
259	260	// PSL: preset low(BL) master strobe latch
260	261	switch (m_bl)
r243579	r243580
281	282	}
282	283	}
283	284
284		void amis2000_base_device::op_eur()
	285	void amis2000_device::op_eur()
285	286	{
286	287	// EUR: set timer frequency(European) and D-latch polarity, via ACC
287	288	m_d_polarity = (m_acc & 1) ? 0x00 : 0xff;
r243579	r243580
291	292
292	293	// Program Control Instructions
293	294
294		void amis2000_base_device::op_pp()
	295	void amis2000_device::op_pp()
295	296	{
296	297	// PP _X: prepare page/bank with _X
297	298	UINT8 param = ~m_op & 0x0f;
r243579	r243580
301	302	m_pbr = param & 7;
302	303	}
303	304
304		void amis2000_base_device::op_jmp()
	305	void amis2000_device::op_jmp()
305	306	{
306	307	// JMP X: jump to X(+PP)
307	308	UINT16 mask = 0x3f;
r243579	r243580
316	317	m_pc = (m_pc & ~mask) | param;
317	318	}
318	319
319		void amis2000_base_device::op_jms()
	320	void amis2000_device::op_jms()
320	321	{
321	322	// JMS X: call to X(+PP)
322	323	m_icount--;
r243579	r243580
328	329	m_pc |= 0x3c0;
329	330	}
330	331
331		void amis2000_base_device::op_rt()
	332	void amis2000_device::op_rt()
332	333	{
333	334	// RT: return from subroutine
334	335	pop_callstack();
335	336	}
336	337
337		void amis2000_base_device::op_rts()
	338	void amis2000_device::op_rts()
338	339	{
339	340	// RTS: return from subroutine and skip next
340	341	op_rt();
341	342	m_skip = true;
342	343	}
343	344
344		void amis2000_base_device::op_nop()
	345	void amis2000_device::op_nop()
345	346	{
346	347	// NOP: no operation
347	348	}
348	349
349		void amis2000_base_device::op_halt()
	350	void amis2000_device::op_halt()
350	351	{
351	352	// HALT: debugger breakpoint for devkit-use
352	353	logerror("%s unknown opcode $%02X at $%04X\n", tag(), m_op, m_pc);
r243579	r243580
355	356
356	357	// Skip Instructions
357	358
358		void amis2000_base_device::op_szc()
	359	void amis2000_device::op_szc()
359	360	{
360	361	// SZC: skip next on zero(no) carry
361	362	m_skip = !m_carry;
362	363	}
363	364
364		void amis2000_base_device::op_szm()
	365	void amis2000_device::op_szm()
365	366	{
366	367	// SZM Z: skip next on zero RAM bit Z
367	368	UINT8 param = 1 << (m_op & 0x03);
368	369	m_skip = !(ram_r() & param);
369	370	}
370	371
371		void amis2000_base_device::op_szi()
	372	void amis2000_device::op_szi()
372	373	{
373		// SZI: skip next on I pin(s)
374		m_skip = ((~m_read_i(0, 0xff) & m_ki_mask) != 0);
	374	// SZI: skip next on zero I pin(s)
	375	m_skip = !m_i;
375	376	}
376	377
377		void amis2000_base_device::op_szk()
	378	void amis2000_device::op_szk()
378	379	{
379		// SZK: skip next on K pin(s)
380		m_skip = ((~m_read_k(0, 0xff) & m_ki_mask) != 0);
	380	// SZK: skip next on zero K pin(s)
	381	m_skip = !m_k;
381	382	}
382	383
383		void amis2000_base_device::op_sbe()
	384	void amis2000_device::op_sbe()
384	385	{
385	386	// SBE: skip next on BL equals E
386	387	m_skip = (m_bl == m_e);
387	388	}
388	389
389		void amis2000_base_device::op_sam()
	390	void amis2000_device::op_sam()
390	391	{
391	392	// SAM: skip next on ACC equals RAM
392	393	m_skip = (m_acc == ram_r());
393	394	}
394	395
395		void amis2000_base_device::op_sos()
	396	void amis2000_device::op_sos()
396	397	{
397	398	// SOS: skip next on SF(timer output), clear SF
398	399	logerror("%s unknown opcode $%02X at $%04X\n", tag(), m_op, m_pc);
399	400	}
400	401
401		void amis2000_base_device::op_tf1()
	402	void amis2000_device::op_tf1()
402	403	{
403	404	// TF1: skip next on flag 1
404	405	m_skip = ((m_f & 0x01) != 0);
405	406	}
406	407
407		void amis2000_base_device::op_tf2()
	408	void amis2000_device::op_tf2()
408	409	{
409	410	// TF2: skip next on flag 2
410	411	m_skip = ((m_f & 0x02) != 0);
r243579	r243580
413	414
414	415	// Arithmetic and Logical Instructions
415	416
416		void amis2000_base_device::op_adcs()
	417	void amis2000_device::op_adcs()
417	418	{
418	419	// ADCS: add RAM to ACC+carry, skip next on not carry
419	420	m_acc += ram_r() + m_carry;
r243579	r243580
422	423	m_acc &= 0xf;
423	424	}
424	425
425		void amis2000_base_device::op_adis()
	426	void amis2000_device::op_adis()
426	427	{
427	428	// ADIS X: add X to ACC, skip next on not carry
428	429	UINT8 param = m_op & 0x0f;
r243579	r243580
431	432	m_acc &= 0xf;
432	433	}
433	434
434		void amis2000_base_device::op_add()
	435	void amis2000_device::op_add()
435	436	{
436	437	// ADD: add RAM to ACC
437	438	m_acc = (m_acc + ram_r()) & 0xf;
438	439	}
439	440
440		void amis2000_base_device::op_and()
	441	void amis2000_device::op_and()
441	442	{
442	443	// AND: and ACC with RAM
443	444	m_acc &= ram_r();
444	445	}
445	446
446		void amis2000_base_device::op_xor()
	447	void amis2000_device::op_xor()
447	448	{
448	449	// XOR: xor ACC with RAM
449	450	m_acc ^= ram_r();
450	451	}
451	452
452		void amis2000_base_device::op_stc()
	453	void amis2000_device::op_stc()
453	454	{
454	455	// STC: set carry
455	456	m_carry = 1;
456	457	}
457	458
458		void amis2000_base_device::op_rsc()
	459	void amis2000_device::op_rsc()
459	460	{
460	461	// RSC: reset carry
461	462	m_carry = 0;
462	463	}
463	464
464		void amis2000_base_device::op_cma()
	465	void amis2000_device::op_cma()
465	466	{
466	467	// CMA: complement ACC
467	468	m_acc ^= 0xf;
468	469	}
469	470
470		void amis2000_base_device::op_sf1()
	471	void amis2000_device::op_sf1()
471	472	{
472	473	// SF1: set flag 1
473	474	m_f |= 0x01;
474	475	}
475	476
476		void amis2000_base_device::op_rf1()
	477	void amis2000_device::op_rf1()
477	478	{
478	479	// RF1: reset flag 1
479	480	m_f &= ~0x01;
480	481	}
481	482
482		void amis2000_base_device::op_sf2()
	483	void amis2000_device::op_sf2()
483	484	{
484	485	// SF2: set flag 2
485	486	m_f |= 0x02;
486	487	}
487	488
488		void amis2000_base_device::op_rf2()
	489	void amis2000_device::op_rf2()
489	490	{
490	491	// RF2: reset flag 2
491	492	m_f &= ~0x02;

trunk/src/emu/cpu/ucom4/ucom4.c

r243579	r243580
10	10	I've also looked at asterick's JavaScript D553 emulator for verification, with permission.
11	11
12	12	TODO:
	13	- add external interrupt
13	14	- what happens with uCOM-43 opcodes on an uCOM-44/45 MCU?
14	15	- what's the data after the ROM data for? (eg. 2000-2047, official ROM size is 2000)
15	16
r243579	r243580
152	153	m_timer_f = 0;
153	154	m_int_f = 0;
154	155	m_inte_f = 0;
155		m_int_line = CLEAR_LINE;
156	156
157	157	// register for savestates
158	158	save_item(NAME(m_stack));
r243579	r243580
168	168	save_item(NAME(m_carry_s_f));
169	169	save_item(NAME(m_timer_f));
170	170	save_item(NAME(m_int_f));
171		save_item(NAME(m_int_line));
	171	save_item(NAME(m_inte_f));
172	172
173	173	// register state for debugger
174	174	state_add(UCOM4_PC, "PC",  m_pc).formatstr("%04X");
r243579	r243580
195	195	m_skip = false;
196	196
197	197	m_timer->adjust(attotime::never);
198
199		// clear interrupt
200		m_int_line = CLEAR_LINE;
201		m_int_f = 0;
202		m_inte_f = (m_family == NEC_UCOM43) ? 0 : 1;
203
	198
204	199	// clear i/o
205	200	for (int i = NEC_UCOM4_PORTC; i <= NEC_UCOM4_PORTI; i++)
206	201	output_w(i, 0xf);
r243579	r243580
212	207	//  execute
213	208	//-------------------------------------------------
214	209
215		void ucom4_cpu_device::execute_set_input(int line, int state)
216		{
217		switch (line)
218		{
219		case 0:
220		// edge triggered
221		if (m_int_line == CLEAR_LINE && state)
222		m_int_f = 1;
223		m_int_line = state;
224
225		break;
226
227		default:
228		break;
229		}
230		}
231
232	210	inline void ucom4_cpu_device::increment_pc()
233	211	{
234	212	// upper bits (field register) don't auto-increment
r243579	r243580
255	233	// remember previous opcode
256	234	m_prev_op = m_op;
257	235
258		// handle interrupt - it not accepted during LI($9x) or EI($31), or while skipping
259		if (m_int_f && m_inte_f && (m_prev_op & 0xf0) != 0x90 && m_prev_op != 0x31 && !m_skip)
260		{
261		m_icount--;
262		push_stack();
263		m_pc = 0xf << 2;
264		m_int_f = 0;
265		m_inte_f = (m_family == NEC_UCOM43) ? 0 : 1;
266
267		standard_irq_callback(0);
268		}
269
270		// fetch next opcode
271	236	debugger_instruction_hook(this, m_pc);
272	237	m_op = m_program->read_byte(m_pc);
273	238	m_bitmask = 1 << (m_op & 0x03);
r243579	r243580
280	245	m_op = 0; // nop
281	246	}
282	247
283		// handle opcode
284	248	switch (m_op & 0xf0)
285	249	{
286	250	case 0x80: op_ldz(); break;

trunk/src/emu/cpu/ucom4/ucom4.h

r243579	r243580
110	110	virtual UINT32 execute_min_cycles() const { return 1; }
111	111	virtual UINT32 execute_max_cycles() const { return 2; }
112	112	virtual UINT32 execute_input_lines() const { return 1; }
113		virtual void execute_set_input(int line, int state);
114	113	virtual void execute_run();
115
	114
116	115	// device_memory_interface overrides
117	116	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return(spacenum == AS_PROGRAM) ? &m_program_config :((spacenum == AS_DATA) ? &m_data_config : NULL); }
118	117
r243579	r243580
154	153	UINT8 m_timer_f;        // timer out flag
155	154	UINT8 m_int_f;          // interrupt flag
156	155	UINT8 m_inte_f;         // interrupt enable flag
157		int m_int_line;         // interrupt pin state
158	156
159	157	// i/o handlers
160	158	devcb_read8 m_read_a;

trunk/src/emu/video/scn2674.c

r243579	r243580
1		/*
2		SCN2674 - Advanced Video Display Controller (AVDC)  (Video Chip)
3		*/
4
5		#include "scn2674.h"
6
7		#define S674VERBOSE 0
8		#define LOG2674(x) do { if (S674VERBOSE) logerror x; } while (0)
9
10		const device_type SCN2674_VIDEO = &device_creator<scn2674_device>;
11
12
13		// default address map
14		static ADDRESS_MAP_START( scn2674_vram, AS_0, 8, scn2674_device )
15		AM_RANGE(0x0000, 0xffff) AM_NOP
16		ADDRESS_MAP_END
17
18		scn2674_device::scn2674_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
19		: device_t(mconfig, SCN2674_VIDEO, "Signetics SCN2674 AVDC", tag, owner, clock, "scn2674_device", __FILE__),
20		device_video_interface(mconfig, *this),
21		device_memory_interface(mconfig, *this),
22		m_irq_cb(*this),
23		m_space_config("videoram", ENDIANNESS_LITTLE, 8, 16, 0, NULL, *ADDRESS_MAP_NAME(scn2674_vram))
24		{
25		}
26
27		void scn2674_device::device_start()
28		{
29		// resolve callbacks
30		m_display_cb.bind_relative_to(*owner());
31		m_irq_cb.resolve_safe();
32		m_scanline_timer = timer_alloc(TIMER_SCANLINE);
33		m_screen->register_screen_bitmap(m_bitmap);
34
35		save_item(NAME(m_address));
36		save_item(NAME(m_linecounter));
37		save_item(NAME(m_screen2_l));
38		save_item(NAME(m_screen2_h));
39		}
40
41		void scn2674_device::device_reset()
42		{
43		m_IR_pointer= 0;
44		m_screen1_l= 0;
45		m_screen1_h= 0;
46		m_cursor_l= 0;
47		m_cursor_h= 0;
48		m_screen2_l= 0;
49		m_screen2_h= 0;
50		m_irq_register= 0;
51		m_status_register= 0;
52		m_irq_mask= 0;
53		m_gfx_enabled= 0;
54		m_display_enabled= 0;
55		m_display_enabled_field= 0;
56		m_display_enabled_scanline= 0;
57		m_cursor_enabled= 0;
58		m_IR0_double_ht_wd= 0;
59		m_IR0_scanline_per_char_row= 0;
60		m_IR0_sync_select= 0;
61		m_IR0_buffer_mode_select= 0;
62		m_IR1_interlace_enable= 0;
63		m_IR1_equalizing_constant= 0;
64		m_IR2_row_table= 0;
65		m_IR2_horz_sync_width= 0;
66		m_IR2_horz_back_porch= 0;
67		m_IR3_vert_front_porch= 0;
68		m_IR3_vert_back_porch= 0;
69		m_IR4_rows_per_screen= 0;
70		m_IR4_character_blink_rate_divisor= 0;
71		m_IR5_character_per_row= 0;
72		m_IR6_cursor_first_scanline= 0;
73		m_IR6_cursor_last_scanline= 0;
74		m_IR7_cursor_underline_position= 0;
75		m_IR7_cursor_rate_divisor= 0;
76		m_IR7_cursor_blink= 0;
77		m_IR7_vsync_width= 0;
78		m_IR8_display_buffer_first_address_LSB= 0;
79		m_IR9_display_buffer_first_address_MSB= 0;
80		m_IR9_display_buffer_last_address= 0;
81		m_IR10_display_pointer_address_lower= 0;
82		m_IR11_display_pointer_address_upper= 0;
83		m_IR11_reset_scanline_counter_on_scrollup= 0;
84		m_IR11_reset_scanline_counter_on_scrolldown= 0;
85		m_IR12_scroll_start= 0;
86		m_IR12_split_register_1= 0;
87		m_IR13_scroll_end= 0;
88		m_IR13_split_register_2= 0;
89		m_IR14_scroll_lines= 0;
90		m_IR14_double_1= 0;
91		m_IR14_double_2= 0;
92		m_spl1= 0;
93		m_spl2= 0;
94		m_dbl1= 0;
95		m_linecounter= 0;
96		m_irq_state= 0;
97		m_IR_pointer = 0;
98		m_address = 0;
99		m_hpixels_per_column = m_text_hpixels_per_column;
100		}
101
102		// 15 Initialization Registers (8-bit each)
103		void scn2674_device::write_init_regs(UINT8 data)
104		{
105		LOG2674(("scn2674_write_init_regs %02x %02x\n",m_IR_pointer,data));
106
107		switch ( m_IR_pointer) /* display some debug info, set mame specific variables */
108		{
109		case 0:
110		m_IR0_double_ht_wd = (data & 0x80)>>7;
111		m_IR0_scanline_per_char_row = ((data & 0x78)>>3) + 1;
112		m_IR0_sync_select = (data&0x04)>>2;
113		m_IR0_buffer_mode_select = (data&0x03);
114
115		LOG2674(("IR0 - Double Ht Wd %02x\n",m_IR0_double_ht_wd));//affects IR14 as well
116		LOG2674(("IR0 - Scanlines per Character Row %02x\n",m_IR0_scanline_per_char_row));//value+1 = scanlines
117		LOG2674(("IR0 - Sync Select %02x\n",m_IR0_sync_select));//1 = csync
118		LOG2674(("IR0 - Buffer Mode Select %02x\n",m_IR0_buffer_mode_select)); //0 independent 1 transparent 2 shared 3 row
119		break;
120
121		case 1:
122		m_IR1_interlace_enable = (data&0x80)>>7;
123		m_IR1_equalizing_constant = (data&0x7f)+1;
124
125		LOG2674(("IR1 - Interlace Enable %02x\n",m_IR1_interlace_enable));
126		LOG2674(("IR1 - Equalizing Constant %02i CCLKs\n",m_IR1_equalizing_constant));
127		break;
128
129		case 2:
130		m_IR2_row_table = (data&0x80)>>7;
131		m_IR2_horz_sync_width = (((data&0x78)>>3)*2) + 2;
132		m_IR2_horz_back_porch = ((data&0x07)*4) - 1;
133
134		LOG2674(("IR2 - Row Table %02x\n",m_IR2_row_table));
135		LOG2674(("IR2 - Horizontal Sync Width %02i CCLKs\n",m_IR2_horz_sync_width));
136		LOG2674(("IR2 - Horizontal Back Porch %02i CCLKs\n",m_IR2_horz_back_porch));
137		break;
138
139		case 3:
140		m_IR3_vert_front_porch =  (((data&0xe0)>>5) * 4)+4 ;
141		m_IR3_vert_back_porch = ((data&0x1f) * 2) + 4;
142
143		LOG2674(("IR3 - Vertical Front Porch %02i Lines\n",m_IR3_vert_front_porch));
144		LOG2674(("IR3 - Vertical Back Porch %02i Lines\n",m_IR3_vert_back_porch));
145		break;
146
147		case 4:
148		m_IR4_rows_per_screen = (data&0x7f) + 1;
149		m_IR4_character_blink_rate_divisor = ((data & 0x80)>>7 ? 128:64);
150
151		LOG2674(("IR4 - Rows Per Screen %02i\n",m_IR4_rows_per_screen));
152		LOG2674(("IR4 - Character Blink Rate = 1/%02i\n",m_IR4_character_blink_rate_divisor));
153		break;
154
155		case 5:
156		/* IR5 - Active Characters Per Row
157		cccc cccc
158		c = Characters Per Row */
159		m_IR5_character_per_row = data + 1;
160		LOG2674(("IR5 - Active Characters Per Row %02i\n",m_IR5_character_per_row));
161		break;
162
163		case 6:
164		m_IR6_cursor_last_scanline = (data & 0x0f);
165		m_IR6_cursor_first_scanline = (data & 0xf0)>>4;
166		LOG2674(("IR6 - First Line of Cursor %02x\n",m_IR6_cursor_first_scanline));
167		LOG2674(("IR6 - Last Line of Cursor %02x\n",m_IR6_cursor_last_scanline));
168		break;
169
170		case 7:
171		{
172		const UINT8 vsync_table[4] = {3,1,5,7};
173		m_IR7_cursor_underline_position = (data & 0x0f);
174		m_IR7_cursor_rate_divisor = ((data & 0x10)>>4 ? 64:32);
175		m_IR7_cursor_blink = (data & 0x20)>>5;
176
177		m_IR7_vsync_width = vsync_table[(data & 0xC0)>>6];
178
179		LOG2674(("IR7 - Underline Position %02x\n",m_IR7_cursor_underline_position));
180		LOG2674(("IR7 - Cursor rate 1/%02i\n",m_IR7_cursor_rate_divisor));
181		LOG2674(("IR7 - Cursor blink %02x\n",m_IR7_cursor_blink));
182		LOG2674(("IR7 - Vsync Width  %02i Lines\n",m_IR7_vsync_width));
183		break;
184		}
185
186		case 8:
187		m_IR8_display_buffer_first_address_LSB = data;
188		LOG2674(("IR8 - Display Buffer First Address LSB %02x\n",m_IR8_display_buffer_first_address_LSB));
189		break;
190
191		case 9:
192		m_IR9_display_buffer_first_address_MSB = data & 0x0f;
193		m_IR9_display_buffer_last_address = (data & 0xf0)>>4;
194		LOG2674(("IR9 - Display Buffer First Address MSB %02x\n",m_IR9_display_buffer_first_address_MSB));
195		LOG2674(("IR9 - Display Buffer Last Address %02x\n",m_IR9_display_buffer_last_address));
196		break;
197
198		case 10:
199		m_IR10_display_pointer_address_lower = data;
200		LOG2674(("IR10 - Display Pointer Address Lower %02x\n",m_IR10_display_pointer_address_lower));
201		break;
202
203		case 11:
204		m_IR11_display_pointer_address_upper= data&0x3f;
205		m_IR11_reset_scanline_counter_on_scrollup= (data&0x40 >> 6);
206		m_IR11_reset_scanline_counter_on_scrolldown= (data&0x80 >> 7);
207
208		LOG2674(("IR11 - Display Pointer Address Lower %02x\n",m_IR11_display_pointer_address_upper));
209		LOG2674(("IR11 - Reset Scanline Counter on Scroll Up %02x\n",m_IR11_reset_scanline_counter_on_scrollup));
210		LOG2674(("IR11 - Reset Scanline Counter on Scroll Down %02x\n",m_IR11_reset_scanline_counter_on_scrolldown));
211		break;
212
213		case 12:
214		m_IR12_scroll_start = (data & 0x80)>>7;
215		m_IR12_split_register_1 = (data & 0x7f);
216		LOG2674(("IR12 - Scroll Start %02x\n",m_IR12_scroll_start));
217		LOG2674(("IR12 - Split Register 1 %02x\n",m_IR12_split_register_1));
218		break;
219
220		case 13:
221		m_IR13_scroll_end = (data & 0x80)>>7;
222		m_IR13_split_register_2 = (data & 0x7f);
223		LOG2674(("IR13 - Scroll End %02x\n",m_IR13_scroll_end));
224		LOG2674(("IR13 - Split Register 2 %02x\n",m_IR13_split_register_2));
225		break;
226
227		case 14:
228		m_IR14_scroll_lines = (data & 0x0f);
229		if (!m_IR0_double_ht_wd)
230		{
231		m_IR14_double_2 = (data & 0x30)>>4;
232		LOG2674(("IR14 - Double 2 %02x\n",m_IR14_double_2));
233		}
234		//0 normal, 1, double width, 2, double width and double tops 3, double width and double bottoms
235		//1 affects SSR1, 2 affects SSR2
236		//If Double Height enabled in IR0, Screen start 1 upper (bits 7 and 6)replace Double 1, and Double 2 is unused
237		m_IR14_double_1 = (data & 0xc0)>>6;
238		LOG2674(("IR14 - Double 1 %02x\n",m_IR14_double_1));
239
240		LOG2674(("IR14 - Scroll Lines %02i\n",m_IR14_scroll_lines));
241		break;
242
243		case 15: /* not valid! */
244		break;
245
246		}
247		if(m_display_enabled)
248		recompute_parameters();
249
250		m_IR_pointer++;
251		if (m_IR_pointer>14)m_IR_pointer=14;
252		}
253
254		void scn2674_device::write_command(UINT8 data)
255		{
256		UINT8 operand;
257		int i;
258
259
260		if (data==0x00)
261		{
262		/* master reset, configures registers */
263		LOG2674(("master reset\n"));
264		m_IR_pointer=0;
265		m_irq_register = 0x00;
266		m_status_register = 0x20;//RDFLG activated
267		m_linecounter =0;
268		m_irq_mask = 0x00;
269		m_gfx_enabled = 0;
270		m_display_enabled = 0;
271		m_cursor_enabled = 0;
272		m_IR2_row_table = 0;
273		}
274
275		if ((data&0xf0)==0x10)
276		{
277		/* set IR pointer */
278		operand = data & 0x0f;
279		LOG2674(("set IR pointer %02x\n",operand));
280
281		m_IR_pointer=operand;
282
283		}
284
285		/* ANY COMBINATION OF THESE ARE POSSIBLE */
286
287		if ((data&0xe3)==0x22)
288		{
289		/* Disable GFX */
290		LOG2674(("disable GFX %02x\n",data));
291		m_gfx_enabled = 0;
292		if(m_display_enabled)
293		recompute_parameters();
294		}
295
296		if ((data&0xe3)==0x23)
297		{
298		/* Enable GFX */
299		LOG2674(("enable GFX %02x\n",data));
300		m_gfx_enabled = 1;
301		if(m_display_enabled)
302		recompute_parameters();
303		}
304
305		if ((data&0xe9)==0x28)
306		{
307		/* Display off */
308		operand = data & 0x04;
309
310		m_display_enabled = 0;
311
312		if (operand)
313		LOG2674(("display OFF - float DADD bus %02x\n",data));
314		else
315		LOG2674(("display OFF - no float DADD bus %02x\n",data));
316		}
317
318		if ((data&0xe9)==0x29)
319		{
320		/* Display on */
321		operand = data & 0x04;
322
323		if (operand)
324		{
325		m_display_enabled_field = 1;
326		LOG2674(("display ON - next field %02x\n",data));
327		}
328		else
329		{
330		m_display_enabled_scanline = 1;
331		LOG2674(("display ON - next scanline %02x\n",data));
332		}
333		recompute_parameters(); // start the scanline timer
334		}
335
336		if ((data&0xf1)==0x30)
337		{
338		/* Cursor Off */
339		LOG2674(("cursor off %02x\n",data));
340		m_cursor_enabled = 0;
341		}
342
343		if ((data&0xf1)==0x31)
344		{
345		/* Cursor On */
346		LOG2674(("cursor on %02x\n",data));
347		m_cursor_enabled = 1;
348		}
349
350		/* END */
351
352		if ((data&0xe0)==0x40)
353		{
354		/* Reset Interrupt / Status bit */
355		operand = data & 0x1f;
356		LOG2674(("reset interrupt / status bit %02x\n",operand));
357
358		m_irq_register &= ~(data & 0x1f);
359		m_status_register &= ~(data & 0x1f);
360
361		LOG2674(("IRQ Status after reset\n"));
362		LOG2674(("Split 2   IRQ: %d Active\n",(m_irq_register>>0)&1));
363		LOG2674(("Ready     IRQ: %d Active\n",(m_irq_register>>1)&1));
364		LOG2674(("Split 1   IRQ: %d Active\n",(m_irq_register>>2)&1));
365		LOG2674(("Line Zero IRQ: %d Active\n",(m_irq_register>>3)&1));
366		LOG2674(("V-Blank   IRQ: %d Active\n",(m_irq_register>>4)&1));
367
368		m_irq_state = 0;
369
370		for (i = 0; i < 5; i++)
371		{
372		if ((m_irq_register>>i&1)&(m_irq_mask>>i&1))
373		{
374		m_irq_state = 1;
375		}
376		}
377		m_irq_cb(m_irq_register ? 1 : 0);
378
379		}
380		if ((data&0xe0)==0x80)
381		{
382		/* Disable Interrupt mask*/
383		operand = data & 0x1f;
384		m_irq_mask &= ~(operand);
385		LOG2674(("IRQ Mask after disable %x\n",operand));
386		LOG2674(("Split 2   IRQ: %d Unmasked\n",(m_irq_mask>>0)&1));
387		LOG2674(("Ready     IRQ: %d Unmasked\n",(m_irq_mask>>1)&1));
388		LOG2674(("Split 1   IRQ: %d Unmasked\n",(m_irq_mask>>2)&1));
389		LOG2674(("Line Zero IRQ: %d Unmasked\n",(m_irq_mask>>3)&1));
390		LOG2674(("V-Blank   IRQ: %d Unmasked\n",(m_irq_mask>>4)&1));
391
392		}
393
394		if ((data&0xe0)==0x60)
395		{
396		/* Enable Interrupt mask*/
397		operand = data & 0x1f;
398		m_irq_mask |= (data & 0x1f);
399
400		LOG2674(("IRQ Mask after enable %x\n",operand));
401		LOG2674(("Split 2   IRQ: %d Unmasked\n",(m_irq_mask>>0)&1));
402		LOG2674(("Ready     IRQ: %d Unmasked\n",(m_irq_mask>>1)&1));
403		LOG2674(("Split 1   IRQ: %d Unmasked\n",(m_irq_mask>>2)&1));
404		LOG2674(("Line Zero IRQ: %d Unmasked\n",(m_irq_mask>>3)&1));
405		LOG2674(("V-Blank   IRQ: %d Unmasked\n",(m_irq_mask>>4)&1));
406
407		}
408
409		/* Delayed Commands */
410		/* These set 0x20 in status register when done */
411
412		if (data == 0xa4)
413		{
414		/* read at pointer address */
415		LOG2674(("DELAYED read at pointer address %02x\n",data));
416		}
417
418		if (data == 0xa2)
419		{
420		/* write at pointer address */
421		LOG2674(("DELAYED write at pointer address %02x\n",data));
422		}
423
424		if (data == 0xa9)
425		{
426		/* increase cursor address */
427		LOG2674(("DELAYED increase cursor address %02x\n",data));
428		}
429
430		if (data == 0xac)
431		{
432		/* read at cursor address */
433		LOG2674(("DELAYED read at cursor address %02x\n",data));
434		}
435
436		if (data == 0xaa)
437		{
438		/* write at cursor address */
439		LOG2674(("DELAYED write at cursor address %02x\n",data));
440		}
441
442		if (data == 0xad)
443		{
444		/* read at cursor address + increment */
445		LOG2674(("DELAYED read at cursor address+increment %02x\n",data));
446		}
447
448		if (data == 0xab)
449		{
450		/* write at cursor address + increment */
451		LOG2674(("DELAYED write at cursor address+increment %02x\n",data));
452		}
453
454		if (data == 0xbb)
455		{
456		/* write from cursor address to pointer address */
457		LOG2674(("DELAYED write from cursor address to pointer address %02x\n",data));
458		}
459
460		if (data == 0xbd)
461		{
462		/* read from cursor address to pointer address */
463		LOG2674(("DELAYED read from cursor address to pointer address %02x\n",data));
464		}
465		}
466
467
468		READ8_MEMBER( scn2674_device::read )
469		{
470		/*
471		Offset:  Purpose
472		0       Interrupt Register
473		1       Status Register
474		2       Screen Start 1 Lower Register
475		3       Screen Start 1 Upper Register
476		4       Cursor Address Lower Register
477		5       Cursor Address Upper Register
478		6       Screen Start 2 Lower Register
479		7       Screen Start 2 Upper Register
480		*/
481
482		switch (offset)
483		{
484		/*  Status / Irq Register
485
486		--RV ZSRs
487
488		6+7 -- = ALWAYS 0
489		5  R  = RDFLG (Status Register Only)
490		4  V  = Vblank
491		3  Z  = Line Zero
492		2  S  = Split 1
493		1  R  = Ready
494		0  s  = Split 2
495		*/
496
497		case 0:
498		LOG2674(("Read Irq Register %02x %06x\n",m_irq_register,space.device().safe_pc()));
499		return m_irq_register;
500
501		case 1:
502		LOG2674(("Read Status Register %02X %06x\n",m_status_register,space.device().safe_pc()));
503		return m_status_register;
504
505		case 2: LOG2674(("Read Screen1_l Register %06x\n",space.device().safe_pc()));return m_screen1_l;
506		case 3: LOG2674(("Read Screen1_h Register %06x\n",space.device().safe_pc()));return m_screen1_h & 0x3f;
507		case 4: LOG2674(("Read Cursor_l Register %06x\n",space.device().safe_pc()));return m_cursor_l;
508		case 5: LOG2674(("Read Cursor_h Register %06x\n",space.device().safe_pc()));return m_cursor_h;
509		case 6: LOG2674(("Read Screen2_l Register %06x\n",space.device().safe_pc()));return m_screen2_l;
510		case 7: LOG2674(("Read Screen2_h Register %06x\n",space.device().safe_pc()));return m_screen2_h;
511		}
512
513		return 0xff;
514		}
515
516
517		WRITE8_MEMBER( scn2674_device::write )
518		{
519		/*
520		Offset:  Purpose
521		0       Initialization Registers
522		1       Command Register
523		2       Screen Start 1 Lower Register
524		3       Screen Start 1 Upper Register
525		4       Cursor Address Lower Register
526		5       Cursor Address Upper Register
527		6       Screen Start 2 Lower Register
528		7       Screen Start 2 Upper Register
529		*/
530
531		switch (offset)
532		{
533		case 0:
534		write_init_regs(data);
535		break;
536
537		case 1:
538		write_command(data);
539		break;
540
541		case 2: m_screen1_l = data; break;
542		case 3:
543		m_screen1_h = data;
544		m_dbl1=(data & 0xc0)>>6;
545		if (m_IR0_double_ht_wd)
546		{
547		m_IR14_double_1 = m_dbl1;
548		m_screen1_h &= 0x3f;
549		LOG2674(("IR14 - Double 1 overridden %02x\n",m_IR14_double_1));
550		}
551		break;
552
553		case 4: m_cursor_l  = data; break;
554		case 5: m_cursor_h  = (data & 0x3f); break;
555		case 6: m_screen2_l = data; break;
556		case 7:
557		m_screen2_h = (data&0x3f);
558		m_spl1 = (data & 0x40);
559		m_spl2 = (data & 0x80);
560		break;
561		}
562		}
563
564		void scn2674_device::recompute_parameters()
565		{
566		m_hpixels_per_column = m_gfx_enabled ? m_gfx_hpixels_per_column : m_text_hpixels_per_column;
567		int horiz_pix_total = ((m_IR1_equalizing_constant + (m_IR2_horz_sync_width << 1)) << 1) * m_hpixels_per_column;
568		int vert_pix_total = m_IR4_rows_per_screen * m_IR0_scanline_per_char_row + m_IR3_vert_front_porch + m_IR3_vert_back_porch + m_IR7_vsync_width;
569		attoseconds_t refresh = m_screen->frame_period().attoseconds;
570		int max_visible_x = (m_IR5_character_per_row * m_hpixels_per_column) - 1;
571		int max_visible_y = (m_IR4_rows_per_screen * m_IR0_scanline_per_char_row) - 1;
572
573		LOG2674(("width %u height %u max_x %u max_y %u refresh %f\n", horiz_pix_total, vert_pix_total, max_visible_x, max_visible_y, 1 / ATTOSECONDS_TO_DOUBLE(refresh)));
574
575		rectangle visarea;
576		visarea.set(0, max_visible_x, 0, max_visible_y);
577		m_screen->configure(horiz_pix_total, vert_pix_total, visarea, refresh);
578
579		m_scanline_timer->adjust(m_screen->time_until_pos(0, 0), 0, m_screen->scan_period());
580		}
581
582		void scn2674_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
583		{
584		switch(id)
585		{
586		case TIMER_SCANLINE:
587		{
588		int dw = m_IR0_double_ht_wd ? m_IR14_double_1 : 0;  // double width
589		if(((m_display_enabled_scanline) || (m_display_enabled_field && !m_IR1_interlace_enable)) && (!m_display_enabled))
590		{
591		m_display_enabled = 1;
592		m_display_enabled_scanline = 0;
593		m_display_enabled_field = 0;
594		}
595		else if(!m_display_enabled)
596		break;
597		else
598		m_linecounter++;
599
600		// should be triggered at the start of each ROW (line zero for that row)
601		if(m_linecounter >= m_screen->height())
602		{
603		m_status_register |= 0x08;
604		if (m_irq_mask & 0x08)
605		{
606		LOG2674(("SCN2674 Line Zero\n"));
607		m_irq_state = 1;
608		m_irq_register |= 0x08;
609		m_irq_cb(1);
610		}
611		m_linecounter = 0;
612		m_address = (m_screen1_h << 8) | m_screen1_l;
613		}
614
615		if(m_linecounter == (m_IR4_rows_per_screen * m_IR0_scanline_per_char_row))
616		{
617		m_status_register |= 0x10;
618		if(m_irq_mask & 0x10)
619		{
620		LOG2674(("vblank irq\n"));
621		m_irq_state = 1;
622		m_irq_register |= 0x10;
623		m_irq_cb(1);
624		}
625		}
626
627		if(m_linecounter >= (m_IR4_rows_per_screen * m_IR0_scanline_per_char_row))
628		break;
629
630		if((m_linecounter == (m_IR12_split_register_1 * m_IR0_scanline_per_char_row)) && m_linecounter) /* Split Screen 1 */
631		{
632		m_status_register |= 0x04;
633		if(m_irq_mask & 0x04)
634		{
635		LOG2674(("SCN2674 Split Screen 1 irq\n"));
636		m_irq_state = 1;
637		m_irq_register |= 0x04;
638		m_irq_cb(1);
639		}
640		if(m_spl1)
641		m_address = (m_screen2_h << 8) | m_screen2_l;
642		if(!m_IR0_double_ht_wd)
643		dw = m_IR14_double_1;
644		}
645
646		if((m_linecounter == (m_IR13_split_register_2 * m_IR0_scanline_per_char_row)) && m_linecounter) /* Split Screen 2 */
647		{
648		m_status_register |= 0x01;
649		if(m_irq_mask & 0x01)
650		{
651		LOG2674(("SCN2674 Split Screen 2 irq\n"));
652		m_irq_state = 1;
653		m_irq_register |= 0x01;
654		m_irq_cb(1);
655		}
656		if(m_spl2)
657		m_address = (m_screen2_h << 8) | m_screen2_l;
658		if(!m_IR0_double_ht_wd)
659		dw = m_IR14_double_2;
660		}
661
662		int charrow = m_linecounter % m_IR0_scanline_per_char_row;
663		int tilerow = charrow;
664
665		if(m_IR2_row_table)
666		{
667		if(m_IR0_double_ht_wd)
668		dw = m_screen1_h >> 6;
669		if(!charrow)
670		{
671		UINT16 addr = (m_screen2_h << 8) | m_screen2_l;
672		UINT16 line = space().read_word(addr);
673		m_screen1_h = (line >> 8);
674		m_screen1_l = line & 0xff;
675		if(m_IR0_double_ht_wd)
676		{
677		dw = line >> 14;
678		line &= ~0xc000;
679		}
680		m_address = line;
681		addr += 2;
682		m_screen2_h = (addr >> 8) & 0x3f;
683		m_screen2_l = addr & 0xff;
684		}
685
686		}
687
688		if(dw == 2)
689		tilerow >>= 1;
690		else if(dw == 3)
691		tilerow = (charrow + m_IR0_scanline_per_char_row) >> 1;
692
693		UINT16 address = m_address;
694
695		for(int i = 0; i < m_IR5_character_per_row; i++)
696		{
697		if((address & 0x3fff) == ((m_cursor_h << 8) | m_cursor_l))
698		m_cursor_on = true;
699
700		if (!m_display_cb.isnull())
701		m_display_cb(m_bitmap,
702		i * m_hpixels_per_column,
703		m_linecounter,
704		tilerow,
705		space().read_byte(address),
706		address,
707		(charrow >= m_IR6_cursor_first_scanline) && m_cursor_on,
708		dw != 0,
709		m_gfx_enabled != 0,
710		charrow == m_IR7_cursor_underline_position,
711		m_IR7_cursor_blink && (m_screen->frame_number() & (m_IR7_cursor_rate_divisor ? 0x40 : 0x20)));
712		address = (address + 1) & 0xffff;
713
714		if(address > ((m_IR9_display_buffer_last_address << 10) | 0x3ff))
715		address = (m_IR9_display_buffer_first_address_MSB << 8) | m_IR8_display_buffer_first_address_LSB;
716		}
717
718		if(charrow == m_IR6_cursor_last_scanline)
719		m_cursor_on = false;
720
721		if(m_gfx_enabled || (charrow == (m_IR0_scanline_per_char_row - 1)))
722		m_address = address;
723		}
724		}
725		}
726
727		UINT32 scn2674_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
728		{
729		if (!m_display_enabled)
730		m_bitmap.fill(rgb_t::black);
731		else
732		copybitmap(bitmap, m_bitmap, 0, 0, 0, 0, cliprect);
733
734		return 0;
735		}

trunk/src/emu/video/scn2674.h

r243579	r243580
1		#ifndef SCN2674_H
2		#define SCN2674_h
3
4		#include "emu.h"
5
6		#define MCFG_SCN2674_VIDEO_ADD(_tag, _clock, _irq) \
7		MCFG_DEVICE_ADD(_tag, SCN2674_VIDEO, _clock) \
8		devcb = &scn2674_device::set_irq_callback(*device, DEVCB_##_irq);
9
10		#define MCFG_SCN2674_TEXT_CHARACTER_WIDTH(_value) \
11		scn2674_device::static_set_character_width(*device, _value);
12
13		#define MCFG_SCN2674_GFX_CHARACTER_WIDTH(_value) \
14		scn2674_device::static_set_gfx_character_width(*device, _value);
15
16		#define MCFG_SCN2674_DRAW_CHARACTER_CALLBACK_OWNER(_class, _method) \
17		scn2674_device::static_set_display_callback(*device, scn2674_device::draw_character_delegate(&_class::_method, #_class "::" #_method, downcast<_class *>(owner)));
18
19		#define SCN2674_DRAW_CHARACTER_MEMBER(_name) void _name(bitmap_rgb32 &bitmap, int x, int y, UINT8 linecount, UINT8 charcode, UINT16 address, UINT8 cursor, UINT8 dw, UINT8 lg, UINT8 ul, UINT8 blink)
20
21		class scn2674_device : public device_t,
22		public device_video_interface,
23		public device_memory_interface
24		{
25		public:
26		scn2674_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
27
28		typedef device_delegate<void (bitmap_rgb32 &bitmap, int x, int y, UINT8 linecount, UINT8 charcode, UINT16 address, UINT8 cursor, UINT8 dw, UINT8 lg, UINT8 ul, UINT8 blink)> draw_character_delegate;
29
30		// static configuration
31		template<class _Object> static devcb_base &set_irq_callback(device_t &device, _Object object) { return downcast<scn2674_device &>(device).m_irq_cb.set_callback(object); }
32		static void static_set_character_width(device_t &device, int value) { downcast<scn2674_device &>(device).m_text_hpixels_per_column = value; }
33		static void static_set_gfx_character_width(device_t &device, int value) { downcast<scn2674_device &>(device).m_gfx_hpixels_per_column = value; }
34		static void static_set_display_callback(device_t &device, draw_character_delegate callback) { downcast<scn2674_device &>(device).m_display_cb = callback; }
35
36		DECLARE_READ8_MEMBER( read );
37		DECLARE_WRITE8_MEMBER( write );
38
39		UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
40		virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_0) ? &m_space_config : NULL; }
41
42		protected:
43		virtual void device_start();
44		virtual void device_reset();
45		virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
46
47		private:
48		bitmap_rgb32 m_bitmap;
49		devcb_write_line m_irq_cb;
50
51		UINT8 m_IR_pointer;
52		UINT8 m_screen1_l;
53		UINT8 m_screen1_h;
54		UINT8 m_cursor_l;
55		UINT8 m_cursor_h;
56		UINT8 m_screen2_l;
57		UINT8 m_screen2_h;
58		UINT8 m_irq_register;
59		UINT8 m_status_register;
60		UINT8 m_irq_mask;
61		UINT8 m_gfx_enabled;
62		UINT8 m_display_enabled;
63		UINT8 m_display_enabled_field;
64		UINT8 m_display_enabled_scanline;
65		UINT8 m_cursor_enabled;
66		UINT8 m_hpixels_per_column;
67		UINT8 m_text_hpixels_per_column;
68		UINT8 m_gfx_hpixels_per_column;
69		UINT8 m_IR0_double_ht_wd;
70		UINT8 m_IR0_scanline_per_char_row;
71		UINT8 m_IR0_sync_select;
72		UINT8 m_IR0_buffer_mode_select;
73		UINT8 m_IR1_interlace_enable;
74		UINT8 m_IR1_equalizing_constant;
75		UINT8 m_IR2_row_table;
76		UINT8 m_IR2_horz_sync_width;
77		UINT8 m_IR2_horz_back_porch;
78		UINT8 m_IR3_vert_front_porch;
79		UINT8 m_IR3_vert_back_porch;
80		UINT8 m_IR4_rows_per_screen;
81		UINT8 m_IR4_character_blink_rate_divisor;
82		UINT8 m_IR5_character_per_row;
83		UINT8 m_IR6_cursor_first_scanline;
84		UINT8 m_IR6_cursor_last_scanline;
85		UINT8 m_IR7_cursor_underline_position;
86		UINT8 m_IR7_cursor_rate_divisor;
87		UINT8 m_IR7_cursor_blink;
88		UINT8 m_IR7_vsync_width;
89		UINT8 m_IR8_display_buffer_first_address_LSB;
90		UINT8 m_IR9_display_buffer_first_address_MSB;
91		UINT8 m_IR9_display_buffer_last_address;
92		UINT8 m_IR10_display_pointer_address_lower;
93		UINT8 m_IR11_display_pointer_address_upper;
94		UINT8 m_IR11_reset_scanline_counter_on_scrollup;
95		UINT8 m_IR11_reset_scanline_counter_on_scrolldown;
96		UINT8 m_IR12_scroll_start;
97		UINT8 m_IR12_split_register_1;
98		UINT8 m_IR13_scroll_end;
99		UINT8 m_IR13_split_register_2;
100		UINT8 m_IR14_scroll_lines;
101		UINT8 m_IR14_double_1;
102		UINT8 m_IR14_double_2;
103		UINT8 m_spl1;
104		UINT8 m_spl2;
105		UINT8 m_dbl1;
106		int m_linecounter;
107		UINT16 m_address;
108		bool m_cursor_on;
109
110		UINT8 m_irq_state;
111
112		void write_init_regs(UINT8 data);
113		void write_command(UINT8 data);
114		void recompute_parameters();
115
116		draw_character_delegate m_display_cb;
117		emu_timer *m_scanline_timer;
118		const address_space_config m_space_config;
119		enum
120		{
121		TIMER_SCANLINE
122		};
123		};
124
125
126		extern const device_type SCN2674_VIDEO;
127
128		#endif

trunk/src/emu/video/video.mak

r243579	r243580
455	455
456	456	#-------------------------------------------------
457	457	#
458		#@src/emu/video/scn2674.h,VIDEOS += SCN2674
459		#-------------------------------------------------
460		ifneq ($(filter SCN2674,$(VIDEOS)),)
461		VIDEOOBJS+= $(VIDEOOBJ)/scn2674.o
462		endif
463
464		#-------------------------------------------------
465		#
466	458	#@src/emu/video/snes_ppu.h,VIDEOS += SNES_PPU
467	459	#-------------------------------------------------
468	460	ifneq ($(filter SNES_PPU,$(VIDEOS)),)

trunk/src/mame/drivers/mpu4vid.c

r243579	r243580
277	277	DECLARE_MACHINE_START(mpu4_vid);
278	278	DECLARE_MACHINE_RESET(mpu4_vid);
279	279	DECLARE_VIDEO_START(mpu4_vid);
280		SCN2674_DRAW_CHARACTER_MEMBER(display_pixels);
	280	UINT32 screen_update_mpu4_vid(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	281	TIMER_DEVICE_CALLBACK_MEMBER(scanline_timer_callback);
281	282	DECLARE_WRITE_LINE_MEMBER(m6809_acia_irq);
282	283	DECLARE_WRITE_LINE_MEMBER(m68k_acia_irq);
283	284	DECLARE_WRITE_LINE_MEMBER(cpu1_ptm_irq);
r243579	r243580
296	297	DECLARE_WRITE8_MEMBER( vidcharacteriser_w );
297	298	DECLARE_READ8_MEMBER( vidcharacteriser_r );
298	299	DECLARE_WRITE_LINE_MEMBER(mpu_video_reset);
299		DECLARE_WRITE8_MEMBER( vram_w );
300		DECLARE_READ8_MEMBER( vram_r );
301	300	};
302	301
303	302	/*************************************
r243579	r243580
325	324	{
326	325	m_videocpu->set_input_line(1, m_m6840_irq_state ? ASSERT_LINE : CLEAR_LINE);
327	326	m_videocpu->set_input_line(2, m_m6850_irq_state ? ASSERT_LINE : CLEAR_LINE);
	327	m_videocpu->set_input_line(3, m_scn2674->get_irq_state() ? ASSERT_LINE : CLEAR_LINE);
328	328	}
329	329
330	330	/* Communications with 6809 board */
r243579	r243580
384	384	8*32
385	385	};
386	386
387		WRITE8_MEMBER(mpu4vid_state::vram_w)
	387
	388	/* double height */
	389	static const gfx_layout mpu4_vid_char_8x16_layout =
388	390	{
389		m_vid_mainram[offset] = data | (m_vid_mainram[offset] & 0xff00);
390		}
	391	8,16,
	392	0x1000, /* 0x1000 tiles (128k of GFX RAM, 0x20 bytes per tile) */
	393	4,
	394	{ 0,8,16,24 },
	395	{ 0,1,2,3,4,5,6,7 },
	396	{ 0*32, 0*32, 1*32, 1*32, 2*32, 2*32, 3*32, 3*32, 4*32, 4*32, 5*32, 5*32, 6*32, 6*32, 7*32, 7*32},
	397	8*32
	398	};
391	399
392		READ8_MEMBER(mpu4vid_state::vram_r)
	400
	401	/* double width */
	402	static const gfx_layout mpu4_vid_char_16x8_layout =
393	403	{
394		return m_vid_mainram[offset];
395		}
	404	16,8,
	405	0x1000, /* 0x1000 tiles (128k of GFX RAM, 0x20 bytes per tile) */
	406	4,
	407	{ 0,8,16,24 },
	408	{ 0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7 },
	409	{ 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32},
	410	8*32
	411	};
396	412
397		static ADDRESS_MAP_START( mpu4_vram, AS_0, 8, mpu4vid_state )
398		AM_RANGE(0x0000, 0x7fff) AM_READWRITE(vram_r, vram_w)
399		ADDRESS_MAP_END
400	413
401		SCN2674_DRAW_CHARACTER_MEMBER(mpu4vid_state::display_pixels)
	414	/* double height & width */
	415	static const gfx_layout mpu4_vid_char_16x16_layout =
402	416	{
403		if(!lg)
404		{
405		UINT16 tile = m_vid_mainram[address & 0x7fff];
406		const UINT8 *line = m_gfxdecode->gfx(m_gfx_index+0)->get_data(tile & 0xfff);
407		int offset = m_gfxdecode->gfx(m_gfx_index+0)->rowbytes() * linecount;
408		for(int i = 0; i < 8; i++)
409		bitmap.pix32(y, x + i) = (tile >> 12) ? m_palette->pen(line[offset + i]) : m_palette->black_pen();
410		}
	417	16,16,
	418	0x1000,  /* 0x1000 tiles (128k of GFX RAM, 0x20 bytes per tile) */
	419	4,
	420	{ 0,8,16,24 },
	421	{ 0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7 },
	422	{ 0*32, 0*32, 1*32, 1*32, 2*32, 2*32, 3*32, 3*32, 4*32, 4*32, 5*32, 5*32, 6*32, 6*32, 7*32, 7*32},
	423	8*32
	424	};
	425
	426
	427
	428
	429	UINT32 mpu4vid_state::screen_update_mpu4_vid(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	430	{
	431	bitmap.fill(0, cliprect);
	432
	433	m_scn2674->scn2574_draw(machine(), bitmap, cliprect, m_vid_mainram );
	434
	435	return 0;
411	436	}
412	437
413	438
r243579	r243580
422	447	COMBINE_DATA(&m_vid_vidram[offset]);
423	448	offset <<= 1;
424	449	m_gfxdecode->gfx(m_gfx_index+0)->mark_dirty(offset/0x20);
	450	m_gfxdecode->gfx(m_gfx_index+1)->mark_dirty(offset/0x20);
	451	m_gfxdecode->gfx(m_gfx_index+2)->mark_dirty(offset/0x20);
	452	m_gfxdecode->gfx(m_gfx_index+3)->mark_dirty(offset/0x20);
425	453	}
426	454
427	455
428	456	VIDEO_START_MEMBER(mpu4vid_state,mpu4_vid)
429	457	{
	458	/* if anything uses tile sizes other than 8x8 we can't really do it this way.. we'll have to draw tiles by hand.
	459	All Barcrest stuff uses 8x8, son unless the BwB is different, we don't need to */
	460
430	461	m_vid_vidram.allocate(0x20000/2);
431	462
432	463	memset(m_vid_vidram,0,0x20000);
r243579	r243580
440	471
441	472	/* create the char set (gfx will then be updated dynamically from RAM) */
442	473	m_gfxdecode->set_gfx(m_gfx_index+0, global_alloc(gfx_element(m_palette, mpu4_vid_char_8x8_layout, reinterpret_cast<UINT8 *>(m_vid_vidram.target()), NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries() / 16, 0)));
	474	m_gfxdecode->set_gfx(m_gfx_index+1, global_alloc(gfx_element(m_palette, mpu4_vid_char_8x16_layout, reinterpret_cast<UINT8 *>(m_vid_vidram.target()), NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries() / 16, 0)));
	475	m_gfxdecode->set_gfx(m_gfx_index+2, global_alloc(gfx_element(m_palette, mpu4_vid_char_16x8_layout, reinterpret_cast<UINT8 *>(m_vid_vidram.target()), NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries() / 16, 0)));
	476	m_gfxdecode->set_gfx(m_gfx_index+3, global_alloc(gfx_element(m_palette, mpu4_vid_char_16x16_layout, reinterpret_cast<UINT8 *>(m_vid_vidram.target()), NATIVE_ENDIAN_VALUE_LE_BE(8,0), m_palette->entries() / 16, 0)));
	477
	478	m_scn2674->init_stuff();
	479
	480
443	481	}
444	482
445	483
r243579	r243580
1251	1289	/*  AM_RANGE(0xa00004, 0xa0000f) AM_READWRITE(mpu4_vid_unmap_r, mpu4_vid_unmap_w) */
1252	1290
1253	1291
1254		AM_RANGE(0xb00000, 0xb0000f) AM_DEVREADWRITE8("scn2674_vid", scn2674_device, read, write,0x00ff)
	1292	AM_RANGE(0xb00000, 0xb0000f) AM_DEVREADWRITE8("scn2674_vid", scn2674_device, mpu4_vid_scn2674_r, mpu4_vid_scn2674_w,0x00ff)
1255	1293
1256	1294	AM_RANGE(0xc00000, 0xc1ffff) AM_READWRITE(mpu4_vid_vidram_r, mpu4_vid_vidram_w) AM_SHARE("vid_vidram")
1257	1295	AM_RANGE(0xff8000, 0xff8001) AM_DEVREADWRITE8("acia6850_1", acia6850_device, status_r, control_w, 0x00ff)
r243579	r243580
1269	1307	AM_RANGE(0x900002, 0x900003) AM_DEVWRITE8("saa", saa1099_device, control_w, 0x00ff)
1270	1308	AM_RANGE(0xa00000, 0xa00003) AM_READWRITE8(ef9369_r, ef9369_w,0x00ff)
1271	1309
1272		AM_RANGE(0xb00000, 0xb0000f) AM_DEVREADWRITE8("scn2674_vid", scn2674_device, read, write,0x00ff)
	1310	AM_RANGE(0xb00000, 0xb0000f) AM_DEVREADWRITE8("scn2674_vid", scn2674_device, mpu4_vid_scn2674_r, mpu4_vid_scn2674_w,0x00ff)
1273	1311
1274	1312	AM_RANGE(0xc00000, 0xc1ffff) AM_READWRITE(mpu4_vid_vidram_r, mpu4_vid_vidram_w) AM_SHARE("vid_vidram")
1275	1313	AM_RANGE(0xff8000, 0xff8001) AM_DEVREADWRITE8("acia6850_1", acia6850_device, status_r, control_w, 0x00ff)
r243579	r243580
1293	1331	//  AM_RANGE(0xa00000, 0xa0000f) AM_READWRITE(bt471_r,bt471_w) //Some games use this
1294	1332	/*  AM_RANGE(0xa00004, 0xa0000f) AM_READWRITE(mpu4_vid_unmap_r, mpu4_vid_unmap_w) */
1295	1333
1296		AM_RANGE(0xb00000, 0xb0000f) AM_DEVREADWRITE8("scn2674_vid", scn2674_device, read, write,0x00ff)
	1334	AM_RANGE(0xb00000, 0xb0000f) AM_DEVREADWRITE8("scn2674_vid", scn2674_device, mpu4_vid_scn2674_r, mpu4_vid_scn2674_w,0x00ff)
1297	1335	AM_RANGE(0xc00000, 0xc1ffff) AM_READWRITE(mpu4_vid_vidram_r, mpu4_vid_vidram_w) AM_SHARE("vid_vidram")
1298	1336	AM_RANGE(0xe00000, 0xe00001) AM_DEVREADWRITE8("acia6850_1", acia6850_device, status_r, control_w, 0x00ff)
1299	1337	AM_RANGE(0xe00002, 0xe00003) AM_DEVREADWRITE8("acia6850_1", acia6850_device, data_r, data_w, 0x00ff)
r243579	r243580
1311	1349	//AM_RANGE(0xa00000, 0xa00003) AM_READWRITE8(bt471_r,bt471_w,0x00ff) Some games use this
1312	1350	/*  AM_RANGE(0xa00004, 0xa0000f) AM_READWRITE(mpu4_vid_unmap_r, mpu4_vid_unmap_w) */
1313	1351
1314		AM_RANGE(0xb00000, 0xb0000f) AM_DEVREADWRITE8("scn2674_vid", scn2674_device, read, write,0x00ff)
	1352	AM_RANGE(0xb00000, 0xb0000f) AM_DEVREADWRITE8("scn2674_vid", scn2674_device, mpu4_vid_scn2674_r, mpu4_vid_scn2674_w,0x00ff)
1315	1353	AM_RANGE(0xc00000, 0xc1ffff) AM_READWRITE(mpu4_vid_vidram_r, mpu4_vid_vidram_w) AM_SHARE("vid_vidram")
1316	1354	AM_RANGE(0xe00000, 0xe00001) AM_DEVREADWRITE8("acia6850_1", acia6850_device, status_r, control_w, 0x00ff)
1317	1355	AM_RANGE(0xe00002, 0xe00003) AM_DEVREADWRITE8("acia6850_1", acia6850_device, data_r, data_w, 0x00ff)
r243579	r243580
1345	1383
1346	1384
1347	1385
	1386	TIMER_DEVICE_CALLBACK_MEMBER(mpu4vid_state::scanline_timer_callback)
	1387	{
	1388	m_scn2674->scn2674_do_scanline(machine(), param);
	1389	}
	1390
	1391
1348	1392	static MACHINE_CONFIG_START( mpu4_vid, mpu4vid_state )
1349	1393	MCFG_CPU_ADD("maincpu", M6809, MPU4_MASTER_CLOCK/4 )
1350	1394	MCFG_CPU_PROGRAM_MAP(mpu4_6809_map)
r243579	r243580
1359	1403	MCFG_SCREEN_VISIBLE_AREA(0, (63*8)+(0)-1, 0, (37*8)+0-1)
1360	1404
1361	1405	MCFG_SCREEN_REFRESH_RATE(50)
1362		MCFG_SCREEN_UPDATE_DEVICE("scn2674_vid", scn2674_device, screen_update)
	1406	MCFG_SCREEN_UPDATE_DRIVER(mpu4vid_state, screen_update_mpu4_vid)
1363	1407
1364	1408	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
1365	1409
1366		MCFG_SCN2674_VIDEO_ADD("scn2674_vid", 0, INPUTLINE("video", 3))
1367		MCFG_SCN2674_TEXT_CHARACTER_WIDTH(8)
1368		MCFG_SCN2674_GFX_CHARACTER_WIDTH(8)
1369		MCFG_SCN2674_DRAW_CHARACTER_CALLBACK_OWNER(mpu4vid_state, display_pixels)
1370		MCFG_DEVICE_ADDRESS_MAP(AS_0, mpu4_vram)
	1410	MCFG_SCN2674_VIDEO_ADD("scn2674_vid", 0, WRITELINE(mpu4vid_state, update_mpu68_interrupts));
	1411	MCFG_SCN2674_GFXDECODE("gfxdecode")
	1412	MCFG_SCN2674_PALETTE("palette")
1371	1413
1372
1373	1414	MCFG_CPU_ADD("video", M68000, VIDEO_MASTER_CLOCK )
1374	1415	MCFG_CPU_PROGRAM_MAP(mpu4_68k_map)
1375	1416
r243579	r243580
1403	1444	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("acia6850_0", acia6850_device, write_rxd))
1404	1445	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("acia6850_0", acia6850_device, write_dcd))
1405	1446	MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(mpu4vid_state, m68k_acia_irq))
	1447
	1448	// for the video timing
	1449	MCFG_TIMER_DRIVER_ADD_SCANLINE("scan_timer", mpu4vid_state, scanline_timer_callback, "screen", 0, 1)
1406	1450	MACHINE_CONFIG_END
1407	1451
1408	1452	static MACHINE_CONFIG_DERIVED( crmaze, mpu4_vid )

trunk/src/mame/drivers/wc90.c

r243579	r243580
55	55	*                           *
56	56	*****************************
57	57
58		There is known to be a Pacman hack running on this hardware.  It was done by Mike C. and isn't meant
	58	There is known to be a Pacman hack running on this hardware.  It was done by Mike C. and isn't ment
59	59	for inclusion in MAME.  However the roms with checksums are listed below to prevent it being added
60	60	as a newly "found" game:
61	61
r243579	r243580
79	79	#include "includes/wc90.h"
80	80
81	81
82		WRITE8_MEMBER(wc90_state::bankswitch_w)
	82	WRITE8_MEMBER(wc90_state::wc90_bankswitch_w)
83	83	{
84	84	int bankaddress;
85	85	UINT8 *RAM = memregion("maincpu")->base();
r243579	r243580
89	89	membank("bank1")->set_base(&RAM[bankaddress] );
90	90	}
91	91
92		WRITE8_MEMBER(wc90_state::bankswitch1_w)
	92	WRITE8_MEMBER(wc90_state::wc90_bankswitch1_w)
93	93	{
94	94	int bankaddress;
95	95	UINT8 *RAM = memregion("sub")->base();
r243579	r243580
99	99	membank("bank2")->set_base(&RAM[bankaddress] );
100	100	}
101	101
102		WRITE8_MEMBER(wc90_state::sound_command_w)
	102	WRITE8_MEMBER(wc90_state::wc90_sound_command_w)
103	103	{
104	104	soundlatch_byte_w(space, offset, data);
105	105	m_audiocpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
r243579	r243580
110	110	static ADDRESS_MAP_START( wc90_map_1, AS_PROGRAM, 8, wc90_state )
111	111	AM_RANGE(0x0000, 0x7fff) AM_ROM
112	112	AM_RANGE(0x8000, 0x9fff) AM_RAM     /* Main RAM */
113		AM_RANGE(0xa000, 0xafff) AM_RAM_WRITE(fgvideoram_w) AM_SHARE("fgvideoram") /* fg video ram */
	113	AM_RANGE(0xa000, 0xafff) AM_RAM_WRITE(wc90_fgvideoram_w) AM_SHARE("fgvideoram") /* fg video ram */
114	114	AM_RANGE(0xb000, 0xbfff) AM_RAM
115		AM_RANGE(0xc000, 0xcfff) AM_RAM_WRITE(bgvideoram_w) AM_SHARE("bgvideoram")
	115	AM_RANGE(0xc000, 0xcfff) AM_RAM_WRITE(wc90_bgvideoram_w) AM_SHARE("bgvideoram")
116	116	AM_RANGE(0xd000, 0xdfff) AM_RAM
117		AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(txvideoram_w) AM_SHARE("txvideoram") /* tx video ram */
	117	AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(wc90_txvideoram_w) AM_SHARE("txvideoram") /* tx video ram */
118	118	AM_RANGE(0xf000, 0xf7ff) AM_ROMBANK("bank1")
119	119	AM_RANGE(0xf800, 0xfbff) AM_RAM AM_SHARE("share1")
120	120	AM_RANGE(0xfc00, 0xfc00) AM_READ_PORT("P1")
r243579	r243580
134	134	AM_RANGE(0xfc43, 0xfc43) AM_WRITEONLY AM_SHARE("scroll2yhi")
135	135	AM_RANGE(0xfc46, 0xfc46) AM_WRITEONLY AM_SHARE("scroll2xlo")
136	136	AM_RANGE(0xfc47, 0xfc47) AM_WRITEONLY AM_SHARE("scroll2xhi")
137		AM_RANGE(0xfcc0, 0xfcc0) AM_WRITE(sound_command_w)
	137	AM_RANGE(0xfcc0, 0xfcc0) AM_WRITE(wc90_sound_command_w)
138	138	AM_RANGE(0xfcd0, 0xfcd0) AM_WRITE(watchdog_reset_w)
139		AM_RANGE(0xfce0, 0xfce0) AM_WRITE(bankswitch_w)
	139	AM_RANGE(0xfce0, 0xfce0) AM_WRITE(wc90_bankswitch_w)
140	140	ADDRESS_MAP_END
141	141
142	142	static ADDRESS_MAP_START( wc90_map_2, AS_PROGRAM, 8, wc90_state )
r243579	r243580
147	147	AM_RANGE(0xe000, 0xe7ff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
148	148	AM_RANGE(0xf000, 0xf7ff) AM_ROMBANK("bank2")
149	149	AM_RANGE(0xf800, 0xfbff) AM_RAM AM_SHARE("share1")
150		AM_RANGE(0xfc00, 0xfc00) AM_WRITE(bankswitch1_w)
	150	AM_RANGE(0xfc00, 0xfc00) AM_WRITE(wc90_bankswitch1_w)
151	151	AM_RANGE(0xfc01, 0xfc01) AM_WRITE(watchdog_reset_w)
152	152	ADDRESS_MAP_END
153	153
r243579	r243580
316	316	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
317	317	MCFG_SCREEN_SIZE(32*8, 32*8)
318	318	MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 2*8, 30*8-1)
319		MCFG_SCREEN_UPDATE_DRIVER(wc90_state, screen_update)
	319	MCFG_SCREEN_UPDATE_DRIVER(wc90_state, screen_update_wc90)
320	320	MCFG_SCREEN_PALETTE("palette")
321	321
322	322	MCFG_GFXDECODE_ADD("gfxdecode", "palette", wc90)
r243579	r243580
472	472	ROM_LOAD( "ic82_06.bin",  0x00000, 0x20000, CRC(2fd692ed) SHA1(0273dc39181504320bec0187d074b2f86c821508) )
473	473	ROM_END
474	474
475		GAME( 1989, wc90,  0,    wc90, wc90, driver_device, 0, ROT0, "Tecmo", "Tecmo World Cup '90 (World)", GAME_IMPERFECT_SOUND | GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
476		GAME( 1989, wc90a, wc90, wc90, wc90, driver_device, 0, ROT0, "Tecmo", "Tecmo World Cup '90 (Euro set 1)", GAME_IMPERFECT_SOUND | GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
477		GAME( 1989, wc90b, wc90, wc90, wc90, driver_device, 0, ROT0, "Tecmo", "Tecmo World Cup '90 (Euro set 2)", GAME_IMPERFECT_SOUND | GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
478		GAME( 1989, wc90t, wc90, wc90t,wc90, driver_device, 0, ROT0, "Tecmo", "Tecmo World Cup '90 (trackball set 1)", GAME_IMPERFECT_SOUND | GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
	475	GAME( 1989, wc90,  0,    wc90, wc90, driver_device, 0, ROT0, "Tecmo", "Tecmo World Cup '90 (World)", GAME_IMPERFECT_SOUND | GAME_NO_COCKTAIL )
	476	GAME( 1989, wc90a, wc90, wc90, wc90, driver_device, 0, ROT0, "Tecmo", "Tecmo World Cup '90 (Euro set 1)", GAME_IMPERFECT_SOUND | GAME_NO_COCKTAIL )
	477	GAME( 1989, wc90b, wc90, wc90, wc90, driver_device, 0, ROT0, "Tecmo", "Tecmo World Cup '90 (Euro set 2)", GAME_IMPERFECT_SOUND | GAME_NO_COCKTAIL )
	478	GAME( 1989, wc90t, wc90, wc90t,wc90, driver_device, 0, ROT0, "Tecmo", "Tecmo World Cup '90 (trackball set 1)", GAME_IMPERFECT_SOUND | GAME_NO_COCKTAIL )

trunk/src/mame/drivers/wwfsstar.c

r243579	r243580
121	121	04 Mar 2002 | Fixed Dip Switches and Inputs    (Steph)
122	122	| Fixed screen flipping by using similar routine to the one
123	123	| in src/video/wwfwfest.c        (Steph)
124		18 Jun 2001 | Changed Interrupt Function .. it's not fully understood what
	124	18 Jun 2001 | Changed Interrupt Function .. its not fully understood whats
125	125	| is meant to be going on ..
126	126	15 Jun 2001 | Cleaned up Sprite Drawing a bit, correcting some clipping probs,
127	127	| mapped DSW's
r243579	r243580
170	170
171	171	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, wwfsstar_state )
172	172	AM_RANGE(0x000000, 0x03ffff) AM_ROM
173		AM_RANGE(0x080000, 0x080fff) AM_RAM_WRITE(fg0_videoram_w) AM_SHARE("fg0_videoram") /* FG0 Ram */
174		AM_RANGE(0x0c0000, 0x0c0fff) AM_RAM_WRITE(bg0_videoram_w) AM_SHARE("bg0_videoram") /* BG0 Ram */
	173	AM_RANGE(0x080000, 0x080fff) AM_RAM_WRITE(wwfsstar_fg0_videoram_w) AM_SHARE("fg0_videoram") /* FG0 Ram */
	174	AM_RANGE(0x0c0000, 0x0c0fff) AM_RAM_WRITE(wwfsstar_bg0_videoram_w) AM_SHARE("bg0_videoram") /* BG0 Ram */
175	175	AM_RANGE(0x100000, 0x1003ff) AM_RAM AM_SHARE("spriteram")       /* SPR Ram */
176	176	AM_RANGE(0x140000, 0x140fff) AM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
177		AM_RANGE(0x180000, 0x180003) AM_WRITE(irqack_w)
	177	AM_RANGE(0x180000, 0x180003) AM_WRITE(wwfsstar_irqack_w)
178	178	AM_RANGE(0x180000, 0x180001) AM_READ_PORT("DSW1")
179	179	AM_RANGE(0x180002, 0x180003) AM_READ_PORT("DSW2")
180	180	AM_RANGE(0x180004, 0x180005) AM_READ_PORT("P1")
181		AM_RANGE(0x180004, 0x180007) AM_WRITE(scroll_w)
	181	AM_RANGE(0x180004, 0x180007) AM_WRITE(wwfsstar_scrollwrite)
182	182	AM_RANGE(0x180006, 0x180007) AM_READ_PORT("P2")
183	183	AM_RANGE(0x180008, 0x180009) AM_READ_PORT("SYSTEM")
184		AM_RANGE(0x180008, 0x180009) AM_WRITE(sound_w)
185		AM_RANGE(0x18000a, 0x18000b) AM_WRITE(flipscreen_w)
	184	AM_RANGE(0x180008, 0x180009) AM_WRITE(wwfsstar_soundwrite)
	185	AM_RANGE(0x18000a, 0x18000b) AM_WRITE(wwfsstar_flipscreen_w)
186	186	AM_RANGE(0x1c0000, 0x1c3fff) AM_RAM                             /* Work Ram */
187	187	ADDRESS_MAP_END
188	188
r243579	r243580
201	201	as used by the above memory map
202	202	*******************************************************************************/
203	203
204		WRITE16_MEMBER(wwfsstar_state::scroll_w)
	204	WRITE16_MEMBER(wwfsstar_state::wwfsstar_scrollwrite)
205	205	{
206	206	switch (offset)
207	207	{
r243579	r243580
214	214	}
215	215	}
216	216
217		WRITE16_MEMBER(wwfsstar_state::sound_w)
	217	WRITE16_MEMBER(wwfsstar_state::wwfsstar_soundwrite)
218	218	{
219	219	soundlatch_byte_w(space, 1, data & 0xff);
220	220	m_audiocpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE );
221	221	}
222	222
223		WRITE16_MEMBER(wwfsstar_state::flipscreen_w)
	223	WRITE16_MEMBER(wwfsstar_state::wwfsstar_flipscreen_w)
224	224	{
225	225	flip_screen_set(data & 1);
226	226	}
227	227
228		WRITE16_MEMBER(wwfsstar_state::irqack_w)
	228	WRITE16_MEMBER(wwfsstar_state::wwfsstar_irqack_w)
229	229	{
230	230	if (offset == 0)
231	231	m_maincpu->set_input_line(6, CLEAR_LINE);
r243579	r243580
247	247	A hack is required: raise the vblank bit a scanline early.
248	248	*/
249	249
250		TIMER_DEVICE_CALLBACK_MEMBER(wwfsstar_state::scanline)
	250	TIMER_DEVICE_CALLBACK_MEMBER(wwfsstar_state::wwfsstar_scanline)
251	251	{
252	252	int scanline = param;
253	253
r243579	r243580
278	278	}
279	279	}
280	280
281		CUSTOM_INPUT_MEMBER(wwfsstar_state::vblank_r)
	281	CUSTOM_INPUT_MEMBER(wwfsstar_state::wwfsstar_vblank_r)
282	282	{
283	283	return m_vblank;
284	284	}
r243579	r243580
313	313	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("Button B (1P VS 2P - Buy-in)")
314	314
315	315	PORT_START("SYSTEM")
316		PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, wwfsstar_state, vblank_r, NULL) /* VBlank */
	316	PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, wwfsstar_state,wwfsstar_vblank_r, NULL) /* VBlank */
317	317	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN1 )
318	318	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN2 )
319	319	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_SERVICE1 )
r243579	r243580
416	416	/* basic machine hardware */
417	417	MCFG_CPU_ADD("maincpu", M68000, CPU_CLOCK)
418	418	MCFG_CPU_PROGRAM_MAP(main_map)
419		MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", wwfsstar_state, scanline, "screen", 0, 1)
	419	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", wwfsstar_state, wwfsstar_scanline, "screen", 0, 1)
420	420
421	421	MCFG_CPU_ADD("audiocpu", Z80, XTAL_3_579545MHz)
422	422	MCFG_CPU_PROGRAM_MAP(sound_map)
r243579	r243580
424	424	/* video hardware */
425	425	MCFG_SCREEN_ADD("screen", RASTER)
426	426	MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, 320, 0, 256, 272, 8, 248)   /* HTOTAL and VTOTAL are guessed */
427		MCFG_SCREEN_UPDATE_DRIVER(wwfsstar_state, screen_update)
	427	MCFG_SCREEN_UPDATE_DRIVER(wwfsstar_state, screen_update_wwfsstar)
428	428	MCFG_SCREEN_PALETTE("palette")
429	429
430	430	MCFG_GFXDECODE_ADD("gfxdecode", "palette", wwfsstar)
r243579	r243580
627	627
628	628
629	629
630		GAME( 1989, wwfsstar,   0,        wwfsstar, wwfsstar, driver_device,  0, ROT0, "Technos Japan", "WWF Superstars (Europe)", GAME_SUPPORTS_SAVE )
631		GAME( 1989, wwfsstaru,  wwfsstar, wwfsstar, wwfsstar, driver_device,  0, ROT0, "Technos Japan", "WWF Superstars (US, Newer)", GAME_SUPPORTS_SAVE )
632		GAME( 1989, wwfsstarua, wwfsstar, wwfsstar, wwfsstar, driver_device,  0, ROT0, "Technos Japan", "WWF Superstars (US)", GAME_SUPPORTS_SAVE )
633		GAME( 1989, wwfsstarj,  wwfsstar, wwfsstar, wwfsstar, driver_device,  0, ROT0, "Technos Japan", "WWF Superstars (Japan)", GAME_SUPPORTS_SAVE )
634		GAME( 1989, wwfsstarb,  wwfsstar, wwfsstar, wwfsstar, driver_device,  0, ROT0, "bootleg",       "WWF Superstars (bootleg)", GAME_SUPPORTS_SAVE )
	630	GAME( 1989, wwfsstar,   0,        wwfsstar, wwfsstar, driver_device,  0, ROT0, "Technos Japan", "WWF Superstars (Europe)", 0 )
	631	GAME( 1989, wwfsstaru,  wwfsstar, wwfsstar, wwfsstar, driver_device,  0, ROT0, "Technos Japan", "WWF Superstars (US, Newer)", 0 )
	632	GAME( 1989, wwfsstarua, wwfsstar, wwfsstar, wwfsstar, driver_device,  0, ROT0, "Technos Japan", "WWF Superstars (US)", 0 )
	633	GAME( 1989, wwfsstarj,  wwfsstar, wwfsstar, wwfsstar, driver_device,  0, ROT0, "Technos Japan", "WWF Superstars (Japan)", 0 )
	634	GAME( 1989, wwfsstarb,  wwfsstar, wwfsstar, wwfsstar, driver_device,  0, ROT0, "bootleg",       "WWF Superstars (bootleg)", 0 )

trunk/src/mame/drivers/xxmissio.c

r243579	r243580
14	14	#include "includes/xxmissio.h"
15	15
16	16
17		WRITE8_MEMBER(xxmissio_state::bank_sel_w)
	17	WRITE8_MEMBER(xxmissio_state::xxmissio_bank_sel_w)
18	18	{
19	19	membank("bank1")->set_entry(data & 7);
20	20	}
21	21
22		CUSTOM_INPUT_MEMBER(xxmissio_state::status_r)
	22	CUSTOM_INPUT_MEMBER(xxmissio_state::xxmissio_status_r)
23	23	{
24	24	int bit_mask = (FPTR)param;
25	25	return (m_status & bit_mask) ? 1 : 0;
26	26	}
27	27
28		WRITE8_MEMBER(xxmissio_state::status_m_w)
	28	WRITE8_MEMBER(xxmissio_state::xxmissio_status_m_w)
29	29	{
30	30	switch (data)
31	31	{
r243579	r243580
44	44	}
45	45	}
46	46
47		WRITE8_MEMBER(xxmissio_state::status_s_w)
	47	WRITE8_MEMBER(xxmissio_state::xxmissio_status_s_w)
48	48	{
49	49	switch (data)
50	50	{
r243579	r243580
63	63	}
64	64	}
65	65
66		INTERRUPT_GEN_MEMBER(xxmissio_state::interrupt_m)
	66	INTERRUPT_GEN_MEMBER(xxmissio_state::xxmissio_interrupt_m)
67	67	{
68	68	m_status &= ~0x20;
69		m_maincpu->set_input_line(0, HOLD_LINE);
	69	device.execute().set_input_line(0, HOLD_LINE);
70	70	}
71	71
72		INTERRUPT_GEN_MEMBER(xxmissio_state::interrupt_s)
	72	INTERRUPT_GEN_MEMBER(xxmissio_state::xxmissio_interrupt_s)
73	73	{
74	74	m_status &= ~0x10;
75		m_subcpu->set_input_line(0, HOLD_LINE);
	75	device.execute().set_input_line(0, HOLD_LINE);
76	76	}
77	77
78	78	void xxmissio_state::machine_start()
79	79	{
80	80	membank("bank1")->configure_entries(0, 8, memregion("user1")->base(), 0x4000);
81	81	membank("bank1")->set_entry(0);
82
83		save_item(NAME(m_status));
84	82	}
85	83
86	84	/****************************************************************************/
r243579	r243580
94	92	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("P1")
95	93	AM_RANGE(0xa001, 0xa001) AM_READ_PORT("P2")
96	94	AM_RANGE(0xa002, 0xa002) AM_READ_PORT("STATUS")
97		AM_RANGE(0xa002, 0xa002) AM_WRITE(status_m_w)
98		AM_RANGE(0xa003, 0xa003) AM_WRITE(flipscreen_w)
	95	AM_RANGE(0xa002, 0xa002) AM_WRITE(xxmissio_status_m_w)
	96	AM_RANGE(0xa003, 0xa003) AM_WRITE(xxmissio_flipscreen_w)
99	97
100	98	AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("fgram")
101		AM_RANGE(0xc800, 0xcfff) AM_READWRITE(bgram_r, bgram_w) AM_SHARE("bgram")
	99	AM_RANGE(0xc800, 0xcfff) AM_READWRITE(xxmissio_bgram_r, xxmissio_bgram_w) AM_SHARE("bgram")
102	100	AM_RANGE(0xd000, 0xd7ff) AM_RAM AM_SHARE("spriteram")
103	101
104	102	AM_RANGE(0xd800, 0xdaff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
r243579	r243580
114	112
115	113	AM_RANGE(0x8000, 0x8001) AM_DEVREADWRITE("ym1", ym2203_device, read, write)
116	114	AM_RANGE(0x8002, 0x8003) AM_DEVREADWRITE("ym2", ym2203_device, read, write)
117		AM_RANGE(0x8006, 0x8006) AM_WRITE(bank_sel_w)
	115	AM_RANGE(0x8006, 0x8006) AM_WRITE(xxmissio_bank_sel_w)
118	116
119	117	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("P1")
120	118	AM_RANGE(0xa001, 0xa001) AM_READ_PORT("P2")
121	119	AM_RANGE(0xa002, 0xa002) AM_READ_PORT("STATUS")
122		AM_RANGE(0xa002, 0xa002) AM_WRITE(status_s_w)
123		AM_RANGE(0xa003, 0xa003) AM_WRITE(flipscreen_w)
	120	AM_RANGE(0xa002, 0xa002) AM_WRITE(xxmissio_status_s_w)
	121	AM_RANGE(0xa003, 0xa003) AM_WRITE(xxmissio_flipscreen_w)
124	122
125	123	AM_RANGE(0xc000, 0xc7ff) AM_SHARE("fgram") AM_RAM
126		AM_RANGE(0xc800, 0xcfff) AM_SHARE("bgram") AM_READWRITE(bgram_r, bgram_w)
	124	AM_RANGE(0xc800, 0xcfff) AM_SHARE("bgram") AM_READWRITE(xxmissio_bgram_r, xxmissio_bgram_w)
127	125	AM_RANGE(0xd000, 0xd7ff) AM_SHARE("spriteram") AM_RAM
128	126
129	127	AM_RANGE(0xd800, 0xdaff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
r243579	r243580
198	196	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" ) /* Shown as "Unused" in the manual */
199	197
200	198	PORT_START("STATUS")
201		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state, status_r, (void *)0x01)
	199	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state,xxmissio_status_r, (void *)0x01)
202	200	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
203		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state, status_r, (void *)0x04)
204		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state, status_r, (void *)0x08)
205		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state, status_r, (void *)0x10)
206		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state, status_r, (void *)0x20)
207		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state, status_r, (void *)0x40)
208		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state, status_r, (void *)0x80)
	201	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state,xxmissio_status_r, (void *)0x04)
	202	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state,xxmissio_status_r, (void *)0x08)
	203	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state,xxmissio_status_r, (void *)0x10)
	204	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state,xxmissio_status_r, (void *)0x20)
	205	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state,xxmissio_status_r, (void *)0x40)
	206	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xxmissio_state,xxmissio_status_r, (void *)0x80)
209	207	INPUT_PORTS_END
210	208
211	209	/****************************************************************************/
r243579	r243580
260	258	/* basic machine hardware */
261	259	MCFG_CPU_ADD("maincpu", Z80,12000000/4) /* 3.0MHz */
262	260	MCFG_CPU_PROGRAM_MAP(map1)
263		MCFG_CPU_VBLANK_INT_DRIVER("screen", xxmissio_state,  interrupt_m)
	261	MCFG_CPU_VBLANK_INT_DRIVER("screen", xxmissio_state,  xxmissio_interrupt_m)
264	262
265	263	MCFG_CPU_ADD("sub", Z80,12000000/4) /* 3.0MHz */
266	264	MCFG_CPU_PROGRAM_MAP(map2)
267		MCFG_CPU_PERIODIC_INT_DRIVER(xxmissio_state, interrupt_s, 2*60)
	265	MCFG_CPU_PERIODIC_INT_DRIVER(xxmissio_state, xxmissio_interrupt_s, 2*60)
268	266
269	267	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
270	268
r243579	r243580
275	273	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
276	274	MCFG_SCREEN_SIZE(64*8, 32*8)
277	275	MCFG_SCREEN_VISIBLE_AREA(0*8, 64*8-1, 4*8, 28*8-1)
278		MCFG_SCREEN_UPDATE_DRIVER(xxmissio_state, screen_update)
	276	MCFG_SCREEN_UPDATE_DRIVER(xxmissio_state, screen_update_xxmissio)
279	277	MCFG_SCREEN_PALETTE("palette")
280	278
281	279	MCFG_GFXDECODE_ADD("gfxdecode", "palette", xxmissio)
r243579	r243580
295	293	MCFG_SOUND_ROUTE(3, "mono", 0.40)
296	294
297	295	MCFG_SOUND_ADD("ym2", YM2203, 12000000/8)
298		MCFG_AY8910_PORT_A_WRITE_CB(WRITE8(xxmissio_state, scroll_x_w))
299		MCFG_AY8910_PORT_B_WRITE_CB(WRITE8(xxmissio_state, scroll_y_w))
	296	MCFG_AY8910_PORT_A_WRITE_CB(WRITE8(xxmissio_state, xxmissio_scroll_x_w))
	297	MCFG_AY8910_PORT_B_WRITE_CB(WRITE8(xxmissio_state, xxmissio_scroll_y_w))
300	298	MCFG_SOUND_ROUTE(0, "mono", 0.15)
301	299	MCFG_SOUND_ROUTE(1, "mono", 0.15)
302	300	MCFG_SOUND_ROUTE(2, "mono", 0.15)
r243579	r243580
328	326	ROM_LOAD16_BYTE( "xx11.4b", 0x0001,  0x8000, CRC(d9dd827c) SHA1(aea3a5abd871adf7f75ad4d6cc57eff0833135c7) )
329	327	ROM_END
330	328
331		GAME( 1986, xxmissio, 0, xxmissio, xxmissio, driver_device, 0, ROT90, "UPL", "XX Mission", GAME_SUPPORTS_SAVE )
	329	GAME( 1986, xxmissio, 0, xxmissio, xxmissio, driver_device, 0, ROT90, "UPL", "XX Mission", 0 )

trunk/src/mame/includes/wc90.h

r243579	r243580
5	5	public:
6	6	wc90_state(const machine_config &mconfig, device_type type, const char *tag)
7	7	: driver_device(mconfig, type, tag),
8		m_maincpu(*this, "maincpu"),
9		m_audiocpu(*this, "audiocpu"),
10		m_gfxdecode(*this, "gfxdecode"),
11		m_palette(*this, "palette"),
12		m_sprgen(*this, "spritegen"),
13	8	m_fgvideoram(*this, "fgvideoram"),
14	9	m_bgvideoram(*this, "bgvideoram"),
15	10	m_txvideoram(*this, "txvideoram"),
r243579	r243580
25	20	m_scroll1yhi(*this, "scroll1yhi"),
26	21	m_scroll2ylo(*this, "scroll2ylo"),
27	22	m_scroll2yhi(*this, "scroll2yhi"),
28		m_spriteram(*this, "spriteram")
	23	m_spriteram(*this, "spriteram"),
	24	m_maincpu(*this, "maincpu"),
	25	m_audiocpu(*this, "audiocpu"),
	26	m_gfxdecode(*this, "gfxdecode"),
	27	m_palette(*this, "palette"),
	28	m_sprgen(*this, "spritegen")
29	29	{ }
30	30
31
32		required_device<cpu_device> m_maincpu;
33		required_device<cpu_device> m_audiocpu;
34		required_device<gfxdecode_device> m_gfxdecode;
35		required_device<palette_device> m_palette;
36		required_device<tecmo_spr_device> m_sprgen;
37	31
	32
38	33	required_shared_ptr<UINT8> m_fgvideoram;
39	34	required_shared_ptr<UINT8> m_bgvideoram;
40	35	required_shared_ptr<UINT8> m_txvideoram;
r243579	r243580
50	45	required_shared_ptr<UINT8> m_scroll1yhi;
51	46	required_shared_ptr<UINT8> m_scroll2ylo;
52	47	required_shared_ptr<UINT8> m_scroll2yhi;
53		required_shared_ptr<UINT8> m_spriteram;
54
55	48	tilemap_t *m_tx_tilemap;
56	49	tilemap_t *m_fg_tilemap;
57	50	tilemap_t *m_bg_tilemap;
58
59		DECLARE_WRITE8_MEMBER(bankswitch_w);
60		DECLARE_WRITE8_MEMBER(bankswitch1_w);
61		DECLARE_WRITE8_MEMBER(sound_command_w);
62		DECLARE_WRITE8_MEMBER(bgvideoram_w);
63		DECLARE_WRITE8_MEMBER(fgvideoram_w);
64		DECLARE_WRITE8_MEMBER(txvideoram_w);
65		DECLARE_WRITE_LINE_MEMBER(irqhandler);
66
	51	required_shared_ptr<UINT8> m_spriteram;
	52	DECLARE_WRITE8_MEMBER(wc90_bankswitch_w);
	53	DECLARE_WRITE8_MEMBER(wc90_bankswitch1_w);
	54	DECLARE_WRITE8_MEMBER(wc90_sound_command_w);
	55	DECLARE_WRITE8_MEMBER(wc90_bgvideoram_w);
	56	DECLARE_WRITE8_MEMBER(wc90_fgvideoram_w);
	57	DECLARE_WRITE8_MEMBER(wc90_txvideoram_w);
67	58	TILE_GET_INFO_MEMBER(get_bg_tile_info);
68	59	TILE_GET_INFO_MEMBER(get_fg_tile_info);
69	60	TILE_GET_INFO_MEMBER(get_tx_tile_info);
70	61	TILE_GET_INFO_MEMBER(track_get_bg_tile_info);
71	62	TILE_GET_INFO_MEMBER(track_get_fg_tile_info);
72
73	63	virtual void video_start();
74	64	DECLARE_VIDEO_START(wc90t);
75
76		UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	65	UINT32 screen_update_wc90(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	66
	67	DECLARE_WRITE_LINE_MEMBER(irqhandler);
	68	required_device<cpu_device> m_maincpu;
	69	required_device<cpu_device> m_audiocpu;
	70	required_device<gfxdecode_device> m_gfxdecode;
	71	required_device<palette_device> m_palette;
	72	required_device<tecmo_spr_device> m_sprgen;
77	73	};

trunk/src/mame/includes/wwfsstar.h

r243579	r243580
3	3	public:
4	4	wwfsstar_state(const machine_config &mconfig, device_type type, const char *tag)
5	5	: driver_device(mconfig, type, tag),
	6	m_spriteram(*this, "spriteram"),
	7	m_fg0_videoram(*this, "fg0_videoram"),
	8	m_bg0_videoram(*this, "bg0_videoram"),
6	9	m_maincpu(*this, "maincpu"),
7	10	m_audiocpu(*this, "audiocpu"),
8	11	m_gfxdecode(*this, "gfxdecode"),
9	12	m_screen(*this, "screen"),
10		m_palette(*this, "palette"),
11		m_spriteram(*this, "spriteram"),
12		m_fg0_videoram(*this, "fg0_videoram"),
13		m_bg0_videoram(*this, "bg0_videoram") { }
	13	m_palette(*this, "palette") { }
14	14
15		required_device<cpu_device> m_maincpu;
16		required_device<cpu_device> m_audiocpu;
17		required_device<gfxdecode_device> m_gfxdecode;
18		required_device<screen_device> m_screen;
19		required_device<palette_device> m_palette;
20
21		required_shared_ptr<UINT16> m_spriteram;
22		required_shared_ptr<UINT16> m_fg0_videoram;
23		required_shared_ptr<UINT16> m_bg0_videoram;
24
25	15	int m_vblank;
26	16	int m_scrollx;
27	17	int m_scrolly;
	18	required_shared_ptr<UINT16> m_spriteram;
	19	required_shared_ptr<UINT16> m_fg0_videoram;
	20	required_shared_ptr<UINT16> m_bg0_videoram;
28	21	tilemap_t *m_fg0_tilemap;
29	22	tilemap_t *m_bg0_tilemap;
30
31		DECLARE_WRITE16_MEMBER(scroll_w);
32		DECLARE_WRITE16_MEMBER(sound_w);
33		DECLARE_WRITE16_MEMBER(flipscreen_w);
34		DECLARE_WRITE16_MEMBER(irqack_w);
35		DECLARE_WRITE16_MEMBER(fg0_videoram_w);
36		DECLARE_WRITE16_MEMBER(bg0_videoram_w);
37
38		DECLARE_CUSTOM_INPUT_MEMBER(vblank_r);
39
40		TIMER_DEVICE_CALLBACK_MEMBER(scanline);
41
	23	DECLARE_WRITE16_MEMBER(wwfsstar_scrollwrite);
	24	DECLARE_WRITE16_MEMBER(wwfsstar_soundwrite);
	25	DECLARE_WRITE16_MEMBER(wwfsstar_flipscreen_w);
	26	DECLARE_WRITE16_MEMBER(wwfsstar_irqack_w);
	27	DECLARE_WRITE16_MEMBER(wwfsstar_fg0_videoram_w);
	28	DECLARE_WRITE16_MEMBER(wwfsstar_bg0_videoram_w);
	29	DECLARE_CUSTOM_INPUT_MEMBER(wwfsstar_vblank_r);
42	30	TILE_GET_INFO_MEMBER(get_fg0_tile_info);
43	31	TILEMAP_MAPPER_MEMBER(bg0_scan);
44	32	TILE_GET_INFO_MEMBER(get_bg0_tile_info);
45
46	33	virtual void video_start();
47
48		UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	34	UINT32 screen_update_wwfsstar(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	35	TIMER_DEVICE_CALLBACK_MEMBER(wwfsstar_scanline);
49	36	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect );
	37	required_device<cpu_device> m_maincpu;
	38	required_device<cpu_device> m_audiocpu;
	39	required_device<gfxdecode_device> m_gfxdecode;
	40	required_device<screen_device> m_screen;
	41	required_device<palette_device> m_palette;
50	42	};

trunk/src/mame/includes/xxmissio.h

r243579	r243580
3	3	public:
4	4	xxmissio_state(const machine_config &mconfig, device_type type, const char *tag)
5	5	: driver_device(mconfig, type, tag),
	6	m_bgram(*this, "bgram"),
	7	m_fgram(*this, "fgram"),
	8	m_spriteram(*this, "spriteram"),
6	9	m_maincpu(*this, "maincpu"),
7	10	m_subcpu(*this, "sub"),
8	11	m_gfxdecode(*this, "gfxdecode"),
9		m_palette(*this, "palette"),
10		m_bgram(*this, "bgram"),
11		m_fgram(*this, "fgram"),
12		m_spriteram(*this, "spriteram")  { }
	12	m_palette(*this, "palette")  { }
13	13
14		required_device<cpu_device> m_maincpu;
15		required_device<cpu_device> m_subcpu;
16		required_device<gfxdecode_device> m_gfxdecode;
17		required_device<palette_device> m_palette;
18
	14	UINT8 m_status;
19	15	required_shared_ptr<UINT8> m_bgram;
20	16	required_shared_ptr<UINT8> m_fgram;
21	17	required_shared_ptr<UINT8> m_spriteram;
22
23	18	tilemap_t *m_bg_tilemap;
24	19	tilemap_t *m_fg_tilemap;
25		UINT8 m_status;
26	20	UINT8 m_xscroll;
27	21	UINT8 m_yscroll;
28	22	UINT8 m_flipscreen;
29
30		DECLARE_WRITE8_MEMBER(bank_sel_w);
31		DECLARE_WRITE8_MEMBER(status_m_w);
32		DECLARE_WRITE8_MEMBER(status_s_w);
33		DECLARE_WRITE8_MEMBER(flipscreen_w);
34		DECLARE_WRITE8_MEMBER(bgram_w);
35		DECLARE_READ8_MEMBER(bgram_r);
36		DECLARE_WRITE8_MEMBER(scroll_x_w);
37		DECLARE_WRITE8_MEMBER(scroll_y_w);
38
39		DECLARE_CUSTOM_INPUT_MEMBER(status_r);
40
41		INTERRUPT_GEN_MEMBER(interrupt_m);
42		INTERRUPT_GEN_MEMBER(interrupt_s);
43
	23	DECLARE_WRITE8_MEMBER(xxmissio_bank_sel_w);
	24	DECLARE_WRITE8_MEMBER(xxmissio_status_m_w);
	25	DECLARE_WRITE8_MEMBER(xxmissio_status_s_w);
	26	DECLARE_WRITE8_MEMBER(xxmissio_flipscreen_w);
	27	DECLARE_WRITE8_MEMBER(xxmissio_bgram_w);
	28	DECLARE_READ8_MEMBER(xxmissio_bgram_r);
	29	DECLARE_CUSTOM_INPUT_MEMBER(xxmissio_status_r);
44	30	TILE_GET_INFO_MEMBER(get_bg_tile_info);
45	31	TILE_GET_INFO_MEMBER(get_fg_tile_info);
46
47	32	virtual void machine_start();
48	33	virtual void video_start();
49
50		UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	34	UINT32 screen_update_xxmissio(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	35	INTERRUPT_GEN_MEMBER(xxmissio_interrupt_m);
	36	INTERRUPT_GEN_MEMBER(xxmissio_interrupt_s);
	37	DECLARE_WRITE8_MEMBER(xxmissio_scroll_x_w);
	38	DECLARE_WRITE8_MEMBER(xxmissio_scroll_y_w);
51	39	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, gfx_element *gfx);
	40	required_device<cpu_device> m_maincpu;
	41	required_device<cpu_device> m_subcpu;
	42	required_device<gfxdecode_device> m_gfxdecode;
	43	required_device<palette_device> m_palette;
52	44	};

trunk/src/mame/mame.mak

r243579	r243580
327	327	VIDEOS += RAMDAC
328	328	#VIDEOS += S2636
329	329	VIDEOS += SAA5050
330		VIDEOS += SCN2674
331	330	#VIDEOS += SED1200
332	331	#VIDEOS += SED1330
333	332	#VIDEOS += SED1520
r243579	r243580
961	960	$(DRIVERS)/mpu4crystal.o \
962	961	$(DRIVERS)/mpu4bwb.o \
963	962	$(DRIVERS)/mpu4misc.o \
	963	$(VIDEO)/scn2674.o \
964	964	$(DRIVERS)/mpu5hw.o $(DRIVERS)/mpu5.o \
965	965	$(VIDEO)/awpvid.o \
966	966	$(MACHINE)/meters.o \

trunk/src/mame/video/scn2674.c

r0	r243580
	1	/*
	2	SCN2674 - Advanced Video Display Controller (AVDC)  (Video Chip)
	3
	4	This is a somewhat terrible implementation and should probably just be rewritten from scratch
	5	it is currently used by mpu4vid.c and still quite heavily tied to the behavior of that.
	6
	7	I don't know if the timing bugs with those games comes from this, or emulation of the other
	8	MPU4 devices tho because even some of the non-video games seem laggy and prone to failure.
	9
	10	-- currently expects (from the host driver)
	11	decoded gfx in regions 0,1,2,3 in various formats (normal, double height etc.)
	12	eventually the chip should just handle this without the need to decode anything
	13
	14	a callback function for when the irqs are changed / updated
	15
	16	a call from the video start from your video start function
	17
	18	a call to the scanline function each scanline
	19
	20	a call to the video draw (with ram pointer) from a screen update function
	21
	22	video to be on the primary screen
	23
	24	this could all be simplified / changed, the chip can actually be hooked up in various ways
	25	including working on a per scanline basis with almost no ram
	26	*/
	27
	28	#include "emu.h"
	29	#include "scn2674.h"
	30
	31
	32
	33	const device_type SCN2674_VIDEO = &device_creator<scn2674_device>;
	34
	35
	36	scn2674_device::scn2674_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	37	: device_t(mconfig, SCN2674_VIDEO, "SCN2674 VDC", tag, owner, clock, "scn2674_device", __FILE__),
	38	m_interrupt_callback(*this),
	39	m_gfxdecode(*this),
	40	m_palette(*this)
	41	{
	42	}
	43
	44	//-------------------------------------------------
	45	//  static_set_gfxdecode_tag: Set the tag of the
	46	//  gfx decoder
	47	//-------------------------------------------------
	48
	49	void scn2674_device::static_set_gfxdecode_tag(device_t &device, const char *tag)
	50	{
	51	downcast<scn2674_device &>(device).m_gfxdecode.set_tag(tag);
	52	}
	53
	54	//-------------------------------------------------
	55	//  static_set_palette_tag: Set the tag of the
	56	//  palette device
	57	//-------------------------------------------------
	58
	59	void scn2674_device::static_set_palette_tag(device_t &device, const char *tag)
	60	{
	61	downcast<scn2674_device &>(device).m_palette.set_tag(tag);
	62	}
	63
	64	void scn2674_device::device_start()
	65	{
	66	// resolve callbacks
	67	m_interrupt_callback.resolve_safe();
	68	}
	69
	70	void scn2674_device::device_reset()
	71	{
	72	m_scn2674_IR_pointer= 0;
	73	m_scn2674_screen1_l= 0;
	74	m_scn2674_screen1_h= 0;
	75	m_scn2674_cursor_l= 0;
	76	m_scn2674_cursor_h= 0;
	77	m_scn2674_screen2_l= 0;
	78	m_scn2674_screen2_h= 0;
	79	m_scn2674_irq_register= 0;
	80	m_scn2674_status_register= 0;
	81	m_scn2674_irq_mask= 0;
	82	m_scn2674_gfx_enabled= 0;
	83	m_scn2674_display_enabled= 0;
	84	m_scn2674_display_enabled_field= 0;
	85	m_scn2674_display_enabled_scanline= 0;
	86	m_scn2674_cursor_enabled= 0;
	87	m_IR0_scn2674_double_ht_wd= 0;
	88	m_IR0_scn2674_scanline_per_char_row= 0;
	89	m_IR0_scn2674_sync_select= 0;
	90	m_IR0_scn2674_buffer_mode_select= 0;
	91	m_IR1_scn2674_interlace_enable= 0;
	92	m_IR1_scn2674_equalizing_constant= 0;
	93	m_IR2_scn2674_row_table= 0;
	94	m_IR2_scn2674_horz_sync_width= 0;
	95	m_IR2_scn2674_horz_back_porch= 0;
	96	m_IR3_scn2674_vert_front_porch= 0;
	97	m_IR3_scn2674_vert_back_porch= 0;
	98	m_IR4_scn2674_rows_per_screen= 0;
	99	m_IR4_scn2674_character_blink_rate_divisor= 0;
	100	m_IR5_scn2674_character_per_row= 0;
	101	m_IR6_scn2674_cursor_first_scanline= 0;
	102	m_IR6_scn2674_cursor_last_scanline= 0;
	103	m_IR7_scn2674_cursor_underline_position= 0;
	104	m_IR7_scn2674_cursor_rate_divisor= 0;
	105	m_IR7_scn2674_cursor_blink= 0;
	106	m_IR7_scn2674_vsync_width= 0;
	107	m_IR8_scn2674_display_buffer_first_address_LSB= 0;
	108	m_IR9_scn2674_display_buffer_first_address_MSB= 0;
	109	m_IR9_scn2674_display_buffer_last_address= 0;
	110	m_IR10_scn2674_display_pointer_address_lower= 0;
	111	m_IR11_scn2674_display_pointer_address_upper= 0;
	112	m_IR11_scn2674_reset_scanline_counter_on_scrollup= 0;
	113	m_IR11_scn2674_reset_scanline_counter_on_scrolldown= 0;
	114	m_IR12_scn2674_scroll_start= 0;
	115	m_IR12_scn2674_split_register_1= 0;
	116	m_IR13_scn2674_scroll_end= 0;
	117	m_IR13_scn2674_split_register_2= 0;
	118	m_IR14_scn2674_scroll_lines= 0;
	119	m_IR14_scn2674_double_1= 0;
	120	m_IR14_scn2674_double_2= 0;
	121	m_scn2674_horz_front_porch= 0;
	122	m_scn2674_spl1= 0;
	123	m_scn2674_spl2= 0;
	124	m_scn2674_dbl1= 0;
	125	m_rowcounter= 0;
	126	m_linecounter= 0;
	127	m_scn2674_irq_state= 0;
	128	}
	129
	130	// 15 Initialization Registers (8-bit each)
	131	void scn2674_device::scn2674_write_init_regs(UINT8 data)
	132	{
	133	LOG2674(("scn2674_write_init_regs %02x %02x\n",m_scn2674_IR_pointer,data));
	134
	135	//  m_scn2674_IR[m_scn2674_IR_pointer]=data;
	136
	137
	138	switch ( m_scn2674_IR_pointer) /* display some debug info, set mame specific variables */
	139	{
	140	case 0:
	141	m_IR0_scn2674_double_ht_wd = (data & 0x80)>>7;
	142	m_IR0_scn2674_scanline_per_char_row = ((data & 0x78)>>3) + 1;
	143	m_IR0_scn2674_sync_select = (data&0x04)>>2;
	144	m_IR0_scn2674_buffer_mode_select = (data&0x03);
	145
	146	LOG2674(("IR0 - Double Ht Wd %02x\n",m_IR0_scn2674_double_ht_wd));//affects IR14 as well
	147	LOG2674(("IR0 - Scanlines per Character Row %02x\n",m_IR0_scn2674_scanline_per_char_row));//value+1 = scanlines
	148
	149	if (m_IR0_scn2674_scanline_per_char_row != 8)
	150	{
	151	popmessage("Row size change, contact MAMEDEV");
	152	}
	153	LOG2674(("IR0 - Sync Select %02x\n",m_IR0_scn2674_sync_select));//1 = csync
	154	LOG2674(("IR0 - Buffer Mode Select %02x\n",m_IR0_scn2674_buffer_mode_select)); //0 independent 1 transparent 2 shared 3 row
	155	break;
	156
	157	case 1:
	158	m_IR1_scn2674_interlace_enable = (data&0x80)>>7;
	159	m_IR1_scn2674_equalizing_constant = (data&0x7f)+1;
	160
	161	LOG2674(("IR1 - Interlace Enable %02x\n",m_IR1_scn2674_interlace_enable));
	162	LOG2674(("IR1 - Equalizing Constant %02i CCLKs\n",m_IR1_scn2674_equalizing_constant));
	163	break;
	164
	165	case 2:
	166	m_IR2_scn2674_row_table = (data&0x80)>>7;
	167	m_IR2_scn2674_horz_sync_width = (((data&0x78)>>3)*2) + 2;
	168	m_IR2_scn2674_horz_back_porch = ((data&0x07)*4) - 1;
	169
	170	LOG2674(("IR2 - Row Table %02x\n",m_IR2_scn2674_row_table));
	171	LOG2674(("IR2 - Horizontal Sync Width %02i CCLKs\n",m_IR2_scn2674_horz_sync_width));
	172	LOG2674(("IR2 - Horizontal Back Porch %02i CCLKs\n",m_IR2_scn2674_horz_back_porch));
	173	break;
	174
	175	case 3:
	176	m_IR3_scn2674_vert_front_porch =  (((data&0xe0)>>5) * 4)+4 ;
	177	m_IR3_scn2674_vert_back_porch = ((data&0x1f) * 2) + 4;
	178
	179	LOG2674(("IR3 - Vertical Front Porch %02i Lines\n",m_IR3_scn2674_vert_front_porch));
	180	LOG2674(("IR3 - Vertical Back Porch %02i Lines\n",m_IR3_scn2674_vert_back_porch));
	181	break;
	182
	183	case 4:
	184	m_IR4_scn2674_rows_per_screen = (data&0x7f) + 1;
	185	m_IR4_scn2674_character_blink_rate_divisor = ((data & 0x80)>>7 ? 128:64);
	186
	187	LOG2674(("IR4 - Rows Per Screen %02i\n",m_IR4_scn2674_rows_per_screen));
	188	LOG2674(("IR4 - Character Blink Rate = 1/%02i\n",m_IR4_scn2674_character_blink_rate_divisor));
	189	break;
	190
	191	case 5:
	192	/* IR5 - Active Characters Per Row
	193	cccc cccc
	194	c = Characters Per Row */
	195	m_IR5_scn2674_character_per_row = data + 1;
	196	LOG2674(("IR5 - Active Characters Per Row %02i\n",m_IR5_scn2674_character_per_row));
	197	break;
	198
	199	case 6:
	200	m_IR6_scn2674_cursor_last_scanline = (data & 0x0f);
	201	m_IR6_scn2674_cursor_first_scanline = (data & 0xf0)>>4;
	202	LOG2674(("IR6 - First Line of Cursor %02x\n",m_IR6_scn2674_cursor_first_scanline));
	203	LOG2674(("IR6 - Last Line of Cursor %02x\n",m_IR6_scn2674_cursor_last_scanline));
	204	break;
	205
	206	case 7:
	207	m_IR7_scn2674_cursor_underline_position = (data & 0x0f);
	208	m_IR7_scn2674_cursor_rate_divisor = ((data & 0x10)>>4 ? 64:32);
	209	m_IR7_scn2674_cursor_blink = (data & 0x20)>>5;
	210
	211	m_IR7_scn2674_vsync_width = vsync_table[(data & 0xC0)>>6];
	212
	213	LOG2674(("IR7 - Underline Position %02x\n",m_IR7_scn2674_cursor_underline_position));
	214	LOG2674(("IR7 - Cursor rate 1/%02i\n",m_IR7_scn2674_cursor_rate_divisor));
	215	LOG2674(("IR7 - Cursor blink %02x\n",m_IR7_scn2674_cursor_blink));
	216	LOG2674(("IR7 - Vsync Width  %02i Lines\n",m_IR7_scn2674_vsync_width));
	217	break;
	218
	219	case 8:
	220	m_IR8_scn2674_display_buffer_first_address_LSB = data;
	221	LOG2674(("IR8 - Display Buffer First Address LSB %02x\n",m_IR8_scn2674_display_buffer_first_address_LSB));
	222	break;
	223
	224	case 9:
	225	m_IR9_scn2674_display_buffer_first_address_MSB = data & 0x0f;
	226	m_IR9_scn2674_display_buffer_last_address = (data & 0xf0)>>4;
	227	LOG2674(("IR9 - Display Buffer First Address MSB %02x\n",m_IR9_scn2674_display_buffer_first_address_MSB));
	228	LOG2674(("IR9 - Display Buffer Last Address %02x\n",m_IR9_scn2674_display_buffer_last_address));
	229	break;
	230
	231	case 10:
	232	m_IR10_scn2674_display_pointer_address_lower = data;
	233	LOG2674(("IR10 - Display Pointer Address Lower %02x\n",m_IR10_scn2674_display_pointer_address_lower));
	234	break;
	235
	236	case 11:
	237	m_IR11_scn2674_display_pointer_address_upper= data&0x3f;
	238	m_IR11_scn2674_reset_scanline_counter_on_scrollup= (data&0x40 >> 6);
	239	m_IR11_scn2674_reset_scanline_counter_on_scrolldown= (data&0x80 >> 7);
	240
	241	LOG2674(("IR11 - Display Pointer Address Lower %02x\n",m_IR11_scn2674_display_pointer_address_upper));
	242	LOG2674(("IR11 - Reset Scanline Counter on Scroll Up %02x\n",m_IR11_scn2674_reset_scanline_counter_on_scrollup));
	243	LOG2674(("IR11 - Reset Scanline Counter on Scroll Down %02x\n",m_IR11_scn2674_reset_scanline_counter_on_scrolldown));
	244	break;
	245
	246	case 12:
	247	m_IR12_scn2674_scroll_start = (data & 0x80)>>7;
	248	m_IR12_scn2674_split_register_1 = (data & 0x7f);
	249	LOG2674(("IR12 - Scroll Start %02x\n",m_IR12_scn2674_scroll_start));
	250	LOG2674(("IR12 - Split Register 1 %02x\n",m_IR12_scn2674_split_register_1));
	251	break;
	252
	253	case 13:
	254	m_IR13_scn2674_scroll_end = (data & 0x80)>>7;
	255	m_IR13_scn2674_split_register_2 = (data & 0x7f);
	256	LOG2674(("IR13 - Scroll End %02x\n",m_IR13_scn2674_scroll_end));
	257	LOG2674(("IR13 - Split Register 2 %02x\n",m_IR13_scn2674_split_register_2));
	258	break;
	259
	260	case 14:
	261	m_IR14_scn2674_scroll_lines = (data & 0x0f);
	262	if (!m_IR0_scn2674_double_ht_wd)
	263	{
	264	m_IR14_scn2674_double_2 = (data & 0x30)>>4;
	265	LOG2674(("IR14 - Double 2 %02x\n",m_IR14_scn2674_double_2));
	266	}
	267	//0 normal, 1, double width, 2, double width and double tops 3, double width and double bottoms
	268	//1 affects SSR1, 2 affects SSR2
	269	//If Double Height enabled in IR0, Screen start 1 upper (bits 7 and 6)replace Double 1, and Double 2 is unused
	270	m_IR14_scn2674_double_1 = (data & 0xc0)>>6;
	271	LOG2674(("IR14 - Double 1 %02x\n",m_IR14_scn2674_double_1));
	272
	273	LOG2674(("IR14 - Scroll Lines %02i\n",m_IR14_scn2674_scroll_lines));
	274	break;
	275
	276	case 15: /* not valid! */
	277	break;
	278
	279	}
	280
	281	m_scn2674_horz_front_porch = 2*(m_IR1_scn2674_equalizing_constant) + 3*(m_IR2_scn2674_horz_sync_width)-(m_IR5_scn2674_character_per_row) - m_IR2_scn2674_horz_back_porch;
	282	LOG2674(("Horizontal Front Porch %02x CCLKs\n",m_scn2674_horz_front_porch));
	283
	284	m_scn2674_IR_pointer++;
	285	if (m_scn2674_IR_pointer>14)m_scn2674_IR_pointer=14;
	286	}
	287
	288	void scn2674_device::scn2674_write_command(running_machine &machine, UINT8 data)
	289	{
	290	UINT8 operand;
	291	int i;
	292
	293	LOG2674(("scn2674_write_command %02x\n",data));
	294
	295	if (data==0x00)
	296	{
	297	/* master reset, configures registers */
	298	LOG2674(("master reset\n"));
	299	m_scn2674_IR_pointer=0;
	300	m_scn2674_irq_register = 0x00;
	301	m_scn2674_status_register = 0x20;//RDFLG activated
	302	m_linecounter =0;
	303	m_rowcounter =0;
	304	m_scn2674_irq_mask = 0x00;
	305	m_scn2674_gfx_enabled = 0;
	306	m_scn2674_display_enabled = 0;
	307	m_scn2674_cursor_enabled = 0;
	308	m_IR2_scn2674_row_table = 0;
	309	}
	310
	311	if ((data&0xf0)==0x10)
	312	{
	313	/* set IR pointer */
	314	operand = data & 0x0f;
	315	LOG2674(("set IR pointer %02x\n",operand));
	316
	317	m_scn2674_IR_pointer=operand;
	318
	319	}
	320
	321	/* ANY COMBINATION OF THESE ARE POSSIBLE */
	322
	323	if ((data&0xe3)==0x22)
	324	{
	325	/* Disable GFX */
	326	LOG2674(("disable GFX %02x\n",data));
	327	m_scn2674_gfx_enabled = 0;
	328	}
	329
	330	if ((data&0xe3)==0x23)
	331	{
	332	/* Enable GFX */
	333	LOG2674(("enable GFX %02x\n",data));
	334	m_scn2674_gfx_enabled = 1;
	335	}
	336
	337	if ((data&0xe9)==0x28)
	338	{
	339	/* Display off */
	340	operand = data & 0x04;
	341
	342	m_scn2674_display_enabled = 0;
	343
	344	if (operand)
	345	LOG2674(("display OFF - float DADD bus %02x\n",data));
	346	else
	347	LOG2674(("display OFF - no float DADD bus %02x\n",data));
	348	}
	349
	350	if ((data&0xe9)==0x29)
	351	{
	352	/* Display on */
	353	operand = data & 0x04;
	354
	355	if (operand)
	356	{
	357	m_scn2674_display_enabled_field = 1;
	358	LOG2674(("display ON - next field %02x\n",data));
	359	}
	360	else
	361	{
	362	m_scn2674_display_enabled_scanline = 1;
	363	LOG2674(("display ON - next scanline %02x\n",data));
	364	}
	365	}
	366
	367	if ((data&0xf1)==0x30)
	368	{
	369	/* Cursor Off */
	370	LOG2674(("cursor off %02x\n",data));
	371	m_scn2674_cursor_enabled = 0;
	372	}
	373
	374	if ((data&0xf1)==0x31)
	375	{
	376	/* Cursor On */
	377	LOG2674(("cursor on %02x\n",data));
	378	m_scn2674_cursor_enabled = 1;
	379	}
	380
	381	/* END */
	382
	383	if ((data&0xe0)==0x40)
	384	{
	385	/* Reset Interrupt / Status bit */
	386	operand = data & 0x1f;
	387	LOG2674(("reset interrupt / status bit %02x\n",operand));
	388
	389	m_scn2674_irq_register &= ~(data & 0x1f);
	390	m_scn2674_status_register &= ~(data & 0x1f);
	391
	392	LOG2674(("IRQ Status after reset\n"));
	393	LOG2674(("Split 2   IRQ: %d Active\n",(m_scn2674_irq_register>>0)&1));
	394	LOG2674(("Ready     IRQ: %d Active\n",(m_scn2674_irq_register>>1)&1));
	395	LOG2674(("Split 1   IRQ: %d Active\n",(m_scn2674_irq_register>>2)&1));
	396	LOG2674(("Line Zero IRQ: %d Active\n",(m_scn2674_irq_register>>3)&1));
	397	LOG2674(("V-Blank   IRQ: %d Active\n",(m_scn2674_irq_register>>4)&1));
	398
	399	m_scn2674_irq_state = 0;
	400
	401	for (i = 0; i < 5; i++)
	402	{
	403	if ((m_scn2674_irq_register>>i&1)&(m_scn2674_irq_mask>>i&1))
	404	{
	405	m_scn2674_irq_state = 1;
	406	}
	407	}
	408	m_interrupt_callback(1);
	409
	410	}
	411	if ((data&0xe0)==0x80)
	412	{
	413	/* Disable Interrupt mask*/
	414	operand = data & 0x1f;
	415	m_scn2674_irq_mask &= ~(operand);
	416	LOG2674(("IRQ Mask after disable %x\n",operand));
	417	LOG2674(("Split 2   IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>0)&1));
	418	LOG2674(("Ready     IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>1)&1));
	419	LOG2674(("Split 1   IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>2)&1));
	420	LOG2674(("Line Zero IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>3)&1));
	421	LOG2674(("V-Blank   IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>4)&1));
	422
	423	}
	424
	425	if ((data&0xe0)==0x60)
	426	{
	427	/* Enable Interrupt mask*/
	428	operand = data & 0x1f;
	429	m_scn2674_irq_mask |= (data & 0x1f);
	430
	431	LOG2674(("IRQ Mask after enable %x\n",operand));
	432	LOG2674(("Split 2   IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>0)&1));
	433	LOG2674(("Ready     IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>1)&1));
	434	LOG2674(("Split 1   IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>2)&1));
	435	LOG2674(("Line Zero IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>3)&1));
	436	LOG2674(("V-Blank   IRQ: %d Unmasked\n",(m_scn2674_irq_mask>>4)&1));
	437
	438	}
	439
	440	/* Delayed Commands */
	441	/* These set 0x20 in status register when done */
	442
	443	if (data == 0xa4)
	444	{
	445	/* read at pointer address */
	446	LOG2674(("DELAYED read at pointer address %02x\n",data));
	447	}
	448
	449	if (data == 0xa2)
	450	{
	451	/* write at pointer address */
	452	LOG2674(("DELAYED write at pointer address %02x\n",data));
	453	}
	454
	455	if (data == 0xa9)
	456	{
	457	/* increase cursor address */
	458	LOG2674(("DELAYED increase cursor address %02x\n",data));
	459	}
	460
	461	if (data == 0xac)
	462	{
	463	/* read at cursor address */
	464	LOG2674(("DELAYED read at cursor address %02x\n",data));
	465	}
	466
	467	if (data == 0xaa)
	468	{
	469	/* write at cursor address */
	470	LOG2674(("DELAYED write at cursor address %02x\n",data));
	471	}
	472
	473	if (data == 0xad)
	474	{
	475	/* read at cursor address + increment */
	476	LOG2674(("DELAYED read at cursor address+increment %02x\n",data));
	477	}
	478
	479	if (data == 0xab)
	480	{
	481	/* write at cursor address + increment */
	482	LOG2674(("DELAYED write at cursor address+increment %02x\n",data));
	483	}
	484
	485	if (data == 0xbb)
	486	{
	487	/* write from cursor address to pointer address */
	488	LOG2674(("DELAYED write from cursor address to pointer address %02x\n",data));
	489	}
	490
	491	if (data == 0xbd)
	492	{
	493	/* read from cursor address to pointer address */
	494	LOG2674(("DELAYED read from cursor address to pointer address %02x\n",data));
	495	}
	496	}
	497
	498
	499	READ8_MEMBER( scn2674_device::mpu4_vid_scn2674_r )
	500	{
	501	/*
	502	Offset:  Purpose
	503	0       Interrupt Register
	504	1       Status Register
	505	2       Screen Start 1 Lower Register
	506	3       Screen Start 1 Upper Register
	507	4       Cursor Address Lower Register
	508	5       Cursor Address Upper Register
	509	6       Screen Start 2 Lower Register
	510	7       Screen Start 2 Upper Register
	511	*/
	512
	513	switch (offset)
	514	{
	515	/*  Status / Irq Register
	516
	517	--RV ZSRs
	518
	519	6+7 -- = ALWAYS 0
	520	5  R  = RDFLG (Status Register Only)
	521	4  V  = Vblank
	522	3  Z  = Line Zero
	523	2  S  = Split 1
	524	1  R  = Ready
	525	0  s  = Split 2
	526	*/
	527
	528	case 0:
	529	LOG2674(("Read Irq Register %02x %06x\n",m_scn2674_irq_register,space.device().safe_pc()));
	530	return m_scn2674_irq_register;
	531
	532	case 1:
	533	LOG2674(("Read Status Register %02X %06x\n",m_scn2674_status_register,space.device().safe_pc()));
	534	return m_scn2674_status_register;
	535
	536	case 2: LOG2674(("Read Screen1_l Register %06x\n",space.device().safe_pc()));return m_scn2674_screen1_l;
	537	case 3: LOG2674(("Read Screen1_h Register %06x\n",space.device().safe_pc()));return m_scn2674_screen1_h;
	538	case 4: LOG2674(("Read Cursor_l Register %06x\n",space.device().safe_pc()));return m_scn2674_cursor_l;
	539	case 5: LOG2674(("Read Cursor_h Register %06x\n",space.device().safe_pc()));return m_scn2674_cursor_h;
	540	case 6: LOG2674(("Read Screen2_l Register %06x\n",space.device().safe_pc()));return m_scn2674_screen2_l;
	541	case 7: LOG2674(("Read Screen2_h Register %06x\n",space.device().safe_pc()));return m_scn2674_screen2_h;
	542	}
	543
	544	return 0xff;
	545	}
	546
	547
	548	WRITE8_MEMBER( scn2674_device::mpu4_vid_scn2674_w )
	549	{
	550	/*
	551	Offset:  Purpose
	552	0       Initialization Registers
	553	1       Command Register
	554	2       Screen Start 1 Lower Register
	555	3       Screen Start 1 Upper Register
	556	4       Cursor Address Lower Register
	557	5       Cursor Address Upper Register
	558	6       Screen Start 2 Lower Register
	559	7       Screen Start 2 Upper Register
	560	*/
	561
	562	switch (offset)
	563	{
	564	case 0:
	565	scn2674_write_init_regs(data);
	566	break;
	567
	568	case 1:
	569	scn2674_write_command(space.machine(), data);
	570	break;
	571
	572	case 2: m_scn2674_screen1_l = data; break;
	573	case 3:
	574	m_scn2674_screen1_h = (data&0x3f);//uppermost two bytes not part of register
	575	m_scn2674_dbl1=(data & 0xc0)>>6;
	576	if (m_IR0_scn2674_double_ht_wd)
	577	{
	578	m_IR14_scn2674_double_1 = m_scn2674_dbl1;
	579	LOG2674(("IR14 - Double 1 overridden %02x\n",m_IR14_scn2674_double_1));
	580	}
	581	break;
	582
	583	case 4: m_scn2674_cursor_l  = data; break;
	584	case 5: m_scn2674_cursor_h  = data; break;
	585	case 6: m_scn2674_screen2_l = data; break;
	586	case 7:
	587	m_scn2674_screen2_h = (data&0x3f);
	588	m_scn2674_spl1 = (data & 0x40);
	589	m_scn2674_spl2 = (data & 0x80);
	590	break;
	591	}
	592	}
	593
	594
	595
	596	void scn2674_device::scn2674_line(running_machine &machine)
	597	{
	598	if (m_linecounter==0)/* Ready - this triggers for the first scanline of the screen */
	599	{
	600	m_scn2674_status_register |= 0x02;
	601	if (m_scn2674_irq_mask&0x02)
	602	{
	603	LOG2674(("SCN2674 Ready\n"));
	604	m_scn2674_irq_state = 1;
	605	m_scn2674_irq_register |= 0x02;
	606	m_interrupt_callback(1);
	607	}
	608	}
	609
	610	// should be triggered at the start of each ROW (line zero for that row)
	611	if (( m_linecounter%8 == 0)&& (m_linecounter < 297) )
	612	{
	613	m_scn2674_status_register |= 0x08;
	614	if (m_scn2674_irq_mask&0x08)
	615	{
	616	LOG2674(("SCN2674 Line Zero\n"));
	617	m_scn2674_irq_state = 1;
	618	m_scn2674_irq_register |= 0x08;
	619	m_interrupt_callback(1);
	620	}
	621	m_rowcounter = ((m_rowcounter+1)% 37);//Not currently used
	622	}
	623
	624	// this is ROWS not scanlines!!
	625	if ((m_linecounter == m_IR12_scn2674_split_register_1*8)&&(m_linecounter != 0))
	626	/* Split Screen 1 */
	627	{
	628	if (m_scn2674_spl1)
	629	{
	630	popmessage("Split screen 1 address shift required, contact MAMEDEV");
	631	}
	632	m_scn2674_status_register |= 0x04;
	633	if (m_scn2674_irq_mask&0x04)
	634	{
	635	machine.first_screen()->update_partial(m_linecounter);
	636	m_scn2674_irq_register |= 0x04;
	637	LOG2674(("SCN2674 Split Screen 1\n"));
	638	m_scn2674_irq_state = 1;
	639	m_interrupt_callback(1);
	640	//          machine.first_screen()->update_partial(m_linecounter);
	641	}
	642	}
	643
	644	// this is in ROWS not scanlines!!!
	645	if ((m_linecounter == m_IR13_scn2674_split_register_2*8)&&(m_linecounter != 0))
	646	/* Split Screen 2 */
	647	{
	648	if (m_scn2674_spl2)
	649	{
	650	popmessage("Split screen 2 address shift required, contact MAMEDEV");
	651	}
	652	m_scn2674_status_register |= 0x01;
	653	if (m_scn2674_irq_mask&0x01)
	654	{
	655	machine.first_screen()->update_partial(m_linecounter);
	656	LOG2674(("SCN2674 Split Screen 2 irq\n"));
	657	m_scn2674_irq_state = 1;
	658	m_scn2674_irq_register |= 0x01;
	659	m_interrupt_callback(1);
	660	//machine.first_screen()->update_partial(m_linecounter);
	661	}
	662	}
	663
	664	if (m_linecounter==296)//front porch
	665	{
	666	m_scn2674_status_register |= 0x10;
	667	if (m_scn2674_irq_mask&0x10)
	668	{
	669	LOG2674(("vblank irq\n"));
	670	m_scn2674_irq_state = 1;
	671	m_scn2674_irq_register |= 0x10;
	672	m_interrupt_callback(1);
	673	}
	674
	675	}
	676
	677	}
	678
	679
	680	// scanline timer
	681
	682
	683	void scn2674_device::scn2674_do_scanline(running_machine &machine, int scanline)
	684	{
	685	//This represents the scanline counter in the SCN2674. Note that we ignore the horizontal blanking
	686
	687	if (((m_scn2674_display_enabled_scanline) || (m_scn2674_display_enabled_field && (m_IR1_scn2674_interlace_enable == 0)))&&(!m_scn2674_display_enabled))
	688	{
	689	m_scn2674_display_enabled = 1;
	690	m_scn2674_display_enabled_scanline = 0;
	691	m_scn2674_display_enabled_field = 0;
	692	}
	693	if (m_scn2674_display_enabled)
	694	{
	695	m_linecounter = scanline;
	696	}
	697	else
	698	{
	699	m_linecounter =297;//hold the counter in the vsync point, it's not clear whether this is done or not
	700	}
	701	scn2674_line(machine);
	702	//  timer.machine().scheduler().synchronize();
	703	}
	704
	705
	706	////// screen update
	707	template<class _BitmapClass>
	708	void scn2674_device::scn2574_draw_common( running_machine &machine, _BitmapClass &bitmap, const rectangle &cliprect, UINT16* vid_mainram )
	709	{
	710	int x, y/*, count = 0*/;
	711	/* this is in main ram.. i think it must transfer it out of here??? */
	712	/* count = 0x0018b6/2; - crmaze count = 0x004950/2; - turnover */
	713	/* we're in row table mode...thats why */
	714	for(y = 0; y < m_IR4_scn2674_rows_per_screen; y++)
	715	{
	716	int screen2_base = (m_scn2674_screen2_h << 8) | m_scn2674_screen2_l;
	717	UINT16 rowbase = (vid_mainram[1+screen2_base+(y*2)]<<8)|vid_mainram[screen2_base+(y*2)];
	718	int dbl_size=0;
	719	int gfxregion = 0;
	720
	721	if (m_IR0_scn2674_double_ht_wd)
	722	{
	723	dbl_size = (rowbase & 0xc000)>>14;  /* ONLY if double size is enabled.. otherwise it can address more chars given more RAM */
	724	}
	725
	726	if (dbl_size&2)
	727	{
	728	gfxregion = 1;
	729	}
	730	for(x = 0; x < m_IR5_scn2674_character_per_row; x++)
	731	{
	732	UINT16 tiledat;
	733	UINT16 attr;
	734
	735	tiledat = vid_mainram[(rowbase+x)&0x7fff];
	736	attr = tiledat >>12;
	737
	738	if (attr)
	739	m_gfxdecode->gfx(gfxregion)->opaque(bitmap,cliprect,tiledat,0,0,0,(x*8),(y*8));
	740
	741	}
	742	if (dbl_size&2)
	743	{
	744	y++;/* skip a row? */
	745	}
	746
	747	}
	748	}
	749
	750	void scn2674_device::scn2574_draw( running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16* vid_mainram )
	751	{ scn2574_draw_common(machine, bitmap, cliprect, vid_mainram); }
	752
	753	void scn2674_device::scn2574_draw( running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT16* vid_mainram )
	754	{ scn2574_draw_common(machine, bitmap, cliprect, vid_mainram); }
	755
	756	void scn2674_device::init_stuff()
	757	{
	758	// from video start
	759	m_scn2674_IR_pointer = 0;
	760	}

trunk/src/mame/video/scn2674.h

r0	r243580
	1
	2	#define S674VERBOSE 0
	3	#define LOG2674(x) do { if (S674VERBOSE) logerror x; } while (0)
	4
	5
	6	#define MCFG_SCN2674_VIDEO_ADD(_tag, _clock, _irq) \
	7	MCFG_DEVICE_ADD(_tag, SCN2674_VIDEO, _clock) \
	8	downcast<scn2674_device *>(device)->set_callbacks(DEVCB_##_irq);
	9
	10	#define MCFG_SCN2674_GFXDECODE(_gfxtag) \
	11	scn2674_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
	12
	13	#define MCFG_SCN2674_PALETTE(_palette_tag) \
	14	scn2674_device::static_set_palette_tag(*device, "^" _palette_tag);
	15
	16	typedef void (*s2574_interrupt_callback_func)(running_machine &machine);
	17
	18	static const UINT8 vsync_table[4] = {3,1,5,7}; //Video related
	19
	20	class scn2674_device : public device_t
	21	{
	22	public:
	23	scn2674_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	24
	25	// static configuration
	26	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
	27	static void static_set_palette_tag(device_t &device, const char *tag);
	28
	29	template<class _irq> void set_callbacks(_irq irq) {
	30	m_interrupt_callback.set_callback(irq);
	31	}
	32	//  int m_gfx_index;
	33
	34	DECLARE_READ8_MEMBER( mpu4_vid_scn2674_r );
	35	DECLARE_WRITE8_MEMBER( mpu4_vid_scn2674_w );
	36
	37	UINT8 get_irq_state( void )
	38	{
	39	return m_scn2674_irq_state;
	40	}
	41
	42
	43
	44	void scn2574_draw(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16* vid_mainram);
	45	void scn2574_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT16* vid_mainram);
	46	void init_stuff();
	47	void scn2674_do_scanline(running_machine &machine, int scanline);
	48
	49
	50	protected:
	51	virtual void device_start();
	52	virtual void device_reset();
	53
	54	devcb_write_line m_interrupt_callback;
	55
	56	UINT8 m_scn2674_IR_pointer;
	57	UINT8 m_scn2674_screen1_l;
	58	UINT8 m_scn2674_screen1_h;
	59	UINT8 m_scn2674_cursor_l;
	60	UINT8 m_scn2674_cursor_h;
	61	UINT8 m_scn2674_screen2_l;
	62	UINT8 m_scn2674_screen2_h;
	63	UINT8 m_scn2674_irq_register;
	64	UINT8 m_scn2674_status_register;
	65	UINT8 m_scn2674_irq_mask;
	66	UINT8 m_scn2674_gfx_enabled;
	67	UINT8 m_scn2674_display_enabled;
	68	UINT8 m_scn2674_display_enabled_field;
	69	UINT8 m_scn2674_display_enabled_scanline;
	70	UINT8 m_scn2674_cursor_enabled;
	71	UINT8 m_IR0_scn2674_double_ht_wd;
	72	UINT8 m_IR0_scn2674_scanline_per_char_row;
	73	UINT8 m_IR0_scn2674_sync_select;
	74	UINT8 m_IR0_scn2674_buffer_mode_select;
	75	UINT8 m_IR1_scn2674_interlace_enable;
	76	UINT8 m_IR1_scn2674_equalizing_constant;
	77	UINT8 m_IR2_scn2674_row_table;
	78	UINT8 m_IR2_scn2674_horz_sync_width;
	79	UINT8 m_IR2_scn2674_horz_back_porch;
	80	UINT8 m_IR3_scn2674_vert_front_porch;
	81	UINT8 m_IR3_scn2674_vert_back_porch;
	82	UINT8 m_IR4_scn2674_rows_per_screen;
	83	UINT8 m_IR4_scn2674_character_blink_rate_divisor;
	84	UINT8 m_IR5_scn2674_character_per_row;
	85	UINT8 m_IR6_scn2674_cursor_first_scanline;
	86	UINT8 m_IR6_scn2674_cursor_last_scanline;
	87	UINT8 m_IR7_scn2674_cursor_underline_position;
	88	UINT8 m_IR7_scn2674_cursor_rate_divisor;
	89	UINT8 m_IR7_scn2674_cursor_blink;
	90	UINT8 m_IR7_scn2674_vsync_width;
	91	UINT8 m_IR8_scn2674_display_buffer_first_address_LSB;
	92	UINT8 m_IR9_scn2674_display_buffer_first_address_MSB;
	93	UINT8 m_IR9_scn2674_display_buffer_last_address;
	94	UINT8 m_IR10_scn2674_display_pointer_address_lower;
	95	UINT8 m_IR11_scn2674_display_pointer_address_upper;
	96	UINT8 m_IR11_scn2674_reset_scanline_counter_on_scrollup;
	97	UINT8 m_IR11_scn2674_reset_scanline_counter_on_scrolldown;
	98	UINT8 m_IR12_scn2674_scroll_start;
	99	UINT8 m_IR12_scn2674_split_register_1;
	100	UINT8 m_IR13_scn2674_scroll_end;
	101	UINT8 m_IR13_scn2674_split_register_2;
	102	UINT8 m_IR14_scn2674_scroll_lines;
	103	UINT8 m_IR14_scn2674_double_1;
	104	UINT8 m_IR14_scn2674_double_2;
	105	UINT8 m_scn2674_horz_front_porch;
	106	UINT8 m_scn2674_spl1;
	107	UINT8 m_scn2674_spl2;
	108	UINT8 m_scn2674_dbl1;
	109	int m_rowcounter;
	110	int m_linecounter;
	111
	112	UINT8 m_scn2674_irq_state;
	113
	114	void scn2674_write_init_regs(UINT8 data);
	115	void scn2674_write_command(running_machine &machine, UINT8 data);
	116	void scn2674_line(running_machine &machine);
	117
	118	template<class _BitmapClass>
	119	void scn2574_draw_common( running_machine &machine, _BitmapClass &bitmap, const rectangle &cliprect, UINT16* vid_mainram );
	120
	121	private:
	122	required_device<gfxdecode_device> m_gfxdecode;
	123	required_device<palette_device> m_palette;
	124	};
	125
	126
	127	extern const device_type SCN2674_VIDEO;

trunk/src/mame/video/wc90.c

r243579	r243580
94	94
95	95	***************************************************************************/
96	96
97		WRITE8_MEMBER(wc90_state::bgvideoram_w)
	97	WRITE8_MEMBER(wc90_state::wc90_bgvideoram_w)
98	98	{
99	99	m_bgvideoram[offset] = data;
100	100	m_bg_tilemap->mark_tile_dirty(offset & 0x7ff);
101	101	}
102	102
103		WRITE8_MEMBER(wc90_state::fgvideoram_w)
	103	WRITE8_MEMBER(wc90_state::wc90_fgvideoram_w)
104	104	{
105	105	m_fgvideoram[offset] = data;
106	106	m_fg_tilemap->mark_tile_dirty(offset & 0x7ff);
107	107	}
108	108
109		WRITE8_MEMBER(wc90_state::txvideoram_w)
	109	WRITE8_MEMBER(wc90_state::wc90_txvideoram_w)
110	110	{
111	111	m_txvideoram[offset] = data;
112	112	m_tx_tilemap->mark_tile_dirty(offset & 0x7ff);
r243579	r243580
121	121	***************************************************************************/
122	122
123	123
124		UINT32 wc90_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	124	UINT32 wc90_state::screen_update_wc90(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
125	125	{
126	126	m_bg_tilemap->set_scrollx(0,m_scroll2xlo[0] + 256 * m_scroll2xhi[0]);
127	127	m_bg_tilemap->set_scrolly(0,m_scroll2ylo[0] + 256 * m_scroll2yhi[0]);

trunk/src/mame/video/wwfsstar.c

r243579	r243580
15	15	for writes to Video Ram
16	16	*******************************************************************************/
17	17
18		WRITE16_MEMBER(wwfsstar_state::fg0_videoram_w)
	18	WRITE16_MEMBER(wwfsstar_state::wwfsstar_fg0_videoram_w)
19	19	{
20	20	COMBINE_DATA(&m_fg0_videoram[offset]);
21	21	m_fg0_tilemap->mark_tile_dirty(offset/2);
22	22	}
23	23
24		WRITE16_MEMBER(wwfsstar_state::bg0_videoram_w)
	24	WRITE16_MEMBER(wwfsstar_state::wwfsstar_bg0_videoram_w)
25	25	{
26	26	COMBINE_DATA(&m_bg0_videoram[offset]);
27	27	m_bg0_tilemap->mark_tile_dirty(offset/2);
r243579	r243580
207	207
208	208	m_bg0_tilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(wwfsstar_state::get_bg0_tile_info),this),tilemap_mapper_delegate(FUNC(wwfsstar_state::bg0_scan),this), 16, 16,32,32);
209	209	m_fg0_tilemap->set_transparent_pen(0);
210
211		save_item(NAME(m_vblank));
212		save_item(NAME(m_scrollx));
213		save_item(NAME(m_scrolly));
214	210	}
215	211
216		UINT32 wwfsstar_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	212	UINT32 wwfsstar_state::screen_update_wwfsstar(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
217	213	{
218	214	m_bg0_tilemap->set_scrolly(0, m_scrolly  );
219	215	m_bg0_tilemap->set_scrollx(0, m_scrollx  );

trunk/src/mame/video/xxmissio.c

r243579	r243580
12	12	#include "includes/xxmissio.h"
13	13
14	14
15		WRITE8_MEMBER(xxmissio_state::scroll_x_w)
	15	WRITE8_MEMBER(xxmissio_state::xxmissio_scroll_x_w)
16	16	{
17	17	m_xscroll = data;
18	18	}
19		WRITE8_MEMBER(xxmissio_state::scroll_y_w)
	19	WRITE8_MEMBER(xxmissio_state::xxmissio_scroll_y_w)
20	20	{
21	21	m_yscroll = data;
22	22	}
23	23
24		WRITE8_MEMBER(xxmissio_state::flipscreen_w)
	24	WRITE8_MEMBER(xxmissio_state::xxmissio_flipscreen_w)
25	25	{
26	26	m_flipscreen = data & 0x01;
27	27	}
28	28
29		WRITE8_MEMBER(xxmissio_state::bgram_w)
	29	WRITE8_MEMBER(xxmissio_state::xxmissio_bgram_w)
30	30	{
31	31	int x = (offset + (m_xscroll >> 3)) & 0x1f;
32	32	offset = (offset & 0x7e0) | x;
33	33
34	34	m_bgram[offset] = data;
35	35	}
36		READ8_MEMBER(xxmissio_state::bgram_r)
	36	READ8_MEMBER(xxmissio_state::xxmissio_bgram_r)
37	37	{
38	38	int x = (offset + (m_xscroll >> 3)) & 0x1f;
39	39	offset = (offset & 0x7e0) | x;
r243579	r243580
69	69	m_bg_tilemap->set_scrolldx(2, 12);
70	70
71	71	m_fg_tilemap->set_transparent_pen(0);
72
73		save_item(NAME(m_xscroll));
74		save_item(NAME(m_yscroll));
75		save_item(NAME(m_flipscreen));
76	72	}
77	73
78	74
r243579	r243580
126	122	}
127	123
128	124
129		UINT32 xxmissio_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	125	UINT32 xxmissio_state::screen_update_xxmissio(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
130	126	{
131	127	machine().tilemap().mark_all_dirty();
132	128	machine().tilemap().set_flip_all(m_flipscreen ? TILEMAP_FLIPX | TILEMAP_FLIPY : 0);

trunk/src/mess/drivers/alnchase.c

r243579	r243580
16	16
17	17	NOTE!: MESS external artwork is required to be able to play
18	18
19
20		TODO:
21		- display should go off when sound is played, needs decay simulation?
22
23	19	***************************************************************************/
24	20
25	21	#include "emu.h"

trunk/src/mess/drivers/edracula.c

r243579	r243580
13	13
14	14	NOTE!: MESS external artwork is required to be able to play
15	15
16
17		TODO:
18		- display should go off when sound is played, needs decay simulation?
19
20	16	***************************************************************************/
21	17
22	18	#include "emu.h"

trunk/src/mess/drivers/ngen.c

r243579	r243580
15	15	channel 1 - X-Bus expansion modules (except disk and graphics)
16	16	channel 2 - graphics?
17	17	channel 3 - hard disk
18		On the CP-001/B26 channels 4 on are handled by the 80186.
19		channel 4 - floppy disk
20	18
21	19	To get to "menu mode", press Space quickly after reset (might need good timing)
22	20	The bootstrap ROM version number is displayed, along with "B,D,L,M,P,T:"
r243579	r243580
81	79	ngen_state(const machine_config &mconfig, device_type type, const char *tag)
82	80	: driver_device(mconfig, type, tag),
83	81	m_maincpu(*this,"maincpu"),
84		m_i386cpu(*this,"i386cpu"),
85	82	m_crtc(*this,"crtc"),
86	83	m_viduart(*this,"videouart"),
87	84	m_iouart(*this,"iouart"),
r243579	r243580
144	141	virtual void machine_start();
145	142
146	143	private:
147		optional_device<i80186_cpu_device> m_maincpu;
148		optional_device<i386_device> m_i386cpu;
	144	required_device<i80186_cpu_device> m_maincpu;
149	145	required_device<mc6845_device> m_crtc;
150	146	required_device<i8251_device> m_viduart;
151	147	required_device<upd7201_device> m_iouart;
r243579	r243580
179	175	UINT8 m_disk_page;
180	176	};
181	177
182		class ngen386_state : public ngen_state
	178	class ngen386_state : public driver_device
183	179	{
184	180	public:
185	181	ngen386_state(const machine_config &mconfig, device_type type, const char *tag)
186		: ngen_state(mconfig, type, tag)
	182	: driver_device(mconfig, type, tag),
	183	m_maincpu(*this,"maincpu"),
	184	m_pic(*this,"pic")
187	185	{}
188	186	private:
	187	required_device<i386_device> m_maincpu;
	188	required_device<pic8259_device> m_pic;
189	189	};
190	190
191	191	WRITE_LINE_MEMBER(ngen_state::pit_out0_w)
r243579	r243580
210	210
211	211	WRITE_LINE_MEMBER(ngen_state::cpu_timer_w)
212	212	{
213		if(state != 0)
214		popmessage("80186 Timer 0 state %i\n",state);
215		m_pic->ir5_w(state);
	213	logerror("80186 Timer 1 state %i\n",state);
216	214	}
217	215
218	216	WRITE_LINE_MEMBER(ngen_state::timer_clk_out)
219	217	{
220	218	m_viduart->write_rxc(state);  // Keyboard UART Rx/Tx clocks
221	219	m_viduart->write_txc(state);
222		// 80186 timer pins also?  EXT bit is enabled for BTOS PIT test.
223		if(m_maincpu)
224		{
225		m_maincpu->tmrin0_w(state);
226		//m_maincpu->tmrin1_w(state);
227		}
228	220	}
229	221
230	222	WRITE16_MEMBER(ngen_state::cpu_peripheral_cb)
r243579	r243580
281	273	case 0x0f:
282	274	if(mem_mask & 0x00ff)
283	275	m_dmac->write(space,offset,data & 0xff);
	276	logerror("(PC=%06x) DMA write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask);
284	277	break;
285	278	case 0x80: // DMA page offset?
286	279	case 0x81:
r243579	r243580
328	321	m_viduart->control_w(space,0,data & 0xff);
329	322	break;
330	323	case 0x1a0:  // serial?
331		logerror("Serial(?) 0x1a0 write offset %04x data %04x mask %04x\n",offset,data,mem_mask);
	324	logerror("(PC=%06x) Serial(?) 0x1a0 write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask);
332	325	break;
333	326	default:
334		logerror("Unknown 80186 peripheral write offset %04x data %04x mask %04x\n",offset,data,mem_mask);
	327	logerror("(PC=%06x) Unknown 80186 peripheral write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask);
335	328	}
336	329	}
337	330
r243579	r243580
358	351	case 0x0f:
359	352	if(mem_mask & 0x00ff)
360	353	ret = m_dmac->read(space,offset);
361		logerror("DMA read offset %04x mask %04x returning %04x\n",offset,mem_mask,ret);
	354	logerror("(PC=%06x) DMA read offset %04x mask %04x returning %04x\n",m_maincpu->device_t::safe_pc(),offset,mem_mask,ret);
362	355	break;
363	356	case 0x80: // DMA page offset?
364	357	case 0x81:
r243579	r243580
405	398	case 0x1a0:  // I/O control register?
406	399	ret = m_control;  // end of DMA transfer? (maybe a per-channel EOP?) Bit 6 is set during a transfer?
407	400	break;
408		//   default:
409		//      logerror("Unknown 80186 peripheral read offset %04x mask %04x returning %04x\n",offset,mem_mask,ret);
	401	default:
	402	logerror("(PC=%06x) Unknown 80186 peripheral read offset %04x mask %04x returning %04x\n",m_maincpu->device_t::safe_pc(),offset,mem_mask,ret);
410	403	}
411	404	return ret;
412	405	}
r243579	r243580
419	412	WRITE16_MEMBER(ngen_state::xbus_w)
420	413	{
421	414	UINT16 addr = (data & 0x00ff) << 8;
422		cpu_device* cpu;
423
424		if(m_maincpu)
425		cpu = m_maincpu;
426		else
427		cpu = m_i386cpu;
428		address_space& io = cpu->device_t::memory().space(AS_IO);
	415	address_space& io = m_maincpu->device_t::memory().space(AS_IO);
429	416	switch(m_xbus_current)
430	417	{
431	418	case 0x00:  // Floppy/Hard disk module
432	419	io.install_readwrite_handler(addr,addr+0xff,0,0,read16_delegate(FUNC(ngen_state::fhd_r),this),write16_delegate(FUNC(ngen_state::hfd_w),this));
433	420	break;
434	421	default:
435		cpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);  // reached end of the modules
	422	m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);  // reached end of the modules
436	423	break;
437	424	}
438	425	if(addr != 0)
r243579	r243580
455	442	ret = 0x1070;  // Floppy/Hard disk module
456	443	break;
457	444	default:
458		if(m_maincpu)
459		m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);  // reached the end of the modules
460		else
461		m_i386cpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);
	445	m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);  // reached the end of the modules
462	446	ret = 0x0080;
463	447	break;
464	448	}
r243579	r243580
474	458	case 0x00:
475	459	case 0x01:
476	460	case 0x02:
477		if(mem_mask & 0x00ff)
478		m_fdc->write(space,offset,data & 0xff);
479		break;
480	461	case 0x03:
481	462	if(mem_mask & 0x00ff)
482		{
483	463	m_fdc->write(space,offset,data & 0xff);
484		m_fdc_timer->write_clk0(1);
485		m_fdc_timer->write_clk0(0);  // Data register access clocks the FDC's PIT channel 0
486		}
487	464	break;
488	465	case 0x04:
489	466	if(mem_mask & 0x00ff)
490		fdc_control_w(space,0,data & 0xff);
	467	fdc_control_w(space,offset,data & 0xff);
491	468	break;
492	469	case 0x05:
493	470	if(mem_mask & 0x00ff)
494		hdc_control_w(space,0,data & 0xff);
	471	hdc_control_w(space,offset,data & 0xff);
495	472	break;
496	473	case 0x07:
497	474	if(mem_mask & 0x00ff)
498		disk_addr_ext(space,0,data & 0xff);
	475	disk_addr_ext(space,offset,data & 0xff);
499	476	break;
500	477	case 0x08:
501	478	case 0x09:
r243579	r243580
535	512	case 0x00:
536	513	case 0x01:
537	514	case 0x02:
538		if(mem_mask & 0x00ff)
539		ret = m_fdc->read(space,offset);
540		break;
541	515	case 0x03:
542	516	if(mem_mask & 0x00ff)
543		{
544	517	ret = m_fdc->read(space,offset);
545		m_fdc_timer->write_clk0(1);
546		m_fdc_timer->write_clk0(0);  // Data register access clocks the FDC's PIT channel 0
547		}
548	518	break;
549	519	case 0x08:
550	520	case 0x09:
r243579	r243580
640	610
641	611	WRITE_LINE_MEMBER( ngen_state::dma_hrq_changed )
642	612	{
643		if(m_maincpu)
644		m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
645		else
646		m_i386cpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
	613	m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
647	614	}
648	615
649	616	WRITE_LINE_MEMBER( ngen_state::dma_eop_changed )
r243579	r243580
698	665
699	666	READ8_MEMBER(ngen_state::dma_read_word)
700	667	{
701		cpu_device* cpu;
	668	address_space& prog_space = m_maincpu->space(AS_PROGRAM); // get the right address space
702	669	UINT16 result;
703
704		if(m_maincpu)
705		cpu = m_maincpu;
706		else
707		cpu = m_i386cpu;
708		address_space& prog_space = cpu->space(AS_PROGRAM); // get the right address space
709
710	670	if(m_dma_channel == -1)
711	671	return 0xff;
712	672	offs_t page_offset = (((offs_t) m_dma_offset[m_dma_channel]) << 16) & 0xFE0000;
r243579	r243580
720	680
721	681	WRITE8_MEMBER(ngen_state::dma_write_word)
722	682	{
723		cpu_device* cpu;
724
725		if(m_maincpu)
726		cpu = m_maincpu;
727		else
728		cpu = m_i386cpu;
729		address_space& prog_space = cpu->space(AS_PROGRAM); // get the right address space
730
	683	address_space& prog_space = m_maincpu->space(AS_PROGRAM); // get the right address space
731	684	if(m_dma_channel == -1)
732	685	return;
733	686	offs_t page_offset = (((offs_t) m_dma_offset[m_dma_channel]) << 16) & 0xFE0000;
r243579	r243580
774	727	m_fd0->get_device()->set_rpm(300);
775	728	}
776	729
777		// boot ROMs from modules are not mapped anywhere, instead, they have to send the code from the boot ROM via DMA
778	730	static ADDRESS_MAP_START( ngen_mem, AS_PROGRAM, 16, ngen_state )
779	731	AM_RANGE(0x00000, 0xf7fff) AM_RAM
780	732	AM_RANGE(0xf8000, 0xf9fff) AM_RAM AM_SHARE("vram")
781	733	AM_RANGE(0xfa000, 0xfbfff) AM_RAM AM_SHARE("fontram")
782		AM_RANGE(0xfc000, 0xfcfff) AM_RAM
	734	AM_RANGE(0xfc000, 0xfcfff) AM_ROM AM_REGION("disk",0)
783	735	AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("bios",0)
784	736	ADDRESS_MAP_END
785	737
r243579	r243580
799	751
800	752	static ADDRESS_MAP_START( ngen386_mem, AS_PROGRAM, 32, ngen_state )
801	753	AM_RANGE(0x00000000, 0x000fdfff) AM_RAM
802		AM_RANGE(0x000f8000, 0x000f9fff) AM_RAM AM_SHARE("vram")
803		AM_RANGE(0x000fa000, 0x000fbfff) AM_RAM AM_SHARE("fontram")
804		AM_RANGE(0x000fc000, 0x000fcfff) AM_RAM
805	754	AM_RANGE(0x000fe000, 0x000fffff) AM_ROM AM_REGION("bios",0)
806	755	AM_RANGE(0xffffe000, 0xffffffff) AM_ROM AM_REGION("bios",0)
807	756	ADDRESS_MAP_END
808	757
809	758	static ADDRESS_MAP_START( ngen386i_mem, AS_PROGRAM, 32, ngen_state )
810	759	AM_RANGE(0x00000000, 0x000fbfff) AM_RAM
811		AM_RANGE(0x000f8000, 0x000f9fff) AM_RAM AM_SHARE("vram")
812		AM_RANGE(0x000fa000, 0x000fbfff) AM_RAM AM_SHARE("fontram")
813	760	AM_RANGE(0x000fc000, 0x000fffff) AM_ROM AM_REGION("bios",0)
814	761	AM_RANGE(0xffffc000, 0xffffffff) AM_ROM AM_REGION("bios",0)
815	762	ADDRESS_MAP_END
816	763
817	764	static ADDRESS_MAP_START( ngen386_io, AS_IO, 32, ngen_state )
818		AM_RANGE(0x0000, 0x0003) AM_READWRITE16(xbus_r, xbus_w, 0x0000ffff)
819		AM_RANGE(0xf800, 0xfeff) AM_READWRITE16(peripheral_r, peripheral_w,0xffffffff)
	765	AM_RANGE(0xfd0c, 0xfd0f) AM_DEVREADWRITE8("pic",pic8259_device,read,write,0xffffffff)
820	766	ADDRESS_MAP_END
821	767
822	768	static INPUT_PORTS_START( ngen )
r243579	r243580
836	782	MCFG_CPU_PROGRAM_MAP(ngen_mem)
837	783	MCFG_CPU_IO_MAP(ngen_io)
838	784	MCFG_80186_CHIP_SELECT_CB(WRITE16(ngen_state, cpu_peripheral_cb))
839		MCFG_80186_TMROUT0_HANDLER(WRITELINE(ngen_state, cpu_timer_w))
	785	MCFG_80186_TMROUT1_HANDLER(WRITELINE(ngen_state, cpu_timer_w))
840	786	MCFG_80186_IRQ_SLAVE_ACK(READ8(ngen_state, irq_cb))
841	787
842	788	MCFG_PIC8259_ADD( "pic", DEVWRITELINE("maincpu",i80186_cpu_device,int0_w), VCC, NULL )
r243579	r243580
905	851
906	852	// keyboard UART (patent says i8251 is used for keyboard communications, it is located on the video board)
907	853	MCFG_DEVICE_ADD("videouart", I8251, 0)  // main clock unknown, Rx/Tx clocks are 19.53kHz
908		//   MCFG_I8251_TXEMPTY_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w))
	854	//  MCFG_I8251_TXEMPTY_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w))
909	855	MCFG_I8251_TXD_HANDLER(DEVWRITELINE("keyboard", rs232_port_device, write_txd))
910	856	MCFG_RS232_PORT_ADD("keyboard", keyboard, "ngen")
911	857	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("videouart", i8251_device, write_rxd))
r243579	r243580
919	865	MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu",i80186_cpu_device,drq1_w))
920	866	MCFG_WD_FDC_FORCE_READY
921	867	MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0)
922		MCFG_PIT8253_CLK0(0)
923		MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w))  // clocked on FDC data register access
	868	MCFG_PIT8253_CLK0(XTAL_20MHz / 20)
	869	MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))  // clocked on FDC data register access
924	870	MCFG_PIT8253_CLK1(XTAL_20MHz / 20)
925		//   MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w))  // 1MHz
926		MCFG_PIT8253_CLK2(XTAL_20MHz / 20)
927		//   MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w))
928
	871	MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))  // 1MHz
	872	MCFG_PIT8253_CLK2(XTAL_20MHz / 10)
	873	MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))
929	874	// TODO: WD1010 HDC (not implemented), use WD2010 for now
930	875	MCFG_DEVICE_ADD("hdc", WD2010, XTAL_20MHz / 4)
931		MCFG_WD2010_OUT_INTRQ_CB(DEVWRITELINE("pic",pic8259_device,ir2_w))
932	876	MCFG_WD2010_IN_BCS_CB(READ8(ngen_state,hd_buffer_r))
933	877	MCFG_WD2010_OUT_BCS_CB(WRITE8(ngen_state,hd_buffer_w))
934	878	MCFG_WD2010_IN_DRDY_CB(VCC)
r243579	r243580
944	888	MACHINE_CONFIG_END
945	889
946	890	static MACHINE_CONFIG_START( ngen386, ngen386_state )
947		MCFG_CPU_ADD("i386cpu", I386, XTAL_50MHz / 2)
	891	MCFG_CPU_ADD("maincpu", I386, XTAL_50MHz / 2)
948	892	MCFG_CPU_PROGRAM_MAP(ngen386_mem)
949	893	MCFG_CPU_IO_MAP(ngen386_io)
950		MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic", pic8259_device, inta_cb)
951
952		MCFG_PIC8259_ADD( "pic", INPUTLINE("i386cpu",0), VCC, NULL )
953
954		MCFG_DEVICE_ADD("pit", PIT8254, 0)
955		MCFG_PIT8253_CLK0(78120/4)  // 19.53kHz, /4 of the CPU timer output?
956		MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out0_w))  // RS232 channel B baud rate
957		MCFG_PIT8253_CLK1(XTAL_14_7456MHz/12)  // correct? - based on patent
958		MCFG_PIT8253_OUT1_HANDLER(WRITELINE(ngen_state, pit_out1_w))  // RS232 channel A baud rate
959		MCFG_PIT8253_CLK2(XTAL_14_7456MHz/12)
960		MCFG_PIT8253_OUT2_HANDLER(WRITELINE(ngen_state, pit_out2_w))
961
962		MCFG_DEVICE_ADD("dmac", AM9517A, XTAL_14_7456MHz / 3)  // NEC D8237A, divisor unknown
963		MCFG_I8237_OUT_HREQ_CB(WRITELINE(ngen_state, dma_hrq_changed))
964		MCFG_I8237_OUT_EOP_CB(WRITELINE(ngen_state, dma_eop_changed))
965		MCFG_I8237_IN_MEMR_CB(READ8(ngen_state, dma_read_word))  // DMA is always 16-bit
966		MCFG_I8237_OUT_MEMW_CB(WRITE8(ngen_state, dma_write_word))
967		MCFG_I8237_OUT_DACK_0_CB(WRITELINE(ngen_state, dack0_w))
968		MCFG_I8237_OUT_DACK_1_CB(WRITELINE(ngen_state, dack1_w))
969		MCFG_I8237_OUT_DACK_2_CB(WRITELINE(ngen_state, dack2_w))
970		MCFG_I8237_OUT_DACK_3_CB(WRITELINE(ngen_state, dack3_w))
971		MCFG_I8237_IN_IOR_0_CB(READ8(ngen_state, dma_0_dack_r))
972		MCFG_I8237_IN_IOR_1_CB(READ8(ngen_state, dma_1_dack_r))
973		MCFG_I8237_IN_IOR_2_CB(READ8(ngen_state, dma_2_dack_r))
974		MCFG_I8237_IN_IOR_3_CB(READ8(ngen_state, dma_3_dack_r))
975		MCFG_I8237_OUT_IOW_0_CB(WRITE8(ngen_state, dma_0_dack_w))
976		MCFG_I8237_OUT_IOW_1_CB(WRITE8(ngen_state, dma_1_dack_w))
977		MCFG_I8237_OUT_IOW_2_CB(WRITE8(ngen_state, dma_2_dack_w))
978		MCFG_I8237_OUT_IOW_3_CB(WRITE8(ngen_state, dma_3_dack_w))
979
980		// I/O board
981		MCFG_UPD7201_ADD("iouart",0,0,0,0,0) // clocked by PIT channel 2?
982		MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd))
983		MCFG_Z80DART_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd))
984		MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_dtr))
985		MCFG_Z80DART_OUT_DTRB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_dtr))
986		MCFG_Z80DART_OUT_RTSA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_rts))
987		MCFG_Z80DART_OUT_RTSB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_rts))
988
989		MCFG_RS232_PORT_ADD("rs232_a", default_rs232_devices, NULL)
990		MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_device, rxa_w))
991		MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_device, ctsa_w))
992		MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcda_w))
993		MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, ria_w))
994
995		MCFG_RS232_PORT_ADD("rs232_b", default_rs232_devices, NULL)
996		MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_device, rxb_w))
997		MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_device, ctsb_w))
998		MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcdb_w))
999		MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, rib_w))
1000
1001		// TODO: SCN2652 MPCC (not implemented), used for RS-422 cluster communications?
1002
1003		// video board
1004		MCFG_SCREEN_ADD("screen", RASTER)
1005		MCFG_SCREEN_SIZE(720,348)
1006		MCFG_SCREEN_VISIBLE_AREA(0,719,0,347)
1007		MCFG_SCREEN_REFRESH_RATE(60)
1008		MCFG_SCREEN_UPDATE_DEVICE("crtc",mc6845_device, screen_update)
1009
1010		MCFG_MC6845_ADD("crtc", MC6845, NULL, 19980000 / 9)  // divisor unknown -- /9 gives 60Hz output, so likely correct
1011		MCFG_MC6845_SHOW_BORDER_AREA(false)
1012		MCFG_MC6845_CHAR_WIDTH(9)
1013		MCFG_MC6845_UPDATE_ROW_CB(ngen_state, crtc_update_row)
1014		MCFG_VIDEO_SET_SCREEN("screen")
1015
1016		// keyboard UART (patent says i8251 is used for keyboard communications, it is located on the video board)
1017		MCFG_DEVICE_ADD("videouart", I8251, 0)  // main clock unknown, Rx/Tx clocks are 19.53kHz
1018		//   MCFG_I8251_TXEMPTY_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w))
1019		MCFG_I8251_TXD_HANDLER(DEVWRITELINE("keyboard", rs232_port_device, write_txd))
1020		MCFG_RS232_PORT_ADD("keyboard", keyboard, "ngen")
1021		MCFG_RS232_RXD_HANDLER(DEVWRITELINE("videouart", i8251_device, write_rxd))
1022
1023		MCFG_DEVICE_ADD("refresh_clock", CLOCK, 19200*16)  // should be 19530Hz
1024		MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(ngen_state,timer_clk_out))
1025
1026		// floppy disk / hard disk module (WD2797 FDC, WD1010 HDC, plus an 8253 timer for each)
1027		MCFG_WD2797x_ADD("fdc", XTAL_20MHz / 20)
1028		MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(ngen_state,fdc_irq_w))
1029		//   MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("i386cpu",i80186_cpu_device,drq1_w))
1030		MCFG_WD_FDC_FORCE_READY
1031		MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0)
1032		MCFG_PIT8253_CLK0(0)
1033		MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w))  // clocked on FDC data register access
1034		MCFG_PIT8253_CLK1(XTAL_20MHz / 20)
1035		//   MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w))  // 1MHz
1036		MCFG_PIT8253_CLK2(XTAL_20MHz / 20)
1037		//   MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir5_w))
1038
1039		// TODO: WD1010 HDC (not implemented), use WD2010 for now
1040		MCFG_DEVICE_ADD("hdc", WD2010, XTAL_20MHz / 4)
1041		MCFG_WD2010_OUT_INTRQ_CB(DEVWRITELINE("pic",pic8259_device,ir2_w))
1042		MCFG_WD2010_IN_BCS_CB(READ8(ngen_state,hd_buffer_r))
1043		MCFG_WD2010_OUT_BCS_CB(WRITE8(ngen_state,hd_buffer_w))
1044		MCFG_WD2010_IN_DRDY_CB(VCC)
1045		MCFG_WD2010_IN_INDEX_CB(VCC)
1046		MCFG_WD2010_IN_WF_CB(VCC)
1047		MCFG_WD2010_IN_TK000_CB(VCC)
1048		MCFG_WD2010_IN_SC_CB(VCC)
1049		MCFG_DEVICE_ADD("hdc_timer", PIT8253, 0)
1050		MCFG_PIT8253_CLK2(XTAL_20MHz / 10)  // 2MHz
1051		MCFG_FLOPPY_DRIVE_ADD("fdc:0", ngen_floppies, "525qd", floppy_image_device::default_floppy_formats)
1052		MCFG_HARDDISK_ADD("hard0")
	894	MCFG_PIC8259_ADD( "pic", INPUTLINE("maincpu", 0), VCC, NULL )
1053	895	MACHINE_CONFIG_END
1054	896
1055	897	static MACHINE_CONFIG_DERIVED( 386i, ngen386 )
1056		MCFG_CPU_MODIFY("i386cpu")
	898	MCFG_CPU_MODIFY("maincpu")
1057	899	MCFG_CPU_PROGRAM_MAP(ngen386i_mem)
1058	900	MACHINE_CONFIG_END
1059	901

trunk/src/mess/drivers/pcd.c

r243579	r243580
20	20	#include "machine/mc146818.h"
21	21	#include "sound/speaker.h"
22	22	#include "video/scn2674.h"
23		#include "formats/pc_dsk.h"
24	23
25	24	//**************************************************************************
26	25	//  TYPE DEFINITIONS
r243579	r243580
39	38	m_fdc(*this, "fdc"),
40	39	m_rtc(*this, "rtc"),
41	40	m_crtc(*this, "crtc"),
42		m_palette(*this, "palette"),
43		m_gfxdecode(*this, "gfxdecode"),
44	41	m_vram(*this, "vram"),
45	42	m_charram(8*1024)
46	43	{ }
r243579	r243580
49	46	TIMER_DEVICE_CALLBACK_MEMBER( timer0_tick );
50	47	DECLARE_WRITE_LINE_MEMBER( i186_timer1_w );
51	48
52		DECLARE_READ8_MEMBER( nmi_io_r );
53		DECLARE_WRITE8_MEMBER( nmi_io_w );
	49	DECLARE_READ8_MEMBER( charram_r );
	50	DECLARE_WRITE8_MEMBER( charram_w );
	51	DECLARE_READ16_MEMBER( nmi_io_r );
	52	DECLARE_WRITE16_MEMBER( nmi_io_w );
54	53	DECLARE_READ8_MEMBER( rtc_r );
55	54	DECLARE_WRITE8_MEMBER( rtc_w );
56	55	DECLARE_READ8_MEMBER( stat_r );
57	56	DECLARE_WRITE8_MEMBER( stat_w );
58	57	DECLARE_READ8_MEMBER( led_r );
59	58	DECLARE_WRITE8_MEMBER( led_w );
60		DECLARE_READ8_MEMBER( detect_r );
61		DECLARE_WRITE8_MEMBER( detect_w );
62		DECLARE_READ8_MEMBER( dskctl_r );
63		DECLARE_WRITE8_MEMBER( dskctl_w );
64		DECLARE_READ8_MEMBER( mcu_r );
65		DECLARE_WRITE8_MEMBER( mcu_w );
66		DECLARE_WRITE8_MEMBER( vram_sw_w );
67		DECLARE_READ16_MEMBER( vram_r );
68		DECLARE_WRITE16_MEMBER( vram_w );
69		SCN2674_DRAW_CHARACTER_MEMBER(display_pixels);
70		DECLARE_FLOPPY_FORMATS( floppy_formats );
	59	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
71	60
72	61	protected:
73	62	// driver_device overrides
r243579	r243580
83	72	required_device<wd2793_t> m_fdc;
84	73	required_device<mc146818_device> m_rtc;
85	74	required_device<scn2674_device> m_crtc;
86		required_device<palette_device> m_palette;
87		required_device<gfxdecode_device> m_gfxdecode;
88	75	required_shared_ptr<UINT16> m_vram;
89	76	dynamic_buffer m_charram;
90		UINT8 m_stat, m_led, m_dskctl, m_vram_sw;
	77	UINT8 m_stat, m_led;
91	78	};
92	79
93	80
r243579	r243580
109	96	};
110	97	void pcd_state::machine_start()
111	98	{
112		m_gfxdecode->set_gfx(0, global_alloc(gfx_element(machine().device<palette_device>("palette"), pcd_charlayout, m_charram, 0, 1, 0)));
	99	machine().device<gfxdecode_device>("gfxdecode")->set_gfx(0, global_alloc(gfx_element(machine().device<palette_device>("palette"), pcd_charlayout, m_charram, 0, 2, 0)));
113	100	}
114	101
115	102	void pcd_state::machine_reset()
116	103	{
117	104	m_stat = 0;
118	105	m_led = 0;
119		m_dskctl = 0;
120		m_vram_sw = 1;
121	106	}
122	107
123	108	READ8_MEMBER( pcd_state::irq_callback )
r243579	r243580
136	121	m_speaker->level_w(state);
137	122	}
138	123
139		READ16_MEMBER( pcd_state::vram_r )
	124	READ8_MEMBER( pcd_state::charram_r )
140	125	{
141		return m_vram[offset];
	126	return m_charram[offset >> 1];
142	127	}
143	128
144		WRITE16_MEMBER( pcd_state::vram_w )
	129	WRITE8_MEMBER( pcd_state::charram_w )
145	130	{
146		if(m_vram_sw)
147		COMBINE_DATA(&m_vram[offset]);
148		else if(mem_mask & 0xff)
149		{
150		m_charram[offset & 0x1fff] = data;
151		m_gfxdecode->gfx(0)->mark_dirty(offset/16);
152		}
	131	m_charram[offset >> 1] = data;
153	132	}
154	133
155		WRITE8_MEMBER( pcd_state::vram_sw_w )
	134	READ16_MEMBER( pcd_state::nmi_io_r )
156	135	{
157		m_vram_sw = data & 1;
158		}
159
160		READ8_MEMBER( pcd_state::nmi_io_r )
161		{
162	136	if(space.debugger_access())
163	137	return 0;
164		logerror("%s: unmapped %s %04x\n", machine().describe_context(), space.name(), offset);
	138	logerror("%s: unmapped %s %04x\n", machine().describe_context(), space.name(), offset << 1);
165	139	m_stat |= 8;
166	140	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
167	141	return 0;
168	142	}
169	143
170		WRITE8_MEMBER( pcd_state::nmi_io_w )
	144	WRITE16_MEMBER( pcd_state::nmi_io_w )
171	145	{
172	146	if(space.debugger_access())
173	147	return;
174		logerror("%s: unmapped %s %04x\n", machine().describe_context(), space.name(), offset);
	148	logerror("%s: unmapped %s %04x\n", machine().describe_context(), space.name(), offset << 1);
175	149	m_stat |= 8;
176	150	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
177	151	}
r243579	r243580
195	169
196	170	WRITE8_MEMBER( pcd_state::stat_w )
197	171	{
198		m_stat &= ~data;
	172	m_stat = data;
199	173	}
200	174
201		READ8_MEMBER( pcd_state::detect_r )
202		{
203		return 0;
204		}
205
206		WRITE8_MEMBER( pcd_state::detect_w )
207		{
208		}
209
210		READ8_MEMBER( pcd_state::mcu_r )
211		{
212		return 0x20;
213		}
214
215		WRITE8_MEMBER( pcd_state::mcu_w )
216		{
217		}
218
219		READ8_MEMBER( pcd_state::dskctl_r )
220		{
221		return m_dskctl;
222		}
223
224		WRITE8_MEMBER( pcd_state::dskctl_w )
225		{
226		floppy_image_device *floppy0 = m_fdc->subdevice<floppy_connector>("0")->get_device();
227		floppy_image_device *floppy1 = m_fdc->subdevice<floppy_connector>("1")->get_device();
228
229		if((data & 1) && floppy0)
230		m_fdc->set_floppy(floppy0);
231
232		if(floppy0)
233		{
234		floppy0->mon_w(!(data & 4));
235		floppy0->ss_w((data & 8) != 0);
236		}
237		if(floppy1)
238		{
239		floppy1->mon_w(!(data & 4));
240		floppy1->ss_w((data & 8) != 0);
241		}
242		m_dskctl = data;
243		}
244
245	175	READ8_MEMBER( pcd_state::led_r )
246	176	{
247		// DIPs?
248		// 0x01 no mmu
249		// 0x10 enter monitor after post
250		// 0x20 enter monitor before post
251		return 0x01;
	177	return m_led;
252	178	}
253	179
254	180	WRITE8_MEMBER( pcd_state::led_w )
r243579	r243580
259	185	m_led = data;
260	186	}
261	187
262		SCN2674_DRAW_CHARACTER_MEMBER(pcd_state::display_pixels)
	188	UINT32 pcd_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
263	189	{
264		if(lg)
265		{
266		UINT16 data = m_vram[address];
267		data = (data >> 8) | (data << 8);
268		for(int i = 0; i < 16; i++)
269		bitmap.pix32(y, x + i) = m_palette->pen((data & (1 << (16 - i))) ? 1 : 0);
270		}
271		else
272		{
273		UINT8 data = m_charram[(m_vram[address] & 0xff) * 16 + linecount];
274		for(int i = 0; i < 8; i++)
275		bitmap.pix32(y, x + i) = m_palette->pen((data & (1 << (8 - i))) ? 1 : 0);
276		}
	190	//bitmap.fill(0, cliprect);
	191	m_crtc->scn2574_draw(machine(), bitmap, cliprect, m_vram);
	192	return 0;
277	193	}
278	194
279	195	//**************************************************************************
r243579	r243580
282	198
283	199	static ADDRESS_MAP_START( pcd_map, AS_PROGRAM, 16, pcd_state )
284	200	AM_RANGE(0x00000, 0x3ffff) AM_RAM // fixed 256k for now
285		AM_RANGE(0xf0000, 0xf7fff) AM_READWRITE(vram_r, vram_w) AM_SHARE("vram")
	201	AM_RANGE(0xf0000, 0xf7fff) AM_RAM AM_SHARE("vram")
	202	//AM_RANGE(0xf7000, 0xfbfff) AM_READWRITE8(charram_r, charram_w, 0xffff)
286	203	AM_RANGE(0xfc000, 0xfffff) AM_ROM AM_REGION("bios", 0)
287		AM_RANGE(0x00000, 0xfffff) AM_READWRITE8(nmi_io_r, nmi_io_w, 0xffff)
	204	AM_RANGE(0x00000, 0xfffff) AM_READWRITE(nmi_io_r, nmi_io_w)
288	205	ADDRESS_MAP_END
289	206
290	207	static ADDRESS_MAP_START( pcd_io, AS_IO, 16, pcd_state )
291	208	ADDRESS_MAP_UNMAP_HIGH
292		AM_RANGE(0x0000, 0xefff) AM_READWRITE8(nmi_io_r, nmi_io_w, 0xffff)
293	209	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_SHARE("nvram")
294	210	AM_RANGE(0xf800, 0xf801) AM_DEVREADWRITE8("pic1", pic8259_device, read, write, 0xffff)
295	211	AM_RANGE(0xf820, 0xf821) AM_DEVREADWRITE8("pic2", pic8259_device, read, write, 0xffff)
296	212	AM_RANGE(0xf840, 0xf841) AM_READWRITE8(stat_r, stat_w, 0x00ff)
297	213	AM_RANGE(0xf840, 0xf841) AM_READWRITE8(led_r, led_w, 0xff00)
298	214	AM_RANGE(0xf880, 0xf8bf) AM_READWRITE8(rtc_r, rtc_w, 0xffff)
299		AM_RANGE(0xf900, 0xf903) AM_DEVREADWRITE8("fdc", wd2793_t, read, write, 0xffff)
300		AM_RANGE(0xf904, 0xf905) AM_READWRITE8(dskctl_r, dskctl_w, 0x00ff)
	215	AM_RANGE(0xf900, 0xf907) AM_DEVREADWRITE8("fdc", wd2793_t, read, write, 0xffff)
301	216	//AM_RANGE(0xf940, 0xf943) scsi
302		AM_RANGE(0xf980, 0xf98f) AM_DEVWRITE8("crtc", scn2674_device, write, 0x00ff)
303		AM_RANGE(0xf980, 0xf98f) AM_DEVREAD8("crtc", scn2674_device, read, 0xff00)
304		AM_RANGE(0xf9a0, 0xf9a1) AM_WRITE8(vram_sw_w, 0x00ff)
305		AM_RANGE(0xf9b0, 0xf9b3) AM_READWRITE8(mcu_r, mcu_w, 0x00ff) // 8741 comms
306	217	AM_RANGE(0xf9c0, 0xf9c3) AM_DEVREADWRITE8("usart1",mc2661_device,read,write,0xffff)  // UARTs
307	218	AM_RANGE(0xf9d0, 0xf9d3) AM_DEVREADWRITE8("usart2",mc2661_device,read,write,0xffff)
308	219	AM_RANGE(0xf9e0, 0xf9e3) AM_DEVREADWRITE8("usart3",mc2661_device,read,write,0xffff)
	220	AM_RANGE(0xf980, 0xf987) AM_DEVWRITE8("crtc", scn2674_device, mpu4_vid_scn2674_w, 0x00ff)
	221	AM_RANGE(0xf980, 0xf987) AM_DEVREAD8("crtc", scn2674_device, mpu4_vid_scn2674_r, 0xff00)
309	222	//   AM_RANGE(0xfa00, 0xfa7f) // pcs4-n (peripheral chip select)
310		AM_RANGE(0xfb00, 0xfb01) AM_READWRITE8(detect_r, detect_w, 0xff00) // expansion card detection?
311		AM_RANGE(0xfb00, 0xffff) AM_READWRITE8(nmi_io_r, nmi_io_w, 0xffff)
	223	AM_RANGE(0x0000, 0xffff) AM_READWRITE(nmi_io_r, nmi_io_w)
312	224	ADDRESS_MAP_END
313	225
314	226
r243579	r243580
319	231	static SLOT_INTERFACE_START( pcd_floppies )
320	232	SLOT_INTERFACE("55f", TEAC_FD_55F)
321	233	SLOT_INTERFACE("55g", TEAC_FD_55G)
322		SLOT_INTERFACE("525dsqd", FLOPPY_525_QD) // the devices above cause a crash in floppy_image_format_t::generate_track_from_levels
323	234	SLOT_INTERFACE_END
324	235
325		FLOPPY_FORMATS_MEMBER( pcd_state::floppy_formats )
326		FLOPPY_PC_FORMAT
327		FLOPPY_FORMATS_END
328
329	236	static MACHINE_CONFIG_START( pcd, pcd_state )
330	237	MCFG_CPU_ADD("maincpu", I80186, XTAL_16MHz)
331	238	MCFG_CPU_PROGRAM_MAP(pcd_map)
r243579	r243580
351	258	MCFG_OMTI5100_ADD("sasi")
352	259
353	260	// floppy disk controller
354		MCFG_WD2793x_ADD("fdc", XTAL_16MHz/8/2)
	261	MCFG_WD2793x_ADD("fdc", XTAL_16MHz/8)
355	262	MCFG_WD_FDC_INTRQ_CALLBACK(DEVWRITELINE("pic1", pic8259_device, ir6_w))
356	263	MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu", i80186_cpu_device, drq1_w))
357	264
358	265	// floppy drives
359		MCFG_FLOPPY_DRIVE_ADD("fdc:0", pcd_floppies, "525dsqd", pcd_state::floppy_formats)
360		MCFG_FLOPPY_DRIVE_ADD("fdc:1", pcd_floppies, "525dsqd", pcd_state::floppy_formats)
	266	MCFG_FLOPPY_DRIVE_ADD("fdc:0", pcd_floppies, "55g", floppy_image_device::default_floppy_formats)
	267	MCFG_FLOPPY_DRIVE_ADD("fdc:1", pcd_floppies, "55g", floppy_image_device::default_floppy_formats)
361	268
362	269	// usart
363	270	MCFG_DEVICE_ADD("usart1", MC2661, XTAL_4_9152MHz)
r243579	r243580
377	284	MCFG_SCREEN_SIZE(640, 350)
378	285	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 349)
379	286	MCFG_SCREEN_REFRESH_RATE(50)
380		MCFG_SCREEN_UPDATE_DEVICE("crtc", scn2674_device, screen_update)
	287	MCFG_SCREEN_UPDATE_DRIVER(pcd_state, screen_update)
381	288
382	289	MCFG_GFXDECODE_ADD("gfxdecode", "palette", empty)
383	290	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
384	291
385	292	MCFG_SCN2674_VIDEO_ADD("crtc", 0, NULL);
386		MCFG_SCN2674_TEXT_CHARACTER_WIDTH(8)
387		MCFG_SCN2674_GFX_CHARACTER_WIDTH(16)
388		MCFG_SCN2674_DRAW_CHARACTER_CALLBACK_OWNER(pcd_state, display_pixels)
	293	MCFG_SCN2674_GFXDECODE("gfxdecode")
	294	MCFG_SCN2674_PALETTE("palette")
389	295
390	296	// rtc
391	297	MCFG_MC146818_ADD("rtc", XTAL_32_768kHz)
r243579	r243580
403	309	ROM_LOAD16_BYTE("s26361-d359.d43", 0x0000, 0x2000, CRC(e03db2ec) SHA1(fcae8b0c9e7543706817b0a53872826633361fda))
404	310	ROM_FILL(0xb64, 1, 0xe2)  // post expects 0xd0 fdc command to be instant, give it a delay
405	311	ROM_FILL(0xb65, 1, 0xfe)
406		ROM_FILL(0xb35, 1, 0x90)  // fdc delay_register_commit is too long
407		ROM_FILL(0xb36, 1, 0x90)
408		ROM_FILL(0x3ffe, 1, 0xf4)  // fix csum
409		ROM_FILL(0x3fff, 1, 0x3d)
	312	ROM_FILL(0x3ffe, 1, 0xb4)  // fix csum
	313	ROM_FILL(0x3fff, 1, 0x22)
410	314
411	315	// gfx card (scn2674 with 8741), to be moved
412	316	ROM_REGION(0x400, "graphics", 0)

trunk/src/mess/drivers/tmtennis.c

r243579	r243580
16	16
17	17	NOTE!: MESS external artwork is required to be able to play
18	18
19
20		TODO:
21		- display should go off when sound is played, needs decay simulation?
22
23	19	***************************************************************************/
24	20
25	21	#include "emu.h"

trunk/src/mess/drivers/wildfire.c

r243579	r243580
13	13
14	14
15	15	TODO:
16		- bad sound (probably MCU related)
17		- when the game strobes a led faster, it should appear brighter, for example when
18		the ball hits one of the bumpers
	16	- no sound
	17	- flipper buttons aren't working correctly
19	18	- some 7segs digits are wrong (mcu on-die decoder is customizable?)
20	19	- MCU clock is unknown
21	20
r243579	r243580
51	50	UINT16 m_display_cache[0x10];
52	51	UINT8 m_display_decay[0x100];
53	52
	53	DECLARE_READ8_MEMBER(read_k);
54	54	DECLARE_WRITE8_MEMBER(write_d);
55	55	DECLARE_WRITE16_MEMBER(write_a);
56	56
r243579	r243580
83	83
84	84	// lamp translation table: Lzz from patent US4334679 FIG.4 = MESS lampxxy,
85	85	// where xx is led column and y is led row, eg. lamp103 is output A10 D3
86		// (note: 2 mistakes in the patent: the L19 between L12 and L14 should be L13, and L84 should of course be L48)
87	86	/*
88	87	L0  = -         L10 = lamp60    L20 = lamp41    L30 = lamp53    L40 = lamp57    L50 = lamp110
89	88	L1  = lamp107   L11 = lamp50    L21 = lamp42    L31 = lamp43    L41 = lamp66    L51 = lamp111
r243579	r243580
154	153
155	154	***************************************************************************/
156	155
	156	READ8_MEMBER(wildfire_state::read_k)
	157	{
	158	// ?
	159	return 0xf;
	160	}
	161
157	162	WRITE8_MEMBER(wildfire_state::write_d)
158	163	{
159		// D0-D7: leds out
160	164	m_d = data;
161	165	display_update();
162	166	}
163	167
164	168	WRITE16_MEMBER(wildfire_state::write_a)
165	169	{
166		// A12: enable speaker out
167		// this is in combination with the MCU K4-pin, how?
168		m_speaker->level_w(data >> 12 & 1);
169
170		// A0-A2: select 7segleds
171		// A3-A11: select other leds
172	170	m_a = data;
173	171	display_update();
174	172	}
r243579	r243580
222	220	/* basic machine hardware */
223	221	MCFG_CPU_ADD("maincpu", AMI_S2150, MASTER_CLOCK)
224	222	MCFG_AMI_S2000_READ_I_CB(IOPORT("IN1"))
	223	MCFG_AMI_S2000_READ_K_CB(READ8(wildfire_state, read_k))
225	224	MCFG_AMI_S2000_WRITE_D_CB(WRITE8(wildfire_state, write_d))
226	225	MCFG_AMI_S2000_WRITE_A_CB(WRITE16(wildfire_state, write_a))
227	226
r243579	r243580
252	251	ROM_END
253	252
254	253
255		CONS( 1979, wildfire, 0, 0, wildfire, wildfire, driver_device, 0, "Parker Brothers", "Wildfire (prototype)", GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
	254	CONS( 1979, wildfire, 0, 0, wildfire, wildfire, driver_device, 0, "Parker Brothers", "Wildfire (prototype)", GAME_NOT_WORKING | GAME_NO_SOUND | GAME_SUPPORTS_SAVE )

trunk/src/mess/machine/ngen_kb.c

r243579	r243580
17	17	// When setting an error code via the LEDs, 0xB0 then 0xAE is sent (presumably for error code 0xE0),
18	18	// so that means that 0xAx controls the Overtype, Lock, F1 and F2 LEDs, and 0xBx controls the F3, F8, F9 and F10 LEDs.
19	19	logerror("KB: received character %02x\n",data);
20		switch(data)
21		{
22		case 0x92:  // reset(?)
23		m_last_reset = true;
24		break;
25		}
26	20	}
27	21
28	22	UINT8 ngen_keyboard_device::row_number(UINT8 code)
r243579	r243580
43	37	int i;
44	38	UINT8 code = 0;
45	39	UINT8 key_code = 0;
46		UINT8 retVal = 0x00;
	40	UINT8 retVal = 0;
47	41	UINT8 shift = BIT(m_io_kbdc->read(), 1);
48	42	UINT8 caps  = BIT(m_io_kbdc->read(), 2);
49	43	UINT8 ctrl  = BIT(m_io_kbdc->read(), 0);
r243579	r243580
159	153	if (shift) key_code+=0x20;
160	154	}
161	155	m_keys_down = true;
162		m_last_reset = false;
163	156	retVal = key_code;
164	157	}
165	158	else
r243579	r243580
174	167	}
175	168	}
176	169	}
	170	// TODO: add scan code 0xc0 (all keys up)
177	171	return retVal;
178	172	}
179	173
r243579	r243580
217	211	{
218	212	serial_keyboard_device::device_reset();
219	213	m_keys_down = false;
220		m_last_reset = true;
221	214	}
222	215
223	216	void ngen_keyboard_device::rcv_complete()

trunk/src/mess/machine/ngen_kb.h

r243579	r243580
10	10	public:
11	11	ngen_keyboard_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
12	12	virtual ioport_constructor device_input_ports() const;
13		virtual DECLARE_WRITE_LINE_MEMBER( input_txd ) { device_serial_interface::rx_w(state); }
	13	virtual DECLARE_WRITE_LINE_MEMBER( input_txd ) {/* printf("TX: %i\n",state);*/ device_serial_interface::rx_w(state); }
14	14
15	15	protected:
16	16	virtual void device_start();
r243579	r243580
23	23	void write(UINT8 data);
24	24
25	25	bool m_keys_down;
26		bool m_last_reset;
27	26	};
28	27
29	28	extern const device_type NGEN_KEYBOARD;

trunk/src/mess/mess.mak

r243579	r243580
327	327	VIDEOS += V9938
328	328	VIDEOS += VIC4567
329	329	#VIDEOS += VOODOO
330		VIDEOS += SCN2674
331	330
332	331	#-------------------------------------------------
333	332	# specify available machine cores
r243579	r243580
941	940	$(MAME_VIDEO)/vectrex.o     \
942	941	$(MAME_DRIVERS)/cps1.o      \
943	942	$(MAME_VIDEO)/cps1.o        \
	943	$(MAME_VIDEO)/scn2674.o     \
944	944
945	945
946	946	#-------------------------------------------------

trunk/src/osd/sdl/sdl.mak

r243579	r243580
558	558	CCOMFLAGS += -DNO_SDL_GLEXT
559	559	# Remove libSDLmain, as its symbols conflict with SDLMain_tmpl.m
560	560	LIBS += `$(SDL_CONFIG) --libs | sed 's/-lSDLmain//'` -lpthread -framework Cocoa -framework OpenGL
	561	BASELIBS += `$(SDL_CONFIG) --libs | sed 's/-lSDLmain//'` -lpthread -framework Cocoa -framework OpenGL
561	562	DEFS += -DMACOSX_USE_LIBSDL
562	563	endif   # MACOSX_USE_LIBSDL
563	564

https://github.com/mamedev/mame/commit/320c41ceae3177bbb335dbb5759ada94ed66b7f4

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