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r35016 Saturday 14th February, 2015 at 07:27:47 UTC by Osso
exzisus.c: added save state support, removed trampolines (nw)
[src/mame/drivers]exzisus.c
[src/mame/includes]exzisus.h
[src/mame/video]exzisus.c

trunk/src/mame/drivers/exzisus.c
r243527r243528
4646
4747***************************************************************************/
4848
49WRITE8_MEMBER(exzisus_state::exzisus_cpua_bankswitch_w)
49WRITE8_MEMBER(exzisus_state::cpua_bankswitch_w)
5050{
51   UINT8 *RAM = memregion("cpua")->base();
52
5351   if ( (data & 0x0f) != m_cpua_bank )
5452   {
5553      m_cpua_bank = data & 0x0f;
5654      if (m_cpua_bank >= 2)
5755      {
58         membank("bank2")->set_base(&RAM[ 0x10000 + ( (m_cpua_bank - 2) * 0x4000 ) ] );
56         membank("bank2")->set_entry(m_cpua_bank - 2);
5957      }
6058   }
6159
6260   flip_screen_set(data & 0x40);
6361}
6462
65WRITE8_MEMBER(exzisus_state::exzisus_cpub_bankswitch_w)
63WRITE8_MEMBER(exzisus_state::cpub_bankswitch_w)
6664{
67   UINT8 *RAM = memregion("cpub")->base();
68
6965   if ( (data & 0x0f) != m_cpub_bank )
7066   {
7167      m_cpub_bank = data & 0x0f;
7268      if (m_cpub_bank >= 2)
7369      {
74         membank("bank1")->set_base(&RAM[ 0x10000 + ( (m_cpub_bank - 2) * 0x4000 ) ] );
70         membank("bank1")->set_entry(m_cpub_bank - 2);
7571      }
7672   }
7773
7874   flip_screen_set(data & 0x40);
7975}
8076
81WRITE8_MEMBER(exzisus_state::exzisus_coincounter_w)
77WRITE8_MEMBER(exzisus_state::coincounter_w)
8278{
8379   coin_lockout_w(machine(), 0,~data & 0x01);
8480   coin_lockout_w(machine(), 1,~data & 0x02);
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8682   coin_counter_w(machine(), 1,data & 0x08);
8783}
8884
89READ8_MEMBER(exzisus_state::exzisus_sharedram_ab_r)
90{
91   return m_sharedram_ab[offset];
92}
93
94READ8_MEMBER(exzisus_state::exzisus_sharedram_ac_r)
95{
96   return m_sharedram_ac[offset];
97}
98
99WRITE8_MEMBER(exzisus_state::exzisus_sharedram_ab_w)
100{
101   m_sharedram_ab[offset] = data;
102}
103
104WRITE8_MEMBER(exzisus_state::exzisus_sharedram_ac_w)
105{
106   m_sharedram_ac[offset] = data;
107}
108
10985// is it ok that cpub_reset refers to cpuc?
110WRITE8_MEMBER(exzisus_state::exzisus_cpub_reset_w)
86WRITE8_MEMBER(exzisus_state::cpub_reset_w)
11187{
11288   m_cpuc->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
11389}
11490
11591#if 0
116// without exzisus_cpub_reset_w, the following patch would be needed for
92// without cpub_reset_w, the following patch would be needed for
11793// the RAM check to work
11894DRIVER_INIT_MEMBER(exzisus_state,exzisus)
11995{
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137113static ADDRESS_MAP_START( cpua_map, AS_PROGRAM, 8, exzisus_state )
138114   AM_RANGE(0x0000, 0x7fff) AM_ROM
139115   AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank2")
140   AM_RANGE(0xc000, 0xc5ff) AM_READWRITE(exzisus_objectram_1_r, exzisus_objectram_1_w) AM_SHARE("objectram1")
141   AM_RANGE(0xc600, 0xdfff) AM_READWRITE(exzisus_videoram_1_r, exzisus_videoram_1_w) AM_SHARE("videoram1")
142   AM_RANGE(0xe000, 0xefff) AM_READWRITE(exzisus_sharedram_ac_r, exzisus_sharedram_ac_w) AM_SHARE("sharedram_ac")
143   AM_RANGE(0xf400, 0xf400) AM_WRITE(exzisus_cpua_bankswitch_w)
144   AM_RANGE(0xf404, 0xf404) AM_WRITE(exzisus_cpub_reset_w) // ??
145   AM_RANGE(0xf800, 0xffff) AM_READWRITE(exzisus_sharedram_ab_r, exzisus_sharedram_ab_w) AM_SHARE("sharedram_ab")
116   AM_RANGE(0xc000, 0xc5ff) AM_RAM AM_SHARE("objectram1")
117   AM_RANGE(0xc600, 0xdfff) AM_RAM AM_SHARE("videoram1")
118   AM_RANGE(0xe000, 0xefff) AM_RAM AM_SHARE("sharedram_ac")
119   AM_RANGE(0xf400, 0xf400) AM_WRITE(cpua_bankswitch_w)
120   AM_RANGE(0xf404, 0xf404) AM_WRITE(cpub_reset_w) // ??
121   AM_RANGE(0xf800, 0xffff) AM_RAM AM_SHARE("sharedram_ab")
146122ADDRESS_MAP_END
147123
148124static ADDRESS_MAP_START( cpub_map, AS_PROGRAM, 8, exzisus_state )
149125   AM_RANGE(0x0000, 0x7fff) AM_ROM
150126   AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
151   AM_RANGE(0xc000, 0xc5ff) AM_READWRITE(exzisus_objectram_0_r, exzisus_objectram_0_w) AM_SHARE("objectram0")
152   AM_RANGE(0xc600, 0xdfff) AM_READWRITE(exzisus_videoram_0_r, exzisus_videoram_0_w) AM_SHARE("videoram0")
127   AM_RANGE(0xc000, 0xc5ff) AM_RAM AM_SHARE("objectram0")
128   AM_RANGE(0xc600, 0xdfff) AM_RAM AM_SHARE("videoram0")
153129   AM_RANGE(0xe000, 0xefff) AM_RAM
154130   AM_RANGE(0xf000, 0xf000) AM_READNOP AM_DEVWRITE("tc0140syt", tc0140syt_device, master_port_w)
155131   AM_RANGE(0xf001, 0xf001) AM_DEVREADWRITE("tc0140syt", tc0140syt_device, master_comm_r, master_comm_w)
156132   AM_RANGE(0xf400, 0xf400) AM_READ_PORT("P1")
157   AM_RANGE(0xf400, 0xf400) AM_WRITE(exzisus_cpub_bankswitch_w)
133   AM_RANGE(0xf400, 0xf400) AM_WRITE(cpub_bankswitch_w)
158134   AM_RANGE(0xf401, 0xf401) AM_READ_PORT("P2")
159135   AM_RANGE(0xf402, 0xf402) AM_READ_PORT("SYSTEM")
160   AM_RANGE(0xf402, 0xf402) AM_WRITE(exzisus_coincounter_w)
136   AM_RANGE(0xf402, 0xf402) AM_WRITE(coincounter_w)
161137   AM_RANGE(0xf404, 0xf404) AM_READ_PORT("DSWA")
162138   AM_RANGE(0xf404, 0xf404) AM_WRITENOP // ??
163139   AM_RANGE(0xf405, 0xf405) AM_READ_PORT("DSWB")
164   AM_RANGE(0xf800, 0xffff) AM_READWRITE(exzisus_sharedram_ab_r, exzisus_sharedram_ab_w)
140   AM_RANGE(0xf800, 0xffff) AM_RAM AM_SHARE("sharedram_ab")
165141ADDRESS_MAP_END
166142
167143static ADDRESS_MAP_START( cpuc_map, AS_PROGRAM, 8, exzisus_state )
168144   AM_RANGE(0x0000, 0x7fff) AM_ROM
169   AM_RANGE(0x8000, 0x85ff) AM_READWRITE(exzisus_objectram_1_r, exzisus_objectram_1_w)
170   AM_RANGE(0x8600, 0x9fff) AM_READWRITE(exzisus_videoram_1_r, exzisus_videoram_1_w)
171   AM_RANGE(0xa000, 0xafff) AM_READWRITE(exzisus_sharedram_ac_r, exzisus_sharedram_ac_w)
145   AM_RANGE(0x8000, 0x85ff) AM_RAM AM_SHARE("objectram1")
146   AM_RANGE(0x8600, 0x9fff) AM_RAM AM_SHARE("videoram1")
147   AM_RANGE(0xa000, 0xafff) AM_RAM AM_SHARE("sharedram_ac")
172148   AM_RANGE(0xb000, 0xbfff) AM_RAM
173149ADDRESS_MAP_END
174150
r243527r243528
234210
235211***************************************************************************/
236212
213void exzisus_state::machine_start()
214{
215   membank("bank1")->configure_entries(0, 16, memregion("cpub")->base() + 0x10000, 0x4000);
216   membank("bank2")->configure_entries(0, 16, memregion("cpua")->base() + 0x10000, 0x4000);
217   
218   save_item(NAME(m_cpua_bank));
219   save_item(NAME(m_cpub_bank));
220}
221
237222static const gfx_layout charlayout =
238223{
239224   8, 8,
r243527r243528
279264   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
280265   MCFG_SCREEN_SIZE(32*8, 32*8)
281266   MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 2*8, 30*8-1)
282   MCFG_SCREEN_UPDATE_DRIVER(exzisus_state, screen_update_exzisus)
267   MCFG_SCREEN_UPDATE_DRIVER(exzisus_state, screen_update)
283268   MCFG_SCREEN_PALETTE("palette")
284269
285270   MCFG_GFXDECODE_ADD("gfxdecode", "palette", exzisus)
r243527r243528
424409   ROM_LOAD( "b23-05.16l", 0x00800, 0x00400, CRC(87f0f69a) SHA1(37df6fd56245fab9beaabfd86fd8f95d7c42c2a5) )
425410ROM_END
426411
427GAME( 1987, exzisus,  0,       exzisus, exzisus, driver_device, 0, ROT0, "Taito Corporation", "Exzisus (Japan, dedicated)",  0 )
428GAME( 1987, exzisusa, exzisus, exzisus, exzisus, driver_device, 0, ROT0, "Taito Corporation", "Exzisus (Japan, conversion)", 0 )
429GAME( 1987, exzisust, exzisus, exzisus, exzisus, driver_device, 0, ROT0, "Taito Corporation (TAD license)", "Exzisus (TAD license)", 0 )
412GAME( 1987, exzisus,  0,       exzisus, exzisus, driver_device, 0, ROT0, "Taito Corporation", "Exzisus (Japan, dedicated)",  GAME_SUPPORTS_SAVE )
413GAME( 1987, exzisusa, exzisus, exzisus, exzisus, driver_device, 0, ROT0, "Taito Corporation", "Exzisus (Japan, conversion)", GAME_SUPPORTS_SAVE )
414GAME( 1987, exzisust, exzisus, exzisus, exzisus, driver_device, 0, ROT0, "Taito Corporation (TAD license)", "Exzisus (TAD license)", GAME_SUPPORTS_SAVE )
trunk/src/mame/includes/exzisus.h
r243527r243528
33public:
44   exzisus_state(const machine_config &mconfig, device_type type, const char *tag)
55      : driver_device(mconfig, type, tag),
6      m_cpuc(*this, "cpuc"),
7      m_gfxdecode(*this, "gfxdecode"),
8      m_palette(*this, "palette"),
69      m_objectram1(*this, "objectram1"),
710      m_videoram1(*this, "videoram1"),
811      m_sharedram_ac(*this, "sharedram_ac"),
912      m_sharedram_ab(*this, "sharedram_ab"),
1013      m_objectram0(*this, "objectram0"),
11      m_videoram0(*this, "videoram0"),
12      m_cpuc(*this, "cpuc"),
13      m_gfxdecode(*this, "gfxdecode"),
14      m_palette(*this, "palette") { }
14      m_videoram0(*this, "videoram0") { }
1515
16   required_device<cpu_device> m_cpuc;
17   required_device<gfxdecode_device> m_gfxdecode;
18   required_device<palette_device> m_palette;
19   
1620   required_shared_ptr<UINT8> m_objectram1;
1721   required_shared_ptr<UINT8> m_videoram1;
1822   required_shared_ptr<UINT8> m_sharedram_ac;
1923   required_shared_ptr<UINT8> m_sharedram_ab;
2024   required_shared_ptr<UINT8> m_objectram0;
2125   required_shared_ptr<UINT8> m_videoram0;
22   required_device<cpu_device> m_cpuc;
23   required_device<gfxdecode_device> m_gfxdecode;
24   required_device<palette_device> m_palette;
2526
2627   int m_cpua_bank;
2728   int m_cpub_bank;
2829
29   DECLARE_WRITE8_MEMBER(exzisus_cpua_bankswitch_w);
30   DECLARE_WRITE8_MEMBER(exzisus_cpub_bankswitch_w);
31   DECLARE_WRITE8_MEMBER(exzisus_coincounter_w);
32   DECLARE_READ8_MEMBER(exzisus_sharedram_ab_r);
33   DECLARE_READ8_MEMBER(exzisus_sharedram_ac_r);
34   DECLARE_WRITE8_MEMBER(exzisus_sharedram_ab_w);
35   DECLARE_WRITE8_MEMBER(exzisus_sharedram_ac_w);
36   DECLARE_WRITE8_MEMBER(exzisus_cpub_reset_w);
37   DECLARE_READ8_MEMBER(exzisus_videoram_0_r);
38   DECLARE_READ8_MEMBER(exzisus_videoram_1_r);
39   DECLARE_READ8_MEMBER(exzisus_objectram_0_r);
40   DECLARE_READ8_MEMBER(exzisus_objectram_1_r);
41   DECLARE_WRITE8_MEMBER(exzisus_videoram_0_w);
42   DECLARE_WRITE8_MEMBER(exzisus_videoram_1_w);
43   DECLARE_WRITE8_MEMBER(exzisus_objectram_0_w);
44   DECLARE_WRITE8_MEMBER(exzisus_objectram_1_w);
45   UINT32 screen_update_exzisus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
30   DECLARE_WRITE8_MEMBER(cpua_bankswitch_w);
31   DECLARE_WRITE8_MEMBER(cpub_bankswitch_w);
32   DECLARE_WRITE8_MEMBER(coincounter_w);
33   DECLARE_WRITE8_MEMBER(cpub_reset_w);
34   
35   virtual void machine_start();
36   
37   UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
4638};
trunk/src/mame/video/exzisus.c
r243527r243528
1313
1414
1515/***************************************************************************
16  Memory handlers
17***************************************************************************/
18
19READ8_MEMBER(exzisus_state::exzisus_videoram_0_r)
20{
21   return m_videoram0[offset];
22}
23
24
25READ8_MEMBER(exzisus_state::exzisus_videoram_1_r)
26{
27   return m_videoram1[offset];
28}
29
30
31READ8_MEMBER(exzisus_state::exzisus_objectram_0_r)
32{
33   return m_objectram0[offset];
34}
35
36
37READ8_MEMBER(exzisus_state::exzisus_objectram_1_r)
38{
39   return m_objectram1[offset];
40}
41
42
43WRITE8_MEMBER(exzisus_state::exzisus_videoram_0_w)
44{
45   m_videoram0[offset] = data;
46}
47
48
49WRITE8_MEMBER(exzisus_state::exzisus_videoram_1_w)
50{
51   m_videoram1[offset] = data;
52}
53
54
55WRITE8_MEMBER(exzisus_state::exzisus_objectram_0_w)
56{
57   m_objectram0[offset] = data;
58}
59
60
61WRITE8_MEMBER(exzisus_state::exzisus_objectram_1_w)
62{
63   m_objectram1[offset] = data;
64}
65
66
67/***************************************************************************
6816  Screen refresh
6917***************************************************************************/
7018
71UINT32 exzisus_state::screen_update_exzisus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
19UINT32 exzisus_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
7220{
7321   int offs;
7422   int sx, sy, xc, yc;

https://github.com/mamedev/mame/commit/619982dc06b0d322f13092c943be98bd66136d8c

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