Previous 199869 Revisions Next

r34971 Thursday 12th February, 2015 at 00:59:09 UTC by Robbbert
(MESS) mbee : fixed RTC on rom-based models; fixed crash in mbee128. (nw)
[src/mess/drivers]mbee.c
[src/mess/includes]mbee.h
[src/mess/machine]mbee.c
[src/mess/video]mbee.c

trunk/src/mess/drivers/mbee.c
r243482r243483
6565          This rom can be replaced with the Dreamdisk Chip-8 rom.
6666        Note that Telcom 3.21 is 8k, it uses a rombank switch
6767        (by reading port 0A) to swap between the two halves.
68        Most parts of NET can be called up from Basic, e.g.
69        NET CLOCK will turn on the clock, NET CLOCKD will remove
70        the resultant status bar, NET TIME hhmm to set the time, etc.
71        Further, after doing a NET command, the 80x24 mode becomes
72        available to Basic. OUT#7 to turn it on, OUT#0 for 64x16.
68   See Telcom notes below.
7369
74    EDASM - Jump to C000, usually the editor/Assembler package.
70    EDASM - Jump to C000, usually the Editor/Assembler package.
7571
7672    MENU - Do a rombank switch to bank 5 and jump to C000 to start the Shell
7773
r243482r243483
8581    - Change it to parallel by entering OUTL#1
8682    - After you mount/create a printfile, you can LPRINT and LLIST.
8783
84    Notes about Telcom:
85    - On the older models, Telcom is called up by entering NET from within Basic. Models
86      from the pc85 onwards have it as a menu option.
87    - To exit, press Enter without any input. Disk versions, enter CPM or press ^C.
88    - After being used, version 3 and up will enable the use of OUT#7 in Basic, which
89      changes the screen to 80x24. Enter OUT#0 to revert to normal.
90    - Most versions of Telcom can have their parameters adjusted directly from Basic,
91      without needing to enter the Telcom program.
92    - Most versions of Telcom have an optional clock. In older models firstly select VS
93      from the MESS config menu, then enter NET CLOCK to enable it. NET TIME hhmm to set
94      the time (24hour format). NET CLOCKD is supposed to remove the status line, but it
95      doesn't, although the clock stops updating. NET CLOCK and NET CLOCKD are toggles.
96    - Telcom 1.2 (used in mbeeic) has a bug. If you enter NET CLOCK, the status line is
97      filled with inverse K. You can fix this from Basic by doing NET CLOCK 3 times.
8898
8999***************************************************************************
90100
91101    TODO/not working:
92102
93103    - Printer needs to be understood and fixed.
94
104    - Keyboard loses characters if you type at a normal rate.
95105    - Fix Paste (it loses most of the characters)
96106
97    - all except 256tc: RTC is optional, but it is being totally ignored.
98
99    - Most early models have a clock in Telcom, and in the menu. It doesn't
100      work.
101
102107    - various fdc issues:
103108        - B drive doesn't work.
104109        - some disks cause MESS to freeze.
r243482r243483
113118    - 128k: GOLD PAL needs to be dumped for the bankswitching.
114119    - 64k: RED PAL needs to be dumped for the bankswitching.
115120
116    - Teleterm: keyboard is problematic, and cursor doesn't show. Also, the
117                schematic shows it using the old-style keyboard, however this
118                must be wrong since the computer has function keys, which are
119                only available on the new keyboard.
121    - Teleterm: keyboard has multiple severe problems. Also, the schematic shows
122                it using the old-style keyboard, however this must be wrong since
123                the computer has function keys, which are only available on the
124                new keyboard.
120125
121126    - Mouse: a few programs support the use of a serial mouse which interfaced
122127             directly to the Z80PIO. However there's little info to be found.
r243482r243483
287292   AM_RANGE(0x000b, 0x000b) AM_MIRROR(0xff10) AM_READWRITE(mbee_0b_r, mbee_0b_w)
288293   AM_RANGE(0x000c, 0x000c) AM_MIRROR(0xff00) AM_READWRITE(m6545_status_r, m6545_index_w)
289294   AM_RANGE(0x000d, 0x000d) AM_MIRROR(0xff10) AM_READWRITE(m6545_data_r, m6545_data_w)
290   AM_RANGE(0x001c, 0x001c) AM_MIRROR(0xff00) AM_READWRITE(mbeeppc_1c_r,mbeeppc_1c_w)
295   AM_RANGE(0x001c, 0x001c) AM_MIRROR(0xff00) AM_READWRITE(mbeeppc_1c_r, mbeeppc_1c_w)
291296   AM_RANGE(0x010a, 0x010a) AM_MIRROR(0xfe10) AM_READWRITE(mbeepc_telcom_high_r, mbeeic_0a_w)
292297ADDRESS_MAP_END
293298
r243482r243483
311316   AM_RANGE(0x0b, 0x0b) AM_READWRITE(mbee_0b_r, mbee_0b_w)
312317   AM_RANGE(0x0c, 0x0c) AM_READWRITE(m6545_status_r, m6545_index_w)
313318   AM_RANGE(0x0d, 0x0d) AM_READWRITE(m6545_data_r, m6545_data_w)
314   AM_RANGE(0x1c, 0x1f) AM_READWRITE(mbeeppc_1c_r,mbee256_1c_w)
319   AM_RANGE(0x1c, 0x1f) AM_READWRITE(mbeeppc_1c_r, mbee256_1c_w)
315320   AM_RANGE(0x44, 0x47) AM_DEVREADWRITE("fdc", wd2793_t, read, write)
316321   AM_RANGE(0x48, 0x4f) AM_READWRITE(mbee_fdc_status_r, mbee_fdc_motor_w)
317322   AM_RANGE(0x50, 0x57) AM_WRITE(mbee128_50_w)
r243482r243483
331336   AM_RANGE(0x000d, 0x000d) AM_MIRROR(0xff00) AM_READWRITE(m6545_data_r, m6545_data_w)
332337   // AM_RANGE(0x0010, 0x0013) AM_MIRROR(0xff00) Optional SN76489AN audio chip
333338   AM_RANGE(0x0018, 0x001b) AM_MIRROR(0xff00) AM_READ(mbee256_18_r)
334   AM_RANGE(0x001c, 0x001f) AM_MIRROR(0xff00) AM_READWRITE(mbeeppc_1c_r,mbee256_1c_w)
339   AM_RANGE(0x001c, 0x001f) AM_MIRROR(0xff00) AM_READWRITE(mbeeppc_1c_r, mbee256_1c_w)
335340   AM_RANGE(0x0044, 0x0047) AM_MIRROR(0xff00) AM_DEVREADWRITE("fdc", wd2793_t, read, write)
336341   AM_RANGE(0x0048, 0x004f) AM_MIRROR(0xff00) AM_READWRITE(mbee_fdc_status_r, mbee_fdc_motor_w)
337342   AM_RANGE(0x0050, 0x0057) AM_MIRROR(0xff00) AM_WRITE(mbee256_50_w)
r243482r243483
446451   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("(Insert)") PORT_CODE(KEYCODE_INSERT) PORT_CHAR(UCHAR_MAMEKEY(INSERT))
447452   PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
448453
449   /* Enhanced options not available on real hardware */
454   // Autorun on quickload
450455   PORT_START("CONFIG")
451456   PORT_CONFNAME( 0x01, 0x01, "Autorun on Quickload")
452457   PORT_CONFSETTING(    0x00, DEF_STR(No))
453458   PORT_CONFSETTING(    0x01, DEF_STR(Yes))
459   // Wire links on motherboard
460   PORT_CONFNAME( 0xc0, 0x80, "PIO B7")
461   PORT_CONFSETTING(    0x00, "VS") // sync pulse to enable telcom clock
462   PORT_CONFSETTING(    0x40, "RTC") // optional board usually not fitted
463   PORT_CONFSETTING(    0x80, "Not used") // default resistor to vcc
464   PORT_CONFSETTING(    0xc0, "Centronics") // busy line
454465INPUT_PORTS_END
455466
456467static INPUT_PORTS_START( mbee256 )
r243482r243483
574585
575586   PORT_START("X14") /* IN6 KEY ROW 6 [+70] */
576587   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Alt") PORT_CODE(KEYCODE_LALT) PORT_CODE(KEYCODE_RALT)
588
589   // Autorun on quickload
590   PORT_START("CONFIG")
591   PORT_CONFNAME( 0x01, 0x01, "Autorun on Quickload")
592   PORT_CONFSETTING(    0x00, DEF_STR(No))
593   PORT_CONFSETTING(    0x01, DEF_STR(Yes))
594   // Wire links on motherboard
595   PORT_CONFNAME( 0xc0, 0x80, "PIO B7") // default - do nothing
596   PORT_CONFSETTING(    0x00, "VS") // sync pulse to enable telcom clock
597   PORT_CONFSETTING(    0x40, "RTC") // optional board usually not fitted
598   PORT_CONFSETTING(    0x80, "Not used") // default resistor to vcc
599   PORT_CONFSETTING(    0xc0, "Centronics") // busy line
577600INPUT_PORTS_END
578601
579602static const z80_daisy_config mbee_daisy_chain[] =
r243482r243483
657680   MCFG_MC6845_CHAR_WIDTH(8)
658681   MCFG_MC6845_UPDATE_ROW_CB(mbee_state, mbee_update_row)
659682   MCFG_MC6845_ADDR_CHANGED_CB(mbee_state, mbee_update_addr)
683   MCFG_MC6845_OUT_VSYNC_CB(WRITELINE(mbee_state, crtc_vs))
660684
661685   MCFG_QUICKLOAD_ADD("quickload", mbee_state, mbee, "mwb,com,bee", 2)
662686   MCFG_QUICKLOAD_ADD("quickload2", mbee_state, mbee_z80bin, "bin", 2)
r243482r243483
677701   MCFG_CPU_PROGRAM_MAP(mbeeic_mem)
678702   MCFG_CPU_IO_MAP(mbeeic_io)
679703   MCFG_CPU_CONFIG(mbee_daisy_chain)
680   //MCFG_CPU_VBLANK_INT_DRIVER("screen", mbee_state,  mbee_interrupt)
681704
682705   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee)
683706
r243482r243483
698721   MCFG_GFXDECODE_ADD("gfxdecode", "palette", mbeeic)
699722
700723   MCFG_PALETTE_ADD("palette", 96)
701   MCFG_PALETTE_INIT_OWNER(mbee_state,mbeeic)
724   MCFG_PALETTE_INIT_OWNER(mbee_state, mbeeic)
702725
703   MCFG_VIDEO_START_OVERRIDE(mbee_state,mbeeic)
726   MCFG_VIDEO_START_OVERRIDE(mbee_state, mbeeic)
704727
705728   /* sound hardware */
706729   MCFG_SPEAKER_STANDARD_MONO("mono")
r243482r243483
715738   MCFG_MC6845_CHAR_WIDTH(8)
716739   MCFG_MC6845_UPDATE_ROW_CB(mbee_state, mbeeic_update_row)
717740   MCFG_MC6845_ADDR_CHANGED_CB(mbee_state, mbee_update_addr)
741   MCFG_MC6845_OUT_VSYNC_CB(WRITELINE(mbee_state, crtc_vs))
718742
719743   MCFG_QUICKLOAD_ADD("quickload", mbee_state, mbee, "mwb,com,bee", 2)
720744   MCFG_QUICKLOAD_ADD("quickload2", mbee_state, mbee_z80bin, "bin", 2)
r243482r243483
742766
743767static MACHINE_CONFIG_DERIVED( mbeepc85b, mbeepc85 )
744768   MCFG_PALETTE_MODIFY("palette")
745   MCFG_PALETTE_INIT_OWNER(mbee_state,mbeepc85b)
769   MCFG_PALETTE_INIT_OWNER(mbee_state, mbeepc85b)
746770MACHINE_CONFIG_END
747771
748772static MACHINE_CONFIG_DERIVED( mbeeppc, mbeeic )
749773   MCFG_CPU_MODIFY( "maincpu" )
750774   MCFG_CPU_PROGRAM_MAP(mbeeppc_mem)
751775   MCFG_CPU_IO_MAP(mbeeppc_io)
752   MCFG_VIDEO_START_OVERRIDE(mbee_state,mbeeppc)
776   MCFG_VIDEO_START_OVERRIDE(mbee_state, mbeeppc)
753777   MCFG_GFXDECODE_MODIFY("gfxdecode", mbeeppc)
754778   MCFG_PALETTE_MODIFY("palette")
755779   MCFG_PALETTE_ENTRIES(16)
756   MCFG_PALETTE_INIT_OWNER(mbee_state,mbeeppc)
780   MCFG_PALETTE_INIT_OWNER(mbee_state, mbeeppc)
757781
758782   MCFG_DEVICE_REMOVE("crtc")
759783   MCFG_MC6845_ADD("crtc", SY6545_1, "screen", XTAL_13_5MHz / 8)
r243482r243483
761785   MCFG_MC6845_CHAR_WIDTH(8)
762786   MCFG_MC6845_UPDATE_ROW_CB(mbee_state, mbeeppc_update_row)
763787   MCFG_MC6845_ADDR_CHANGED_CB(mbee_state, mbee_update_addr)
788   MCFG_MC6845_OUT_VSYNC_CB(WRITELINE(mbee_state, crtc_vs))
764789MACHINE_CONFIG_END
765790
766791static MACHINE_CONFIG_DERIVED( mbee56, mbeeic )
r243482r243483
775800   MCFG_FLOPPY_DRIVE_ADD("fdc:1", mbee_floppies, "drive5b", floppy_image_device::default_floppy_formats)
776801MACHINE_CONFIG_END
777802
803static MACHINE_CONFIG_DERIVED( mbee128, mbee56 )
804   MCFG_CPU_MODIFY( "maincpu" )
805   MCFG_CPU_PROGRAM_MAP(mbee256_mem)
806   MCFG_CPU_IO_MAP(mbee128_io)
807   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128)
808MACHINE_CONFIG_END
809
778810static MACHINE_CONFIG_DERIVED( mbee128p, mbeeppc )
779811   MCFG_CPU_MODIFY( "maincpu" )
780812   MCFG_CPU_PROGRAM_MAP(mbee256_mem)
r243482r243483
787819   MCFG_FLOPPY_DRIVE_ADD("fdc:1", mbee_floppies, "drive5b", floppy_image_device::default_floppy_formats)
788820MACHINE_CONFIG_END
789821
790static MACHINE_CONFIG_DERIVED( mbee128, mbee128p )
791   MCFG_VIDEO_START_OVERRIDE(mbee_state,mbeeic)
792MACHINE_CONFIG_END
793
794822static MACHINE_CONFIG_DERIVED( mbee256, mbee128p )
795823   MCFG_CPU_MODIFY( "maincpu" )
796824   MCFG_CPU_PROGRAM_MAP(mbee256_mem)
r243482r243483
10771105ROM_END
10781106
10791107ROM_START( mbee128 ) // Standard 128k (CIAB is the same thing with half the ram)
1080   ROM_REGION(0x10000, "rams", ROMREGION_ERASEFF)
1108   ROM_REGION(0x20000, "rams", ROMREGION_ERASEFF)
10811109
1082   ROM_REGION(0x7000, "roms", ROMREGION_ERASEFF)
1110   ROM_REGION(0x8000, "roms", 0)
10831111   ROM_LOAD("bn54.bin",              0x0000,  0x2000, CRC(995c53db) SHA1(46e1a5cfd5795b8cf528bacf9dc79398ff7d64af) )
10841112
10851113   ROM_REGION(0x2000, "gfx", 0)
trunk/src/mess/includes/mbee.h
r243482r243483
7272      , m_screen(*this, "screen")
7373   { }
7474
75   DECLARE_WRITE8_MEMBER( mbee_04_w );
76   DECLARE_WRITE8_MEMBER( mbee_06_w );
77   DECLARE_READ8_MEMBER( mbee_07_r );
78   DECLARE_READ8_MEMBER( mbeeic_0a_r );
79   DECLARE_WRITE8_MEMBER( mbeeic_0a_w );
80   DECLARE_READ8_MEMBER( mbeepc_telcom_low_r );
81   DECLARE_READ8_MEMBER( mbeepc_telcom_high_r );
82   DECLARE_READ8_MEMBER( mbee256_speed_low_r );
83   DECLARE_READ8_MEMBER( mbee256_speed_high_r );
84   DECLARE_READ8_MEMBER( mbee256_18_r );
85   DECLARE_WRITE8_MEMBER( mbee64_50_w );
86   DECLARE_WRITE8_MEMBER( mbee128_50_w );
87   DECLARE_WRITE8_MEMBER( mbee256_50_w );
88   DECLARE_READ8_MEMBER( m6545_status_r );
89   DECLARE_WRITE8_MEMBER( m6545_index_w );
90   DECLARE_READ8_MEMBER( m6545_data_r );
91   DECLARE_WRITE8_MEMBER( m6545_data_w );
92   DECLARE_READ8_MEMBER( mbee_low_r );
93   DECLARE_READ8_MEMBER( mbee_high_r );
94   DECLARE_READ8_MEMBER( mbeeic_high_r );
95   DECLARE_WRITE8_MEMBER( mbeeic_high_w );
96   DECLARE_WRITE8_MEMBER( mbee_low_w );
97   DECLARE_WRITE8_MEMBER( mbee_high_w );
98   DECLARE_READ8_MEMBER( mbeeic_08_r );
99   DECLARE_WRITE8_MEMBER( mbeeic_08_w );
100   DECLARE_READ8_MEMBER( mbee_0b_r );
101   DECLARE_WRITE8_MEMBER( mbee_0b_w );
102   DECLARE_READ8_MEMBER( mbeeppc_1c_r );
103   DECLARE_WRITE8_MEMBER( mbeeppc_1c_w );
104   DECLARE_WRITE8_MEMBER( mbee256_1c_w );
105   DECLARE_READ8_MEMBER( mbeeppc_low_r );
106   DECLARE_READ8_MEMBER( mbeeppc_high_r );
107   DECLARE_WRITE8_MEMBER( mbeeppc_high_w );
108   DECLARE_WRITE8_MEMBER( mbeeppc_low_w );
109   DECLARE_WRITE8_MEMBER( pio_port_a_w );
110   DECLARE_WRITE8_MEMBER( pio_port_b_w );
111   DECLARE_READ8_MEMBER( pio_port_b_r );
112   DECLARE_WRITE_LINE_MEMBER( pio_ardy );
75   DECLARE_WRITE8_MEMBER(mbee_04_w);
76   DECLARE_WRITE8_MEMBER(mbee_06_w);
77   DECLARE_READ8_MEMBER(mbee_07_r);
78   DECLARE_READ8_MEMBER(mbeeic_0a_r);
79   DECLARE_WRITE8_MEMBER(mbeeic_0a_w);
80   DECLARE_READ8_MEMBER(mbeepc_telcom_low_r);
81   DECLARE_READ8_MEMBER(mbeepc_telcom_high_r);
82   DECLARE_READ8_MEMBER(mbee256_speed_low_r);
83   DECLARE_READ8_MEMBER(mbee256_speed_high_r);
84   DECLARE_READ8_MEMBER(mbee256_18_r);
85   DECLARE_WRITE8_MEMBER(mbee64_50_w);
86   DECLARE_WRITE8_MEMBER(mbee128_50_w);
87   DECLARE_WRITE8_MEMBER(mbee256_50_w);
88   DECLARE_READ8_MEMBER(m6545_status_r);
89   DECLARE_WRITE8_MEMBER(m6545_index_w);
90   DECLARE_READ8_MEMBER(m6545_data_r);
91   DECLARE_WRITE8_MEMBER(m6545_data_w);
92   DECLARE_READ8_MEMBER(mbee_low_r);
93   DECLARE_READ8_MEMBER(mbee_high_r);
94   DECLARE_READ8_MEMBER(mbeeic_high_r);
95   DECLARE_WRITE8_MEMBER(mbeeic_high_w);
96   DECLARE_WRITE8_MEMBER(mbee_low_w);
97   DECLARE_WRITE8_MEMBER(mbee_high_w);
98   DECLARE_READ8_MEMBER(mbeeic_08_r);
99   DECLARE_WRITE8_MEMBER(mbeeic_08_w);
100   DECLARE_READ8_MEMBER(mbee_0b_r);
101   DECLARE_WRITE8_MEMBER(mbee_0b_w);
102   DECLARE_READ8_MEMBER(mbeeppc_1c_r);
103   DECLARE_WRITE8_MEMBER(mbeeppc_1c_w);
104   DECLARE_WRITE8_MEMBER(mbee256_1c_w);
105   DECLARE_READ8_MEMBER(mbeeppc_low_r);
106   DECLARE_READ8_MEMBER(mbeeppc_high_r);
107   DECLARE_WRITE8_MEMBER(mbeeppc_high_w);
108   DECLARE_WRITE8_MEMBER(mbeeppc_low_w);
109   DECLARE_WRITE8_MEMBER(pio_port_a_w);
110   DECLARE_WRITE8_MEMBER(pio_port_b_w);
111   DECLARE_READ8_MEMBER(pio_port_b_r);
112   DECLARE_WRITE_LINE_MEMBER(pio_ardy);
113   DECLARE_WRITE_LINE_MEMBER(crtc_vs);
113114   DECLARE_READ8_MEMBER(mbee_fdc_status_r);
114115   DECLARE_WRITE8_MEMBER(mbee_fdc_motor_w);
115116   DECLARE_DRIVER_INIT(mbeepc85);
r243482r243483
161162private:
162163   bool m_is_premium;
163164   size_t m_size;
164   UINT8 m_clock_pulse;
165   bool m_b7_rtc;
166   bool m_b7_vs;
165167   UINT8 m_mbee256_key_available;
166168   UINT8 m_mbee256_was_pressed[15];
167169   UINT8 m_mbee256_q[20];
trunk/src/mess/machine/mbee.c
r243482r243483
7272
7373   if (m_cassette->input() > 0.03) data |= 1;
7474
75   data |= m_clock_pulse;
75   switch (m_io_config->read() & 0xc0)
76   {
77      case 0x00:
78         data |= (UINT8)m_b7_vs << 7;
79         break;
80      case 0x40:
81         data |= (UINT8)m_b7_rtc << 7;
82         break;
83      case 0x80:
84         data |= 0x80;
85         break;
86      case 0xc0:
87         data |= 0x80; // centronics busy line - FIXME
88         break;
89   }
90
7691   data |= m_mbee256_key_available;
7792
78   m_clock_pulse = 0;
79
8093   return data;
8194};
8295
r243482r243483
254267   return m_rtc->read(space, 1);
255268}
256269
257TIMER_CALLBACK_MEMBER(mbee_state::mbee_rtc_irq)
270// This doesn't seem to do anything; the time works without it.
271TIMER_CALLBACK_MEMBER( mbee_state::mbee_rtc_irq )
258272{
259   UINT8 data = m_rtc->read(m_maincpu->space(AS_PROGRAM), 12);
260   if (data) m_clock_pulse = 0x80;
261   timer_set(attotime::from_hz(1), TIMER_MBEE_RTC_IRQ);
273   UINT8 data = m_rtc->read(m_maincpu->space(AS_IO), 12);
274   m_b7_rtc = (data) ? 1 : 0;
275
276   if ((m_io_config->read() & 0xc0) == 0x40) // RTC selected in config menu
277      m_pio->port_b_write(pio_port_b_r(generic_space(),0,0xff));
278
279   timer_set(attotime::from_hz(10), TIMER_MBEE_RTC_IRQ);
262280}
263281
264282
r243482r243483
522540
523541   /* once per frame, pulse the PIO B bit 7 - it is in the schematic as an option,
524542   but need to find out what it does */
525   m_clock_pulse = 0x80;
543   m_b7_busy = 0x80;
526544   irq0_line_hold(device);
527545
528546#endif
r243482r243483
623641      membank(banktag)->configure_entries(0, 32, &RAM[0x0000], 0x1000); // RAM banks
624642      membank(banktag)->configure_entries(64, 1, &ROM[0x4000], 0x1000); // dummy rom
625643   }
626   m_size = 0xf000;
644   m_size = 0x8000;
627645}
628646
629647DRIVER_INIT_MEMBER( mbee_state, mbee256 )
r243482r243483
683701{
684702   address_space &space = m_maincpu->space(AS_PROGRAM);
685703   UINT16 i, j;
686   UINT8 data, sw = ioport("CONFIG")->read() & 1;   /* reading the dipswitch: 1 = autorun */
704   UINT8 data, sw = m_io_config->read() & 1;   /* reading the config switch: 1 = autorun */
687705
688706   if (!core_stricmp(image.filetype(), "mwb"))
689707   {
r243482r243483
784802   /* is this file executable? */
785803   if (execute_address != 0xffff)
786804   {
787      /* check to see if autorun is on (I hate how this works) */
788      autorun = ioport("CONFIG")->read_safe(0xFF) & 1;
805      /* check to see if autorun is on */
806      autorun = m_io_config->read_safe(0xFF) & 1;
789807
790808      address_space &space = m_maincpu->space(AS_PROGRAM);
791809
trunk/src/mess/video/mbee.c
r243482r243483
2828
2929#include "includes/mbee.h"
3030
31WRITE_LINE_MEMBER( mbee_state::crtc_vs )
32{
33   m_b7_vs = state;
34   if ((m_io_config->read() & 0xc0) == 0) // VS selected in config menu
35      m_pio->port_b_write(pio_port_b_r(generic_space(),0,0xff));
36}
3137
3238/***********************************************************
3339
r243482r243483
314320      m_sy6545_status &= 0x80; // turn off lpen_strobe
315321      break;
316322   case 31:
317            /* This firstly pushes the contents of the transparent registers onto the MA lines,
318            then increments the address, then sets update strobe on. */
323      // This firstly pushes the contents of the transparent registers onto the MA lines,
324      // then increments the address, then sets update strobe on.
319325      addr = (m_sy6545_reg[18] << 8) | m_sy6545_reg[19];
320326      keyboard_matrix_r(addr);
321327      m_sy6545_reg[19]++;
r243482r243483
346352         memcpy(m_p_gfxram, memregion("gfx")->base() + (((data & 0x30) == 0x20) << 11), 0x800);
347353      break;
348354   case 31:
349      /* This firstly pushes the contents of the transparent registers onto the MA lines,
350      then increments the address, then sets update strobe on. */
355      // This firstly pushes the contents of the transparent registers onto the MA lines,
356      // then increments the address, then sets update strobe on.
351357      addr = (m_sy6545_reg[18] << 8) | m_sy6545_reg[19];
352358      keyboard_matrix_r(addr);
353359      m_sy6545_reg[19]++;
r243482r243483
369375
370376************************************************************/
371377
372VIDEO_START_MEMBER(mbee_state,mbee)
378VIDEO_START_MEMBER( mbee_state, mbee )
373379{
374380   m_p_videoram = memregion("videoram")->base();
375381   m_p_gfxram = memregion("gfx")->base()+0x1000;
376382   m_is_premium = 0;
377383}
378384
379VIDEO_START_MEMBER(mbee_state,mbeeic)
385VIDEO_START_MEMBER( mbee_state, mbeeic )
380386{
381387   m_p_videoram = memregion("videoram")->base();
382388   m_p_colorram = memregion("colorram")->base();
r243482r243483
384390   m_is_premium = 0;
385391}
386392
387VIDEO_START_MEMBER(mbee_state,mbeeppc)
393VIDEO_START_MEMBER( mbee_state, mbeeppc )
388394{
389395   m_p_videoram = memregion("videoram")->base();
390396   m_p_colorram = memregion("colorram")->base();
r243482r243483
546552
547553************************************************************/
548554
549PALETTE_INIT_MEMBER(mbee_state,mbeeic)
555PALETTE_INIT_MEMBER( mbee_state, mbeeic )
550556{
551557   const UINT8 *color_prom = memregion("proms")->base();
552558   UINT16 i;
r243482r243483
574580}
575581
576582
577PALETTE_INIT_MEMBER(mbee_state,mbeepc85b)
583PALETTE_INIT_MEMBER( mbee_state, mbeepc85b )
578584{
579585   const UINT8 *color_prom = memregion("proms")->base();
580586   UINT16 i;
r243482r243483
604610}
605611
606612
607PALETTE_INIT_MEMBER(mbee_state,mbeeppc)
613PALETTE_INIT_MEMBER( mbee_state, mbeeppc )
608614{
609615   UINT16 i;
610616   UINT8 r, b, g;

https://github.com/mamedev/mame/commit/a5303d9d556e7e7d4220601806f915fd7bb26ad6

Previous 199869 Revisions Next

© 1997-2024 The MAME Team