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r34902 Saturday 7th February, 2015 at 04:53:04 UTC by Robbbert
(MESS) mbee128: improvements; mbee256: fixed some of the paste problems (nw)
[src/mess/drivers]mbee.c
[src/mess/machine]mbee.c

trunk/src/mess/drivers/mbee.c
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9090      work.
9191
9292    - various fdc issues:
93        - only some ds40 disks can be used. All 80-track disks fail.
94        - some disks show no or partial directory listing.
9593        - some disks cause MESS to freeze.
9694        - ENMF pin missing from wd_fdc.
9795        - incorrect timing for track register causes 256tc failure to boot a disk.
r243413r243414
10199      crashes due to a bug in z80pio emulation.
102100   
103101    - 256tc: Keyboard ROM U60 needs to be dumped.
104    - 128k: PROM PAL needs to be dumped, so that the bankswitching can be fixed.
102    - 128k: PROM PAL needs to be dumped for the bankswitching.
105103
106104    - Teleterm: keyboard is problematic, and cursor doesn't show.
107105
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115113              and intrq/drq on read.
116114      intrq and drq are OR'd together, then gated to bit 7 of the
117115      data bus whenever port 48 is activated on read. There are
118      no interrupts used in the disk system.
116      no interrupts used.
119117
120      Despite the simplicity of this design, disks have not worked
121      in the emulator for some years. Conversion to the new modern
122      implementation (2013-07-05) has not resolved the issue.
123
124118****************************************************************************/
125119
126120
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203197   AM_RANGE(0xf800, 0xffff) AM_READWRITE(mbeeic_high_r, mbeeic_high_w)
204198ADDRESS_MAP_END
205199
206static ADDRESS_MAP_START(mbee128_mem, AS_PROGRAM, 8, mbee_state)
207   AM_RANGE(0x0000, 0x0fff) AM_RAMBANK("boot")
208   AM_RANGE(0x1000, 0x7fff) AM_RAMBANK("bank1")
209   AM_RANGE(0x8000, 0x87ff) AM_RAMBANK("bank8l")
210   AM_RANGE(0x8800, 0x8fff) AM_RAMBANK("bank8h")
211   AM_RANGE(0x9000, 0xefff) AM_RAMBANK("bank9")
212   AM_RANGE(0xf000, 0xf7ff) AM_RAMBANK("bankfl")
213   AM_RANGE(0xf800, 0xffff) AM_RAMBANK("bankfh")
214ADDRESS_MAP_END
215
216200static ADDRESS_MAP_START(mbee256_mem, AS_PROGRAM, 8, mbee_state)
217201   AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bankr0") AM_WRITE_BANK("bankw0")
218202   AM_RANGE(0x1000, 0x1fff) AM_READ_BANK("bankr1") AM_WRITE_BANK("bankw1")
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535519   PORT_START("X6") /* IN6 KEY ROW 6 [+30] */
536520   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F7") PORT_CODE(KEYCODE_F7)
537521   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("6 &") PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
538   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('u') PORT_CHAR('Y') PORT_CHAR(0x19)
522   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') PORT_CHAR(0x19)
539523   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') PORT_CHAR(0x08)
540524   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/ (num)") PORT_CODE(KEYCODE_SLASH_PAD)
541525   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("(Down)") PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
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587571   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/ ?") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
588572
589573   PORT_START("X12") /* IN4 KEY ROW 4 [+60] */
590   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT)
574   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
591575
592576   PORT_START("X13") /* IN5 KEY ROW 5 [+68] */
593   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL)
577   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
594578
595579   PORT_START("X14") /* IN6 KEY ROW 6 [+70] */
596580   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Alt") PORT_CODE(KEYCODE_LALT) PORT_CODE(KEYCODE_RALT)
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643627   MCFG_CPU_IO_MAP(mbee_io)
644628   MCFG_CPU_CONFIG(mbee_daisy_chain)
645629
646   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee )
630   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee)
647631
648632   MCFG_DEVICE_ADD("z80pio", Z80PIO, XTAL_12MHz / 6)
649633   MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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699683   MCFG_CPU_CONFIG(mbee_daisy_chain)
700684   //MCFG_CPU_VBLANK_INT_DRIVER("screen", mbee_state,  mbee_interrupt)
701685
702   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee )
686   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee)
703687
704688   MCFG_DEVICE_ADD("z80pio", Z80PIO, 3375000)
705689   MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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787771   MCFG_CPU_MODIFY( "maincpu" )
788772   MCFG_CPU_PROGRAM_MAP(mbee56_mem)
789773   MCFG_CPU_IO_MAP(mbee56_io)
790   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee56 )
774   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee56)
791775   MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4) // divided by 2 externally, then divided by 2 internally (/ENMF pin not emulated)
792776   MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(mbee_state, fdc_intrq_w))
793777   MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(mbee_state, fdc_drq_w))
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799783   MCFG_CPU_MODIFY( "maincpu" )
800784   MCFG_CPU_PROGRAM_MAP(mbee64_mem)
801785   MCFG_CPU_IO_MAP(mbee64_io)
802   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee64 )
786   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee64)
803787MACHINE_CONFIG_END
804788
805789static MACHINE_CONFIG_DERIVED( mbee128, mbeeppc )
806790   MCFG_CPU_MODIFY( "maincpu" )
807   MCFG_CPU_PROGRAM_MAP(mbee128_mem)
791   MCFG_CPU_PROGRAM_MAP(mbee256_mem)
808792   MCFG_CPU_IO_MAP(mbee128_io)
809   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128 )
793   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128)
810794   MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4)
811795   MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(mbee_state, fdc_intrq_w))
812796   MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(mbee_state, fdc_drq_w))
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818802   MCFG_CPU_MODIFY( "maincpu" )
819803   MCFG_CPU_PROGRAM_MAP(mbee256_mem)
820804   MCFG_CPU_IO_MAP(mbee256_io)
821   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee256 )
805   MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee256)
822806   MCFG_MC146818_ADD( "rtc", XTAL_32_768kHz )
823807
824808   MCFG_DEVICE_REMOVE("crtc")
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892876   ROM_REGION(0x10000,"maincpu", ROMREGION_ERASEFF)
893877   ROM_LOAD("bas522a.rom",           0x8000,  0x2000, CRC(7896a696) SHA1(a158f7803296766160e1f258dfc46134735a9477) )
894878   ROM_LOAD("bas522b.rom",           0xa000,  0x2000, CRC(b21d9679) SHA1(332844433763331e9483409cd7da3f90ac58259d) )
895
896879   ROM_LOAD_OPTIONAL("telcom12.rom", 0xe000,  0x1000, CRC(0231bda3) SHA1(be7b32499034f985cc8f7865f2bc2b78c485585c) )
897880
898881   /* PAK option roms */
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11191102ROM_END
11201103
11211104ROM_START( mbee128 ) // 128K
1122   ROM_REGION(0x20000,"maincpu", ROMREGION_ERASEFF)
1105   ROM_REGION(0x20000, "rams", ROMREGION_ERASEFF)
11231106
1124   ROM_REGION(0x7000,"bootrom", ROMREGION_ERASEFF)
1107   ROM_REGION(0x8000, "roms", 0) // rom plus optional undumped roms plus dummy area
11251108   ROM_SYSTEM_BIOS( 0, "bn60", "Version 2.03" )
11261109   ROMX_LOAD("bn60.rom",     0x0000, 0x2000, CRC(ed15d4ee) SHA1(3ea42b63d42b9a4c5402676dee8912ad1f906bda), ROM_BIOS(1) )
11271110   ROM_SYSTEM_BIOS( 1, "bn59", "Version 2.02" )
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11351118   ROM_SYSTEM_BIOS( 5, "hd18", "Hard Disk System" )
11361119   ROMX_LOAD("hd18.rom",     0x0000, 0x2000, CRC(ed53ace7) SHA1(534e2e00cc527197c76b3c106b3c9ff7f1328487), ROM_BIOS(6) )
11371120
1121   ROM_REGION(0x4000, "proms", 0) // undumped; using prom from 256tc for now
1122   ROM_LOAD( "silver.u39", 0x0000, 0x4000, BAD_DUMP CRC(c34aab64) SHA1(781fe648488dec90185760f8e081e488b73b68bf) )
1123
11381124   ROM_REGION(0x9800, "gfx", 0)
11391125   ROM_LOAD("charrom.bin",           0x1000,  0x1000, CRC(1f9fcee4) SHA1(e57ac94e03638075dde68a0a8c834a4f84ba47b0) )
11401126   ROM_RELOAD( 0x0000, 0x1000 )
trunk/src/mess/machine/mbee.c
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276276
277277void mbee_state::mbee256_setup_banks(UINT8 data)
278278{
279   data &= 0x3f; // U28 (bits 0-5 are referred to as S0-S5)
279   // (bits 0-5 are referred to as S0-S5)
280280   address_space &mem = m_maincpu->space(AS_PROGRAM);
281281   UINT8 *prom = memregion("proms")->base();
282282   UINT8 b_data = BITSWAP8(data, 7,5,3,2,4,6,1,0) & 0x3b; // arrange data bits to S0,S1,-,S4,S2,S3
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338338
339339WRITE8_MEMBER( mbee_state::mbee256_50_w )
340340{
341   mbee256_setup_banks(data);
341   mbee256_setup_banks(data & 0x3f);
342342}
343343
344344/***********************************************************
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356356
357357WRITE8_MEMBER( mbee_state::mbee128_50_w )
358358{
359   address_space &mem = m_maincpu->space(AS_PROGRAM);
360
361   // primary low banks
362   m_boot->set_entry((data & 3));
363   m_bank1->set_entry((data & 3));
364
365   // 9000-EFFF
366   m_bank9->set_entry((data & 4) ? 1 : 0);
367
368   // 8000-8FFF, F000-FFFF
369   mem.unmap_readwrite (0x8000, 0x87ff);
370   mem.unmap_readwrite (0x8800, 0x8fff);
371   mem.unmap_readwrite (0xf000, 0xf7ff);
372   mem.unmap_readwrite (0xf800, 0xffff);
373
374   switch (data & 0x1c)
375   {
376      case 0x00:
377         mem.install_read_bank (0x8000, 0x87ff, "bank8l");
378         mem.install_read_bank (0x8800, 0x8fff, "bank8h");
379         mem.install_readwrite_handler (0xf000, 0xf7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this));
380         mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this));
381         m_bank8l->set_entry(0); // rom
382         m_bank8h->set_entry(0); // rom
383         break;
384      case 0x04:
385         // these 2 lines were read_bank but readwrite is needed for bios 2,3,4,5 to boot
386         mem.install_readwrite_bank (0x8000, 0x87ff, "bank8l");
387         mem.install_readwrite_bank (0x8800, 0x8fff, "bank8h");
388         mem.install_readwrite_handler (0xf000, 0xf7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this));
389         mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this));
390         m_bank8l->set_entry(1); // ram
391         m_bank8h->set_entry(1); // ram
392         break;
393      case 0x08:
394      case 0x18:
395         mem.install_read_bank (0x8000, 0x87ff, "bank8l");
396         mem.install_read_bank (0x8800, 0x8fff, "bank8h");
397         mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
398         mem.install_read_bank (0xf800, 0xffff, "bankfh");
399         m_bank8l->set_entry(0); // rom
400         m_bank8h->set_entry(0); // rom
401         m_bankfl->set_entry(0); // ram
402         m_bankfh->set_entry(0); // ram
403         break;
404      case 0x0c:
405      case 0x1c:
406         mem.install_read_bank (0x8000, 0x87ff, "bank8l");
407         mem.install_read_bank (0x8800, 0x8fff, "bank8h");
408         mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
409         mem.install_read_bank (0xf800, 0xffff, "bankfh");
410         m_bank8l->set_entry(1); // ram
411         m_bank8h->set_entry(1); // ram
412         m_bankfl->set_entry(0); // ram
413         m_bankfh->set_entry(0); // ram
414         break;
415      case 0x10:
416      case 0x14:
417         mem.install_readwrite_handler (0x8000, 0x87ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this));
418         mem.install_readwrite_handler (0x8800, 0x8fff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this));
419         mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
420         mem.install_read_bank (0xf800, 0xffff, "bankfh");
421         m_bankfl->set_entry(0); // ram
422         m_bankfh->set_entry(0); // ram
423         break;
424   }
359   mbee256_setup_banks(data & 0x1f); // S5 not used
425360}
426361
427362
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507442
508443
509444/* after the first 4 bytes have been read from ROM, switch the ram back in */
510TIMER_CALLBACK_MEMBER(mbee_state::mbee_reset)
445TIMER_CALLBACK_MEMBER( mbee_state::mbee_reset )
511446{
512447   m_boot->set_entry(0);
513448}
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517452   m_fdc_rq = 0;
518453}
519454
520MACHINE_RESET_MEMBER(mbee_state,mbee)
455MACHINE_RESET_MEMBER( mbee_state, mbee )
521456{
522457   m_boot->set_entry(1);
523458   timer_set(attotime::from_usec(4), TIMER_MBEE_RESET);
524459}
525460
526MACHINE_RESET_MEMBER(mbee_state,mbee56)
461MACHINE_RESET_MEMBER( mbee_state, mbee56 )
527462{
528463   machine_reset_common_disk();
529464   m_boot->set_entry(1);
530465   timer_set(attotime::from_usec(4), TIMER_MBEE_RESET);
531466}
532467
533MACHINE_RESET_MEMBER(mbee_state,mbee64)
468MACHINE_RESET_MEMBER( mbee_state, mbee64 )
534469{
535470   machine_reset_common_disk();
536471   m_boot->set_entry(1);
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538473   m_bankh->set_entry(1);
539474}
540475
541MACHINE_RESET_MEMBER(mbee_state,mbee128)
476MACHINE_RESET_MEMBER( mbee_state, mbee128 )
542477{
543   address_space &mem = m_maincpu->space(AS_IO);
544478   machine_reset_common_disk();
545   mbee128_50_w(mem,0,0); // set banks to default
546   m_boot->set_entry(8); // boot time
479   mbee256_setup_banks(0); // set banks to default
480   m_maincpu->set_pc(0x8000);
547481}
548482
549MACHINE_RESET_MEMBER(mbee_state,mbee256)
483MACHINE_RESET_MEMBER( mbee_state, mbee256 )
550484{
551485   UINT8 i;
552   machine_reset_common_disk();
553486   for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0;
554487   m_mbee256_q_pos = 0;
488   machine_reset_common_disk();
555489   mbee256_setup_banks(0); // set banks to default
556490   m_maincpu->set_pc(0x8000);
557491}
558492
559MACHINE_RESET_MEMBER(mbee_state,mbeett)
493MACHINE_RESET_MEMBER( mbee_state, mbeett )
560494{
561495   UINT8 i;
562496   for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0;
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565499   timer_set(attotime::from_usec(4), TIMER_MBEE_RESET);
566500}
567501
568INTERRUPT_GEN_MEMBER(mbee_state::mbee_interrupt)
502INTERRUPT_GEN_MEMBER( mbee_state::mbee_interrupt )
569503{
570504// Due to the uncertainly and hackage here, this is commented out for now - Robbbert - 05-Oct-2010
571505#if 0
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588522#endif
589523}
590524
591DRIVER_INIT_MEMBER(mbee_state,mbee)
525DRIVER_INIT_MEMBER( mbee_state, mbee )
592526{
593527   UINT8 *RAM = memregion("maincpu")->base();
594528   m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
595529   m_size = 0x4000;
596530}
597531
598DRIVER_INIT_MEMBER(mbee_state,mbeeic)
532DRIVER_INIT_MEMBER( mbee_state, mbeeic )
599533{
600534   UINT8 *RAM = memregion("maincpu")->base();
601535   m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
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607541   m_size = 0x8000;
608542}
609543
610DRIVER_INIT_MEMBER(mbee_state,mbeepc)
544DRIVER_INIT_MEMBER( mbee_state, mbeepc )
611545{
612546   UINT8 *RAM = memregion("maincpu")->base();
613547   m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
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623557   m_size = 0x8000;
624558}
625559
626DRIVER_INIT_MEMBER(mbee_state,mbeepc85)
560DRIVER_INIT_MEMBER( mbee_state, mbeepc85 )
627561{
628562   UINT8 *RAM = memregion("maincpu")->base();
629563   m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
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639573   m_size = 0x8000;
640574}
641575
642DRIVER_INIT_MEMBER(mbee_state,mbeeppc)
576DRIVER_INIT_MEMBER( mbee_state, mbeeppc )
643577{
644578   UINT8 *RAM = memregion("maincpu")->base();
645579   m_boot->configure_entry(0, &RAM[0x0000]);
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660594   m_size = 0x8000;
661595}
662596
663DRIVER_INIT_MEMBER(mbee_state,mbee56)
597DRIVER_INIT_MEMBER( mbee_state, mbee56 )
664598{
665599   UINT8 *RAM = memregion("maincpu")->base();
666600   m_boot->configure_entries(0, 2, &RAM[0x0000], 0xe000);
667601   m_size = 0xe000;
668602}
669603
670DRIVER_INIT_MEMBER(mbee_state,mbee64)
604DRIVER_INIT_MEMBER( mbee_state, mbee64 )
671605{
672606   UINT8 *RAM = memregion("maincpu")->base();
673607   m_boot->configure_entry(0, &RAM[0x0000]);
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682616   m_size = 0xf000;
683617}
684618
685DRIVER_INIT_MEMBER(mbee_state,mbee128)
619DRIVER_INIT_MEMBER( mbee_state, mbee128 )
686620{
687   UINT8 *RAM = memregion("maincpu")->base();
688   m_boot->configure_entries(0, 4, &RAM[0x0000], 0x8000); // standard banks 0000
689   m_bank1->configure_entries(0, 4, &RAM[0x1000], 0x8000); // standard banks 1000
690   m_bank8l->configure_entry(1, &RAM[0x0000]); // shadow ram
691   m_bank8h->configure_entry(1, &RAM[0x0800]); // shadow ram
692   m_bank9->configure_entry(1, &RAM[0x1000]); // shadow ram
693   m_bankfl->configure_entry(0, &RAM[0xf000]); // shadow ram
694   m_bankfh->configure_entry(0, &RAM[0xf800]); // shadow ram
621   UINT8 *RAM = memregion("rams")->base();
622   UINT8 *ROM = memregion("roms")->base();
623   char banktag[10];
695624
696   RAM = memregion("bootrom")->base();
697   m_bank9->configure_entry(0, &RAM[0x1000]); // rom
698   m_boot->configure_entry(8, &RAM[0x0000]); // rom at boot for 4usec
699   m_bank8l->configure_entry(0, &RAM[0x0000]); // rom
700   m_bank8h->configure_entry(0, &RAM[0x0800]); // rom
625   for (UINT8 b_bank = 0; b_bank < 16; b_bank++)
626   {
627      sprintf(banktag, "bankr%d", b_bank);
628      membank(banktag)->configure_entries(0, 32, &RAM[0x0000], 0x1000); // RAM banks
629      membank(banktag)->configure_entries(64, 4, &ROM[0x0000], 0x1000); // rom
701630
631      sprintf(banktag, "bankw%d", b_bank);
632      membank(banktag)->configure_entries(0, 32, &RAM[0x0000], 0x1000); // RAM banks
633      membank(banktag)->configure_entries(64, 1, &ROM[0x4000], 0x1000); // dummy rom
634   }
635
702636   m_size = 0x8000;
703637}
704638
705DRIVER_INIT_MEMBER(mbee_state,mbee256)
639DRIVER_INIT_MEMBER( mbee_state, mbee256 )
706640{
707641   UINT8 *RAM = memregion("rams")->base();
708642   UINT8 *ROM = memregion("roms")->base();
r243413r243414
725659   m_size = 0x8000;
726660}
727661
728DRIVER_INIT_MEMBER(mbee_state,mbeett)
662DRIVER_INIT_MEMBER( mbee_state, mbeett )
729663{
730664   UINT8 *RAM = memregion("maincpu")->base();
731665   m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);

https://github.com/mamedev/mame/commit/be6304da892763f7c74f0237d73c9ed251b8722e

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