MAME SVN History

199869 Revisions

r34565 Friday 23rd January, 2015 at 19:35:04 UTC by Angelo Salese
Prepare for rewrite.

[/branches/kale/src/mess/drivers]	c65.c
[/branches/kale/src/mess/includes]	c65.h
[/branches/kale/src/mess/machine]	c65.c

branches/kale/src/mess/drivers/c65.c
r243076	r243077
	1	// license: MAME
	2	// copyright-holders: Angelo Salese
1	3	/***************************************************************************
2	4
3		commodore c65 home computer
4		PeT mess@utanet.at
	5	C=65 / C=64DX (c) 1991 Commodore
5	6
6		documention
7		www.funet.fi
	7	Attempt at rewriting the driver ...
8	8
9	9	***************************************************************************/
10	10
11		/*
12	11
13		2008 - Driver Updates
14		---------------------
	12	#include "emu.h"
	13	#include "cpu/m6502/m4510.h"
15	14
16		~~(most of th~~e inf~~ormat~~ion~~s ar~~e ~~taken~~ ~~from http://www.~~z~~immers.net/cbmpics/ )~~
	15	#define MAIN_CLOCK XTAL_8MHz
17	16
	17	class c65_state : public driver_device
	18	{
	19	public:
	20	c65_state(const machine_config &mconfig, device_type type, const char *tag)
	21	: driver_device(mconfig, type, tag),
	22	m_maincpu(*this, "maincpu")
	23	{ }
18	24
19		[CBM systems which belong to this driver]
	25	// devices
	26	required_device<cpu_device> m_maincpu;
20	27
21		* Commodore 65 (1989)
	28	// screen updates
	29	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	30	DECLARE_PALETTE_INIT(c65);
	31	DECLARE_DRIVER_INIT(c65);
	32	DECLARE_DRIVER_INIT(c65pal);
	33	protected:
	34	// driver_device overrides
	35	virtual void machine_start();
	36	virtual void machine_reset();
22	37
23		Also known as C64 DX at early stages of the project. It was cancelled
24		around 1990-1991. Only few units survive (they were sold after Commodore
25		liquidation in 1994).
	38	virtual void video_start();
	39	};
26	40
27		CPU: CSG 4510 (3.54 MHz)
28		RAM: 128 kilobytes, expandable to 8 megabytes
29		ROM: 128 kilobytes
30		Video: CSG 4569 "VIC-III" (6 Video modes; Resolutions from 320x200 to
31		1280x400; 80 columns text; Palette of 4096 colors)
32		Sound: CSG 8580 "SID" x2 (6 voice stereo synthesizer/digital sound
33		capabilities)
34		Ports: CSG 4510 (2 Joystick/Mouse ports; CBM Serial port; CBM 'USER'
35		port; CBM Monitor port; Power and reset switches; C65 bus drive
36		port; RGBI video port; 2 RCA audio ports; RAM expansion port; C65
37		expansion port)
38		Keyboard: Full-sized 77 key QWERTY (12 programmable function keys;
39		4 direction cursor-pad)
40		Additional Hardware: Built in 3.5" DD disk drive (1581 compatible)
41		Miscellaneous: Partially implemented Commodore 64 emulation
42
43		[Notes]
44
45		The datasette port was removed here. C65 supports an additional "dumb"
46		drive externally. It also features, in addition to the standard CBM
47		bus serial (available in all modes), a Fast and a Burst serial bus
48		(both available in C65 mode only)
49
50		*/
51
52
53		#include "emu.h"
54		#include "cpu/m6502/m4510.h"
55		#include "machine/mos6526.h"
56		#include "machine/cbm_snqk.h"
57		#include "includes/c65.h"
58		#include "bus/cbmiec/cbmiec.h"
59		#include "machine/ram.h"
60
61		static void cbm_c65_quick_sethiaddress( address_space &space, UINT16 hiaddress )
	41	void c65_state::video_start()
62	42	{
63		space.write_byte(0x82, hiaddress & 0xff);
64		space.write_byte(0x83, hiaddress >> 8);
65	43	}
66	44
67		QUI~~CKLOAD_LOAD_MEMBER(~~ c65_state, cbm_c65 )
	45	UINT32 c65_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
68	46	{
69		return ~~general_cbm_loadsnap(image, file_type, quickload_size, m_maincpu->space(AS_PROGRAM),~~ 0~~, cbm_c65_quick_sethiaddress)~~;
	47	return 0;
70	48	}
71	49
72		/*************************************
73		*
74		* Main CPU memory handlers
75		*
76		*************************************/
77
78		static ADDRESS_MAP_START( c65_mem , AS_PROGRAM, 8, c65_state )
79		AM_RANGE(0xf0000, 0xf7fff) AM_RAMBANK("bank11")
80		AM_RANGE(0xf8000, 0xf9fff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank12")
81		AM_RANGE(0xfa000, 0xfbfff) AM_READ_BANK("bank2") AM_WRITE_BANK("bank13")
82		AM_RANGE(0xfc000, 0xfcfff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank14")
83		AM_RANGE(0xfd000, 0xfd7ff) AM_READ_BANK("bank4") AM_WRITE_BANK("bank5")
84		AM_RANGE(0xfd800, 0xfdbff) AM_READ_BANK("bank6") AM_WRITE_BANK("bank7")
85		AM_RANGE(0xfdc00, 0xfdfff) AM_READ_BANK("bank8") AM_WRITE_BANK("bank9")
86		AM_RANGE(0xfe000, 0xfffff) AM_READ_BANK("bank10") AM_WRITE_BANK("bank15")
87		// AM_RANGE(0x10000, 0x1f7ff) AM_RAM
88		// AM_RANGE(0x1f800, 0x1ffff) AM_RAM AM_SHARE("colorram")
89		AM_RANGE(0x00000, 0x1ffff) AM_ROM AM_REGION("maincpu",0x20000)
90
91		AM_RANGE(0x20000, 0x207ff) AM_RAM AM_SHARE("colorram")
92
93		AM_RANGE(0x20000, 0x23fff) AM_ROM /* &c65_dos, maps to 0x8000 */
94		AM_RANGE(0x24000, 0x28fff) AM_ROM /* reserved */
95		AM_RANGE(0x29000, 0x29fff) AM_ROM AM_SHARE("c65_chargen")
96		AM_RANGE(0x2a000, 0x2bfff) AM_ROM AM_SHARE("basic")
97		AM_RANGE(0x2c000, 0x2cfff) AM_ROM AM_SHARE("interface")
98		AM_RANGE(0x2d000, 0x2dfff) AM_ROM AM_SHARE("chargen")
99		AM_RANGE(0x2e000, 0x2ffff) AM_ROM AM_SHARE("kernal")
100
101		AM_RANGE(0x30000, 0x31fff) AM_ROM /&c65_monitor, monitor maps to 0x6000 /
102		AM_RANGE(0x32000, 0x37fff) AM_ROM /&c65_basic, /
103		AM_RANGE(0x38000, 0x3bfff) AM_ROM /&c65_graphics, /
104		AM_RANGE(0x3c000, 0x3dfff) AM_ROM /* reserved */
105		AM_RANGE(0x3e000, 0x3ffff) AM_ROM /* &c65_kernal, */
106
107		AM_RANGE(0x40000, 0x7ffff) AM_NOP
108		/* 8 megabyte full address space! */
	50	static ADDRESS_MAP_START( c65_map, AS_PROGRAM, 8, c65_state )
	51	AM_RANGE(0x00000, 0x01fff) AM_RAM // TODO: bank
	52	AM_RANGE(0x0c800, 0x0cfff) AM_ROM AM_REGION("maincpu", 0xc800)
	53	// 0x0d000, 0x0d07f VIC-4567
	54	// 0x0d080, 0x0d09f FDC
	55	// 0x0d0a0, 0x0d0ff Ram Expansion Control (REC)
	56	// 0x0d100, 0x0d1ff Red Palette
	57	// 0x0d200, 0x0d2ff Green Palette
	58	// 0x0d300, 0x0d3ff Blue Palette
	59	// 0x0d400, 0x0d4*f Right SID
	60	// 0x0d440, 0x0d4*f Left SID
	61	// 0x0d600, 0x0d6** UART
	62	// 0x0d700, 0x0d7** DMAgic
	63	// 0x0d800, 0x0d8** Color matrix
	64	// 0x0dc00, 0x0dc** CIA-1
	65	// 0x0dd00, 0x0dd** CIA-2
	66	// 0x0de00, 0x0de** Ext I/O Select 1
	67	// 0x0df00, 0x0df** Ext I/O Select 2
	68	AM_RANGE(0x20000, 0x3ffff) AM_ROM AM_REGION("maincpu",0)
109	69	ADDRESS_MAP_END
110	70
111	71
112		/*************************************
113		*
114		* Input Ports
115		*
116		*************************************/
117	72
118	73	static INPUT_PORTS_START( c65 )
119		PORT_START( "ROW0" )
120		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Crsr Down Up") PORT_CODE(KEYCODE_RALT) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) PORT_CHAR(UCHAR_MAMEKEY(UP))
121		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F5))
122		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F3))
123		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1))
124		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F7))
125		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Crsr Right Left") PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
126		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
127		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("INST DEL") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) PORT_CHAR(UCHAR_MAMEKEY(INSERT))
	74	/* dummy active high structure */
	75	PORT_START("SYSA")
	76	PORT_DIPNAME( 0x01, 0x00, "SYSA" )
	77	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	78	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
	79	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
	80	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	81	PORT_DIPSETTING( 0x02, DEF_STR( On ) )
	82	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
	83	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	84	PORT_DIPSETTING( 0x04, DEF_STR( On ) )
	85	PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
	86	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	87	PORT_DIPSETTING( 0x08, DEF_STR( On ) )
	88	PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
	89	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	90	PORT_DIPSETTING( 0x10, DEF_STR( On ) )
	91	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
	92	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	93	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
	94	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	95	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	96	PORT_DIPSETTING( 0x40, DEF_STR( On ) )
	97	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
	98	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	99	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
128	100
129		PORT_START( "ROW1" )
130		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift (Left)") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
131		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('E')
132		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('S')
133		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('Z')
134		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
135		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('A')
136		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('W')
137		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
138
139		PORT_START( "ROW2" )
140		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('X')
141		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('T')
142		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('F')
143		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('C')
144		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
145		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('D')
146		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('R')
147		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
148
149		PORT_START( "ROW3" )
150		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('V')
151		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('U')
152		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('H')
153		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('B')
154		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
155		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('G')
156		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y')
157		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
158
159		PORT_START( "ROW4" )
160		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('N')
161		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('O')
162		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('K')
163		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('M')
164		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
165		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('J')
166		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('I')
167		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
168
169		PORT_START( "ROW5" )
170		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
171		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@')
172		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(':') PORT_CHAR('[')
173		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
174		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('-')
175		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('L')
176		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('P')
177		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('+')
178
179		PORT_START( "ROW6" )
180		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
181		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("\xE2\x86\x91 Pi") PORT_CODE(KEYCODE_DEL) PORT_CHAR(0x2191) PORT_CHAR(0x03C0)
182		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('=')
183		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift (Right)") PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
184		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("CLR HOME") PORT_CODE(KEYCODE_INSERT) PORT_CHAR(UCHAR_MAMEKEY(HOME))
185		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(';') PORT_CHAR(']')
186		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('*')
187		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('\xA3')
188
189		PORT_START( "ROW7" )
190		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("RUN STOP") PORT_CODE(KEYCODE_HOME)
191		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q')
192		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("CBM") PORT_CODE(KEYCODE_LALT)
193		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
194		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
195		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_SHIFT_2)
196		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("\xE2\x86\x90") PORT_CODE(KEYCODE_TILDE) PORT_CHAR(0x2190)
197		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
198		PORT_START("FUNCT")
199		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("ESC") PORT_CODE(KEYCODE_F1)
200		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F13 F14") PORT_CODE(KEYCODE_F11)
201		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F11 F12") PORT_CODE(KEYCODE_F10)
202		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F9 F10") PORT_CODE(KEYCODE_F9)
203		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("HELP") PORT_CODE(KEYCODE_F12)
204		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("ALT") PORT_CODE(KEYCODE_F2) /* non blocking */
205		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB)
206		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("NO SCRL") PORT_CODE(KEYCODE_F4)
207
208		PORT_START( "SPECIAL" ) /* special keys */
209		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Restore") PORT_CODE(KEYCODE_PRTSCR)
210		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift Lock (switch)") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
211		PORT_CONFNAME( 0x20, 0x00, "(C65) Caps Lock (switch)") PORT_CODE(KEYCODE_F3)
212		PORT_CONFSETTING( 0x00, DEF_STR( Off ) )
213		PORT_CONFSETTING( 0x20, DEF_STR( On ) )
214		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED )
215
216		PORT_START("CTRLSEL") /* Controller selection */
217		PORT_CONFNAME( 0x07, 0x00, "Gameport A" )
218		PORT_CONFSETTING( 0x00, DEF_STR( Joystick ) )
219		PORT_CONFSETTING( 0x01, "Paddles 1 & 2" )
220		PORT_CONFSETTING( 0x02, "Mouse 1351" )
221		PORT_CONFSETTING( 0x03, "Mouse (Non Proportional) 1350" )
222		PORT_CONFSETTING( 0x04, "Lightpen" )
223		// PORT_CONFSETTING( 0x05, "Koala Pad" )
224		PORT_CONFSETTING( 0x06, "Lightgun" )
225		PORT_CONFSETTING( 0x07, "No Device Connected" )
226		PORT_CONFNAME( 0x70, 0x00, "Gameport B" )
227		PORT_CONFSETTING( 0x00, DEF_STR( Joystick ) )
228		PORT_CONFSETTING( 0x10, "Paddles 3 & 4" )
229		// PORT_CONFSETTING( 0x20, "Mouse 1351" )
230		// PORT_CONFSETTING( 0x30, "Mouse (Non Proportional) 1350" )
231		PORT_CONFSETTING( 0x70, "No Device Connected" )
232		PORT_CONFNAME( 0x80, 0x00, "Swap Gameport A and B") PORT_CODE(KEYCODE_F1) PORT_TOGGLE
233		PORT_CONFSETTING( 0x00, DEF_STR( No ) )
234		PORT_CONFSETTING( 0x80, DEF_STR( Yes ) )
235
236		PORT_START("JOY1_1B")
237		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
238		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
239		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
240		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
241		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x00)
242		PORT_BIT( 0xe0, IP_ACTIVE_HIGH, IPT_UNUSED )
243
244		PORT_START("JOY2_1B")
245		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_HOME) PORT_CODE(JOYCODE_Y_UP_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
246		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_END) PORT_CODE(JOYCODE_Y_DOWN_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
247		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_DEL) PORT_CODE(JOYCODE_X_LEFT_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
248		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_PGDN) PORT_CODE(JOYCODE_X_RIGHT_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
249		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_CODE(KEYCODE_INSERT) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x00)
250		PORT_BIT( 0xe0, IP_ACTIVE_HIGH, IPT_UNUSED )
251
252		/* Mouse Commodore 1350 was basically working as a Joystick */
253		PORT_START("JOY1_2B")
254		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("Mouse 1350 Up") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
255		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("Mouse 1350 Down") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
256		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("Mouse 1350 Left") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
257		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1) PORT_NAME("Mouse 1350 Right") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
258		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1) PORT_NAME("Mouse 1350 Button 1") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
259		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(1) PORT_NAME("Mouse 1350 Button 2") PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x03)
260		PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
261
262		/* Still to verify how many mices you were able to plug into a c64 */
263		/* Only one, for now */
264		PORT_START("JOY2_2B")
265		PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED )
266		/* PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_HOME) PORT_CODE(JOYCODE_Y_UP_SWITCH)
267		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_END) PORT_CODE(JOYCODE_Y_DOWN_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
268		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_DEL) PORT_CODE(JOYCODE_X_LEFT_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
269		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2) PORT_CODE(KEYCODE_PGDN) PORT_CODE(JOYCODE_X_RIGHT_SWITCH) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
270		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_CODE(KEYCODE_INSERT) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
271		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2) PORT_CODE(KEYCODE_PGUP) PORT_CODE(JOYCODE_BUTTON2) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x30)
272		PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
273		*/
274		PORT_START("PADDLE1")
275		PORT_BIT( 0xff, 128, IPT_PADDLE) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_MINMAX(0,255) PORT_CENTERDELTA(0) PORT_CODE_DEC(KEYCODE_LEFT) PORT_CODE_INC(KEYCODE_RIGHT) PORT_CODE_DEC(JOYCODE_X_LEFT_SWITCH) PORT_CODE_INC(JOYCODE_X_RIGHT_SWITCH) PORT_PLAYER(1) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x01)
276
277		PORT_START("PADDLE2")
278		PORT_BIT( 0xff, 128, IPT_PADDLE) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_MINMAX(0,255) PORT_CENTERDELTA(0) PORT_CODE_DEC(KEYCODE_DOWN) PORT_CODE_INC(KEYCODE_UP) PORT_CODE_DEC(JOYCODE_Y_UP_SWITCH) PORT_CODE_INC(JOYCODE_Y_DOWN_SWITCH) PORT_PLAYER(2) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x01)
279
280		PORT_START("PADDLE3")
281		PORT_BIT( 0xff, 128, IPT_PADDLE) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_MINMAX(0,255) PORT_CENTERDELTA(0) PORT_CODE_DEC(KEYCODE_HOME) PORT_CODE_INC(KEYCODE_PGUP) PORT_PLAYER(3) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x10)
282
283		PORT_START("PADDLE4")
284		PORT_BIT( 0xff, 128, IPT_PADDLE) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_MINMAX(0,255) PORT_CENTERDELTA(0) PORT_CODE_DEC(KEYCODE_END) PORT_CODE_INC(KEYCODE_PGDN) PORT_PLAYER(4) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x10)
285
286		PORT_START("TRACKX")
287		PORT_BIT( 0x7e, 0x00, IPT_TRACKBALL_X) PORT_SENSITIVITY(100) PORT_KEYDELTA(0) PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x02)
288
289		PORT_START("TRACKY")
290		PORT_BIT( 0x7e, 0x00, IPT_TRACKBALL_Y) PORT_SENSITIVITY(100) PORT_KEYDELTA(0) PORT_PLAYER(1) PORT_REVERSE PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x02)
291
292		PORT_START("LIGHTX")
293		PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X) PORT_NAME("Lightpen X Axis") PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x04)
294
295		PORT_START("LIGHTY")
296		PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y) PORT_NAME("Lightpen Y Axis") PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(30) PORT_KEYDELTA(20) PORT_PLAYER(1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x04)
297
298		PORT_START("OTHER")
299		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_BUTTON1) PORT_NAME("Paddle 1 Button") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x01)
300		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_BUTTON2) PORT_NAME("Paddle 2 Button") PORT_CODE(KEYCODE_LALT) PORT_CODE(JOYCODE_BUTTON2) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x01)
301		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON3) PORT_NAME("Paddle 3 Button") PORT_CODE(KEYCODE_INSERT) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x10)
302		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON4) PORT_NAME("Paddle 4 Button") PORT_CODE(KEYCODE_DEL) PORT_CODE(JOYCODE_BUTTON2) PORT_CONDITION("CTRLSEL", 0xf0, EQUALS, 0x10)
303		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1) PORT_NAME("Lightpen Signal") PORT_CODE(KEYCODE_LCONTROL) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x04)
304		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1) PORT_NAME("Mouse Button Left") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(JOYCODE_BUTTON1) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x02)
305		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON2) PORT_NAME("Mouse Button Right") PORT_CODE(KEYCODE_LALT) PORT_CODE(JOYCODE_BUTTON2) PORT_CONDITION("CTRLSEL", 0x0f, EQUALS, 0x02)INPUT_PORTS_END
306
307
308		static INPUT_PORTS_START( c65ger )
309		PORT_INCLUDE( c65 )
310
311		PORT_MODIFY( "ROW1" )
312		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Z { Y }") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z')
313		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("3 # { 3 Paragraph }") PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
314
315		PORT_MODIFY( "ROW3" )
316		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y { Z }") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y')
317		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("7 ' { 7 / }") PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
318
319		PORT_MODIFY( "ROW4" )
320		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("0 { = }") PORT_CODE(KEYCODE_0) PORT_CHAR('0')
321
322		PORT_MODIFY( "ROW5" )
323		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(", < { ; }") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
324		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Paragraph \xE2\x86\x91 { \xc3\xbc }") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR(0x00A7) PORT_CHAR(0x2191)
325		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(": [ { \xc3\xa4 }") PORT_CODE(KEYCODE_COLON) PORT_CHAR(':') PORT_CHAR('[')
326		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(". > { : }") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
327		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("- { ' ` }") PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('-')
328		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("+ { \xc3\x9f ? }") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('+')
329
330		PORT_MODIFY( "ROW6" )
331		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/ ? { - _ }") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
332		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Sum Pi { ] \\ }") PORT_CODE(KEYCODE_DEL) PORT_CHAR(0x03A3) PORT_CHAR(0x03C0)
333		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("= { # ' }") PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('=')
334		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("; ] { \xc3\xb6 }") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(';') PORT_CHAR(']')
335		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("* ` { + * }") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('*') PORT_CHAR('`')
336		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("\\ { [ \xE2\x86\x91 }") PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('\xa3')
337
338		PORT_MODIFY( "ROW7" )
339		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("_ { < > }") PORT_CODE(KEYCODE_TILDE) PORT_CHAR('_')
340
341		PORT_MODIFY("SPECIAL") /* special keys */
342		PORT_DIPNAME( 0x20, 0x00, "(C65) DIN ASC (switch)") PORT_CODE(KEYCODE_F3)
343		PORT_DIPSETTING( 0x00, "ASC" )
344		PORT_DIPSETTING( 0x20, "DIN" )
	101	/* dummy active low structure */
	102	PORT_START("DSWA")
	103	PORT_DIPNAME( 0x01, 0x01, "DSWA" )
	104	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	105	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	106	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	107	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	108	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	109	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	110	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	111	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	112	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
	113	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	114	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	115	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	116	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	117	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	118	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
	119	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	120	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	121	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
	122	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	123	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	124	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
	125	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	126	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
345	127	INPUT_PORTS_END
346	128
347	129
348
349		/*************************************
350		*
351		* Sound definitions
352		*
353		*************************************/
354
355		int c65_state::c64_paddle_read( device_t *device, address_space &space, int which )
	130	void c65_state::machine_start()
356	131	{
357		int pot1 = 0xff, pot2 = 0xff, pot3 = 0xff, pot4 = 0xff, temp;
358		UINT8 cia0porta = machine().device<mos6526_device>("cia_0")->pa_r(space, 0);
359		int controller1 = ioport("CTRLSEL")->read() & 0x07;
360		int controller2 = ioport("CTRLSEL")->read() & 0x70;
361		/* Notice that only a single input is defined for Mouse & Lightpen in both ports */
362		switch (controller1)
363		{
364		case 0x01:
365		if (which)
366		pot2 = ioport("PADDLE2")->read();
367		else
368		pot1 = ioport("PADDLE1")->read();
369		break;
370
371		case 0x02:
372		if (which)
373		pot2 = ioport("TRACKY")->read();
374		else
375		pot1 = ioport("TRACKX")->read();
376		break;
377
378		case 0x03:
379		if (which && (ioport("JOY1_2B")->read() & 0x20)) /* Joy1 Button 2 */
380		pot1 = 0x00;
381		break;
382
383		case 0x04:
384		if (which)
385		pot2 = ioport("LIGHTY")->read();
386		else
387		pot1 = ioport("LIGHTX")->read();
388		break;
389
390		case 0x06:
391		if (which && (ioport("OTHER")->read() & 0x04)) /* Lightpen Signal */
392		pot2 = 0x00;
393		break;
394
395		case 0x00:
396		case 0x07:
397		break;
398
399		default:
400		logerror("Invalid Controller Setting %d\n", controller1);
401		break;
402		}
403
404		switch (controller2)
405		{
406		case 0x10:
407		if (which)
408		pot4 = ioport("PADDLE4")->read();
409		else
410		pot3 = ioport("PADDLE3")->read();
411		break;
412
413		case 0x20:
414		if (which)
415		pot4 = ioport("TRACKY")->read();
416		else
417		pot3 = ioport("TRACKX")->read();
418		break;
419
420		case 0x30:
421		if (which && (ioport("JOY2_2B")->read() & 0x20)) /* Joy2 Button 2 */
422		pot4 = 0x00;
423		break;
424
425		case 0x40:
426		if (which)
427		pot4 = ioport("LIGHTY")->read();
428		else
429		pot3 = ioport("LIGHTX")->read();
430		break;
431
432		case 0x60:
433		if (which && (ioport("OTHER")->read() & 0x04)) /* Lightpen Signal */
434		pot4 = 0x00;
435		break;
436
437		case 0x00:
438		case 0x70:
439		break;
440
441		default:
442		logerror("Invalid Controller Setting %d\n", controller1);
443		break;
444		}
445
446		if (ioport("CTRLSEL")->read() & 0x80) /* Swap */
447		{
448		temp = pot1; pot1 = pot3; pot3 = temp;
449		temp = pot2; pot2 = pot4; pot4 = temp;
450		}
451
452		switch (cia0porta & 0xc0)
453		{
454		case 0x40:
455		return which ? pot2 : pot1;
456
457		case 0x80:
458		return which ? pot4 : pot3;
459
460		case 0xc0:
461		return which ? pot2 : pot1;
462
463		default:
464		return 0;
465		}
466	132	}
467	133
468		~~READ8_MEMBER(~~ c65_state::sid_~~potx_~~r )
	134	void c65_state::machine_reset()
469	135	{
470		return c64_paddle_read(m_sid_r, space, 0);
471	136	}
472	137
473		READ8_MEMBER( c65_state::sid_poty_r )
474		{
475		return c64_paddle_read(m_sid_r, space, 1);
476		}
477	138
478
479		/*************************************
480		*
481		* VIC III interfaces
482		*
483		*************************************/
484
485		UINT32 c65_state::screen_update_c65(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	139	PALETTE_INIT_MEMBER(c65_state, c65)
486	140	{
487		m_vic->video_update(bitmap, cliprect);
488		return 0;
489	141	}
490	142
491		READ8_MEMBER(c65_state::c65_lightpen_x_cb)
492		{
493		return ioport("LIGHTX")->read() & ~0x01;
494		}
495
496		READ8_MEMBER(c65_state::c65_lightpen_y_cb)
497		{
498		return ioport("LIGHTY")->read() & ~0x01;
499		}
500
501		READ8_MEMBER(c65_state::c65_lightpen_button_cb)
502		{
503		return ioport("OTHER")->read() & 0x04;
504		}
505
506		READ8_MEMBER(c65_state::c65_c64_mem_r)
507		{
508		return m_memory[offset];
509		}
510
511		INTERRUPT_GEN_MEMBER(c65_state::vic3_raster_irq)
512		{
513		m_vic->raster_interrupt_gen();
514		}
515
516		/*************************************
517		*
518		* Machine driver
519		*
520		*************************************/
521
522	143	static MACHINE_CONFIG_START( c65, c65_state )
	144
523	145	/* basic machine hardware */
524		MCFG_CPU_ADD("maincpu", M4510, 3500000) /* or VIC6567_CLOCK, */
525		MCFG_CPU_PROGRAM_MAP(c65_mem)
526		MCFG_CPU_VBLANK_INT_DRIVER("screen", c65_state, c65_frame_interrupt)
527		MCFG_CPU_PERIODIC_INT_DRIVER(c65_state, vic3_raster_irq, VIC6567_HRETRACERATE)
	146	MCFG_CPU_ADD("maincpu",M4510,MAIN_CLOCK/2)
	147	MCFG_CPU_PROGRAM_MAP(c65_map)
528	148
529		MCFG_MACHINE_START_OVERRIDE(c65_state, c65 )
530
531	149	/* video hardware */
532	150	MCFG_SCREEN_ADD("screen", RASTER)
533		MCFG_SCREEN_REFRESH_RATE(VIC6567_VRETRACERATE)
534		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
535		MCFG_SCREEN_SIZE(525 * 2, 520 * 2)
536		MCFG_SCREEN_VISIBLE_AREA(VIC6567_STARTVISIBLECOLUMNS ,(VIC6567_STARTVISIBLECOLUMNS + VIC6567_VISIBLECOLUMNS - 1) * 2, VIC6567_STARTVISIBLELINES, VIC6567_STARTVISIBLELINES + VIC6567_VISIBLELINES - 1)
537		MCFG_SCREEN_UPDATE_DRIVER(c65_state, screen_update_c65)
538		MCFG_SCREEN_PALETTE("vic3:palette")
	151	// MCFG_SCREEN_REFRESH_RATE(60)
	152	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
	153	MCFG_SCREEN_UPDATE_DRIVER(c65_state, screen_update)
	154	// MCFG_SCREEN_SIZE(328, 328)
	155	// MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
	156	MCFG_SCREEN_RAW_PARAMS(MAIN_CLOCK/2, 442, 0, 320, 264, 0, 240) /* generic NTSC video timing, change accordingly */
	157	MCFG_SCREEN_PALETTE("palette")
539	158
540		MCFG_DEVICE_ADD("vic3", VIC3, 0)
541		MCFG_VIC3_CPU("maincpu")
542		MCFG_VIC3_TYPE(VIC4567_NTSC)
543		MCFG_VIC3_LIGHTPEN_X_CB(READ8(c65_state, c65_lightpen_x_cb))
544		MCFG_VIC3_LIGHTPEN_Y_CB(READ8(c65_state, c65_lightpen_y_cb))
545		MCFG_VIC3_LIGHTPEN_BUTTON_CB(READ8(c65_state, c65_lightpen_button_cb))
546		MCFG_VIC3_DMA_READ_CB(READ8(c65_state, c65_dma_read))
547		MCFG_VIC3_DMA_READ_COLOR_CB(READ8(c65_state, c65_dma_read_color))
548		MCFG_VIC3_INTERRUPT_CB(WRITELINE(c65_state, c65_vic_interrupt))
549		MCFG_VIC3_PORT_CHANGED_CB(WRITE8(c65_state, c65_bankswitch_interface))
550		MCFG_VIC3_C64_MEM_R_CB(READ8(c65_state, c65_c64_mem_r))
	159	MCFG_PALETTE_ADD("palette", 0x100)
	160	MCFG_PALETTE_INIT_OWNER(c65_state, c65)
551	161
552	162	/* sound hardware */
553		MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
554		MCFG_SOUND_ADD("sid_r", MOS8580, 985248)
555		MCFG_MOS6581_POTX_CALLBACK(READ8(c65_state, sid_potx_r))
556		MCFG_MOS6581_POTY_CALLBACK(READ8(c65_state, sid_poty_r))
557		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
558		MCFG_SOUND_ADD("sid_l", MOS8580, 985248)
559		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
560
561		/* quickload */
562		MCFG_QUICKLOAD_ADD("quickload", c65_state, cbm_c65, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
563
564		/* cia */
565		MCFG_DEVICE_ADD("cia_0", MOS6526, 3500000)
566		MCFG_MOS6526_TOD(60)
567		MCFG_MOS6526_IRQ_CALLBACK(WRITELINE(c65_state, c65_cia0_interrupt))
568		MCFG_MOS6526_PA_INPUT_CALLBACK(READ8(c65_state, c65_cia0_port_a_r))
569		MCFG_MOS6526_PB_INPUT_CALLBACK(READ8(c65_state, c65_cia0_port_b_r))
570		MCFG_MOS6526_PB_OUTPUT_CALLBACK(WRITE8(c65_state, c65_cia0_port_b_w))
571
572		MCFG_DEVICE_ADD("cia_1", MOS6526, 3500000)
573		MCFG_MOS6526_TOD(60)
574		MCFG_MOS6526_IRQ_CALLBACK(WRITELINE(c65_state, c65_cia1_interrupt))
575		MCFG_MOS6526_PA_INPUT_CALLBACK(READ8(c65_state, c65_cia1_port_a_r))
576		MCFG_MOS6526_PA_OUTPUT_CALLBACK(WRITE8(c65_state, c65_cia1_port_a_w))
577
578		/* floppy from serial bus */
579		MCFG_CBM_IEC_ADD(NULL)
580
581		/* internal ram */
582		MCFG_RAM_ADD(RAM_TAG)
583		MCFG_RAM_DEFAULT_SIZE("128K")
584		MCFG_RAM_EXTRA_OPTIONS("640K,4224K")
	163	MCFG_SPEAKER_STANDARD_MONO("mono")
	164	// MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/4)
	165	// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
585	166	MACHINE_CONFIG_END
586	167
587		static MACHINE_CONFIG_DERIVED( c65pal, c65 )
588		MCFG_SCREEN_MODIFY("screen")
589		MCFG_SCREEN_REFRESH_RATE(VIC6569_VRETRACERATE)
590		MCFG_SCREEN_SIZE(625 * 2, 520 * 2)
591		MCFG_SCREEN_VISIBLE_AREA(VIC6569_STARTVISIBLECOLUMNS, (VIC6569_STARTVISIBLECOLUMNS + VIC6569_VISIBLECOLUMNS - 1) * 2, VIC6569_STARTVISIBLELINES, VIC6569_STARTVISIBLELINES + VIC6569_VISIBLELINES - 1)
592		MCFG_SCREEN_PALETTE("vic3:palette")
593	168
594		MCFG_DEVICE_MODIFY("vic3")
595		MCFG_VIC3_TYPE(VIC4567_PAL)
	169	/***************************************************************************
596	170
597		/* sound hardware */
598		MCFG_SOUND_REPLACE("sid_r", MOS8580, 1022727)
599		MCFG_MOS6581_POTX_CALLBACK(READ8(c65_state, sid_potx_r))
600		MCFG_MOS6581_POTY_CALLBACK(READ8(c65_state, sid_poty_r))
601		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
602		MCFG_SOUND_REPLACE("sid_l", MOS8580, 1022727)
603		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
	171	Game driver(s)
604	172
605		/* cia */
606		MCFG_DEVICE_MODIFY("cia_0")
607		MCFG_MOS6526_TOD(50)
	173	***************************************************************************/
608	174
609		MCFG_DEVICE_MODIFY("cia_1")
610		MCFG_MOS6526_TOD(50)
611		MACHINE_CONFIG_END
612
613
614		/*************************************
615		*
616		* ROM definition(s)
617		*
618		*************************************/
619
620
621	175	ROM_START( c65 )
622		ROM_REGION( 0x400000, "maincpu", 0 )
	176	ROM_REGION( 0x20000, "maincpu", 0 )
623	177	ROM_SYSTEM_BIOS( 0, "910111", "V0.9.910111" )
624		ROMX_LOAD( "910111.bin", 0x20000, 0x20000, CRC(c5d8d32e) SHA1(71c05f098eff29d306b0170e2c1cdeadb1a5f206), ROM_BIOS(1) )
	178	ROMX_LOAD( "910111.bin", 0x0000, 0x20000, CRC(c5d8d32e) SHA1(71c05f098eff29d306b0170e2c1cdeadb1a5f206), ROM_BIOS(1) )
625	179	ROM_SYSTEM_BIOS( 1, "910523", "V0.9.910523" )
626		ROMX_LOAD( "910523.bin", 0x20000, 0x20000, CRC(e8235dd4) SHA1(e453a8e7e5b95de65a70952e9d48012191e1b3e7), ROM_BIOS(2) )
	180	ROMX_LOAD( "910523.bin", 0x0000, 0x20000, CRC(e8235dd4) SHA1(e453a8e7e5b95de65a70952e9d48012191e1b3e7), ROM_BIOS(2) )
627	181	ROM_SYSTEM_BIOS( 2, "910626", "V0.9.910626" )
628		ROMX_LOAD( "910626.bin", 0x20000, 0x20000, CRC(12527742) SHA1(07c185b3bc58410183422f7ac13a37ddd330881b), ROM_BIOS(3) )
	182	ROMX_LOAD( "910626.bin", 0x0000, 0x20000, CRC(12527742) SHA1(07c185b3bc58410183422f7ac13a37ddd330881b), ROM_BIOS(3) )
629	183	ROM_SYSTEM_BIOS( 3, "910828", "V0.9.910828" )
630		ROMX_LOAD( "910828.bin", 0x20000, 0x20000, CRC(3ee40b06) SHA1(b63d970727a2b8da72a0a8e234f3c30a20cbcb26), ROM_BIOS(4) )
	184	ROMX_LOAD( "910828.bin", 0x0000, 0x20000, CRC(3ee40b06) SHA1(b63d970727a2b8da72a0a8e234f3c30a20cbcb26), ROM_BIOS(4) )
631	185	ROM_SYSTEM_BIOS( 4, "911001", "V0.9.911001" )
632		ROMX_LOAD( "911001.bin", 0x20000, 0x20000, CRC(0888b50f) SHA1(129b9a2611edaebaa028ac3e3f444927c8b1fc5d), ROM_BIOS(5) )
	186	ROMX_LOAD( "911001.bin", 0x0000, 0x20000, CRC(0888b50f) SHA1(129b9a2611edaebaa028ac3e3f444927c8b1fc5d), ROM_BIOS(5) )
633	187	ROM_END
634	188
635	189	ROM_START( c64dx )
636		ROM_REGION( 0x400000, "maincpu", 0 )
637		ROM_LOAD( "910429.bin", 0x20000, 0x20000, CRC(b025805c) SHA1(c3b05665684f74adbe33052a2d10170a1063ee7d) )
	190	ROM_REGION( 0x20000, "maincpu", 0 )
	191	ROM_LOAD( "910429.bin", 0x0000, 0x20000, CRC(b025805c) SHA1(c3b05665684f74adbe33052a2d10170a1063ee7d) )
638	192	ROM_END
639	193
640		/***************************************************************************
	194	DRIVER_INIT_MEMBER(c65_state,c65)
	195	{
	196	// m_dma.version = 2;
	197	// c65_common_driver_init();
	198	}
641	199
642		Game driver(s)
	200	DRIVER_INIT_MEMBER(c65_state,c65pal)
	201	{
	202	// m_dma.version = 1;
	203	// c65_common_driver_init();
	204	// m_pal = 1;
	205	}
643	206
644		***************************************************************************/
645
646		/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
647
648		COMP( 1991, c65, 0, 0, c65, c65, c65_state, c65, "Commodore Business Machines", "Commodore 65 Development System (Prototype, NTSC)", GAME_NOT_WORKING )
649		COMP( 1991, c64dx, c65, 0, c65pal, c65ger, c65_state, c65pal, "Commodore Business Machines", "Commodore 64DX Development System (Prototype, PAL, German)", GAME_NOT_WORKING )
	207	COMP( 1991, c65, 0, 0, c65, c65, c65_state, c65, "Commodore Business Machines", "Commodore 65 Development System (Prototype, NTSC)", GAME_NOT_WORKING )
	208	COMP( 1991, c64dx, c65, 0, c65, c65, c65_state, c65pal, "Commodore Business Machines", "Commodore 64DX Development System (Prototype, PAL, German)", GAME_NOT_WORKING )

branches/kale/src/mess/includes/c65.h
r243076	r243077
1		/*****************************************************************************
2		*
3		* includes/c65.h
4		*
5		****************************************************************************/
6	1
7		#ifndef C65_H_
8		#define C65_H_
9
10		#include "machine/mos6526.h"
11		#include "bus/cbmiec/cbmiec.h"
12		#include "imagedev/snapquik.h"
13		#include "machine/ram.h"
14		#include "sound/mos6581.h"
15		#include "video/vic4567.h"
16
17		#define C64_MAX_ROMBANK 64 // .crt files contain multiple 'CHIPs', i.e. rom banks (of variable size) with headers. Known carts have at most 64 'CHIPs'.
18
19		struct C64_ROM {
20		int addr, size, index, start;
21		};
22
23		struct c64_cart_t {
24		C64_ROM bank[C64_MAX_ROMBANK];
25		INT8 game;
26		INT8 exrom;
27		UINT8 mapper;
28		UINT8 n_banks;
29		};
30
31		struct dma_t
32		{
33		int version;
34		UINT8 data[4];
35		};
36
37		struct fdc_t
38		{
39		int state;
40
41		UINT8 reg[0x0f];
42
43		UINT8 buffer[0x200];
44		int cpu_pos;
45		int fdc_pos;
46
47		UINT16 status;
48
49		attotime time;
50		int head,track,sector;
51		};
52
53		struct expansion_ram_t
54		{
55		UINT8 reg;
56		};
57
58		class c65_state : public driver_device
59		{
60		public:
61		c65_state(const machine_config &mconfig, device_type type, const char *tag)
62		: driver_device(mconfig, type, tag),
63		m_cia0(*this, "cia_0"),
64		m_cia1(*this, "cia_1"),
65		m_sid_r(*this, "sid_r"),
66		m_vic(*this, "vic3"),
67		m_iec(*this, CBM_IEC_TAG),
68		m_colorram(*this, "colorram"),
69		m_basic(*this, "basic"),
70		m_chargen(*this, "chargen"),
71		m_kernal(*this, "kernal"),
72		m_c65_chargen(*this, "c65_chargen"),
73		m_interface(*this, "interface"),
74		m_roml_writable(0),
75		m_maincpu(*this, "maincpu"),
76		m_ram(*this, RAM_TAG) { }
77
78		required_device<mos6526_device> m_cia0;
79		required_device<mos6526_device> m_cia1;
80		required_device<mos6581_device> m_sid_r;
81		required_device<vic3_device> m_vic;
82		optional_device<cbm_iec_device> m_iec;
83
84		required_shared_ptr<UINT8> m_colorram;
85		required_shared_ptr<UINT8> m_basic;
86		required_shared_ptr<UINT8> m_chargen;
87		required_shared_ptr<UINT8> m_kernal;
88		required_shared_ptr<UINT8> m_c65_chargen;
89		required_shared_ptr<UINT8> m_interface;
90		int m_old_level;
91		int m_old_data;
92		int m_old_exrom;
93		int m_old_game;
94		UINT8 m_vicirq;
95		emu_timer *m_datasette_timer;
96		emu_timer *m_cartridge_timer;
97		UINT8 *m_memory;
98		int m_pal;
99		int m_tape_on;
100		UINT8 *m_c64_roml;
101		UINT8 *m_c64_romh;
102		UINT8 *m_vicaddr;
103		UINT8 *m_c128_vicaddr;
104		UINT8 m_game;
105		UINT8 m_exrom;
106		UINT8 *m_io_mirror;
107		UINT8 m_port_data;
108		UINT8 *m_roml;
109		UINT8 *m_romh;
110		int m_roml_writable;
111		int m_ultimax;
112		int m_cia1_on;
113		int m_io_enabled;
114		int m_is_sx64;
115		UINT8 *m_io_ram_w_ptr;
116		UINT8 *m_io_ram_r_ptr;
117		c64_cart_t m_cart;
118		int m_nmilevel; int m_charset_select;
119		int m_c64mode;
120		UINT8 m_6511_port;
121		UINT8 m_keyline;
122		int m_old_value;
123		dma_t m_dma;
124		int m_dump_dma;
125		fdc_t m_fdc;
126		expansion_ram_t m_expansion_ram;
127		int m_io_on;
128		int m_io_dc00_on;
129		int m_cia0_irq, m_cia1_irq;
130		DECLARE_DRIVER_INIT(c65);
131		DECLARE_DRIVER_INIT(c65pal);
132
133		DECLARE_READ8_MEMBER( c64_lightpen_x_cb );
134		DECLARE_READ8_MEMBER( c64_lightpen_y_cb );
135		DECLARE_READ8_MEMBER( c64_lightpen_button_cb );
136		DECLARE_READ8_MEMBER( c64_dma_read );
137		DECLARE_READ8_MEMBER( c64_dma_read_ultimax );
138		DECLARE_READ8_MEMBER( c64_dma_read_color );
139		DECLARE_WRITE_LINE_MEMBER( c64_vic_interrupt );
140		DECLARE_READ8_MEMBER( c64_rdy_cb );
141		DECLARE_READ8_MEMBER( sid_potx_r );
142		DECLARE_READ8_MEMBER( sid_poty_r );
143		DECLARE_MACHINE_START(c65);
144		UINT32 screen_update_c65(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
145		INTERRUPT_GEN_MEMBER(vic3_raster_irq);
146		INTERRUPT_GEN_MEMBER(c65_frame_interrupt);
147		DECLARE_READ8_MEMBER(c65_cia0_port_a_r);
148		DECLARE_READ8_MEMBER(c65_cia0_port_b_r);
149		DECLARE_WRITE8_MEMBER(c65_cia0_port_b_w);
150		DECLARE_READ8_MEMBER(c65_cia1_port_a_r);
151		DECLARE_WRITE8_MEMBER(c65_cia1_port_a_w);
152		DECLARE_WRITE_LINE_MEMBER(c65_cia1_interrupt);
153		void c64_legacy_driver_init();
154		DECLARE_DEVICE_IMAGE_LOAD_MEMBER( c64_cart );
155		DECLARE_DEVICE_IMAGE_UNLOAD_MEMBER( c64_cart );
156		DECLARE_WRITE_LINE_MEMBER(c65_cia0_interrupt);
157		DECLARE_READ8_MEMBER(c65_lightpen_x_cb);
158		DECLARE_READ8_MEMBER(c65_lightpen_y_cb);
159		DECLARE_READ8_MEMBER(c65_lightpen_button_cb);
160		DECLARE_READ8_MEMBER(c65_c64_mem_r);
161		DECLARE_READ8_MEMBER(c65_dma_read);
162		DECLARE_READ8_MEMBER(c65_dma_read_color);
163		DECLARE_WRITE_LINE_MEMBER(c65_vic_interrupt);
164		DECLARE_WRITE8_MEMBER(c65_bankswitch_interface);
165		DECLARE_READ8_MEMBER( c65_read_mem );
166		DECLARE_WRITE8_MEMBER( c65_write_mem );
167		DECLARE_READ8_MEMBER( c65_ram_expansion_r );
168		DECLARE_WRITE8_MEMBER( c65_ram_expansion_w );
169		DECLARE_WRITE8_MEMBER( c65_write_io );
170		DECLARE_WRITE8_MEMBER( c65_write_io_dc00 );
171		DECLARE_READ8_MEMBER( c65_read_io );
172		DECLARE_READ8_MEMBER( c65_read_io_dc00 );
173		DECLARE_QUICKLOAD_LOAD_MEMBER( cbm_c65 );
174
175		int c64_paddle_read( device_t *device, address_space &space, int which );
176		void c65_nmi( );
177		void c65_irq( int level );
178		void c65_dma_port_w( int offset, int value );
179		int c65_dma_port_r( int offset );
180		void c65_6511_port_w( int offset, int value );
181		int c65_6511_port_r( int offset );
182		void c65_fdc_state(void);
183		void c65_fdc_w( int offset, int data );
184		int c65_fdc_r( int offset );
185		void c65_bankswitch( );
186		void c65_colorram_write( int offset, int value );
187		void c65_common_driver_init( );
188
189		required_device<cpu_device> m_maincpu;
190		required_device<ram_device> m_ram;
191		};
192
193		MACHINE_CONFIG_EXTERN( c64_cartslot );
194
195		#endif /* C65_H_ */

branches/kale/src/mess/machine/c65.c
r243076	r243077
1		/***************************************************************************
2		commodore c65 home computer
3		peter.trauner@jk.uni-linz.ac.at
4		documention
5		www.funet.fi
6		***************************************************************************/
7	1
8		#include "emu.h"
9
10		#include "includes/c65.h"
11		#include "cpu/m6502/m4510.h"
12		#include "sound/mos6581.h"
13		#include "machine/mos6526.h"
14		#include "bus/cbmiec/cbmiec.h"
15		#include "machine/ram.h"
16		#include "video/vic4567.h"
17		#include "imagedev/cassette.h"
18		#include "crsshair.h"
19		#include "formats/cbm_tap.h"
20
21		#define VERBOSE_LEVEL 0
22		#define DBG_LOG( MACHINE, N, M, A ) \
23		do { \
24		if(VERBOSE_LEVEL >= N) \
25		{ \
26		if( M ) \
27		logerror("%11.6f: %-24s", MACHINE.time().as_double(), (char*) M ); \
28		logerror A; \
29		} \
30		} while (0)
31
32
33
34		/***********************************************
35
36		Input Reading - Common Components
37
38		***********************************************/
39
40		/* These are needed by c64, c65 and c128, each machine has also additional specific
41		components in its INTERRUPT_GEN */
42
43		/* keyboard lines */
44		UINT8 c64_keyline[10];
45
46		void cbm_common_init(void)
47		{
48		int i;
49
50		for (i = 0; i < ARRAY_LENGTH(c64_keyline); i++)
51		c64_keyline[i] = 0xff;
52		}
53
54		static TIMER_CALLBACK( lightpen_tick )
55		{
56		if (((machine.root_device().ioport("CTRLSEL")->read() & 0x07) == 0x04) \|\| ((machine.root_device().ioport("CTRLSEL")->read() & 0x07) == 0x06))
57		{
58		/* enable lightpen crosshair */
59		crosshair_set_screen(machine, 0, CROSSHAIR_SCREEN_ALL);
60		}
61		else
62		{
63		/* disable lightpen crosshair */
64		crosshair_set_screen(machine, 0, CROSSHAIR_SCREEN_NONE);
65		}
66		}
67
68		void cbm_common_interrupt( device_t *device )
69		{
70		int value, i;
71		int controller1 = device->machine().root_device().ioport("CTRLSEL")->read() & 0x07;
72		int controller2 = device->machine().root_device().ioport("CTRLSEL")->read() & 0x70;
73		static const char *const c64ports[] = { "ROW0", "ROW1", "ROW2", "ROW3", "ROW4", "ROW5", "ROW6", "ROW7" };
74
75		/* Lines 0-7 : common keyboard */
76		for (i = 0; i < 8; i++)
77		{
78		value = 0xff;
79		value &= ~device->machine().root_device().ioport(c64ports[i])->read();
80
81		/* Shift Lock is mapped on Left Shift */
82		if ((i == 1) && (device->machine().root_device().ioport("SPECIAL")->read() & 0x40))
83		value &= ~0x80;
84
85		c64_keyline[i] = value;
86		}
87
88
89		value = 0xff;
90		switch(controller1)
91		{
92		case 0x00:
93		value &= ~device->machine().root_device().ioport("JOY1_1B")->read(); /* Joy1 Directions + Button 1 */
94		break;
95
96		case 0x01:
97		if (device->machine().root_device().ioport("OTHER")->read() & 0x40) /* Paddle2 Button */
98		value &= ~0x08;
99		if (device->machine().root_device().ioport("OTHER")->read() & 0x80) /* Paddle1 Button */
100		value &= ~0x04;
101		break;
102
103		case 0x02:
104		if (device->machine().root_device().ioport("OTHER")->read() & 0x02) /* Mouse Button Left */
105		value &= ~0x10;
106		if (device->machine().root_device().ioport("OTHER")->read() & 0x01) /* Mouse Button Right */
107		value &= ~0x01;
108		break;
109
110		case 0x03:
111		value &= ~(device->machine().root_device().ioport("JOY1_2B")->read() & 0x1f); /* Joy1 Directions + Button 1 */
112		break;
113
114		case 0x04:
115		/* was there any input on the lightpen? where is it mapped? */
116		// if (device->machine().root_device().ioport("OTHER")->read() & 0x04) /* Lightpen Signal */
117		// value &= ?? ;
118		break;
119
120		case 0x07:
121		break;
122
123		default:
124		logerror("Invalid Controller 1 Setting %d\n", controller1);
125		break;
126		}
127
128		c64_keyline[8] = value;
129
130
131		value = 0xff;
132		switch(controller2)
133		{
134		case 0x00:
135		value &= ~device->machine().root_device().ioport("JOY2_1B")->read(); /* Joy2 Directions + Button 1 */
136		break;
137
138		case 0x10:
139		if (device->machine().root_device().ioport("OTHER")->read() & 0x10) /* Paddle4 Button */
140		value &= ~0x08;
141		if (device->machine().root_device().ioport("OTHER")->read() & 0x20) /* Paddle3 Button */
142		value &= ~0x04;
143		break;
144
145		case 0x20:
146		if (device->machine().root_device().ioport("OTHER")->read() & 0x02) /* Mouse Button Left */
147		value &= ~0x10;
148		if (device->machine().root_device().ioport("OTHER")->read() & 0x01) /* Mouse Button Right */
149		value &= ~0x01;
150		break;
151
152		case 0x30:
153		value &= ~(device->machine().root_device().ioport("JOY2_2B")->read() & 0x1f); /* Joy2 Directions + Button 1 */
154		break;
155
156		case 0x40:
157		/* was there any input on the lightpen? where is it mapped? */
158		// if (device->machine().root_device().ioport("OTHER")->read() & 0x04) /* Lightpen Signal */
159		// value &= ?? ;
160		break;
161
162		case 0x70:
163		break;
164
165		default:
166		logerror("Invalid Controller 2 Setting %d\n", controller2);
167		break;
168		}
169
170		c64_keyline[9] = value;
171
172		// vic2_frame_interrupt does nothing so this is not necessary
173		// vic2_frame_interrupt (device);
174
175		/* check if lightpen has been chosen as input: if so, enable crosshair */
176		device->machine().scheduler().timer_set(attotime::zero, FUNC(lightpen_tick));
177
178		set_led_status (device->machine(), 1, device->machine().root_device().ioport("SPECIAL")->read() & 0x40 ? 1 : 0); /* Shift Lock */
179		set_led_status (device->machine(), 0, device->machine().root_device().ioport("CTRLSEL")->read() & 0x80 ? 1 : 0); /* Joystick Swap */
180		}
181
182
183		/***********************************************
184
185		CIA Common Handlers
186
187		***********************************************/
188
189		/* These are shared by c64, c65 and c128. c65 and c128 also have additional specific
190		components (to select/read additional keyboard lines) */
191
192		/*
193		* CIA 0 - Port A
194		* bits 7-0 keyboard line select
195		* bits 7,6: paddle select( 01 port a, 10 port b)
196		* bit 4: joystick a fire button
197		* bits 3,2: Paddles port a fire button
198		* bits 3-0: joystick a direction
199		*
200		* CIA 0 - Port B
201		* bits 7-0: keyboard raw values
202		* bit 4: joystick b fire button, lightpen select
203		* bits 3,2: paddle b fire buttons (left,right)
204		* bits 3-0: joystick b direction
205		*
206		* flag cassette read input, serial request in
207		* irq to irq connected
208		*/
209
210		UINT8 cbm_common_cia0_port_a_r( device_t *device, UINT8 output_b )
211		{
212		UINT8 value = 0xff;
213
214		if (!(output_b & 0x80))
215		{
216		UINT8 t = 0xff;
217		if (!(c64_keyline[7] & 0x80)) t &= ~0x80;
218		if (!(c64_keyline[6] & 0x80)) t &= ~0x40;
219		if (!(c64_keyline[5] & 0x80)) t &= ~0x20;
220		if (!(c64_keyline[4] & 0x80)) t &= ~0x10;
221		if (!(c64_keyline[3] & 0x80)) t &= ~0x08;
222		if (!(c64_keyline[2] & 0x80)) t &= ~0x04;
223		if (!(c64_keyline[1] & 0x80)) t &= ~0x02;
224		if (!(c64_keyline[0] & 0x80)) t &= ~0x01;
225		value &= t;
226		}
227
228		if (!(output_b & 0x40))
229		{
230		UINT8 t = 0xff;
231		if (!(c64_keyline[7] & 0x40)) t &= ~0x80;
232		if (!(c64_keyline[6] & 0x40)) t &= ~0x40;
233		if (!(c64_keyline[5] & 0x40)) t &= ~0x20;
234		if (!(c64_keyline[4] & 0x40)) t &= ~0x10;
235		if (!(c64_keyline[3] & 0x40)) t &= ~0x08;
236		if (!(c64_keyline[2] & 0x40)) t &= ~0x04;
237		if (!(c64_keyline[1] & 0x40)) t &= ~0x02;
238		if (!(c64_keyline[0] & 0x40)) t &= ~0x01;
239		value &= t;
240		}
241
242		if (!(output_b & 0x20))
243		{
244		UINT8 t = 0xff;
245		if (!(c64_keyline[7] & 0x20)) t &= ~0x80;
246		if (!(c64_keyline[6] & 0x20)) t &= ~0x40;
247		if (!(c64_keyline[5] & 0x20)) t &= ~0x20;
248		if (!(c64_keyline[4] & 0x20)) t &= ~0x10;
249		if (!(c64_keyline[3] & 0x20)) t &= ~0x08;
250		if (!(c64_keyline[2] & 0x20)) t &= ~0x04;
251		if (!(c64_keyline[1] & 0x20)) t &= ~0x02;
252		if (!(c64_keyline[0] & 0x20)) t &= ~0x01;
253		value &= t;
254		}
255
256		if (!(output_b & 0x10))
257		{
258		UINT8 t = 0xff;
259		if (!(c64_keyline[7] & 0x10)) t &= ~0x80;
260		if (!(c64_keyline[6] & 0x10)) t &= ~0x40;
261		if (!(c64_keyline[5] & 0x10)) t &= ~0x20;
262		if (!(c64_keyline[4] & 0x10)) t &= ~0x10;
263		if (!(c64_keyline[3] & 0x10)) t &= ~0x08;
264		if (!(c64_keyline[2] & 0x10)) t &= ~0x04;
265		if (!(c64_keyline[1] & 0x10)) t &= ~0x02;
266		if (!(c64_keyline[0] & 0x10)) t &= ~0x01;
267		value &= t;
268		}
269
270		if (!(output_b & 0x08))
271		{
272		UINT8 t = 0xff;
273		if (!(c64_keyline[7] & 0x08)) t &= ~0x80;
274		if (!(c64_keyline[6] & 0x08)) t &= ~0x40;
275		if (!(c64_keyline[5] & 0x08)) t &= ~0x20;
276		if (!(c64_keyline[4] & 0x08)) t &= ~0x10;
277		if (!(c64_keyline[3] & 0x08)) t &= ~0x08;
278		if (!(c64_keyline[2] & 0x08)) t &= ~0x04;
279		if (!(c64_keyline[1] & 0x08)) t &= ~0x02;
280		if (!(c64_keyline[0] & 0x08)) t &= ~0x01;
281		value &= t;
282		}
283
284		if (!(output_b & 0x04))
285		{
286		UINT8 t = 0xff;
287		if (!(c64_keyline[7] & 0x04)) t &= ~0x80;
288		if (!(c64_keyline[6] & 0x04)) t &= ~0x40;
289		if (!(c64_keyline[5] & 0x04)) t &= ~0x20;
290		if (!(c64_keyline[4] & 0x04)) t &= ~0x10;
291		if (!(c64_keyline[3] & 0x04)) t &= ~0x08;
292		if (!(c64_keyline[2] & 0x04)) t &= ~0x04;
293		if (!(c64_keyline[1] & 0x04)) t &= ~0x02;
294		if (!(c64_keyline[0] & 0x04)) t &= ~0x01;
295		value &= t;
296		}
297
298		if (!(output_b & 0x02))
299		{
300		UINT8 t = 0xff;
301		if (!(c64_keyline[7] & 0x02)) t &= ~0x80;
302		if (!(c64_keyline[6] & 0x02)) t &= ~0x40;
303		if (!(c64_keyline[5] & 0x02)) t &= ~0x20;
304		if (!(c64_keyline[4] & 0x02)) t &= ~0x10;
305		if (!(c64_keyline[3] & 0x02)) t &= ~0x08;
306		if (!(c64_keyline[2] & 0x02)) t &= ~0x04;
307		if (!(c64_keyline[1] & 0x02)) t &= ~0x02;
308		if (!(c64_keyline[0] & 0x02)) t &= ~0x01;
309		value &= t;
310		}
311
312		if (!(output_b & 0x01))
313		{
314		UINT8 t = 0xff;
315		if (!(c64_keyline[7] & 0x01)) t &= ~0x80;
316		if (!(c64_keyline[6] & 0x01)) t &= ~0x40;
317		if (!(c64_keyline[5] & 0x01)) t &= ~0x20;
318		if (!(c64_keyline[4] & 0x01)) t &= ~0x10;
319		if (!(c64_keyline[3] & 0x01)) t &= ~0x08;
320		if (!(c64_keyline[2] & 0x01)) t &= ~0x04;
321		if (!(c64_keyline[1] & 0x01)) t &= ~0x02;
322		if (!(c64_keyline[0] & 0x01)) t &= ~0x01;
323		value &= t;
324		}
325
326		if ( device->machine().root_device().ioport("CTRLSEL")->read() & 0x80 )
327		value &= c64_keyline[8];
328		else
329		value &= c64_keyline[9];
330
331		return value;
332		}
333
334		UINT8 cbm_common_cia0_port_b_r( device_t *device, UINT8 output_a )
335		{
336		UINT8 value = 0xff;
337
338		if (!(output_a & 0x80)) value &= c64_keyline[7];
339		if (!(output_a & 0x40)) value &= c64_keyline[6];
340		if (!(output_a & 0x20)) value &= c64_keyline[5];
341		if (!(output_a & 0x10)) value &= c64_keyline[4];
342		if (!(output_a & 0x08)) value &= c64_keyline[3];
343		if (!(output_a & 0x04)) value &= c64_keyline[2];
344		if (!(output_a & 0x02)) value &= c64_keyline[1];
345		if (!(output_a & 0x01)) value &= c64_keyline[0];
346
347		if ( device->machine().root_device().ioport("CTRLSEL")->read() & 0x80 )
348		value &= c64_keyline[9];
349		else
350		value &= c64_keyline[8];
351
352		return value;
353		}
354
355
356		/***********************************************
357
358		CBM Cartridges
359
360		***********************************************/
361
362
363		/* All the cartridge specific code has been moved
364		to machine/ drivers. Once more informations
365		surface about the cart expansions for systems
366		in c65.c, c128.c, cbmb.c and pet.c, the shared
367		code could be refactored to have here the
368		common functions */
369
370
371
372		/***********************************************
373
374		CBM Datasette Tapes
375
376		***********************************************/
377
378		#if 0
379		const cassette_interface cbm_cassette_interface =
380		{
381		cbm_cassette_formats,
382		NULL,
383		(cassette_state) (CASSETTE_STOPPED \| CASSETTE_MOTOR_DISABLED \| CASSETTE_SPEAKER_ENABLED),
384		NULL
385		};
386		#endif
387
388
389		/UINT8 c65_basic; */
390		/UINT8 c65_kernal; */
391		/UINT8 c65_dos; */
392		/UINT8 c65_monitor; */
393		/UINT8 c65_graphics; */
394
395
396		void c65_state::c65_nmi( )
397		{
398		if (m_nmilevel != (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq) /* KEY_RESTORE */
399		{
400		m_maincpu->set_input_line(INPUT_LINE_NMI, (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq);
401
402		m_nmilevel = (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq;
403		}
404		}
405
406
407		/***********************************************
408
409		CIA Interfaces
410
411		***********************************************/
412
413		/*
414		* CIA 0 - Port A keyboard line select
415		* CIA 0 - Port B keyboard line read
416		*
417		* flag cassette read input, serial request in
418		* irq to irq connected
419		*
420		* see machine/cbm.c
421		*/
422
423		READ8_MEMBER(c65_state::c65_cia0_port_a_r)
424		{
425		UINT8 cia0portb = m_cia0->pb_r(space, 0);
426
427		return cbm_common_cia0_port_a_r(m_cia0, cia0portb);
428		}
429
430		READ8_MEMBER(c65_state::c65_cia0_port_b_r)
431		{
432		UINT8 value = 0xff;
433		UINT8 cia0porta = m_cia0->pa_r(space, 0);
434
435		value &= cbm_common_cia0_port_b_r(m_cia0, cia0porta);
436
437		if (!(m_6511_port & 0x02))
438		value &= m_keyline;
439
440		return value;
441		}
442
443		WRITE8_MEMBER(c65_state::c65_cia0_port_b_w)
444		{
445		// was there lightpen support in c65 video chip?
446		// vic3_device *vic3 = machine().device<vic3_device>("vic3");
447		// vic3->lightpen_write(data & 0x10);
448		}
449
450		void c65_state::c65_irq( int level )
451		{
452		if (level != m_old_level)
453		{
454		DBG_LOG(machine(), 3, "mos4510", ("irq %s\n", level ? "start" : "end"));
455		m_maincpu->set_input_line(M4510_IRQ_LINE, level);
456		m_old_level = level;
457		}
458		}
459
460		/* is this correct for c65 as well as c64? */
461		WRITE_LINE_MEMBER(c65_state::c65_cia0_interrupt)
462		{
463		m_cia0_irq = state;
464		c65_irq(state \|\| m_vicirq);
465		}
466
467		/* is this correct for c65 as well as c64? */
468		WRITE_LINE_MEMBER(c65_state::c65_vic_interrupt)
469		{
470		#if 1
471		if (state != m_vicirq)
472		{
473		c65_irq (state \|\| m_cia0_irq);
474		m_vicirq = state;
475		}
476		#endif
477		}
478
479		/*
480		* CIA 1 - Port A
481		* bit 7 serial bus data input
482		* bit 6 serial bus clock input
483		* bit 5 serial bus data output
484		* bit 4 serial bus clock output
485		* bit 3 serial bus atn output
486		* bit 2 rs232 data output
487		* bits 1-0 vic-chip system memory bank select
488		*
489		* CIA 1 - Port B
490		* bit 7 user rs232 data set ready
491		* bit 6 user rs232 clear to send
492		* bit 5 user
493		* bit 4 user rs232 carrier detect
494		* bit 3 user rs232 ring indicator
495		* bit 2 user rs232 data terminal ready
496		* bit 1 user rs232 request to send
497		* bit 0 user rs232 received data
498		*
499		* flag restore key or rs232 received data input
500		* irq to nmi connected ?
501		*/
502		READ8_MEMBER(c65_state::c65_cia1_port_a_r)
503		{
504		UINT8 value = 0xff;
505
506		if (!m_iec->clk_r())
507		value &= ~0x40;
508
509		if (!m_iec->data_r())
510		value &= ~0x80;
511
512		return value;
513		}
514
515		WRITE8_MEMBER(c65_state::c65_cia1_port_a_w)
516		{
517		static const int helper[4] = {0xc000, 0x8000, 0x4000, 0x0000};
518
519		m_iec->atn_w(!BIT(data, 3));
520		m_iec->clk_w(!BIT(data, 4));
521		m_iec->data_w(!BIT(data, 5));
522
523		m_vicaddr = m_memory + helper[data & 0x03];
524		}
525
526		WRITE_LINE_MEMBER(c65_state::c65_cia1_interrupt)
527		{
528		m_cia1_irq = state;
529		c65_nmi();
530		}
531
532		/***********************************************
533
534		Memory Handlers
535
536		***********************************************/
537
538		/* processor has only 1 mega address space !? */
539		/* and system 8 megabyte */
540		/* dma controller and bankswitch hardware ?*/
541		READ8_MEMBER( c65_state::c65_read_mem )
542		{
543		UINT8 result;
544		if (offset <= 0x0ffff)
545		result = m_memory[offset];
546		else
547		result = space.read_byte(offset);
548		return result;
549		}
550
551		WRITE8_MEMBER( c65_state::c65_write_mem )
552		{
553		if (offset <= 0x0ffff)
554		m_memory[offset] = data;
555		else
556		space.write_byte(offset, data);
557		}
558
559		/* dma chip at 0xd700
560		used:
561		writing banknumber to offset 2
562		writing hibyte to offset 1
563		writing lobyte to offset 0
564		cpu holded, dma transfer(data at address) executed, cpu activated
565
566		command data:
567		0 command (0 copy, 3 fill)
568		1,2 length
569		3,4,5 source
570		6,7,8 dest
571		9 subcommand
572		10 mod
573
574		version 1:
575		seldom copy (overlapping) from 0x402002 to 0x402008
576		(making place for new line in basic area)
577		for whats this bit 0x400000, or is this really the address?
578		maybe means add counter to address for access,
579		so allowing up or down copies, and reordering copies
580
581		version 2:
582		cmd 0x30 used for this
583		*/
584		void c65_state::c65_dma_port_w( int offset, int value )
585		{
586		PAIR pair, src, dst, len;
587		UINT8 cmd, fill;
588		int i;
589		address_space &space = m_maincpu->space(AS_PROGRAM);
590
591		switch (offset & 3)
592		{
593		case 2:
594		case 1:
595		m_dma.data[offset & 3] = value;
596		break;
597		case 0:
598		pair.b.h3 = 0;
599		pair.b.h2 = m_dma.data[2];
600		pair.b.h = m_dma.data[1];
601		pair.b.l = m_dma.data[0]=value;
602		cmd = c65_read_mem(space, pair.d++);
603		len.w.h = 0;
604		len.b.l = c65_read_mem(space, pair.d++);
605		len.b.h = c65_read_mem(space, pair.d++);
606		src.b.h3 = 0;
607		fill = src.b.l = c65_read_mem(space, pair.d++);
608		src.b.h = c65_read_mem(space, pair.d++);
609		src.b.h2 = c65_read_mem(space, pair.d++);
610		dst.b.h3 = 0;
611		dst.b.l = c65_read_mem(space, pair.d++);
612		dst.b.h = c65_read_mem(space, pair.d++);
613		dst.b.h2 = c65_read_mem(space, pair.d++);
614
615		switch (cmd)
616		{
617		case 0:
618		if (src.d == 0x3ffff) m_dump_dma = 1;
619		if (m_dump_dma)
620		DBG_LOG(space.machine(), 1,"dma copy job",
621		("len:%.4x src:%.6x dst:%.6x sub:%.2x modrm:%.2x\n",
622		len.w.l, src.d, dst.d, c65_read_mem(space, pair.d),
623		c65_read_mem(space, pair.d + 1) ) );
624		if ((m_dma.version == 1)
625		&& ( (src.d&0x400000) \|\| (dst.d & 0x400000)))
626		{
627		if (!(src.d & 0x400000))
628		{
629		dst.d &= ~0x400000;
630		for (i = 0; i < len.w.l; i++)
631		c65_write_mem(space, dst.d--, c65_read_mem(space, src.d++));
632		}
633		else if (!(dst.d & 0x400000))
634		{
635		src.d &= ~0x400000;
636		for (i = 0; i < len.w.l; i++)
637		c65_write_mem(space, dst.d++, c65_read_mem(space, src.d--));
638		}
639		else
640		{
641		src.d &= ~0x400000;
642		dst.d &= ~0x400000;
643		for (i = 0; i < len.w.l; i++)
644		c65_write_mem(space, --dst.d, c65_read_mem(space, --src.d));
645		}
646		}
647		else
648		{
649		for (i = 0; i < len.w.l; i++)
650		c65_write_mem(space, dst.d++, c65_read_mem(space, src.d++));
651		}
652		break;
653		case 3:
654		DBG_LOG(space.machine(), 3,"dma fill job",
655		("len:%.4x value:%.2x dst:%.6x sub:%.2x modrm:%.2x\n",
656		len.w.l, fill, dst.d, c65_read_mem(space, pair.d),
657		c65_read_mem(space, pair.d + 1)));
658		for (i = 0; i < len.w.l; i++)
659		c65_write_mem(space, dst.d++, fill);
660		break;
661		case 0x30:
662		DBG_LOG(space.machine(), 1,"dma copy down",
663		("len:%.4x src:%.6x dst:%.6x sub:%.2x modrm:%.2x\n",
664		len.w.l, src.d, dst.d, c65_read_mem(space, pair.d),
665		c65_read_mem(space, pair.d + 1) ) );
666		for (i = 0; i < len.w.l; i++)
667		c65_write_mem(space, dst.d--,c65_read_mem(space, src.d--));
668		break;
669		default:
670		DBG_LOG(space.machine(), 1,"dma job",
671		("cmd:%.2x len:%.4x src:%.6x dst:%.6x sub:%.2x modrm:%.2x\n",
672		cmd,len.w.l, src.d, dst.d, c65_read_mem(space, pair.d),
673		c65_read_mem(space, pair.d + 1)));
674		}
675		break;
676		default:
677		DBG_LOG(space.machine(), 1, "dma chip write", ("%.3x %.2x\n", offset, value));
678		break;
679		}
680		}
681
682		int c65_state::c65_dma_port_r( int offset )
683		{
684		/* offset 3 bit 7 in progress ? */
685		DBG_LOG(machine(), 2, "dma chip read", ("%.3x\n", offset));
686		return 0x7f;
687		}
688
689		void c65_state::c65_6511_port_w( int offset, int value )
690		{
691		if (offset == 7)
692		{
693		m_6511_port = value;
694		}
695		DBG_LOG(machine(), 2, "r6511 write", ("%.2x %.2x\n", offset, value));
696		}
697
698		int c65_state::c65_6511_port_r( int offset )
699		{
700		int data = 0xff;
701
702		if (offset == 7)
703		{
704		if (ioport("SPECIAL")->read() & 0x20)
705		data &= ~1;
706		}
707		DBG_LOG(machine(), 2, "r6511 read", ("%.2x\n", offset));
708
709		return data;
710		}
711
712		/* one docu states custom 4191 disk controller
713		(for 2 1MB MFM disk drives, 1 internal, the other extern (optional) 1565
714		with integrated 512 byte buffer
715
716		0->0 reset ?
717
718		0->1, 0->0, wait until 2 positiv, 1->0 ???
719
720		0->0, 0 not 0 means no drive ???, other system entries
721
722
723		reg 0 write/read
724		0,1 written
725		bit 1 set
726		bit 2 set
727		bit 3 set
728		bit 4 set
729
730
731		reg 0 read
732		bit 0
733		bit 1
734		bit 2
735		0..2 ->$1d4
736
737		reg 1 write
738		$01 written
739		$18 written
740		$46 written
741		$80 written
742		$a1 written
743		$01 written, dec
744		$10 written
745
746		reg 2 read/write?(lsr)
747		bit 2
748		bit 4
749		bit 5 busy waiting until zero, then reading reg 7
750		bit 6 operation not activ flag!? or set overflow pin used
751		bit 7 busy flag?
752
753		reg 3 read/write?(rcr)
754		bit 1
755		bit 3
756		bit 7 busy flag?
757
758		reg 4
759		track??
760		0 written
761		read -> $1d2
762		cmp #$50
763		bcs
764
765
766		reg 5
767		sector ??
768		1 written
769		read -> $1d3
770		cmp #$b bcc
771
772
773		reg 6
774		head ??
775		0 written
776		read -> $1d1
777		cmp #2 bcc
778
779		reg 7 read
780		#4e written
781		12 times 0, a1 a1 a1 fe written
782
783		reg 8 read
784		#ff written
785		16 times #ff written
786
787		reg 9
788		#60 written
789
790		might use the set overflow input
791
792		$21a6c 9a6c format
793		$21c97 9c97 write operation
794		$21ca0 9ca0 get byte?
795		$21cab 9cab read reg 7
796		$21caf 9caf write reg 7
797		$21cb3
798		*/
799
800		#define FDC_LOST 4
801		#define FDC_CRC 8
802		#define FDC_RNF 0x10
803		#define FDC_BUSY 0x80
804		#define FDC_IRQ 0x200
805
806		#define FDC_CMD_MOTOR_SPIN_UP 0x10
807
808		#if 0
809		void c65_state::c65_fdc_state(void)
810		{
811		switch (m_fdc.state)
812		{
813		case FDC_CMD_MOTOR_SPIN_UP:
814		if (machine().time() - m_fdc.time)
815		{
816		m_fdc.state = 0;
817		m_fdc.status &= ~FDC_BUSY;
818		}
819		break;
820		}
821		}
822		#endif
823
824		void c65_state::c65_fdc_w( int offset, int data )
825		{
826		DBG_LOG(machine(), 1, "fdc write", ("%.5x %.2x %.2x\n", machine().device("maincpu")->safe_pc(), offset, data));
827		switch (offset & 0xf)
828		{
829		case 0:
830		m_fdc.reg[0] = data;
831		break;
832		case 1:
833		m_fdc.reg[1] = data;
834		switch (data & 0xf9)
835		{
836		case 0x20: // wait for motor spin up
837		m_fdc.status &= ~(FDC_IRQ\|FDC_LOST\|FDC_CRC\|FDC_RNF);
838		m_fdc.status \|= FDC_BUSY;
839		m_fdc.time = machine().time();
840		m_fdc.state = FDC_CMD_MOTOR_SPIN_UP;
841		break;
842		case 0: // cancel
843		m_fdc.status &= ~(FDC_BUSY);
844		m_fdc.state = 0;
845		break;
846		case 0x80: // buffered write
847		case 0x40: // buffered read
848		case 0x81: // unbuffered write
849		case 0x41: // unbuffered read
850		case 0x30:case 0x31: // step
851		break;
852		}
853		break;
854		case 2: case 3: // read only
855		break;
856		case 4:
857		m_fdc.reg[offset & 0xf] = data;
858		m_fdc.track = data;
859		break;
860		case 5:
861		m_fdc.reg[offset & 0xf] = data;
862		m_fdc.sector = data;
863		break;
864		case 6:
865		m_fdc.reg[offset & 0xf] = data;
866		m_fdc.head = data;
867		break;
868		case 7:
869		m_fdc.buffer[m_fdc.cpu_pos++] = data;
870		break;
871		default:
872		m_fdc.reg[offset & 0xf] = data;
873		break;
874		}
875		}
876
877		int c65_state::c65_fdc_r( int offset )
878		{
879		UINT8 data = 0;
880		switch (offset & 0xf)
881		{
882		case 0:
883		data = m_fdc.reg[0];
884		break;
885		case 1:
886		data = m_fdc.reg[1];
887		break;
888		case 2:
889		data = m_fdc.status;
890		break;
891		case 3:
892		data = m_fdc.status >> 8;
893		break;
894		case 4:
895		data = m_fdc.track;
896		break;
897		case 5:
898		data = m_fdc.sector;
899		break;
900		case 6:
901		data = m_fdc.head;
902		break;
903		case 7:
904		data = m_fdc.buffer[m_fdc.cpu_pos++];
905		break;
906		default:
907		data = m_fdc.reg[offset & 0xf];
908		break;
909		}
910		DBG_LOG(machine(), 1, "fdc read", ("%.5x %.2x %.2x\n", machine().device("maincpu")->safe_pc(), offset, data));
911		return data;
912		}
913
914		/* version 1 ramcheck
915		write 0:0
916		read write read write 80000,90000,f0000
917		write 0:8
918		read write read write 80000,90000,f0000
919
920		version 2 ramcheck???
921		read 0:
922		write 0:0
923		read 0:
924		first read and second read bit 0x80 set --> nothing
925		write 0:0
926		read 0
927		write 0:ff
928		*/
929
930		READ8_MEMBER( c65_state::c65_ram_expansion_r )
931		{
932		UINT8 data = 0xff;
933		if (m_ram->size() > (128 * 1024))
934		data = m_expansion_ram.reg;
935		return data;
936		}
937
938		WRITE8_MEMBER( c65_state::c65_ram_expansion_w )
939		{
940		offs_t expansion_ram_begin;
941		offs_t expansion_ram_end;
942
943		if (m_ram->size() > (128 * 1024))
944		{
945		m_expansion_ram.reg = data;
946
947		expansion_ram_begin = 0x80000;
948		expansion_ram_end = 0x80000 + (m_ram->size() - 128*1024) - 1;
949
950		if (data == 0x00) {
951		space.install_readwrite_bank(expansion_ram_begin, expansion_ram_end,"bank16");
952		membank("bank16")->set_base(m_ram->pointer() + 128*1024);
953		} else {
954		space.nop_readwrite(expansion_ram_begin, expansion_ram_end);
955		}
956		}
957		}
958
959		WRITE8_MEMBER( c65_state::c65_write_io )
960		{
961		mos6581_device *sid_0 = machine().device<mos6581_device>("sid_r");
962		mos6581_device *sid_1 = machine().device<mos6581_device>("sid_l");
963		vic3_device *vic3 = machine().device<vic3_device>("vic3");
964
965		switch (offset & 0xf00)
966		{
967		case 0x000:
968		if (offset < 0x80)
969		vic3->port_w(space, offset & 0x7f, data);
970		else if (offset < 0xa0)
971		c65_fdc_w(offset & 0x1f, data);
972		else
973		{
974		c65_ram_expansion_w(space, offset & 0x1f, data, mem_mask);
975		/ram expansion crtl optional /
976		}
977		break;
978		case 0x100:
979		case 0x200:
980		case 0x300:
981		vic3->palette_w(space, offset - 0x100, data);
982		break;
983		case 0x400:
984		if (offset<0x420) /* maybe 0x20 */
985		sid_0->write(space, offset & 0x3f, data);
986		else if (offset<0x440)
987		sid_1->write(space, offset & 0x3f, data);
988		else
989		DBG_LOG(machine(), 1, "io write", ("%.3x %.2x\n", offset, data));
990		break;
991		case 0x500:
992		DBG_LOG(machine(), 1, "io write", ("%.3x %.2x\n", offset, data));
993		break;
994		case 0x600:
995		c65_6511_port_w(offset & 0xff,data);
996		break;
997		case 0x700:
998		c65_dma_port_w(offset & 0xff, data);
999		break;
1000		}
1001		}
1002
1003		WRITE8_MEMBER( c65_state::c65_write_io_dc00 )
1004		{
1005		switch (offset & 0xf00)
1006		{
1007		case 0x000:
1008		m_cia0->write(space, offset, data);
1009		break;
1010		case 0x100:
1011		m_cia1->write(space, offset, data);
1012		break;
1013		case 0x200:
1014		case 0x300:
1015		DBG_LOG(machine(), 1, "io write", ("%.3x %.2x\n", offset+0xc00, data));
1016		break;
1017		}
1018		}
1019
1020		READ8_MEMBER( c65_state::c65_read_io )
1021		{
1022		mos6581_device *sid_0 = machine().device<mos6581_device>("sid_r");
1023		mos6581_device *sid_1 = machine().device<mos6581_device>("sid_l");
1024		vic3_device *vic3 = machine().device<vic3_device>("vic3");
1025
1026		switch (offset & 0xf00)
1027		{
1028		case 0x000:
1029		if (offset < 0x80)
1030		return vic3->port_r(space, offset & 0x7f);
1031		if (offset < 0xa0)
1032		return c65_fdc_r(offset & 0x1f);
1033		else
1034		{
1035		return c65_ram_expansion_r(space, offset & 0x1f, mem_mask);
1036		/return; ram expansion crtl optional /
1037		}
1038		case 0x100:
1039		case 0x200:
1040		case 0x300:
1041		/* read only !? */
1042		DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset));
1043		break;
1044		case 0x400:
1045		if (offset < 0x420)
1046		return sid_0->read(space, offset & 0x3f);
1047		if (offset < 0x440)
1048		return sid_1->read(space, offset & 0x3f);
1049		DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset));
1050		break;
1051		case 0x500:
1052		DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset));
1053		break;
1054		case 0x600:
1055		return c65_6511_port_r(offset&0xff);
1056		case 0x700:
1057		return c65_dma_port_r(offset&0xff);
1058		}
1059		return 0xff;
1060		}
1061
1062		READ8_MEMBER( c65_state::c65_read_io_dc00 )
1063		{
1064		switch (offset & 0x300)
1065		{
1066		case 0x000:
1067		return m_cia0->read(space, offset);
1068		case 0x100:
1069		return m_cia1->read(space, offset);
1070		case 0x200:
1071		case 0x300:
1072		DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset+0xc00));
1073		break;
1074		}
1075		return 0xff;
1076		}
1077
1078
1079		/*
1080		d02f:
1081		init a5 96 written (seems to be switch to c65 or vic3 mode)
1082		go64 0 written
1083		*/
1084
1085		/* bit 1 external sync enable (genlock)
1086		bit 2 palette enable
1087		bit 6 vic3 c65 character set */
1088		WRITE8_MEMBER(c65_state::c65_bankswitch_interface)
1089		{
1090		DBG_LOG(machine(), 2, "c65 bankswitch", ("%.2x\n",data));
1091
1092		if (m_io_on)
1093		{
1094		if (data & 1)
1095		{
1096		membank("bank8")->set_base(m_colorram + 0x400);
1097		membank("bank9")->set_base(m_colorram + 0x400);
1098		m_maincpu->space(AS_PROGRAM).install_read_bank(0x0dc00, 0x0dfff, "bank8");
1099		m_maincpu->space(AS_PROGRAM).install_write_bank(0x0dc00, 0x0dfff, "bank9");
1100		}
1101		else
1102		{
1103		m_maincpu->space(AS_PROGRAM).install_read_handler(0x0dc00, 0x0dfff, read8_delegate(FUNC(c65_state::c65_read_io_dc00),this));
1104		m_maincpu->space(AS_PROGRAM).install_write_handler(0x0dc00, 0x0dfff, write8_delegate(FUNC(c65_state::c65_write_io_dc00),this));
1105		}
1106		}
1107
1108		m_io_dc00_on = !(data & 1);
1109		#if 0
1110		/* cartridge roms !?*/
1111		if (data & 0x08)
1112		membank("bank1")->set_base(m_roml);
1113		else
1114		membank("bank1")->set_base(m_memory + 0x8000);
1115
1116		if (data & 0x10)
1117		membank("bank2")->set_base(m_basic);
1118		else
1119		membank("bank2")->set_base(m_memory + 0xa000);
1120		#endif
1121		if ((m_old_value^data) & 0x20)
1122		{
1123		/* bankswitching faulty when doing actual page */
1124		if (data & 0x20)
1125		membank("bank3")->set_base(m_basic);
1126		else
1127		membank("bank3")->set_base(m_memory + 0xc000);
1128		}
1129		m_charset_select = data & 0x40;
1130		#if 0
1131		/* cartridge roms !?*/
1132		if (data & 0x80)
1133		membank("bank8")->set_base(m_kernal);
1134		else
1135		membank("bank6")->set_base(m_memory + 0xe000);
1136		#endif
1137		m_old_value = data;
1138		}
1139
1140		void c65_state::c65_bankswitch( )
1141		{
1142		int data, loram, hiram, charen;
1143
1144		data = 0x00; // machine().device<m4510_device>("maincpu")->get_port();
1145		if (data == m_old_data)
1146		return;
1147
1148		DBG_LOG(machine(), 1, "bankswitch", ("%d\n", data & 7));
1149		loram = (data & 1) ? 1 : 0;
1150		hiram = (data & 2) ? 1 : 0;
1151		charen = (data & 4) ? 1 : 0;
1152
1153		if ((!m_game && m_exrom) \|\| (loram && hiram && !m_exrom))
1154		membank("bank1")->set_base(m_roml);
1155		else
1156		membank("bank1")->set_base(m_memory + 0x8000);
1157
1158		if ((!m_game && m_exrom && hiram) \|\| (!m_exrom))
1159		membank("bank2")->set_base(m_romh);
1160		else if (loram && hiram)
1161		membank("bank2")->set_base(m_basic);
1162		else
1163		membank("bank2")->set_base(m_memory + 0xa000);
1164
1165		if ((!m_game && m_exrom) \|\| (charen && (loram \|\| hiram)))
1166		{
1167		m_io_on = 1;
1168		membank("bank6")->set_base(m_colorram);
1169		membank("bank7")->set_base(m_colorram);
1170
1171		if (m_io_dc00_on)
1172		{
1173		m_maincpu->space(AS_PROGRAM).install_read_handler(0x0dc00, 0x0dfff, read8_delegate(FUNC(c65_state::c65_read_io_dc00),this));
1174		m_maincpu->space(AS_PROGRAM).install_write_handler(0x0dc00, 0x0dfff, write8_delegate(FUNC(c65_state::c65_write_io_dc00),this));
1175		}
1176		else
1177		{
1178		m_maincpu->space(AS_PROGRAM).install_read_bank(0x0dc00, 0x0dfff, "bank8");
1179		m_maincpu->space(AS_PROGRAM).install_write_bank(0x0dc00, 0x0dfff, "bank9");
1180		membank("bank8")->set_base(m_colorram + 0x400);
1181		membank("bank9")->set_base(m_colorram + 0x400);
1182		}
1183		m_maincpu->space(AS_PROGRAM).install_read_handler(0x0d000, 0x0d7ff, read8_delegate(FUNC(c65_state::c65_read_io),this));
1184		m_maincpu->space(AS_PROGRAM).install_write_handler(0x0d000, 0x0d7ff, write8_delegate(FUNC(c65_state::c65_write_io),this));
1185		}
1186		else
1187		{
1188		m_io_on = 0;
1189		membank("bank5")->set_base(m_memory + 0xd000);
1190		membank("bank7")->set_base(m_memory + 0xd800);
1191		membank("bank9")->set_base(m_memory + 0xdc00);
1192		if (!charen && (loram \|\| hiram))
1193		{
1194		membank("bank4")->set_base(m_chargen);
1195		membank("bank6")->set_base(m_chargen + 0x800);
1196		membank("bank8")->set_base(m_chargen + 0xc00);
1197		}
1198		else
1199		{
1200		membank("bank4")->set_base(m_memory + 0xd000);
1201		membank("bank6")->set_base(m_memory + 0xd800);
1202		membank("bank8")->set_base(m_memory + 0xdc00);
1203		}
1204		m_maincpu->space(AS_PROGRAM).install_read_bank(0x0d000, 0x0d7ff, "bank4");
1205		m_maincpu->space(AS_PROGRAM).install_write_bank(0x0d000, 0x0d7ff, "bank5");
1206		}
1207
1208		if (!m_game && m_exrom)
1209		{
1210		membank("bank10")->set_base(m_romh);
1211		}
1212		else
1213		{
1214		if (hiram)
1215		{
1216		membank("bank10")->set_base(m_kernal);
1217		}
1218		else
1219		{
1220		membank("bank10")->set_base(m_memory + 0xe000);
1221		}
1222		}
1223		m_old_data = data;
1224		}
1225
1226		#ifdef UNUSED_FUNCTION
1227		void c65_state::c65_colorram_write( int offset, int value )
1228		{
1229		m_colorram[offset & 0x7ff] = value \| 0xf0;
1230		}
1231		#endif
1232
1233		/*
1234		* only 14 address lines
1235		* a15 and a14 portlines
1236		* 0x1000-0x1fff, 0x9000-0x9fff char rom
1237		*/
1238		READ8_MEMBER(c65_state::c65_dma_read)
1239		{
1240		if (!m_game && m_exrom)
1241		{
1242		if (offset < 0x3000)
1243		return m_memory[offset];
1244		return m_romh[offset & 0x1fff];
1245		}
1246		if ((m_vicaddr == m_memory) \|\| (m_vicaddr == m_memory + 0x8000))
1247		{
1248		if (offset < 0x1000)
1249		return m_vicaddr[offset & 0x3fff];
1250		if (offset < 0x2000) {
1251		if (m_charset_select)
1252		return m_chargen[offset & 0xfff];
1253		else
1254		return m_chargen[offset & 0xfff];
1255		}
1256		return m_vicaddr[offset & 0x3fff];
1257		}
1258		return m_vicaddr[offset & 0x3fff];
1259		}
1260
1261		READ8_MEMBER(c65_state::c65_dma_read_color)
1262		{
1263		if (m_c64mode)
1264		return m_colorram[offset & 0x3ff] & 0xf;
1265		return m_colorram[offset & 0x7ff];
1266		}
1267
1268		void c65_state::c65_common_driver_init( )
1269		{
1270		m_memory = auto_alloc_array_clear(machine(), UINT8, 0x10000);
1271		membank("bank11")->set_base(m_memory + 0x00000);
1272		membank("bank12")->set_base(m_memory + 0x08000);
1273		membank("bank13")->set_base(m_memory + 0x0a000);
1274		membank("bank14")->set_base(m_memory + 0x0c000);
1275		membank("bank15")->set_base(m_memory + 0x0e000);
1276
1277		cbm_common_init();
1278		m_keyline = 0xff;
1279
1280		m_pal = 0;
1281		m_charset_select = 0;
1282		m_6511_port = 0xff;
1283		m_vicirq = 0;
1284		m_old_data = -1;
1285
1286		/* C65 had no datasette port */
1287		m_tape_on = 0;
1288		m_game = 1;
1289		m_exrom = 1;
1290
1291		/memset(m_memory + 0x40000, 0, 0x800000 - 0x40000); /
1292		}
1293
1294		DRIVER_INIT_MEMBER(c65_state,c65)
1295		{
1296		m_dma.version = 2;
1297		c65_common_driver_init();
1298		}
1299
1300		DRIVER_INIT_MEMBER(c65_state,c65pal)
1301		{
1302		m_dma.version = 1;
1303		c65_common_driver_init();
1304		m_pal = 1;
1305		}
1306
1307		MACHINE_START_MEMBER(c65_state,c65)
1308		{
1309		/* clear upper memory */
1310		memset(m_ram->pointer() + 1281024, 0xff, m_ram->size() - 1281024);
1311
1312		//removed cbm_drive_0_config (SERIAL, 10);
1313		//removed cbm_drive_1_config (SERIAL, 11);
1314		m_vicaddr = m_memory;
1315
1316		m_c64mode = 0;
1317
1318		c65_bankswitch_interface(m_maincpu->space(AS_PROGRAM),0,0xff);
1319		c65_bankswitch();
1320		}
1321
1322
1323		INTERRUPT_GEN_MEMBER(c65_state::c65_frame_interrupt)
1324		{
1325		int value;
1326
1327		c65_nmi();
1328
1329		/* common keys input ports */
1330		cbm_common_interrupt(&device);
1331
1332		/* c65 specific: function keys input ports */
1333		value = 0xff;
1334
1335		value &= ~ioport("FUNCT")->read();
1336		m_keyline = value;
1337		}

https://github.com/mamedev/mame/commit/03e3e644613c8b61cfd565d14065caa085f8e83d

199869 Revisions