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r34488 Monday 19th January, 2015 at 01:41:48 UTC by MetalliC
hikaru.c: added protection key for sgnascar [MetalliC]
this romboard uses the same encryption as Naomi M1/Actel-type cartridges
[src/mame/drivers]hikaru.c mappy.c
[src/mess/drivers]ngen.c

trunk/src/mame/drivers/hikaru.c
r242999r243000
738738   ROM_LOAD32_WORD( "mpr-23483.ic32", 0xc000002, 0x1000000, CRC(c37adebe) SHA1(e84f6d2cc364c743f7f3b73d8c8d0271952bb093) )
739739   ROM_LOAD32_WORD( "mpr-23480.ic33", 0xe000000, 0x1000000, CRC(f517b8b3) SHA1(c04740adb612473c4c9f8186e7e93d2f73d1bb1a) )
740740   ROM_LOAD32_WORD( "mpr-23484.ic34", 0xe000002, 0x1000000, CRC(2ebe1aa1) SHA1(16b39f7422da1a334dde27169c2949e1d95bddb3) )
741
742   // 317-0283-COM Actel A54SX32
743   // ID 0x4252
744   ROM_REGION( 4, "rom_key", 0 )
745   ROM_LOAD( "sgnascar-key.bin", 0x000000, 0x000004, CRC(f1452f9e) SHA1(86fb0f278a2eb0aba66a24032fb683f7a516b32b) )
741746ROM_END
742747
743748GAME( 2000, hikaru,   0,        hikaru,   hikaru, driver_device,   0, ROT0, "Sega",            "Hikaru Bios", GAME_NO_SOUND|GAME_NOT_WORKING|GAME_IS_BIOS_ROOT )
trunk/src/mame/drivers/mappy.c
r242999r243000
24622462
24632463/* 3x6809, static tilemap, 2bpp sprites (Gaplus type) */
24642464GAME( 1983, phozon,   0,        phozon,   phozon, mappy_state,   phozon,        ROT90, "Namco", "Phozon (Japan)", GAME_SUPPORTS_SAVE )
2465GAME( 1983, phozons,  phozon,   phozon,   phozon, mappy_state,   phozon,        ROT90, "Namco (Sidam license)", "Phozon (Sidam)", GAME_SUPPORTS_SAVE )
2465GAME( 1983, phozons,  phozon,   phozon,   phozon, mappy_state,   phozon,        ROT90, "bootleg? (Sidam)", "Phozon (Sidam)", GAME_SUPPORTS_SAVE )
24662466
24672467/* 2x6809, scroling tilemap, 4bpp sprites (Super Pacman type) */
24682468GAME( 1983, mappy,    0,        mappy,    mappy, mappy_state,   mappy,        ROT90, "Namco", "Mappy (US)", GAME_SUPPORTS_SAVE )
trunk/src/mess/drivers/ngen.c
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6767#include "machine/pit8253.h"
6868#include "machine/z80dart.h"
6969#include "machine/wd_fdc.h"
70#include "machine/wd2010.h"
7170#include "bus/rs232/rs232.h"
7271#include "machine/ngen_kb.h"
7372#include "machine/clock.h"
74#include "imagedev/harddriv.h"
7573
7674class ngen_state : public driver_device
7775{
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9189      m_fdc(*this,"fdc"),
9290      m_fd0(*this,"fdc:0"),
9391      m_fdc_timer(*this,"fdc_timer"),
94      m_hdc(*this,"hdc"),
95      m_hdc_timer(*this,"hdc_timer"),
96      m_hd_buffer(*this,"hd_buffer_ram")
92      m_hdc_timer(*this,"hdc_timer")
9793   {}
9894
9995   DECLARE_WRITE_LINE_MEMBER(pit_out0_w);
r242999r243000
133129   DECLARE_READ8_MEMBER(irq_cb);
134130   DECLARE_WRITE8_MEMBER(hdc_control_w);
135131   DECLARE_WRITE8_MEMBER(disk_addr_ext);
136   DECLARE_READ8_MEMBER(hd_buffer_r);
137   DECLARE_WRITE8_MEMBER(hd_buffer_w);
138132
139133protected:
140134   virtual void machine_reset();
141   virtual void machine_start();
142135
143136private:
144137   required_device<i80186_cpu_device> m_maincpu;
r242999r243000
154147   optional_device<wd2797_t> m_fdc;
155148   optional_device<floppy_connector> m_fd0;
156149   optional_device<pit8253_device> m_fdc_timer;
157   optional_device<wd2010_device> m_hdc;
158150   optional_device<pit8253_device> m_hdc_timer;
159   optional_shared_ptr<UINT8> m_hd_buffer;
160151
161152   void set_dma_channel(int channel, int state);
162153
r242999r243000
479470      case 0x0a:
480471      case 0x0b:
481472         if(mem_mask & 0x00ff)
482            m_fdc_timer->write(space,offset-0x08,data & 0xff);
473            m_fdc_timer->write(space,offset,data & 0xff);
483474         break;
484475      case 0x10:
485476      case 0x11:
r242999r243000
489480      case 0x15:
490481      case 0x16:
491482      case 0x17:
492         if(mem_mask & 0x00ff)
493            m_hdc->write(space,offset-0x10,data & 0xff);
494483         logerror("WD1010 register %i write %02x mask %04x\n",offset-0x10,data & 0xff,mem_mask);
495484         break;
496485      case 0x18:
r242999r243000
498487      case 0x1a:
499488      case 0x1b:
500489         if(mem_mask & 0x00ff)
501            m_hdc_timer->write(space,offset-0x18,data & 0xff);
490            m_hdc_timer->write(space,offset,data & 0xff);
502491         break;
503492   }
504493}
r242999r243000
521510      case 0x0a:
522511      case 0x0b:
523512         if(mem_mask & 0x00ff)
524            ret = m_fdc_timer->read(space,offset-0x08);
513            ret = m_fdc_timer->read(space,offset);
525514         break;
526515      case 0x10:
527516      case 0x11:
r242999r243000
531520      case 0x15:
532521      case 0x16:
533522      case 0x17:
534         if(mem_mask & 0x00ff)
535            ret = m_hdc->read(space,offset-0x10);
536523         logerror("WD1010 register %i read, mask %04x\n",offset-0x10,mem_mask);
537524         break;
538525      case 0x18:
r242999r243000
540527      case 0x1a:
541528      case 0x1b:
542529         if(mem_mask & 0x00ff)
543            ret = m_hdc_timer->read(space,offset-0x18);
530            ret = m_hdc_timer->read(space,offset);
544531         break;
545532   }
546533
r242999r243000
598585   m_disk_page = data & 0x7f;
599586}
600587
601READ8_MEMBER(ngen_state::hd_buffer_r)
602{
603   return m_hd_buffer[offset];
604}
605
606WRITE8_MEMBER(ngen_state::hd_buffer_w)
607{
608   m_hd_buffer[offset] = data;
609}
610
611588WRITE_LINE_MEMBER( ngen_state::dma_hrq_changed )
612589{
613590   m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
r242999r243000
626603   {
627604      if(state)
628605      {
629         if(m_hdc_control & 0x04) // ROM transfer
606         if(m_hdc_control & 0x04) // ROM transfer?
630607            m_hdc_control &= ~0x04;  // switch it off when done
631608      }
632609   }
r242999r243000
712689   return m_pic->acknowledge();
713690}
714691
715void ngen_state::machine_start()
716{
717   m_hd_buffer.allocate(1024*8);  // 8kB buffer RAM for HD controller
718}
719
720692void ngen_state::machine_reset()
721693{
722694   m_port00 = 0;
r242999r243000
865837   MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu",i80186_cpu_device,drq1_w))
866838   MCFG_WD_FDC_FORCE_READY
867839   MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0)
868   MCFG_PIT8253_CLK0(XTAL_20MHz / 20) 
869   MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))  // clocked on FDC data register access
840   MCFG_PIT8253_CLK0(XTAL_20MHz / 20)
841   MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))
870842   MCFG_PIT8253_CLK1(XTAL_20MHz / 20)
871   MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))  // 1MHz
872   MCFG_PIT8253_CLK2(XTAL_20MHz / 10)
873   MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w)) 
874   // TODO: WD1010 HDC (not implemented), use WD2010 for now
875   MCFG_DEVICE_ADD("hdc", WD2010, XTAL_20MHz / 4)
876   MCFG_WD2010_IN_BCS_CB(READ8(ngen_state,hd_buffer_r))
877   MCFG_WD2010_OUT_BCS_CB(WRITE8(ngen_state,hd_buffer_w))
878   MCFG_WD2010_IN_DRDY_CB(VCC)
879   MCFG_WD2010_IN_INDEX_CB(VCC)
880   MCFG_WD2010_IN_WF_CB(VCC)
881   MCFG_WD2010_IN_TK000_CB(VCC)
882   MCFG_WD2010_IN_SC_CB(VCC)
843   MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))
844   MCFG_PIT8253_CLK2(XTAL_20MHz / 20)
845   MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))
846   // TODO: WD1010 HDC (not implemented)
883847   MCFG_DEVICE_ADD("hdc_timer", PIT8253, 0)
884   MCFG_PIT8253_CLK2(XTAL_20MHz / 10)  // 2MHz
885848   MCFG_FLOPPY_DRIVE_ADD("fdc:0", ngen_floppies, "525qd", floppy_image_device::default_floppy_formats)
886   MCFG_HARDDISK_ADD("hard0")
887849
888850MACHINE_CONFIG_END
889851

https://github.com/mamedev/mame/commit/2c019b4b016bba4310caa6542cc652427f3c20ce

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