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r34485 Monday 19th January, 2015 at 02:16:48 UTC by Barry Rodewald
ngen: added WD2010 controller as a substitute for the WD1010 (they are register-compatible).
[src/mess/drivers]ngen.c

trunk/src/mess/drivers/ngen.c
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6767#include "machine/pit8253.h"
6868#include "machine/z80dart.h"
6969#include "machine/wd_fdc.h"
70#include "machine/wd2010.h"
7071#include "bus/rs232/rs232.h"
7172#include "machine/ngen_kb.h"
7273#include "machine/clock.h"
74#include "imagedev/harddriv.h"
7375
7476class ngen_state : public driver_device
7577{
r242996r242997
8991      m_fdc(*this,"fdc"),
9092      m_fd0(*this,"fdc:0"),
9193      m_fdc_timer(*this,"fdc_timer"),
92      m_hdc_timer(*this,"hdc_timer")
94      m_hdc(*this,"hdc"),
95      m_hdc_timer(*this,"hdc_timer"),
96      m_hd_buffer(*this,"hd_buffer_ram")
9397   {}
9498
9599   DECLARE_WRITE_LINE_MEMBER(pit_out0_w);
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129133   DECLARE_READ8_MEMBER(irq_cb);
130134   DECLARE_WRITE8_MEMBER(hdc_control_w);
131135   DECLARE_WRITE8_MEMBER(disk_addr_ext);
136   DECLARE_READ8_MEMBER(hd_buffer_r);
137   DECLARE_WRITE8_MEMBER(hd_buffer_w);
132138
133139protected:
134140   virtual void machine_reset();
141   virtual void machine_start();
135142
136143private:
137144   required_device<i80186_cpu_device> m_maincpu;
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147154   optional_device<wd2797_t> m_fdc;
148155   optional_device<floppy_connector> m_fd0;
149156   optional_device<pit8253_device> m_fdc_timer;
157   optional_device<wd2010_device> m_hdc;
150158   optional_device<pit8253_device> m_hdc_timer;
159   optional_shared_ptr<UINT8> m_hd_buffer;
151160
152161   void set_dma_channel(int channel, int state);
153162
r242996r242997
470479      case 0x0a:
471480      case 0x0b:
472481         if(mem_mask & 0x00ff)
473            m_fdc_timer->write(space,offset,data & 0xff);
482            m_fdc_timer->write(space,offset-0x08,data & 0xff);
474483         break;
475484      case 0x10:
476485      case 0x11:
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480489      case 0x15:
481490      case 0x16:
482491      case 0x17:
492         if(mem_mask & 0x00ff)
493            m_hdc->write(space,offset-0x10,data & 0xff);
483494         logerror("WD1010 register %i write %02x mask %04x\n",offset-0x10,data & 0xff,mem_mask);
484495         break;
485496      case 0x18:
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487498      case 0x1a:
488499      case 0x1b:
489500         if(mem_mask & 0x00ff)
490            m_hdc_timer->write(space,offset,data & 0xff);
501            m_hdc_timer->write(space,offset-0x18,data & 0xff);
491502         break;
492503   }
493504}
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510521      case 0x0a:
511522      case 0x0b:
512523         if(mem_mask & 0x00ff)
513            ret = m_fdc_timer->read(space,offset);
524            ret = m_fdc_timer->read(space,offset-0x08);
514525         break;
515526      case 0x10:
516527      case 0x11:
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520531      case 0x15:
521532      case 0x16:
522533      case 0x17:
534         if(mem_mask & 0x00ff)
535            ret = m_hdc->read(space,offset-0x10);
523536         logerror("WD1010 register %i read, mask %04x\n",offset-0x10,mem_mask);
524537         break;
525538      case 0x18:
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527540      case 0x1a:
528541      case 0x1b:
529542         if(mem_mask & 0x00ff)
530            ret = m_hdc_timer->read(space,offset);
543            ret = m_hdc_timer->read(space,offset-0x18);
531544         break;
532545   }
533546
r242996r242997
585598   m_disk_page = data & 0x7f;
586599}
587600
601READ8_MEMBER(ngen_state::hd_buffer_r)
602{
603   return m_hd_buffer[offset];
604}
605
606WRITE8_MEMBER(ngen_state::hd_buffer_w)
607{
608   m_hd_buffer[offset] = data;
609}
610
588611WRITE_LINE_MEMBER( ngen_state::dma_hrq_changed )
589612{
590613   m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
r242996r242997
603626   {
604627      if(state)
605628      {
606         if(m_hdc_control & 0x04) // ROM transfer?
629         if(m_hdc_control & 0x04) // ROM transfer
607630            m_hdc_control &= ~0x04;  // switch it off when done
608631      }
609632   }
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689712   return m_pic->acknowledge();
690713}
691714
715void ngen_state::machine_start()
716{
717   m_hd_buffer.allocate(1024*8);  // 8kB buffer RAM for HD controller
718}
719
692720void ngen_state::machine_reset()
693721{
694722   m_port00 = 0;
r242996r242997
837865   MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu",i80186_cpu_device,drq1_w))
838866   MCFG_WD_FDC_FORCE_READY
839867   MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0)
840   MCFG_PIT8253_CLK0(XTAL_20MHz / 20)
841   MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))
868   MCFG_PIT8253_CLK0(XTAL_20MHz / 20) 
869   MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))  // clocked on FDC data register access
842870   MCFG_PIT8253_CLK1(XTAL_20MHz / 20)
843   MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))
844   MCFG_PIT8253_CLK2(XTAL_20MHz / 20)
845   MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))
846   // TODO: WD1010 HDC (not implemented)
871   MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w))  // 1MHz
872   MCFG_PIT8253_CLK2(XTAL_20MHz / 10)
873   MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir7_w)) 
874   // TODO: WD1010 HDC (not implemented), use WD2010 for now
875   MCFG_DEVICE_ADD("hdc", WD2010, XTAL_20MHz / 4)
876   MCFG_WD2010_IN_BCS_CB(READ8(ngen_state,hd_buffer_r))
877   MCFG_WD2010_OUT_BCS_CB(WRITE8(ngen_state,hd_buffer_w))
878   MCFG_WD2010_IN_DRDY_CB(VCC)
879   MCFG_WD2010_IN_INDEX_CB(VCC)
880   MCFG_WD2010_IN_WF_CB(VCC)
881   MCFG_WD2010_IN_TK000_CB(VCC)
882   MCFG_WD2010_IN_SC_CB(VCC)
847883   MCFG_DEVICE_ADD("hdc_timer", PIT8253, 0)
884   MCFG_PIT8253_CLK2(XTAL_20MHz / 10)  // 2MHz
848885   MCFG_FLOPPY_DRIVE_ADD("fdc:0", ngen_floppies, "525qd", floppy_image_device::default_floppy_formats)
886   MCFG_HARDDISK_ADD("hard0")
849887
850888MACHINE_CONFIG_END
851889

https://github.com/mamedev/mame/commit/29faa4ce8395ec222914c818b4e22117c8d196e6

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