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r34453 Sunday 18th January, 2015 at 04:59:11 UTC by R. Belmont
twinkle.c: the 68000 & SPU board now process commands, some sound f/x play now.  [R. Belmont]
[src/emu/sound]rf5c400.c rf5c400.h
[src/mame/drivers]twinkle.c

trunk/src/emu/sound/rf5c400.c
r242964r242965
129129
130130         if (env_phase == PHASE_NONE) break;
131131
132         tmp = rom[pos>>16];
132         tmp = rom[(pos>>16) & m_rommask];
133133         switch ( type )
134134         {
135135            case TYPE_16:
r242964r242965
331331   }
332332
333333   m_stream = stream_alloc(0, 2, clock()/384);
334
335   m_rommask = m_rom.length() - 1;
334336}
335337
336338
trunk/src/emu/sound/rf5c400.h
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9898private:
9999   required_region_ptr<INT16> m_rom;
100100
101   UINT32 m_rommask;
102
101103   sound_stream *m_stream;
102104
103105   double m_env_ar_table[0x9f];
trunk/src/mame/drivers/twinkle.c
r242964r242965
254254      m_maincpu(*this, "maincpu"),
255255      m_audiocpu(*this, "audiocpu")
256256   {
257      m_spu_hle[0x200] = 0;
258      m_spu_hle[0x202] = 0;
259257   }
260258
261259   required_device<am53cf96_device> m_am53cf96;
r242964r242965
264262
265263   UINT16 m_spu_ctrl;      // SPU board control register
266264   UINT8 m_spu_shared[0x400];  // SPU/PSX shared dual-ported RAM
267   UINT8 m_spu_hle[0x400];
268265   UINT32 m_spu_ata_dma;
269266   int m_spu_ata_dmarq;
270267
r242964r242965
285282   DECLARE_WRITE16_MEMBER(twinkle_waveram_w);
286283   DECLARE_READ16_MEMBER(shared_68k_r);
287284   DECLARE_WRITE16_MEMBER(shared_68k_w);
285   DECLARE_READ16_MEMBER(unk_68k_r);
288286   DECLARE_WRITE_LINE_MEMBER(spu_ata_irq);
289287   DECLARE_WRITE_LINE_MEMBER(spu_ata_dmarq);
290288   required_device<cpu_device> m_maincpu;
r242964r242965
671669
672670WRITE8_MEMBER(twinkle_state::shared_psx_w)
673671{
674   //printf("shared_psx_w: %04x, %04x, %04x\n", offset, data, mem_mask);
672//   printf("shared_psx_w: %04x, %04x, %04x\n", offset, data, mem_mask);
675673
676674   m_spu_shared[offset] = data;
677675
678   // HLE sound board
679   m_spu_hle[offset] = data;
680
681676   if (offset == 0x03fe && data == 0xff)
682677   {
683      //printf("spu command %02x %02x\n", m_spu_hle[1], m_spu_hle[3]);
678//      printf("spu command %02x %02x\n", m_spu_shared[1], m_spu_shared[3]);
684679
685      for (int i = 0x200; i < 0x300; i++) m_spu_hle[i] = 0xea;
686
687      switch (m_spu_hle[1])
688      {
689      case 0x91: // hdd sum 1
690         m_spu_hle[0x200] = 0; // ?
691         m_spu_hle[0x202] = 0; // ?
692         break;
693
694      case 0x9a: // hdd sum 2
695         m_spu_hle[0x200] = 0; // ?
696         m_spu_hle[0x202] = 0; // ?
697         m_spu_hle[0x203] = 1; // Must be 1 to pass test
698         break;
699
700      case 0xa1: // version
701         m_spu_hle[0x200] = 0; // ?
702         m_spu_hle[0x202] = 0; // ?
703
704         if (strcmp(machine().system().name, "bmiidx") == 0 ||
705            strcmp(machine().system().name, "bmiidxa") == 0 ||
706            strcmp(machine().system().name, "bmiidxc") == 0 ||
707            strcmp(machine().system().name, "bmiidxca") == 0)
708         {
709            strcpy((char *)&m_spu_hle[0x204], "GQ863JA_A");
710         }
711         else if (strcmp(machine().system().name, "bmiidxs") == 0 ||
712            strcmp(machine().system().name, "bmiidxc2") == 0)
713         {
714            strcpy((char *)&m_spu_hle[0x204], "GC983JA_R");
715         }
716         else if (strcmp(machine().system().name, "bmiidx2") == 0)
717         {
718            strcpy((char *)&m_spu_hle[0x204], "GC985JA_A");
719         }
720         else if (strcmp(machine().system().name, "bmiidx3") == 0 ||
721            strcmp(machine().system().name, "bmiidx3a") == 0)
722         {
723            strcpy((char *)&m_spu_hle[0x204], "GC992JA_A");
724         }
725         else if (strcmp(machine().system().name, "bmiidx4") == 0)
726         {
727            strcpy((char *)&m_spu_hle[0x204], "GCA03JA_A");
728         }
729         else if (strcmp(machine().system().name, "bmiidx5") == 0)
730         {
731            strcpy((char *)&m_spu_hle[0x204], "GCA17JA_A");
732         }
733         else if (strcmp(machine().system().name, "bmiidx6") == 0 ||
734            strcmp(machine().system().name, "bmiidx6a") == 0)
735         {
736            strcpy((char *)&m_spu_hle[0x204], "GCB4UJA_A");
737         }
738         else if (strcmp(machine().system().name, "bmiidx7") == 0)
739         {
740            strcpy((char *)&m_spu_hle[0x204], "GCB44JA_A");
741         }
742         else if (strcmp(machine().system().name, "bmiidx8") == 0)
743         {
744            strcpy((char *)&m_spu_hle[0x204], "GCC44JA_A");
745         }
746         break;
747
748      case 0x30: // play sound [3]=sound code
749      case 0x51: // sound off
750      case 0x25: // spu rom error ([3]==0x0f)
751      case 0x26: // spu rom error ([3]==0x0f)
752      case 0x08: // spu rom error
753      case 0x40: // spu rom error ([3]==0x01 coin sound?)
754      case 0x2f: // spu rom error
755      case 0x52: // spu rom error
756      case 0x04: // spu rom error ([3]==?)
757         m_spu_hle[0x200] = 0;
758         m_spu_hle[0x202] = 0;
759         break;
760      }
680      m_audiocpu->set_input_line(M68K_IRQ_4, HOLD_LINE);
761681   }
762682}
763683
764684READ8_MEMBER(twinkle_state::shared_psx_r)
765685{
766   //UINT32 result = m_spu_shared[offset];
767   UINT32 result = m_spu_hle[offset];
686   UINT32 result = m_spu_shared[offset];
768687
769688   //printf("shared_psx_r: %04x, %04x, %04x\n", offset, result, mem_mask);
770689
r242964r242965
803722/*
804723    System control register (Konami always has one)
805724
806    bit 7  = write 0 to ack IRQ 1, write 1 to enable (IRQ 1 appears to be vblank)
725    bit 7  = write 0 to ack IRQ 1, write 1 to enable (IRQ 1 appears to be an RF5C400-related timer, or some free-running timing source)
807726    bit 8  = write 0 to ack IRQ 2, write 1 to enable (IRQ 2 appears to be DMA completion)
808    bit 9  = write 0 to ack IRQ 4, write 1 to enable (IRQ 4 appears to be "command sent", unsure how the MIPS causes it yet however)
809    bit 10 = write 0 to ack IRQ 6, write 1 to enable (IRQ 6 is IDE)
810    bit 11 = watchdog toggle?
727    bit 9  = write 0 to ack IRQ 4, write 1 to enable (IRQ 4 is "command available")
728    bit 10 = write 0 to ack IRQ 6, write 1 to enable (IRQ 6 is the ATA IRQ)
729    bit 11 = watchdog toggle
811730
812731    Other bits unknown.
813732*/
r242964r242965
836755WRITE16_MEMBER(twinkle_state::spu_ata_dma_low_w)
837756{
838757   m_spu_ata_dma = (m_spu_ata_dma & ~0xffff) | data;
839
840   //printf("dma_low %08x\n", m_spu_ata_dma * 2);
841758}
842759
843760WRITE16_MEMBER(twinkle_state::spu_ata_dma_high_w)
844761{
845762   m_spu_ata_dma = (m_spu_ata_dma & 0xffff) | (data << 16);
846
847   //printf("dma_high %08x\n", m_spu_ata_dma * 2);
848763}
849764
850765WRITE_LINE_MEMBER(twinkle_state::spu_ata_dmarq)
r242964r242965
864779            //waveram[m_spu_ata_dma++] = (data >> 8) | (data << 8);
865780            // bp 4a0e ;bmiidx4 checksum
866781            // bp 4d62 ;bmiidx4 dma
867            m_waveram[m_spu_ata_dma++] = data;
782
783            // $$$HACK - game DMAs nothing useful to 0x400000 but all sound plays are 0x400000 or above
784            //           so limit sound RAM to 4MB (there's 6 MB on the board) and let the 5c400's address masking
785            //           work for us until we figure out what's actually going on.
786            if (m_spu_ata_dma < 0x200000)
787            {
788               m_waveram[m_spu_ata_dma++] = data;
789            }
868790         }
869791
870792         m_ata->write_dmack(CLEAR_LINE);
r242964r242965
886808{
887809   UINT16 result = m_spu_shared[offset];
888810
889   //printf("shared_68k_r: %04x, %04x, %04x\n", offset, result, mem_mask);
811//   printf("shared_68k_r: %04x, %04x, %04x\n", offset, result, mem_mask);
890812
891813   return result;
892814}
893815
894816WRITE16_MEMBER(twinkle_state::shared_68k_w)
895817{
896   //printf("shared_68k_w: %04x, %04x, %04x\n", offset, data, mem_mask);
818//   printf("shared_68k_w: %04x, %04x, %04x\n", offset, data, mem_mask);
897819
898820   m_spu_shared[offset] = data & 0xff;
899821}
900822
823READ16_MEMBER(twinkle_state::unk_68k_r)
824{
825   return 0xffff;   // must return 0xff for 68000 POST to complete properly
826}
827
901828static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 16, twinkle_state )
902829   AM_RANGE(0x000000, 0x07ffff) AM_ROM
903830   AM_RANGE(0x100000, 0x13ffff) AM_RAM
831   AM_RANGE(0x200000, 0x200001) AM_READ(unk_68k_r)
904832   // 220000 = LEDs?
905833   AM_RANGE(0x230000, 0x230003) AM_WRITE(twinkle_spu_ctrl_w)
906834   AM_RANGE(0x240000, 0x240003) AM_WRITE(spu_ata_dma_low_w)
r242964r242965
909837   AM_RANGE(0x280000, 0x280fff) AM_READWRITE(shared_68k_r, shared_68k_w)
910838   AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("ata", ata_interface_device, read_cs0, write_cs0)
911839   // 34000E = ???
840   AM_RANGE(0x34000e, 0x34000f) AM_WRITENOP
912841   AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rfsnd", rf5c400_device, rf5c400_r, rf5c400_w)
913   AM_RANGE(0x800000, 0xffffff) AM_READWRITE(twinkle_waveram_r, twinkle_waveram_w )    // 8 MB window wave RAM
842   AM_RANGE(0x800000, 0xbfffff) AM_READWRITE(twinkle_waveram_r, twinkle_waveram_w )
843   AM_RANGE(0xfe0000, 0xffffff) AM_RAM   // ...and the RAM test checks this last 128k (mirror of the work RAM at 0x100000?)
914844ADDRESS_MAP_END
915845
916846/* SCSI */
r242964r242965
1011941
1012942   MCFG_CPU_ADD("audiocpu", M68000, 32000000/2)    /* 16.000 MHz */
1013943   MCFG_CPU_PROGRAM_MAP( sound_map )
944   MCFG_CPU_PERIODIC_INT_DRIVER(twinkle_state, irq1_line_assert, 60)
945   MCFG_CPU_PERIODIC_INT_DRIVER(twinkle_state, irq2_line_assert, 60)
1014946
1015947   MCFG_WATCHDOG_TIME_INIT(attotime::from_msec(1200)) /* check TD pin on LTC1232 */
1016948
r242964r242965
11491081   ROM_REGION32_LE( 0x080000, "audiocpu", 0 )\
11501082   ROM_LOAD16_WORD_SWAP( "863a05.2x",    0x000000, 0x080000, CRC(6f42a09e) SHA1(cab5209f90f47b9ee6e721479913ad74e3ba84b1) )\
11511083\
1152   ROM_REGION16_LE(0x1800000, "rfsnd", ROMREGION_ERASE00)
1084   ROM_REGION16_LE(0x400000, "rfsnd", ROMREGION_ERASE00)
11531085
11541086ROM_START( gq863 )
11551087   TWINKLE_BIOS

https://github.com/mamedev/mame/commit/23c9ff36017ca8c312ade74bdea4e3f0efc338a0

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