Previous 199869 Revisions Next

r34426 Saturday 17th January, 2015 at 03:21:46 UTC by Barry Rodewald
ngen: re-worked X-bus module selection, based on documentation.
[src/mess/drivers]ngen.c

trunk/src/mess/drivers/ngen.c
r242937r242938
8787      m_vram(*this,"vram"),
8888      m_fontram(*this,"fontram"),
8989      m_fdc(*this,"fdc"),
90      m_fd0(*this,"fdc:0")
90      m_fd0(*this,"fdc:0"),
91      m_fdc_timer(*this,"fdc_timer"),
92      m_hdc_timer(*this,"hdc_timer")
9193   {}
9294
9395   DECLARE_WRITE_LINE_MEMBER(pit_out0_w);
r242937r242938
98100   DECLARE_WRITE16_MEMBER(cpu_peripheral_cb);
99101   DECLARE_WRITE16_MEMBER(peripheral_w);
100102   DECLARE_READ16_MEMBER(peripheral_r);
101   DECLARE_WRITE16_MEMBER(port00_w);
102   DECLARE_READ16_MEMBER(port00_r);
103   DECLARE_WRITE16_MEMBER(xbus_w);
104   DECLARE_READ16_MEMBER(xbus_r);
103105   DECLARE_WRITE_LINE_MEMBER(dma_hrq_changed);
104106   DECLARE_WRITE_LINE_MEMBER(dma_eop_changed);
105107   DECLARE_WRITE_LINE_MEMBER(dack0_w);
r242937r242938
118120   DECLARE_WRITE8_MEMBER( dma_1_dack_w ){  }
119121   DECLARE_WRITE8_MEMBER( dma_2_dack_w ){  }
120122   DECLARE_WRITE8_MEMBER( dma_3_dack_w ){ popmessage("IOW3: data %02x",data); }
123
124   DECLARE_WRITE16_MEMBER(hfd_w);
125   DECLARE_READ16_MEMBER(fhd_r);
121126   DECLARE_WRITE_LINE_MEMBER(fdc_irq_w);
122127   DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
123128   DECLARE_WRITE8_MEMBER(fdc_control_w);
r242937r242938
141146   optional_shared_ptr<UINT16> m_fontram;
142147   optional_device<wd2797_t> m_fdc;
143148   optional_device<floppy_connector> m_fd0;
149   optional_device<pit8253_device> m_fdc_timer;
150   optional_device<pit8253_device> m_hdc_timer;
144151
145152   void set_dma_channel(int channel, int state);
146153
154   UINT8 m_xbus_current;  // currently selected X-Bus module
147155   UINT16 m_peripheral;
148156   UINT16 m_upper;
149157   UINT16 m_middle;
r242937r242938
265273      if(mem_mask & 0x00ff)
266274         m_dma_offset[offset-0x80] = data & 0xff;
267275      break;
276   case 0xc0:  // X-Bus modules reset
277      m_xbus_current = 0;
278      break;
268279   case 0x10c:
269280      if(mem_mask & 0x00ff)
270281         m_pic->write(space,0,data & 0xff);
r242937r242938
386397
387398// X-bus module select
388399// The bootstrap ROM creates a table at 0:FC9h, with a count, followed by the module IDs of each
389// expansion module.  The base I/O address for each module is 0x100*module number.
390// Module 0 is the main processor module, module 1 is the next module attached, and so on.
391WRITE16_MEMBER(ngen_state::port00_w)
400// expansion module.  The base I/O address for the currently selected module is set by writing to
401// this register (bits 0-7 are ignored)
402// TODO: make expansion modules slot devices
403WRITE16_MEMBER(ngen_state::xbus_w)
392404{
393   m_port00 = data;
394   logerror("SYS: X-Bus module select %04x\n",data);
405   UINT16 addr = (data & 0x00ff) << 8;
406   address_space& io = m_maincpu->device_t::memory().space(AS_IO);
407   switch(m_xbus_current)
408   {
409      case 0x00:  // Floppy/Hard disk module
410         io.install_readwrite_handler(addr,addr+0xff,0,0,read16_delegate(FUNC(ngen_state::fhd_r),this),write16_delegate(FUNC(ngen_state::hfd_w),this));
411         break;
412      default:
413         m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);  // reached end of the modules
414         break;
415   }
416   if(addr != 0)
417      logerror("SYS: X-Bus module %i address set %04x\n",m_xbus_current+1,addr);
418   m_xbus_current++;
395419}
396420
397// returns X-bus module ID (what is the low byte for?)
398READ16_MEMBER(ngen_state::port00_r)
421// returns X-bus module ID and info in the low byte (can indicate if the device is bootable, has a boot ROM (needs to be written to RAM via DMA), or if it supports a non-80186 CPU)
422// bit 6, I think, indicates a bootable device
423// Known module IDs:
424//  0x1070 - Floppy/Hard disk module
425//  0x3141 - QIC Tape module
426READ16_MEMBER(ngen_state::xbus_r)
399427{
400   if(m_port00 > 0)
401      m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);
402   if(m_port00 == 0)
403      return 0x1070;  // module ID of 0x1070, according to the floppy/hard disk tech manual
404   else
405      return 0x0080;  // invalid device?
428   UINT16 ret = 0xffff;
429   
430   switch(m_xbus_current)
431   {
432      case 0x00:
433         ret = 0x1070;  // Floppy/Hard disk module
434         break;
435      default:
436         m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);  // reached the end of the modules
437         ret = 0x0080;
438         break;
439   }
440   return ret;
406441}
407442
443
444// Floppy/Hard disk module
445WRITE16_MEMBER(ngen_state::hfd_w)
446{
447   switch(offset)
448   {
449      case 0x00:
450      case 0x01:
451      case 0x02:
452      case 0x03:
453         if(mem_mask & 0x00ff)
454            m_fdc->write(space,offset,data & 0xff);
455         break;
456      case 0x04:
457         if(mem_mask & 0x00ff)
458            fdc_control_w(space,offset,data & 0xff);
459         break;
460      case 0x05:
461         if(mem_mask & 0x00ff)
462            hdc_control_w(space,offset,data & 0xff);
463         break;
464      case 0x07:
465         if(mem_mask & 0x00ff)
466            disk_addr_ext(space,offset,data & 0xff);
467         break;
468      case 0x08:
469      case 0x09:
470      case 0x0a:
471      case 0x0b:
472         if(mem_mask & 0x00ff)
473            m_fdc_timer->write(space,offset,data & 0xff);
474         break;
475      case 0x10:
476      case 0x11:
477      case 0x12:
478      case 0x13:
479      case 0x14:
480      case 0x15:
481      case 0x16:
482      case 0x17:
483         logerror("WD1010 register %i write %02x mask %04x\n",offset-0x10,data & 0xff,mem_mask);
484         break;
485      case 0x18:
486      case 0x19:
487      case 0x1a:
488      case 0x1b:
489         if(mem_mask & 0x00ff)
490            m_hdc_timer->write(space,offset,data & 0xff);
491         break;
492   }
493}
494
495READ16_MEMBER(ngen_state::fhd_r)
496{
497   UINT16 ret = 0xffff;
498
499   switch(offset)
500   {
501      case 0x00:
502      case 0x01:
503      case 0x02:
504      case 0x03:
505         if(mem_mask & 0x00ff)
506            ret = m_fdc->read(space,offset);
507         break;
508      case 0x08:
509      case 0x09:
510      case 0x0a:
511      case 0x0b:
512         if(mem_mask & 0x00ff)
513            ret = m_fdc_timer->read(space,offset);
514         break;
515      case 0x10:
516      case 0x11:
517      case 0x12:
518      case 0x13:
519      case 0x14:
520      case 0x15:
521      case 0x16:
522      case 0x17:
523         logerror("WD1010 register %i read, mask %04x\n",offset-0x10,mem_mask);
524         break;
525      case 0x18:
526      case 0x19:
527      case 0x1a:
528      case 0x1b:
529         if(mem_mask & 0x00ff)
530            ret = m_hdc_timer->read(space,offset);
531         break;
532   }
533
534   return ret;
535}
536
408537WRITE_LINE_MEMBER(ngen_state::fdc_irq_w)
409538{
410539   m_pic->ir7_w(state);
r242937r242938
564693{
565694   m_port00 = 0;
566695   m_control = 0;
696   m_xbus_current = 0;
567697   m_viduart->write_dsr(0);
568698   m_viduart->write_cts(0);
569699   m_fd0->get_device()->set_rpm(300);
r242937r242938
578708ADDRESS_MAP_END
579709
580710static ADDRESS_MAP_START( ngen_io, AS_IO, 16, ngen_state )
581   AM_RANGE(0x0000, 0x0001) AM_READWRITE(port00_r,port00_w)
711   AM_RANGE(0x0000, 0x0001) AM_READWRITE(xbus_r,xbus_w)
582712   
583   // TODO: allow for expansion modules to be allocated where asked to
584713   // Floppy/Hard disk module
585   AM_RANGE(0x0100, 0x0107) AM_DEVREADWRITE8("fdc",wd2797_t,read,write,0x00ff)  // a guess for now
586   AM_RANGE(0x0108, 0x0109) AM_WRITE8(fdc_control_w,0x00ff)
587   AM_RANGE(0x010a, 0x010b) AM_WRITE8(hdc_control_w,0x00ff)
588   AM_RANGE(0x010e, 0x010f) AM_WRITE8(disk_addr_ext,0x00ff)  // X-Bus extended address register
589   AM_RANGE(0x0110, 0x0117) AM_DEVREADWRITE8("fdc_timer",pit8253_device,read,write,0x00ff)
714//   AM_RANGE(0x0100, 0x0107) AM_DEVREADWRITE8("fdc",wd2797_t,read,write,0x00ff)  // a guess for now
715//   AM_RANGE(0x0108, 0x0109) AM_WRITE8(fdc_control_w,0x00ff)
716//   AM_RANGE(0x010a, 0x010b) AM_WRITE8(hdc_control_w,0x00ff)
717//   AM_RANGE(0x010e, 0x010f) AM_WRITE8(disk_addr_ext,0x00ff)  // X-Bus extended address register
718//   AM_RANGE(0x0110, 0x0117) AM_DEVREADWRITE8("fdc_timer",pit8253_device,read,write,0x00ff)
590719   // 0x0120-0x012f - WD1010 Winchester disk controller (unemulated)
591   AM_RANGE(0x0130, 0x0137) AM_DEVREADWRITE8("hdc_timer",pit8253_device,read,write,0x00ff)
720//   AM_RANGE(0x0130, 0x0137) AM_DEVREADWRITE8("hdc_timer",pit8253_device,read,write,0x00ff)
592721   
593722ADDRESS_MAP_END
594723

https://github.com/mamedev/mame/commit/7460af4b6016d9785eb42e2950eade4bf451db95

Previous 199869 Revisions Next

© 1997-2024 The MAME Team