trunk/src/mame/drivers/senjyo.c
| r242711 | r242712 | |
| 11 | 11 | Right now it does at second and half, presumably due of the unknown PCB clocks. |
| 12 | 12 | |
| 13 | 13 | Note: |
| 14 | | - Star Force shows default MAME palette at POST. Putted it all_black for now. |
| 14 | - Star Force shows default MAME palette at POST. Flipped to all_black for now. |
| 15 | 15 | |
| 16 | 16 | This board was obviously born to run Senjyo. Four scrolling layers, gradient |
| 17 | 17 | background, sprite/background priorities, and even a small bitmap for the |
| r242711 | r242712 | |
| 84 | 84 | |
| 85 | 85 | void senjyo_state::machine_reset() |
| 86 | 86 | { |
| 87 | | /* we must avoid generating interrupts for the first few frames otherwise */ |
| 88 | | /* Senjyo locks up. There must be an interrupt enable port somewhere, */ |
| 89 | | /* or maybe interrupts are genenrated by the CTC. */ |
| 90 | | /* Maybe a write to port d002 clears the IRQ line, but I'm not sure. */ |
| 91 | | m_int_delay_kludge = 10; |
| 87 | // ... |
| 92 | 88 | } |
| 93 | 89 | |
| 94 | 90 | INTERRUPT_GEN_MEMBER(senjyo_state::senjyo_interrupt) |
| 95 | 91 | { |
| 96 | | if (m_int_delay_kludge == 0) device.execute().set_input_line(0, HOLD_LINE); |
| 97 | | else m_int_delay_kludge--; |
| 92 | device.execute().set_input_line(0, ASSERT_LINE); |
| 98 | 93 | } |
| 99 | 94 | |
| 95 | WRITE8_MEMBER(senjyo_state::irq_ctrl_w) |
| 96 | { |
| 97 | // irq ack is mandatory for senjyo: it's basically used as an irq mask during POST. |
| 98 | m_maincpu->set_input_line(0, CLEAR_LINE); |
| 99 | } |
| 100 | |
| 100 | 101 | WRITE8_MEMBER(senjyo_state::flip_screen_w) |
| 101 | 102 | { |
| 102 | 103 | flip_screen_set(data); |
| r242711 | r242712 | |
| 154 | 155 | AM_RANGE(0xb800, 0xbbff) AM_RAM AM_SHARE("radarram") |
| 155 | 156 | AM_RANGE(0xd000, 0xd000) AM_READ_PORT("P1") AM_WRITE(flip_screen_w) |
| 156 | 157 | AM_RANGE(0xd001, 0xd001) AM_READ_PORT("P2") |
| 157 | | AM_RANGE(0xd002, 0xd002) AM_READ_PORT("SYSTEM") |
| 158 | AM_RANGE(0xd002, 0xd002) AM_READ_PORT("SYSTEM") AM_WRITE(irq_ctrl_w) |
| 159 | AM_RANGE(0xd003, 0xd003) AM_READNOP // debug cheat port? (i.e. bit 0 in starforc: invincibility, bit 3-0 in senyjo: disables enemy fire) |
| 158 | 160 | AM_RANGE(0xd004, 0xd004) AM_READ_PORT("DSW1") AM_WRITE(sound_cmd_w) |
| 159 | 161 | AM_RANGE(0xd005, 0xd005) AM_READ_PORT("DSW2") |
| 160 | 162 | ADDRESS_MAP_END |
| r242711 | r242712 | |
| 213 | 215 | AM_RANGE(0xb800, 0xbbff) AM_RAM AM_SHARE("radarram") |
| 214 | 216 | AM_RANGE(0xd000, 0xd000) AM_READ_PORT("P1") AM_WRITE(flip_screen_w) |
| 215 | 217 | AM_RANGE(0xd001, 0xd001) AM_READ_PORT("P2") |
| 216 | | AM_RANGE(0xd002, 0xd002) AM_READ_PORT("SYSTEM") |
| 218 | AM_RANGE(0xd002, 0xd002) AM_READ_PORT("SYSTEM") AM_WRITE(irq_ctrl_w) |
| 217 | 219 | AM_RANGE(0xd004, 0xd004) AM_READ_PORT("DSW1") AM_WRITE(sound_cmd_w) |
| 218 | 220 | AM_RANGE(0xd005, 0xd005) AM_READ_PORT("DSW2") |
| 219 | 221 | |
trunk/src/osd/windows/osinline.h
| r242711 | r242712 | |
| 19 | 19 | #include "eivc.h" |
| 20 | 20 | #endif |
| 21 | 21 | |
| 22 | #if __GNUC__ && defined(__i386__) && !defined(__x86_64) |
| 23 | #undef YieldProcessor |
| 24 | #endif |
| 25 | |
| 26 | #ifndef YieldProcessor |
| 27 | #ifdef __GNUC__ |
| 28 | INLINE void osd_yield_processor(void) |
| 29 | { |
| 30 | __asm__ __volatile__ ( "rep; nop" ); |
| 31 | } |
| 32 | #else |
| 33 | INLINE void osd_yield_processor(void) |
| 34 | { |
| 35 | __asm { rep nop } |
| 36 | } |
| 37 | #endif |
| 38 | #else |
| 39 | #define osd_yield_processor YieldProcessor |
| 40 | #endif |
| 41 | |
| 22 | 42 | INT32 win_compare_exchange32(INT32 volatile *ptr, INT32 compare, INT32 exchange); |
| 23 | 43 | INT32 win_atomic_exchange32(INT32 volatile *ptr, INT32 exchange); |
| 24 | 44 | INT32 win_atomic_add32(INT32 volatile *ptr, INT32 delta); |
trunk/src/osd/windows/winwork.c
| r242711 | r242712 | |
| 25 | 25 | |
| 26 | 26 | #include "eminline.h" |
| 27 | 27 | |
| 28 | #include "osinline.h" |
| 28 | 29 | |
| 30 | |
| 29 | 31 | //============================================================ |
| 30 | 32 | // DEBUGGING |
| 31 | 33 | //============================================================ |
| r242711 | r242712 | |
| 57 | 59 | #define end_timing(v) do { } while (0) |
| 58 | 60 | #endif |
| 59 | 61 | |
| 60 | | #if __GNUC__ && defined(__i386__) && !defined(__x86_64) |
| 61 | | #undef YieldProcessor |
| 62 | | #endif |
| 63 | | |
| 64 | | #ifndef YieldProcessor |
| 65 | | #ifdef __GNUC__ |
| 66 | | INLINE void osd_yield_processor(void) |
| 67 | | { |
| 68 | | __asm__ __volatile__ ( "rep; nop" ); |
| 69 | | } |
| 70 | | #else |
| 71 | | INLINE void osd_yield_processor(void) |
| 72 | | { |
| 73 | | __asm { rep nop } |
| 74 | | } |
| 75 | | #endif |
| 76 | | #else |
| 77 | | #define osd_yield_processor YieldProcessor |
| 78 | | #endif |
| 79 | | |
| 80 | | |
| 81 | | |
| 82 | 62 | //============================================================ |
| 83 | 63 | // TYPE DEFINITIONS |
| 84 | 64 | //============================================================ |