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r34089 Sunday 28th December, 2014 at 02:50:51 UTC by Jonathan Gevaryahu
Small comment fixes/addenda. (n/w)
[src/mame/audio]dkong.c
[src/mess/drivers]sdk86.c tispeak.c

trunk/src/mame/audio/dkong.c
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11451145 0: 14 16       ... checkpoint charlie
11461146 1: 14 18       ... checkpoint bravo
11471147 2: 14 1A       ... checkpoint alpha
1148 3: 1C          You'll notice
1148 3: 1C          Use Caution (sounds kinda like 'You'll notice')
11491149 4: 1E 1E       Complete attack mission
11501150 5: 10 10 10    trouble, trouble, trouble
11511151 6: 12 12       all pilots climb up
trunk/src/mess/drivers/sdk86.c
r242600r242601
99        22/06/2011 Working [Robbbert]
1010
1111    TODO:
12    Add 8251A for serial
13    Add optional 2x 8255A
12    Add optional 2x 8255A port read/write logging
1413
1514
1615
r242600r242601
1918There is no speaker or storage facility in the standard kit.
2019
2120Download the User Manual to get the operating procedures.
21The user manual is available from: http://www.bitsavers.org/pdf/intel/8086/9800698A_SDK-86_Users_Man_Apr79.pdf
2222
2323ToDo:
2424- Artwork
trunk/src/mess/drivers/tispeak.c
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1818#include "tispeak.lh"
1919
2020// The master clock is a single stage RC oscillator into TMS5100 RCOSC:
21// C is 68pf, R is a 50kohm trimpot wich is set to 33.6kohm. CPUCLK is this/2, ROMCLK is this/4.
21// In an early 1979 Speak & Spell, C is 68pf, R is a 50kohm trimpot which is set to around 33.6kohm
22// (measured in-circuit). CPUCLK is this osc freq /2, ROMCLK is this osc freq /4.
2223// The typical osc freq curve for TMS5100 is unknown. Let's assume it is set to the default frequency,
23// which is 640kHz according to the TMS5100 documentation.
24// which is 640kHz for 8KHz according to the TMS5100 documentation.
2425
2526#define MASTER_CLOCK (640000)
2627


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