trunk/src/mess/drivers/ngen.c
| r242486 | r242487 | |
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| 126 | 126 | virtual void machine_reset(); |
| 127 | 127 | |
| 128 | 128 | private: |
| 129 | | required_device<cpu_device> m_maincpu; |
| 129 | required_device<i80186_cpu_device> m_maincpu; |
| 130 | 130 | required_device<mc6845_device> m_crtc; |
| 131 | 131 | required_device<i8251_device> m_viduart; |
| 132 | 132 | required_device<upd7201_device> m_iouart; |
| r242486 | r242487 | |
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| 151 | 151 | UINT16 m_control; |
| 152 | 152 | }; |
| 153 | 153 | |
| 154 | class ngen386_state : public driver_device |
| 155 | { |
| 156 | public: |
| 157 | ngen386_state(const machine_config &mconfig, device_type type, const char *tag) |
| 158 | : driver_device(mconfig, type, tag), |
| 159 | m_maincpu(*this,"maincpu"), |
| 160 | m_pic(*this,"pic") |
| 161 | {} |
| 162 | private: |
| 163 | required_device<i386_device> m_maincpu; |
| 164 | required_device<pic8259_device> m_pic; |
| 165 | }; |
| 166 | |
| 154 | 167 | WRITE_LINE_MEMBER(ngen_state::pit_out0_w) |
| 155 | 168 | { |
| 156 | 169 | m_pic->ir3_w(state); // Timer interrupt |
| r242486 | r242487 | |
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| 168 | 181 | { |
| 169 | 182 | m_iouart->rxca_w(state); |
| 170 | 183 | m_iouart->txca_w(state); |
| 171 | | //logerror("PIT Timer 2 state %i\n",state); |
| 184 | popmessage("PIT Timer 2 state %i\n",state); |
| 172 | 185 | } |
| 173 | 186 | |
| 174 | 187 | WRITE_LINE_MEMBER(ngen_state::cpu_timer_w) |
| r242486 | r242487 | |
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| 254 | 267 | m_pic->write(space,1,data & 0xff); |
| 255 | 268 | break; |
| 256 | 269 | case 0x110: |
| 257 | | if(mem_mask & 0x00ff) |
| 258 | | m_pit->write(space,0,data & 0x0ff); |
| 259 | | break; |
| 260 | 270 | case 0x111: |
| 261 | | if(mem_mask & 0x00ff) |
| 262 | | m_pit->write(space,1,data & 0x0ff); |
| 263 | | break; |
| 264 | 271 | case 0x112: |
| 265 | | if(mem_mask & 0x00ff) |
| 266 | | m_pit->write(space,2,data & 0x0ff); |
| 267 | | break; |
| 268 | 272 | case 0x113: |
| 269 | 273 | if(mem_mask & 0x00ff) |
| 270 | | m_pit->write(space,3,data & 0x0ff); |
| 274 | m_pit->write(space,offset-0x110,data & 0xff); |
| 271 | 275 | break; |
| 272 | 276 | case 0x141: |
| 273 | 277 | // bit 1 enables speaker? |
| r242486 | r242487 | |
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| 329 | 333 | if(mem_mask & 0x00ff) |
| 330 | 334 | ret = m_dma_offset[offset-0x80] & 0xff; |
| 331 | 335 | break; |
| 332 | | case 0x110: |
| 336 | case 0x10c: |
| 333 | 337 | if(mem_mask & 0x00ff) |
| 334 | | ret = m_pit->read(space,0); |
| 338 | ret = m_pic->read(space,0); |
| 335 | 339 | break; |
| 336 | | case 0x111: |
| 340 | case 0x10d: |
| 337 | 341 | if(mem_mask & 0x00ff) |
| 338 | | ret = m_pit->read(space,1); |
| 342 | ret = m_pic->read(space,1); |
| 339 | 343 | break; |
| 344 | case 0x110: |
| 345 | case 0x111: |
| 340 | 346 | case 0x112: |
| 341 | | if(mem_mask & 0x00ff) |
| 342 | | ret = m_pit->read(space,2); |
| 343 | | break; |
| 344 | 347 | case 0x113: |
| 345 | 348 | if(mem_mask & 0x00ff) |
| 346 | | ret = m_pit->read(space,3); |
| 349 | ret = m_pit->read(space,offset-0x110); |
| 347 | 350 | break; |
| 348 | 351 | case 0x141: |
| 349 | 352 | ret = m_periph141; |
| r242486 | r242487 | |
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| 368 | 371 | case 0x1a0: // I/O control register? |
| 369 | 372 | ret = m_control; // end of DMA transfer? (maybe a per-channel EOP?) Bit 6 is set during a transfer? |
| 370 | 373 | break; |
| 371 | | case 0x1b1: |
| 372 | | ret = 0; |
| 373 | | ret |= 0x02; // also checked after DMA transfer ends |
| 374 | | break; |
| 375 | 374 | default: |
| 376 | 375 | logerror("(PC=%06x) Unknown 80186 peripheral read offset %04x mask %04x returning %04x\n",m_maincpu->device_t::safe_pc(),offset,mem_mask,ret); |
| 377 | 376 | } |
| r242486 | r242487 | |
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| 516 | 515 | AM_RANGE(0x0000, 0x0001) AM_READWRITE(port00_r,port00_w) |
| 517 | 516 | AM_RANGE(0x0100, 0x0107) AM_DEVREADWRITE8("fdc",wd2797_t,read,write,0x00ff) // a guess for now |
| 518 | 517 | AM_RANGE(0x0108, 0x0109) AM_WRITE8(fdc_control_w,0x00ff) |
| 518 | AM_RANGE(0x0110, 0x0117) AM_DEVREADWRITE8("fdc_timer",pit8253_device,read,write,0x00ff) |
| 519 | 519 | ADDRESS_MAP_END |
| 520 | 520 | |
| 521 | 521 | static ADDRESS_MAP_START( ngen386_mem, AS_PROGRAM, 32, ngen_state ) |
| r242486 | r242487 | |
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| 634 | 634 | MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu",i80186_cpu_device,drq1_w)) |
| 635 | 635 | MCFG_WD_FDC_FORCE_READY |
| 636 | 636 | MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0) |
| 637 | MCFG_PIT8253_CLK0(XTAL_20MHz / 20) |
| 638 | MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w)) |
| 639 | MCFG_PIT8253_CLK1(XTAL_20MHz / 20) |
| 640 | MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w)) |
| 641 | MCFG_PIT8253_CLK2(XTAL_20MHz / 20) |
| 642 | MCFG_PIT8253_OUT2_HANDLER(DEVWRITELINE("pic",pic8259_device,ir4_w)) |
| 637 | 643 | // TODO: WD1010 HDC (not implemented) |
| 638 | 644 | MCFG_DEVICE_ADD("hdc_timer", PIT8253, 0) |
| 639 | 645 | MCFG_FLOPPY_DRIVE_ADD("fdc:0", ngen_floppies, "525qd", floppy_image_device::default_floppy_formats) |
| 640 | 646 | |
| 641 | 647 | MACHINE_CONFIG_END |
| 642 | 648 | |
| 643 | | static MACHINE_CONFIG_DERIVED( ngen386, ngen ) |
| 644 | | MCFG_CPU_REPLACE("maincpu", I386, XTAL_50MHz / 2) |
| 649 | static MACHINE_CONFIG_START( ngen386, ngen386_state ) |
| 650 | MCFG_CPU_ADD("maincpu", I386, XTAL_50MHz / 2) |
| 645 | 651 | MCFG_CPU_PROGRAM_MAP(ngen386_mem) |
| 646 | 652 | MCFG_CPU_IO_MAP(ngen386_io) |
| 647 | | MCFG_DEVICE_REMOVE("pic") |
| 648 | 653 | MCFG_PIC8259_ADD( "pic", INPUTLINE("maincpu", 0), VCC, NULL ) |
| 649 | 654 | MACHINE_CONFIG_END |
| 650 | 655 | |