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r33902 Monday 15th December, 2014 at 16:16:44 UTC by David Haywood
Merge pull request #73 from felipesanches/dona_barata Initial implementation of "Dona Barata" driver (brazilian whack-a-mole s...

[/trunk]	makefile
[hash]	gamate.xml gba.xml leapster.xml vsmile_cart.xml vz_cass.xml*
[src]	version.c
[src/build]	build.mak file2str.c file2str.py*
[src/emu]	luaengine.c luaengine.h mame.h
[src/emu/bus]	bus.mak
[src/emu/bus/ieee488]	c2040fdc.c c2040fdc.h c8050fdc.c* c8050fdc.h*
[src/emu/bus/isa]	cga.c num9rev.c
[src/emu/bus/pc_kbd]	ec1841.c ec1841.h
[src/emu/bus/wangpc]	tig.c
[src/emu/cpu]	cpu.mak
[src/emu/cpu/arcompact]	arcompactdasm.c arcompactdasm_dispatch.c* arcompactdasm_dispatch.h* arcompactdasm_ops.c* arcompactdasm_ops.h*
[src/emu/cpu/e132xs]	e132xs.c e132xs.h
[src/emu/cpu/h8]	h8_intc.c h8_timer16.c
[src/emu/cpu/m68000]	m68kdasm.c
[src/emu/cpu/pps4]	pps4.c
[src/emu/cpu/sh2]	sh2comn.c
[src/emu/cpu/tms0980]	tms0980.c tms0980.h
[src/emu/drivers]	xtal.h
[src/emu/imagedev]	floppy.c
[src/emu/machine]	i6300esb.c i6300esb.h i82875p.c i82875p.h machine.mak pci.c pci.h r10696.c* r10696.h* ra17xx.c* ra17xx.h* smpc.c
[src/emu/video]	upd7220.c upd7220.h
[src/lib]	lib.mak
[src/lib/formats]	d64_dsk.h d80_dsk.c dcp_dsk.c* dcp_dsk.h* dip_dsk.c* dip_dsk.h* fdd_dsk.c* fdd_dsk.h* nfd_dsk.c* nfd_dsk.h* pc98_dsk.c
[src/mame]	mame.lst mame.mak
[src/mame/drivers]	5clown.c bwidow.c f-32.c gts1.c hikaru.c igs009.c lindbergh.c mjkjidai.c naomi.c peplus.c viper.c wallc.c
[src/mame/includes]	bwidow.h stv.h
[src/mame/layout]	gts1.lay
[src/mame/machine]	atarigen.c
[src/mess]	mess.lst mess.mak
[src/mess/drivers]	a5105.c ampro.c apc.c apple2.c apple2e.c asst128.c bigbord2.c bitgraph.c* compis.c dmv.c ec184x.c excali64.c hp16500.c hp9k_3xx.c* if800.c iskr103x.c leapster.c mathmagi.c mc1502.c merlin.c mz3500.c mz6500.c ngen.c pc6001.c pc9801.c qx10.c simon.c tandy12.c* victor9k.c vt240.c vtech1.c
[src/mess/includes]	compis.h genpc.h mc1502.h mikromik.h victor9k.h
[src/mess/layout]	bitgrpha.lay* bitgrphb.lay* mathmagi.lay tandy12.lay*
[src/mess/machine]	victor9kb.c victor9kb.h
[src/mess/video]	apple2.c mikromik.c
[src/osd/sdl]	input.c
[src/osd/sdl/man]	castool.1 chdman.1 floptool.1 imgtool.1 jedutil.1 ldresample.1 ldverify.1 mame.6 mess.6 romcmp.1 testkeys.1
[src/osd/windows]	drawd3d.c input.c

trunk/hash/gamate.xml

r242413	r242414
3	3
4	4	<!--
5	5	Undumped carts, based on Wikipedia list
6		C1010 - Bump N' Run
	6	C1010 - Bump N' Run (Unreleased?)
7	7	C1016 - Volcano Panic
8		C1020 - Bad Bud Chou Chu's Adventure
9		C1025 - Jackpot
10		C1030 - Beach Volleyball
	8	C1020 - Bad Bud Chou Chu's Adventure (Unreleased?)
	9	C1025 - Jackpot (Unreleased?)
	10	C1030 - Beach Volleyball (Unreleased?)
11	11	C1033 - Fist of Thunder
12		C1034 - Superboy
	12	C1034 - Superboy (Unreleased?)
13	13	C1036 - Jewelriss
14		C1038 - Mars Voyage
15		C1039 - Fortress of Fierceness
16		C1040 - Incantational Couple
	14	C1038 - Mars Voyage (Unreleased?)
	15	C1039 - Column #5 (Unreleased?)
	16	C1040 - ??
17	17	C1041 - Mighty Boxer
18	18	C1042 - Flying Goblin
19	19	C1045 - World Cup Soccer
r242413	r242414
21	21	C1047 - Fortune 'n Luck
22	22	C1048 - Baseball (or Super Baseball)
23	23	C1049 - Punk Boy
24		C1050 - Fortress of Fierceness II
25		C1051 - ??
26		C1052 - Famous
	24	C1050 - Fortress of Fierceness
	25	C1051 - Incantational Couple
	26	C1052 - Famous 7
27	27	C1053 - Metamorphosiser
28	28	C1055 - ??
29	29	C1056 - GP Race

trunk/hash/gba.xml

r242413	r242414
30028	30028	<part name="cart" interface="gba_cart">
30029	30029	<feature name="slot" value="gba_eeprom_64k" />
30030	30030	<dataarea name="rom" size="8388608">
30031		<rom name="sansara naga 1x2 (japan).bin" size="8388608" crc="b3780a4f" sha1="b18e525a3a4b008d76a9c5a7b47cdd4a03b0baec" offset="000000" />
	30031	<rom name="sansara naga 1x2 (japan)(rev2).bin" size="8388608" crc="b3780a4f" sha1="b18e525a3a4b008d76a9c5a7b47cdd4a03b0baec" offset="000000" />
30032	30032	</dataarea>
30033	30033	</part>
30034	30034	</software>

trunk/hash/leapster.xml

r242413	r242414
211	211	</part>
212	212	</software>
213	213
214		<software name="digdino" supported="no">
	214	<software name="digdino" supported="no">
215	215	<description>Digging for Dinosaurs (US)</description>
216	216	<year>2003</year>
217	217	<publisher>LeapFrog</publisher>

trunk/hash/vsmile_cart.xml

r242413	r242414
714	714	</part>
715	715	</software>
716	716
	717	<software name="redhood" supported="no">
	718	<description>Entdecke die Welt von Rotkäppchen (Ger)</description>
	719	<year>200?</year>
	720	<publisher>VTech</publisher>
	721	<part name="cart" interface="vsmile_cart">
	722	<dataarea name="rom" size="8388608">
	723	<rom name="52-92024.bin" size="8388608" crc="cdeb71f9" sha1="21d2ecf5bc22fa94a1015de6f670415b6d42a3b1" offset="0" />
	724	</dataarea>
	725	</part>
	726	</software>
	727
717	728	<software name="alphaprk" supported="no">
718	729	<description>Alphabet Park Adventure (USA)</description>
719	730	<year>200?</year>
r242413	r242414
758	769	</part>
759	770	</software>
760	771
	772	<software name="barney" supported="no">
	773	<description>Barney - Erlebnis-Reise (Ger)</description>
	774	<year>200?</year>
	775	<publisher>VTech</publisher>
	776	<part name="cart" interface="vsmile_cart">
	777	<dataarea name="rom" size="8388608">
	778	<rom name="52-92384.bin" size="8388608" crc="a73855fa" sha1="dcc61ecf05bb41779a78196145136c1e9cbfa415" offset="0" />
	779	</dataarea>
	780	</part>
	781	</software>
	782
761	783	<!-- loads if mapped as Batman TV -->
762	784	<software name="bobbday" supported="no">
763	785	<description>Bob the Builder - Bob's Busy Day (USA)</description>
r242413	r242414
904	926	</part>
905	927	</software>
906	928
	929	<software name="elmo" supported="no">
	930	<description>Elmos großes Abenteuer (Ger)</description>
	931	<year>200?</year>
	932	<publisher>VTech</publisher>
	933	<part name="cart" interface="vsmile_cart">
	934	<dataarea name="rom" size="8388608">
	935	<rom name="52-92264.bin" size="8388608" crc="906b6496" sha1="8932008fef144d2ad3d056fd24f64264825af8ce" offset="0" />
	936	</dataarea>
	937	</part>
	938	</software>
	939
907	940	<software name="footschl" supported="no">
908	941	<description>Fußball Schule (Ger)</description>
909	942	<year>200?</year>
r242413	r242414
1069	1102	</part>
1070	1103	</software>
1071	1104
	1105	<software name="scoobydog" cloneof="scoobydo" supported="no">
	1106	<description>Scooby-Doo! - Im Lernpark (Ger)</description>
	1107	<year>200?</year>
	1108	<publisher>VTech</publisher>
	1109	<part name="cart" interface="vsmile_cart">
	1110	<dataarea name="rom" size="8388608">
	1111	<rom name="52-92164.bin" size="8388608" crc="97576369" sha1="81d84286a09068d54a4d1051040187a1b89c9d42" offset="0" />
	1112	</dataarea>
	1113	</part>
	1114	</software>
	1115
1072	1116	<software name="scoobydodk" cloneof="scoobydo" supported="no">
1073	1117	<description>Scooby-Doo! - Sjov i forlystelsesparken (Den)</description>
1074	1118	<year>200?</year>
r242413	r242414
1091	1135	</part>
1092	1136	</software>
1093	1137
	1138	<software name="erniebrt" supported="no">
	1139	<description>Sesamestrasse - Ernies + Berts Fantastisches Abenteuer (Ger)</description>
	1140	<year>2006?</year>
	1141	<publisher>VTech</publisher>
	1142	<part name="cart" interface="vsmile_cart">
	1143	<dataarea name="rom" size="8388608">
	1144	<rom name="52-92464.bin" size="8388608" crc="064c620c" sha1="d44e8a5507f18e544de707cae4b9a7d309c56fdf" offset="0" />
	1145	</dataarea>
	1146	</part>
	1147	</software>
	1148
1094	1149	<software name="shrek3" supported="no">
1095	1150	<description>Shrek The Third - Arthur's School Day Adventure (USA)</description>
1096	1151	<year>200?</year>
r242413	r242414
1113	1168	</part>
1114	1169	</software>
1115	1170
	1171	<software name="spidermn" supported="no">
	1172	<description>Spider-Man &amp; Freunde - Wettkampf im Space-Labor (Ger)</description>
	1173	<year>200?</year>
	1174	<publisher>VTech</publisher>
	1175	<part name="cart" interface="vsmile_cart">
	1176	<dataarea name="rom" size="8388608">
	1177	<rom name="52-92524.bin" size="8388608" crc="eb9e2303" sha1="07ee3fba4e850487c365fd883ac1fb53a25d0028" offset="0" />
	1178	</dataarea>
	1179	</part>
	1180	</software>
	1181
1116	1182	<software name="spongeb" supported="no">
1117	1183	<description>Spongebob Squarepants - A Day in the Life of a Sponge (USA)</description>
1118	1184	<year>200?</year>

trunk/hash/vz_cass.xml

r0	r242414
	1	<?xml version="1.0"?>
	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
	3
	4	<!--
	5
	6	List of known tape releases by Dick Smith in Australia:
	7
	8	X-7274   Attack of the Killer Tomatoes
	9	X-7231   Match Box
	10	X-7232   Poker
	11	X-7233   Hangman
	12	X-7234   Slot Machine/Knock Off/Russian Roulette
	13	X-7235   Blackjack
	14	X-7236   Circus (*)
	15	X-7237   Biorhythm/Pair Matching/Calendar
	16	X-7238   Horse Race
	17	X-7239   Invaders (*)
	18	X-7240   Dynasty Derby
	19	X-7241   Learjet
	20	X-7242   Ghost Hunter (*)
	21	X-7243   Hoppy (*)
	22	X-7244   Super Snake
	23	X-7245   Knights and Dragons
	24	X-7247   Star Blaster (*)
	25	X-7248   VZ-Asteroids
	26	X-7249   Air Traffic Controller
	27	X-7250   Lunar Lander
	28	X-7251   Statistics 1
	29	X-7252   Statistics 2
	30	X-7253   Matrix
	31	X-7254   Tennis Lesson/Golf Lesson
	32	X-7255   Introduction to BASIC
	33	X-7256   Elementary Geometry
	34	X-7257   Speed Reading
	35	X-7258   Typing Teacher
	36	X-7259   Mailing List
	37	X-7261   Portfolio Management
	38	X-7262   Discounted Cash Flow Analysis
	39	X-7263   Financial Ratio Analysis
	40	X-7264   Tennis (*)
	41	X-7265   Checkers
	42	X-7266   Planet Patrol (*)
	43	X-7268   Ladder Challenge (*)
	44	X-7270   Panik (*)
	45	X-7271   Othello
	46	X-7272   Dracula's Castle
	47	X-7273   Backgammon
	48	X-7275   VZ Chess (*)
	49	X-7276   Music Writer
	50	X-7278   Disassembler
	51	X-7279   Duel
	52	X-7280   Hex Utilities
	53	X-7281   Word Processor
	54	X-7282   Editor Assembler
	55	X-7285   Spell'O'Matic 1 & 2
	56	X-7286   Spell'O'Matic 3 & 4
	57	X-7287   Flashword 1 & 2
	58	X-7288   Flashword 3 & 4
	59	X-7289   Metric Spycatcher
	60	X-7290   Whizkid Spycatcher
	61	X-7330   Sprite Generator
	62	X-7331   Formula One
	63	X-7332   Galaxon (*)
	64	X-7333   Dawn Patrol (*)
	65	X-7339   Space RAM
	66	X-7342   Crash
	67	X-7344   Maze of Argon
	68	X-7345   Word Matching
	69
	70	* = dumped
	71
	72	Demonstration Tape (included with the VZ200)
	73	Demonstration Tape (included with the VZ300)
	74
	75	-->
	76
	77	<softwarelist name="vz_cass" description="Dick Smith VZ-200/300 cassettes">
	78
	79	<software name="chess">
	80	<description>Chess</description>
	81	<year>198?</year>
	82	<publisher>Dick Smith</publisher>
	83	<info name="serial" value="X-7275" />
	84	<part name="cass1" interface="vtech1_cass">
	85	<dataarea name="cass" size="2854400">
	86	<rom name="chess.wav" size="2854400" crc="7cc80cf3" sha1="770b09e8755fad97e12f320cd5fea3416669cd36" offset="0" />
	87	</dataarea>
	88	</part>
	89	</software>
	90
	91	<software name="circus">
	92	<description>Circus</description>
	93	<year>198?</year>
	94	<publisher>Dick Smith</publisher>
	95	<info name="serial" value="X-7236" />
	96	<part name="cass1" interface="vtech1_cass">
	97	<dataarea name="cass" size="1317376">
	98	<rom name="circus.wav" size="1317376" crc="ab3ba833" sha1="1b33e2f3f2389f61f2e815be626b5d84083be77e" offset="0" />
	99	</dataarea>
	100	</part>
	101	</software>
	102
	103	<software name="dawn">
	104	<description>Dawn Patrol</description>
	105	<year>198?</year>
	106	<publisher>Dick Smith</publisher>
	107	<info name="serial" value="X-7333" />
	108	<part name="cass1" interface="vtech1_cass">
	109	<dataarea name="cass" size="3640544">
	110	<rom name="dawn.wav" size="3640544" crc="22d096f5" sha1="ac480a16b6d6b8d6f08875e9c6ca13cadc413fa1" offset="0" />
	111	</dataarea>
	112	</part>
	113	</software>
	114
	115	<!-- Not released by Dick Smith? -->
	116	<software name="defpen">
	117	<description>Defense Penetrator</description>
	118	<year>1982</year>
	119	<publisher>Cosmic Software</publisher>
	120	<info name="author" value="Tom Thiel" />
	121	<part name="cass1" interface="vtech1_cass">
	122	<dataarea name="cass" size="1926592">
	123	<rom name="defpen.wav" size="1926592" crc="b3dfa117" sha1="b7b53d11483fd78dfc81484e0830e6f6913c6e47" offset="0" />
	124	</dataarea>
	125	</part>
	126	</software>
	127
	128	<software name="galaxon">
	129	<description>Galaxon</description>
	130	<year>198?</year>
	131	<publisher>Dick Smith</publisher>
	132	<info name="serial" value="X-7332" />
	133	<part name="cass1" interface="vtech1_cass">
	134	<dataarea name="cass" size="1628976">
	135	<rom name="galaxon.wav" size="1628976" crc="8909df05" sha1="4ee1ce9aa8538b8aad9d0839fdb1396335074945" offset="0" />
	136	</dataarea>
	137	</part>
	138	</software>
	139
	140	<software name="ghost">
	141	<description>Ghost Hunter</description>
	142	<year>198?</year>
	143	<publisher>Dick Smith</publisher>
	144	<info name="author" value="Dubois and McNamara" />
	145	<info name="serial" value="X-7242" />
	146	<part name="cass1" interface="vtech1_cass">
	147	<dataarea name="cass" size="1732336">
	148	<rom name="ghost.wav" size="1732336" crc="b5ed2320" sha1="f58e328e0b20d453a1c0486fd8e10c5f3e7ecfa7" offset="0" />
	149	</dataarea>
	150	</part>
	151	</software>
	152
	153	<software name="hamsam">
	154	<description>Hamburger Sam</description>
	155	<year>????</year>
	156	<publisher></publisher>
	157	<part name="cass1" interface="vtech1_cass">
	158	<dataarea name="cass" size="5109472">
	159	<rom name="hamsam.wav" size="5109472" crc="7aed86a7" sha1="b5061edb1401cea4aee97d8cd92c582c9c14e66b" offset="0" />
	160	</dataarea>
	161	</part>
	162	</software>
	163
	164	<software name="hoppy">
	165	<description>Hoppy</description>
	166	<year>198?</year>
	167	<publisher>Dick Smith</publisher>
	168	<info name="serial" value="X-7243" />
	169	<part name="cass1" interface="vtech1_cass">
	170	<dataarea name="cass" size="3172080">
	171	<rom name="hoppy.wav" size="3172080" crc="60e7e15a" sha1="1d56a04af700a94d44d6bb0ddfaf89213db39ce8" offset="0" />
	172	</dataarea>
	173	</part>
	174	</software>
	175
	176	<software name="invaders">
	177	<description>Invaders</description>
	178	<year>198?</year>
	179	<publisher>Dick Smith</publisher>
	180	<info name="author" value="Dubois and McNamara" />
	181	<info name="serial" value="X-7239" />
	182	<part name="cass1" interface="vtech1_cass">
	183	<dataarea name="cass" size="1723824">
	184	<rom name="invaders.wav" size="1723824" crc="f959681e" sha1="e12bc9384e7fe1efc0ecff6356c3e3ded7ee8373" offset="0" />
	185	</dataarea>
	186	</part>
	187	</software>
	188
	189	<software name="ladder">
	190	<description>Ladder Challenge</description>
	191	<year>198?</year>
	192	<publisher>Dick Smith</publisher>
	193	<info name="serial" value="X-7268" />
	194	<part name="cass1" interface="vtech1_cass">
	195	<dataarea name="cass" size="1622288">
	196	<rom name="ladder.wav" size="1622288" crc="47ab9ccf" sha1="e6d72b7bc26b124c906b9c0e0015137ae8844a4d" offset="0" />
	197	</dataarea>
	198	</part>
	199	</software>
	200
	201	<software name="missile">
	202	<description>Missile</description>
	203	<year>????</year>
	204	<publisher></publisher>
	205	<part name="cass1" interface="vtech1_cass">
	206	<dataarea name="cass" size="5109776">
	207	<rom name="missile.wav" size="5109776" crc="55a1fda4" sha1="1de495534447cee16d3db22b043d53b6d15f05fe" offset="0" />
	208	</dataarea>
	209	</part>
	210	</software>
	211
	212	<software name="panik">
	213	<description>Panik</description>
	214	<year>198?</year>
	215	<publisher>Dick Smith</publisher>
	216	<info name="serial" value="X-7270" />
	217	<part name="cass1" interface="vtech1_cass">
	218	<dataarea name="cass" size="1708928">
	219	<rom name="panik.wav" size="1708928" crc="8b8c4c5a" sha1="e9e2ae5c406f9ac79b186cb34b2849b9e2a477e3" offset="0" />
	220	</dataarea>
	221	</part>
	222	</software>
	223
	224	<software name="ppatrol">
	225	<description>Planet Patrol</description>
	226	<year>198?</year>
	227	<publisher>Dick Smith</publisher>
	228	<info name="serial" value="X-7266" />
	229	<part name="cass1" interface="vtech1_cass">
	230	<dataarea name="cass" size="2107776">
	231	<rom name="ppatrol.wav" size="2107776" crc="3eb828ed" sha1="b56777b732587856f554d978d844a3815ec50f69" offset="0" />
	232	</dataarea>
	233	</part>
	234	</software>
	235
	236	<software name="starblas">
	237	<description>Star Blaster</description>
	238	<year>198?</year>
	239	<publisher>Dick Smith</publisher>
	240	<info name="serial" value="X-7247" />
	241	<info name="usage" value="Needs 16k memory expansion" />
	242	<part name="cass1" interface="vtech1_cass">
	243	<dataarea name="cass" size="3327120">
	244	<rom name="starblas.wav" size="3327120" crc="e6a5b55f" sha1="07715fd8104891d0d4d3b06b5609674ca93af920" offset="0" />
	245	</dataarea>
	246	</part>
	247	</software>
	248
	249	<software name="tennis">
	250	<description>Tennis</description>
	251	<year>198?</year>
	252	<publisher>Dick Smith</publisher>
	253	<info name="serial" value="X-7264" />
	254	<part name="cass1" interface="vtech1_cass">
	255	<dataarea name="cass" size="2100784">
	256	<rom name="tennis.wav" size="2100784" crc="3eb5ed00" sha1="6c2f2d4c9d60b6f2bd977eddd397d6dbdbfc52f1" offset="0" />
	257	</dataarea>
	258	</part>
	259	</software>
	260
	261	</softwarelist>

trunk/makefile

r242413	r242414
959	959	@$(CPPCHECK) $(CPPCHECKFLAGS) $<
960	960	endif
961	961
962		$(OBJ)/%.lh: $(SRC)/%.lay $(FILE2STR_TARGET)
	962	$(OBJ)/%.lh: $(SRC)/%.lay $(SRC)/build/file2str.py
963	963	@echo Converting $<...
964		@$(FILE2STR) $< $@ layout_$(basename $(notdir $<))
	964	@$(PYTHON) $(SRC)/build/file2str.py $< $@ layout_$(basename $(notdir $<))
965	965
966		$(OBJ)/%.fh: $(SRC)/%.png $(PNG2BDC_TARGET) $(FILE2STR_TARGET)
	966	$(OBJ)/%.fh: $(SRC)/%.png $(PNG2BDC_TARGET) $(SRC)/build/file2str.py
967	967	@echo Converting $<...
968	968	@$(PNG2BDC) $< $(OBJ)/temp.bdc
969		@$(FILE2STR) $(OBJ)/temp.bdc $@ font_$(basename $(notdir $<)) UINT8
	969	@$(PYTHON) $(SRC)/build/file2str.py $(OBJ)/temp.bdc $@ font_$(basename $(notdir $<)) UINT8
970	970
971	971	$(DRIVLISTOBJ): $(DRIVLISTSRC)
972	972	@echo Compiling $<...

trunk/src/build/build.mak

r242413	r242414
18	18	# set of build targets
19	19	#-------------------------------------------------
20	20
21		FILE2STR_TARGET = $(BUILDOUT)/file2str$(BUILD_EXE)
22	21	MAKEDEP_TARGET = $(BUILDOUT)/makedep$(BUILD_EXE)
23	22	MAKEMAK_TARGET = $(BUILDOUT)/makemak$(BUILD_EXE)
24	23	MAKELIST_TARGET = $(BUILDOUT)/makelist$(BUILD_EXE)
25	24	PNG2BDC_TARGET = $(BUILDOUT)/png2bdc$(BUILD_EXE)
26	25	VERINFO_TARGET = $(BUILDOUT)/verinfo$(BUILD_EXE)
27	26
28		FILE2STR = $(FILE2STR_TARGET)
29	27	MAKEDEP = $(MAKEDEP_TARGET)
30	28	MAKEMAK = $(MAKEMAK_TARGET)
31	29	MAKELIST = $(MAKELIST_TARGET)
r242413	r242414
34	32
35	33	ifneq ($(TERM),cygwin)
36	34	ifeq ($(TARGETOS),win32)
37		FILE2STR = $(subst /,\,$(FILE2STR_TARGET))
38	35	MAKEDEP = $(subst /,\,$(MAKEDEP_TARGET))
39	36	MAKEMAK = $(subst /,\,$(MAKEMAK_TARGET))
40	37	MAKELIST = $(subst /,\,$(MAKELIST_TARGET))
r242413	r242414
45	42
46	43	ifneq ($(CROSS_BUILD),1)
47	44	BUILD += \
48		$(FILE2STR_TARGET) \
49	45	$(MAKEDEP_TARGET) \
50	46	$(MAKEMAK_TARGET) \
51	47	$(MAKELIST_TARGET) \
r242413	r242414
55	51
56	52
57	53	#-------------------------------------------------
58		# file2str
59		#-------------------------------------------------
60
61		FILE2STROBJS = \
62		$(BUILDOBJ)/file2str.o \
63
64		$(FILE2STR_TARGET): $(FILE2STROBJS) $(LIBOCORE)
65		@echo Linking $@...
66		$(LD) $(LDFLAGS) $^ $(LIBS) -o $@
67
68
69
70		#-------------------------------------------------
71	54	# makedep
72	55	#-------------------------------------------------
73	56
74	57	MAKEDEPOBJS = \
75	58	$(BUILDOBJ)/makedep.o \
	59	$(OBJ)/lib/util/astring.o \
	60	$(OBJ)/lib/util/corealloc.o \
	61	$(OBJ)/lib/util/corefile.o \
	62	$(OBJ)/lib/util/unicode.o \
76	63
77		$(MAKEDEP_TARGET): $(MAKEDEPOBJS) $(LIBUTIL) $(LIBOCORE) $(ZLIB)
	64	$(MAKEDEP_TARGET): $(MAKEDEPOBJS) $(LIBOCORE) $(ZLIB)
78	65	@echo Linking $@...
79	66	$(LD) $(LDFLAGS) $^ $(LIBS) -o $@
80	67
r242413	r242414
86	73
87	74	MAKEMAKOBJS = \
88	75	$(BUILDOBJ)/makemak.o \
	76	$(OBJ)/lib/util/astring.o \
	77	$(OBJ)/lib/util/corealloc.o \
	78	$(OBJ)/lib/util/corefile.o \
	79	$(OBJ)/lib/util/corestr.o \
	80	$(OBJ)/lib/util/unicode.o \
89	81
90		# TODO: 7z and flac - really?
91		$(MAKEMAK_TARGET): $(MAKEMAKOBJS) $(LIBUTIL) $(LIBOCORE) $(ZLIB) $(FLAC_LIB) $(7Z_LIB)
	82	$(MAKEMAK_TARGET): $(MAKEMAKOBJS) $(LIBOCORE) $(ZLIB)
92	83	@echo Linking $@...
93	84	$(LD) $(LDFLAGS) $^ $(LIBS) -o $@
94	85
r242413	r242414
100	91
101	92	MAKELISTOBJS = \
102	93	$(BUILDOBJ)/makelist.o \
	94	$(OBJ)/lib/util/astring.o \
	95	$(OBJ)/lib/util/corealloc.o \
	96	$(OBJ)/lib/util/cstrpool.o \
	97	$(OBJ)/lib/util/corefile.o \
	98	$(OBJ)/lib/util/unicode.o \
103	99
104		# TODO: 7z and flac - really?
105		$(MAKELIST_TARGET): $(MAKELISTOBJS) $(LIBUTIL) $(LIBOCORE) $(ZLIB) $(FLAC_LIB) $(7Z_LIB)
	100	$(MAKELIST_TARGET): $(MAKELISTOBJS) $(LIBOCORE) $(ZLIB)
106	101	@echo Linking $@...
107	102	$(LD) $(LDFLAGS) $^ $(LIBS) -o $@
108	103
r242413	r242414
114	109
115	110	PNG2BDCOBJS = \
116	111	$(BUILDOBJ)/png2bdc.o \
	112	$(OBJ)/lib/util/astring.o \
	113	$(OBJ)/lib/util/corefile.o \
	114	$(OBJ)/lib/util/corealloc.o \
	115	$(OBJ)/lib/util/bitmap.o \
	116	$(OBJ)/lib/util/png.o \
	117	$(OBJ)/lib/util/palette.o \
	118	$(OBJ)/lib/util/unicode.o \
117	119
118		$(PNG2BDC_TARGET): $(PNG2BDCOBJS) $(LIBUTIL) $(LIBOCORE) $(ZLIB)
	120	$(PNG2BDC_TARGET): $(PNG2BDCOBJS) $(LIBOCORE) $(ZLIB)
119	121	@echo Linking $@...
120	122	$(LD) $(LDFLAGS) $^ $(LIBS) -o $@
121	123
r242413	r242414
136	138	#-------------------------------------------------
137	139	# It's a CROSS_BUILD. Ensure the targets exist.
138	140	#-------------------------------------------------
139		$(FILE2STR_TARGET):
140		@echo $@ should be built natively. Nothing to do.
141
142	141	$(MAKEDEP_TARGET):
143	142	@echo $@ should be built natively. Nothing to do.
144	143

trunk/src/build/file2str.c

r242413	r242414
1		/***************************************************************************
2
3		file2str.c
4
5		Simple file to string converter.
6
7		Copyright Nicola Salmoria and the MAME Team.
8		Visit http://mamedev.org for licensing and usage restrictions.
9
10		***************************************************************************/
11
12		#include <stdio.h>
13		#include <stdlib.h>
14
15
16		/*-------------------------------------------------
17		main - primary entry point
18		-------------------------------------------------*/
19
20		int main(int argc, char *argv[])
21		{
22		const char *srcfile, *dstfile, *varname, *type;
23		FILE *src, *dst;
24		unsigned char *buffer;
25		int bytes, offs;
26		int terminate = 1;
27
28		/* needs at least three arguments */
29		if (argc < 4)
30		{
31		fprintf(stderr,
32		"Usage:\n"
33		"  laytostr <source.lay> <output.h> <varname> [<type>]\n"
34		"\n"
35		"The default <type> is char, with an assumed NULL terminator\n"
36		);
37		return 0;
38		}
39
40		/* extract arguments */
41		srcfile = argv[1];
42		dstfile = argv[2];
43		varname = argv[3];
44		type = (argc >= 5) ? argv[4] : "char";
45		if (argc >= 5)
46		terminate = 0;
47
48		/* open source file */
49		src = fopen(srcfile, "rb");
50		if (src == NULL)
51		{
52		fprintf(stderr, "Unable to open source file '%s'\n", srcfile);
53		return 1;
54		}
55
56		/* determine file size */
57		fseek(src, 0, SEEK_END);
58		bytes = ftell(src);
59		fseek(src, 0, SEEK_SET);
60
61		/* allocate memory */
62		buffer = (unsigned char *)malloc(bytes + 1);
63		if (buffer == NULL)
64		{
65		fclose(src);
66		fprintf(stderr, "Out of memory allocating %d byte buffer\n", bytes);
67		return 1;
68		}
69
70		/* read the source file */
71		fread(buffer, 1, bytes, src);
72		buffer[bytes] = 0;
73		fclose(src);
74
75		/* open dest file */
76		dst = fopen(dstfile, "w");
77		if (dst == NULL)
78		{
79		free(buffer);
80		fprintf(stderr, "Unable to open output file '%s'\n", dstfile);
81		return 1;
82		}
83
84		/* write the initial header */
85		fprintf(dst, "extern const %s %s[];\n", type, varname);
86		fprintf(dst, "const %s %s[] =\n{\n\t", type, varname);
87
88		/* write out the data */
89		for (offs = 0; offs < bytes + terminate; offs++)
90		{
91		fprintf(dst, "0x%02x%s", buffer[offs], (offs != bytes + terminate - 1) ? "," : "");
92		if (offs % 16 == 15)
93		fprintf(dst, "\n\t");
94		}
95		fprintf(dst, "\n};\n");
96
97		/* close the files */
98		free(buffer);
99		fclose(dst);
100		return 0;
101		}

trunk/src/build/file2str.py

r0	r242414
	1	#!/usr/bin/python
	2
	3	import string
	4	import sys
	5	import os
	6
	7	if (len(sys.argv) < 4) :
	8	print('Usage:')
	9	print('  file2str <source.lay> <output.h> <varname> [<type>]')
	10	print('')
	11	print('The default <type> is char, with an assumed NULL terminator')
	12	sys.exit(0)
	13
	14	terminate = 1
	15	srcfile = sys.argv[1]
	16	dstfile = sys.argv[2]
	17	varname = sys.argv[3]
	18
	19	if (len(sys.argv) >= 5) :
	20	type = sys.argv[4]
	21	terminate = 0
	22	else:
	23	type = 'char'
	24
	25	try:
	26	myfile = open(srcfile, 'rb')
	27	except IOError:
	28	print("Unable to open source file '%s'" % srcfile)
	29	sys.exit(-1)
	30
	31	bytes = os.path.getsize(srcfile)
	32	try:
	33	dst = open(dstfile,'w')
	34	dst.write('extern const %s %s[];\n' % ( type, varname ));
	35	dst.write('const %s %s[] =\n{\n\t' % ( type, varname));
	36	offs = 0
	37	with open(srcfile, "rb") as src:
	38	while True:
	39	chunk = src.read(16)
	40	if chunk:
	41	for b in chunk:
	42	dst.write('0x%02x' % ord(b))
	43	offs = offs + 1
	44	if offs != bytes:
	45	dst.write(',')
	46	else:
	47	break
	48	if offs != bytes:
	49	dst.write('\n\t')
	50	if terminate == 1:
	51	dst.write(',0x00')
	52	dst.write('\n};\n')
	53	dst.close()
	54	except IOError:
	55	print("Unable to open output file '%s'" % dstfile)
	56	sys.exit(-1)
		No newline at end of file

trunk/src/emu/bus/bus.mak

r242413	r242414
403	403	BUSOBJS += $(BUSOBJ)/ieee488/c2040.o
404	404	BUSOBJS += $(BUSOBJ)/ieee488/c2040fdc.o
405	405	BUSOBJS += $(BUSOBJ)/ieee488/c8050.o
	406	BUSOBJS += $(BUSOBJ)/ieee488/c8050fdc.o
406	407	BUSOBJS += $(BUSOBJ)/ieee488/c8280.o
407	408	BUSOBJS += $(BUSOBJ)/ieee488/d9060.o
408	409	BUSOBJS += $(BUSOBJ)/ieee488/softbox.o

trunk/src/emu/bus/ieee488/c2040fdc.c

r242413	r242414
9	9
10	10	**********************************************************************/
11	11
12		/*
13
14		TODO:
15
16		- writing starts in the middle of a byte
17		- 8050 PLL
18
19		*/
20
21	12	#include "c2040fdc.h"
22	13
23	14
r242413	r242414
35	26	//**************************************************************************
36	27
37	28	const device_type C2040_FDC = &device_creator<c2040_fdc_t>;
38		const device_type C8050_FDC = &device_creator<c8050_fdc_t>;
39	29
40	30
41	31	//-------------------------------------------------
r242413	r242414
67	57	//  c2040_fdc_t - constructor
68	58	//-------------------------------------------------
69	59
70		c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
71		device_t(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
72		m_write_sync(*this),
73		m_write_ready(*this),
74		m_write_error(*this),
75		m_gcr_rom(*this, "gcr"),
76		m_floppy0(NULL),
77		m_floppy1(NULL),
78		m_mtr0(1),
79		m_mtr1(1),
80		m_stp0(0),
81		m_stp1(0),
82		m_ds(0),
83		m_drv_sel(0),
84		m_mode_sel(0),
85		m_rw_sel(0),
86		m_period(attotime::from_hz(clock))
87		{
88		cur_live.tm = attotime::never;
89		cur_live.state = IDLE;
90		cur_live.next_state = -1;
91		cur_live.write_position = 0;
92		cur_live.write_start_time = attotime::never;
93		}
94
95	60	c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
96	61	device_t(mconfig, C2040_FDC, "C2040 FDC", tag, owner, clock, "c2040fdc", __FILE__),
97	62	m_write_sync(*this),
r242413	r242414
118	83	cur_live.drv_sel = m_drv_sel;
119	84	}
120	85
121		c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
122		c2040_fdc_t(mconfig, C8050_FDC, "C8050 FDC", tag, owner, clock, "c8050fdc", __FILE__) { }
123	86
124	87
125
126	88	//-------------------------------------------------
127	89	//  device_start - device-specific startup
128	90	//-------------------------------------------------
r242413	r242414
465	427
466	428	UINT8 data = (BIT(e, 6) << 7) | (BIT(i, 7) << 6) | (e & 0x33) | (BIT(e, 2) << 3) | (i & 0x04);
467	429
468		if (LOG) logerror("%s VIA reads data %02x (%03x)\n", machine().time().as_string(), data, checkpoint_live.shift_reg);
	430	if (LOG) logerror("%s %s VIA reads data %02x (%03x)\n", machine().time().as_string(), machine().describe_context(), data, checkpoint_live.shift_reg);
469	431
470	432	return data;
471	433	}
r242413	r242414
477	439	live_sync();
478	440	m_pi = cur_live.pi = data;
479	441	checkpoint();
480		if (LOG) logerror("%s PI %02x\n", machine().time().as_string(), data);
	442	if (LOG) logerror("%s %s PI %02x\n", machine().time().as_string(), machine().describe_context(), data);
481	443	live_run();
482	444	}
483	445	}
r242413	r242414
489	451	live_sync();
490	452	m_drv_sel = cur_live.drv_sel = state;
491	453	checkpoint();
492		if (LOG) logerror("%s DRV SEL %u\n", machine().time().as_string(), state);
	454	if (LOG) logerror("%s %s DRV SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
493	455	live_run();
494	456	}
495	457	}
r242413	r242414
501	463	live_sync();
502	464	m_mode_sel = cur_live.mode_sel = state;
503	465	checkpoint();
504		if (LOG) logerror("%s MODE SEL %u\n", machine().time().as_string(), state);
	466	if (LOG) logerror("%s %s MODE SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
505	467	live_run();
506	468	}
507	469	}
r242413	r242414
513	475	live_sync();
514	476	m_rw_sel = cur_live.rw_sel = state;
515	477	checkpoint();
516		if (LOG) logerror("%s RW SEL %u\n", machine().time().as_string(), state);
	478	if (LOG) logerror("%s %s RW SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
517	479	if (m_rw_sel) {
518	480	stop_writing(machine().time());
519	481	} else {
r242413	r242414
529	491	{
530	492	live_sync();
531	493	m_mtr0 = state;
532		if (LOG) logerror("%s MTR0 %u\n", machine().time().as_string(), state);
	494	if (LOG) logerror("%s %s MTR0 %u\n", machine().time().as_string(), machine().describe_context(), state);
533	495	m_floppy0->mon_w(state);
534	496	checkpoint();
535	497
r242413	r242414
551	513	{
552	514	live_sync();
553	515	m_mtr1 = state;
554		if (LOG) logerror("%s MTR1 %u\n", machine().time().as_string(), state);
	516	if (LOG) logerror("%s %s MTR1 %u\n", machine().time().as_string(), machine().describe_context(), state);
555	517	if (m_floppy1) m_floppy1->mon_w(state);
556	518	checkpoint();
557	519
r242413	r242414
625	587	{
626	588	live_sync();
627	589	m_ds = cur_live.ds = ds;
	590	if (LOG) logerror("%s %s DS %u\n", machine().time().as_string(), machine().describe_context(), ds);
628	591	checkpoint();
629	592	live_run();
630	593	}
r242413	r242414
635	598	m_floppy0 = floppy0;
636	599	m_floppy1 = floppy1;
637	600	}
638
639		void c8050_fdc_t::live_start()
640		{
641		cur_live.tm = machine().time();
642		cur_live.state = RUNNING;
643		cur_live.next_state = -1;
644
645		cur_live.shift_reg = 0;
646		cur_live.shift_reg_write = 0;
647		cur_live.cycle_counter = 0;
648		cur_live.cell_counter = 0;
649		cur_live.bit_counter = 0;
650		cur_live.ds = m_ds;
651		cur_live.drv_sel = m_drv_sel;
652		cur_live.mode_sel = m_mode_sel;
653		cur_live.rw_sel = m_rw_sel;
654		cur_live.pi = m_pi;
655
656		pll_reset(cur_live.tm, attotime::from_double(0));
657		checkpoint_live = cur_live;
658		pll_save_checkpoint();
659
660		live_run();
661		}
662
663		void c8050_fdc_t::pll_reset(const attotime &when, const attotime clock)
664		{
665		cur_pll.reset(when);
666		cur_pll.set_clock(clock);
667		}
668
669		void c8050_fdc_t::pll_save_checkpoint()
670		{
671		checkpoint_pll = cur_pll;
672		}
673
674		void c8050_fdc_t::pll_retrieve_checkpoint()
675		{
676		cur_pll = checkpoint_pll;
677		}
678
679		void c8050_fdc_t::checkpoint()
680		{
681		checkpoint_live = cur_live;
682		pll_save_checkpoint();
683		}
684
685		void c8050_fdc_t::rollback()
686		{
687		cur_live = checkpoint_live;
688		pll_retrieve_checkpoint();
689		}
690
691		void c8050_fdc_t::live_run(const attotime &limit)
692		{
693		if(cur_live.state == IDLE || cur_live.next_state != -1)
694		return;
695
696		for(;;) {
697		switch(cur_live.state) {
698		case RUNNING: {
699		bool syncpoint = false;
700
701		if (cur_live.tm > limit)
702		return;
703
704		int bit = get_next_bit(cur_live.tm, limit);
705		if(bit < 0)
706		return;
707
708		if (syncpoint) {
709		commit(cur_live.tm);
710
711		cur_live.tm += m_period;
712		live_delay(RUNNING_SYNCPOINT);
713		return;
714		}
715
716		cur_live.tm += m_period;
717		break;
718		}
719
720		case RUNNING_SYNCPOINT: {
721		m_write_ready(cur_live.ready);
722		m_write_sync(cur_live.sync);
723		m_write_error(cur_live.error);
724
725		cur_live.state = RUNNING;
726		checkpoint();
727		break;
728		}
729		}
730		}
731		}
732
733		int c8050_fdc_t::get_next_bit(attotime &tm, const attotime &limit)
734		{
735		return cur_pll.get_next_bit(tm, get_floppy(), limit);
736		}
737
738		void c8050_fdc_t::stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp)
739		{
740		if (mtr) return;
741
742		int tracks = 0;
743
744		switch (old_stp)
745		{
746		case 0: if (stp == 1) tracks++; else if (stp == 2) tracks--; break;
747		case 1: if (stp == 3) tracks++; else if (stp == 0) tracks--; break;
748		case 2: if (stp == 0) tracks++; else if (stp == 3) tracks--; break;
749		case 3: if (stp == 2) tracks++; else if (stp == 1) tracks--; break;
750		}
751
752		if (tracks == -1)
753		{
754		floppy->dir_w(1);
755		floppy->stp_w(1);
756		floppy->stp_w(0);
757		}
758		else if (tracks == 1)
759		{
760		floppy->dir_w(0);
761		floppy->stp_w(1);
762		floppy->stp_w(0);
763		}
764
765		old_stp = stp;
766		}
767
768		WRITE_LINE_MEMBER( c8050_fdc_t::odd_hd_w )
769		{
770		if (m_odd_hd != state)
771		{
772		live_sync();
773		m_odd_hd = cur_live.odd_hd = state;
774		if (LOG) logerror("%s ODD HD %u\n", machine().time().as_string(), state);
775		m_floppy0->ss_w(!state);
776		if (m_floppy1) m_floppy1->ss_w(!state);
777		checkpoint();
778		live_run();
779		}
780		}
781
782		WRITE_LINE_MEMBER( c8050_fdc_t::pull_sync_w )
783		{
784		// TODO
785		if (LOG) logerror("%s PULL SYNC %u\n", machine().time().as_string(), state);
786		}

trunk/src/emu/bus/ieee488/c2040fdc.h

r242413	r242414
18	18	#include "formats/d64_dsk.h"
19	19	#include "formats/d67_dsk.h"
20	20	#include "formats/g64_dsk.h"
21		#include "formats/d80_dsk.h"
22		#include "formats/d82_dsk.h"
23	21	#include "imagedev/floppy.h"
24		#include "machine/fdc_pll.h"
25	22
26	23
27	24
r242413	r242414
50	47	{
51	48	public:
52	49	// construction/destruction
53		c2040_fdc_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
54	50	c2040_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
55	51
56	52	template<class _Object> static devcb_base &set_sync_wr_callback(device_t &device, _Object object) { return downcast<c2040_fdc_t &>(device).m_write_sync.set_callback(object); }
r242413	r242414
68	64
69	65	DECLARE_READ_LINE_MEMBER( wps_r ) { return checkpoint_live.drv_sel ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); }
70	66	DECLARE_READ_LINE_MEMBER( sync_r ) { return checkpoint_live.sync; }
71		DECLARE_READ_LINE_MEMBER( ready_r ) { return checkpoint_live.ready; }
72		DECLARE_READ_LINE_MEMBER( error_r ) { return checkpoint_live.error; }
73	67
74	68	void stp0_w(int stp);
75	69	void stp1_w(int stp);
r242413	r242414
147	141	emu_timer *t_gen;
148	142
149	143	floppy_image_device* get_floppy();
150		virtual void live_start();
151		virtual void checkpoint();
152		virtual void rollback();
	144
	145	void live_start();
	146	void checkpoint();
	147	void rollback();
153	148	bool write_next_bit(bool bit, const attotime &limit);
154	149	void start_writing(const attotime &tm);
155	150	void commit(const attotime &tm);
r242413	r242414
157	152	void live_delay(int state);
158	153	void live_sync();
159	154	void live_abort();
160		virtual void live_run(const attotime &limit = attotime::never);
	155	void live_run(const attotime &limit = attotime::never);
161	156	void get_next_edge(const attotime &when);
162		virtual int get_next_bit(attotime &tm, const attotime &limit);
	157	int get_next_bit(attotime &tm, const attotime &limit);
163	158	};
164	159
165	160
166		// ======================> c8050_fdc_t
167
168		class c8050_fdc_t :  public c2040_fdc_t
169		{
170		public:
171		// construction/destruction
172		c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
173
174		DECLARE_WRITE_LINE_MEMBER( odd_hd_w );
175		DECLARE_WRITE_LINE_MEMBER( pull_sync_w );
176
177		protected:
178		fdc_pll_t cur_pll, checkpoint_pll;
179
180		void stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp);
181
182		virtual void live_start();
183		virtual void checkpoint();
184		virtual void rollback();
185		void pll_reset(const attotime &when, const attotime clock);
186		void pll_save_checkpoint();
187		void pll_retrieve_checkpoint();
188		virtual void live_run(const attotime &limit = attotime::never);
189		virtual int get_next_bit(attotime &tm, const attotime &limit);
190		};
191
192
193
194	161	// device type definition
195	162	extern const device_type C2040_FDC;
196		extern const device_type C8050_FDC;
197	163
198	164
199	165

trunk/src/emu/bus/ieee488/c8050fdc.c

r0	r242414
	1	// license:BSD-3-Clause
	2	// copyright-holders:Curt Coder
	3	/**********************************************************************
	4
	5	Commodore 8050 floppy disk controller emulation
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#include "c8050fdc.h"
	13
	14
	15
	16	//**************************************************************************
	17	//  MACROS / CONSTANTS
	18	//**************************************************************************
	19
	20	#define LOG 1
	21
	22	#define GCR_DECODE(_e, _i) \
	23	((BIT(_e, 6) << 7) | (BIT(_i, 7) << 6) | (_e & 0x33) | (BIT(_e, 2) << 3) | (_i & 0x04))
	24
	25	#define GCR_ENCODE(_e, _i) \
	26	((_e & 0xc0) << 2 | (_i & 0x80) | (_e & 0x3c) << 1 | (_i & 0x04) | (_e & 0x03))
	27
	28
	29
	30	//**************************************************************************
	31	//  DEVICE DEFINITIONS
	32	//**************************************************************************
	33
	34	const device_type C8050_FDC = &device_creator<c8050_fdc_t>;
	35
	36
	37	//-------------------------------------------------
	38	//  ROM( c8050_fdc )
	39	//-------------------------------------------------
	40
	41	ROM_START( c8050_fdc )
	42	ROM_REGION( 0x800, "gcr", 0)
	43	ROM_LOAD( "901467.uk6", 0x000, 0x800, CRC(a23337eb) SHA1(97df576397608455616331f8e837cb3404363fa2) )
	44	ROM_END
	45
	46
	47	//-------------------------------------------------
	48	//  rom_region - device-specific ROM region
	49	//-------------------------------------------------
	50
	51	const rom_entry *c8050_fdc_t::device_rom_region() const
	52	{
	53	return ROM_NAME( c8050_fdc );
	54	}
	55
	56
	57
	58	//**************************************************************************
	59	//  LIVE DEVICE
	60	//**************************************************************************
	61
	62	//-------------------------------------------------
	63	//  c8050_fdc_t - constructor
	64	//-------------------------------------------------
	65
	66	c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	67	device_t(mconfig, C8050_FDC, "C8050 FDC", tag, owner, clock, "c8050fdc", __FILE__),
	68	m_write_sync(*this),
	69	m_write_ready(*this),
	70	m_write_error(*this),
	71	m_gcr_rom(*this, "gcr"),
	72	m_floppy0(NULL),
	73	m_floppy1(NULL),
	74	m_mtr0(1),
	75	m_mtr1(1),
	76	m_stp0(0),
	77	m_stp1(0),
	78	m_ds(0),
	79	m_drv_sel(0),
	80	m_mode_sel(0),
	81	m_rw_sel(0)
	82	{
	83	cur_live.tm = attotime::never;
	84	cur_live.state = IDLE;
	85	cur_live.next_state = -1;
	86	cur_live.drv_sel = m_drv_sel;
	87	}
	88
	89
	90
	91	//-------------------------------------------------
	92	//  device_start - device-specific startup
	93	//-------------------------------------------------
	94
	95	void c8050_fdc_t::device_start()
	96	{
	97	// resolve callbacks
	98	m_write_sync.resolve_safe();
	99	m_write_ready.resolve_safe();
	100	m_write_error.resolve_safe();
	101
	102	// allocate timer
	103	t_gen = timer_alloc(0);
	104
	105	// register for state saving
	106	save_item(NAME(m_mtr0));
	107	save_item(NAME(m_mtr1));
	108	save_item(NAME(m_stp0));
	109	save_item(NAME(m_stp1));
	110	save_item(NAME(m_ds));
	111	save_item(NAME(m_drv_sel));
	112	save_item(NAME(m_mode_sel));
	113	save_item(NAME(m_rw_sel));
	114	}
	115
	116
	117	//-------------------------------------------------
	118	//  device_reset - device-specific reset
	119	//-------------------------------------------------
	120
	121	void c8050_fdc_t::device_reset()
	122	{
	123	live_abort();
	124	}
	125
	126
	127	//-------------------------------------------------
	128	//  device_timer - handler timer events
	129	//-------------------------------------------------
	130
	131	void c8050_fdc_t::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	132	{
	133	live_sync();
	134	live_run();
	135	}
	136
	137	floppy_image_device* c8050_fdc_t::get_floppy()
	138	{
	139	return cur_live.drv_sel ? m_floppy1 : m_floppy0;
	140	}
	141
	142	void c8050_fdc_t::stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp)
	143	{
	144	if (mtr) return;
	145
	146	int tracks = 0;
	147
	148	switch (old_stp)
	149	{
	150	case 0: if (stp == 1) tracks++; else if (stp == 2) tracks--; break;
	151	case 1: if (stp == 3) tracks++; else if (stp == 0) tracks--; break;
	152	case 2: if (stp == 0) tracks++; else if (stp == 3) tracks--; break;
	153	case 3: if (stp == 2) tracks++; else if (stp == 1) tracks--; break;
	154	}
	155
	156	if (tracks == -1)
	157	{
	158	floppy->dir_w(1);
	159	floppy->stp_w(1);
	160	floppy->stp_w(0);
	161	}
	162	else if (tracks == 1)
	163	{
	164	floppy->dir_w(0);
	165	floppy->stp_w(1);
	166	floppy->stp_w(0);
	167	}
	168
	169	old_stp = stp;
	170	}
	171
	172	void c8050_fdc_t::stp0_w(int stp)
	173	{
	174	if (m_stp0 != stp)
	175	{
	176	live_sync();
	177	stp_w(m_floppy0, m_mtr0, m_stp0, stp);
	178	checkpoint();
	179	live_run();
	180	}
	181	}
	182
	183	void c8050_fdc_t::stp1_w(int stp)
	184	{
	185	if (m_stp1 != stp)
	186	{
	187	live_sync();
	188	if (m_floppy1) stp_w(m_floppy1, m_mtr1, m_stp1, stp);
	189	checkpoint();
	190	live_run();
	191	}
	192	}
	193
	194	void c8050_fdc_t::ds_w(int ds)
	195	{
	196	if (m_ds != ds)
	197	{
	198	live_sync();
	199	m_ds = cur_live.ds = ds;
	200	pll_reset(cur_live.tm, attotime::from_hz(clock() / (16 - m_ds)));
	201	checkpoint();
	202	live_run();
	203	}
	204	}
	205
	206	void c8050_fdc_t::set_floppy(floppy_image_device *floppy0, floppy_image_device *floppy1)
	207	{
	208	m_floppy0 = floppy0;
	209	m_floppy1 = floppy1;
	210	}
	211
	212	void c8050_fdc_t::live_start()
	213	{
	214	cur_live.tm = machine().time();
	215	cur_live.state = RUNNING;
	216	cur_live.next_state = -1;
	217
	218	cur_live.shift_reg = 0;
	219	cur_live.shift_reg_write = 0;
	220	cur_live.cycle_counter = 0;
	221	cur_live.cell_counter = 0;
	222	cur_live.bit_counter = 0;
	223	cur_live.ds = m_ds;
	224	cur_live.drv_sel = m_drv_sel;
	225	cur_live.mode_sel = m_mode_sel;
	226	cur_live.rw_sel = m_rw_sel;
	227	cur_live.pi = m_pi;
	228
	229	pll_reset(cur_live.tm, attotime::from_hz(clock() / (16 - m_ds)));
	230	checkpoint_live = cur_live;
	231	pll_save_checkpoint();
	232
	233	live_run();
	234	}
	235
	236	void c8050_fdc_t::pll_reset(const attotime &when, const attotime clock)
	237	{
	238	cur_pll.reset(when);
	239	cur_pll.set_clock(clock);
	240	}
	241
	242	void c8050_fdc_t::pll_start_writing(const attotime &tm)
	243	{
	244	cur_pll.start_writing(tm);
	245	}
	246
	247	void c8050_fdc_t::pll_commit(floppy_image_device *floppy, const attotime &tm)
	248	{
	249	cur_pll.commit(floppy, tm);
	250	}
	251
	252	void c8050_fdc_t::pll_stop_writing(floppy_image_device *floppy, const attotime &tm)
	253	{
	254	cur_pll.stop_writing(floppy, tm);
	255	}
	256
	257	void c8050_fdc_t::pll_save_checkpoint()
	258	{
	259	checkpoint_pll = cur_pll;
	260	}
	261
	262	void c8050_fdc_t::pll_retrieve_checkpoint()
	263	{
	264	cur_pll = checkpoint_pll;
	265	}
	266
	267	int c8050_fdc_t::pll_get_next_bit(attotime &tm, floppy_image_device *floppy, const attotime &limit)
	268	{
	269	return cur_pll.get_next_bit(tm, floppy, limit);
	270	}
	271
	272	bool c8050_fdc_t::pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit)
	273	{
	274	return cur_pll.write_next_bit_prev_cell(bit, tm, floppy, limit);
	275	}
	276
	277	void c8050_fdc_t::checkpoint()
	278	{
	279	pll_commit(get_floppy(), cur_live.tm);
	280	checkpoint_live = cur_live;
	281	pll_save_checkpoint();
	282	}
	283
	284	void c8050_fdc_t::rollback()
	285	{
	286	cur_live = checkpoint_live;
	287	pll_retrieve_checkpoint();
	288	}
	289
	290	void c8050_fdc_t::live_delay(int state)
	291	{
	292	cur_live.next_state = state;
	293	if(cur_live.tm != machine().time())
	294	t_gen->adjust(cur_live.tm - machine().time());
	295	else
	296	live_sync();
	297	}
	298
	299	void c8050_fdc_t::live_sync()
	300	{
	301	if(!cur_live.tm.is_never()) {
	302	if(cur_live.tm > machine().time()) {
	303	rollback();
	304	live_run(machine().time());
	305	pll_commit(get_floppy(), cur_live.tm);
	306	} else {
	307	pll_commit(get_floppy(), cur_live.tm);
	308	if(cur_live.next_state != -1) {
	309	cur_live.state = cur_live.next_state;
	310	cur_live.next_state = -1;
	311	}
	312	if(cur_live.state == IDLE) {
	313	pll_stop_writing(get_floppy(), cur_live.tm);
	314	cur_live.tm = attotime::never;
	315	}
	316	}
	317	cur_live.next_state = -1;
	318	checkpoint();
	319	}
	320	}
	321
	322	void c8050_fdc_t::live_abort()
	323	{
	324	if(!cur_live.tm.is_never() && cur_live.tm > machine().time()) {
	325	rollback();
	326	live_run(machine().time());
	327	}
	328
	329	pll_stop_writing(get_floppy(), cur_live.tm);
	330
	331	cur_live.tm = attotime::never;
	332	cur_live.state = IDLE;
	333	cur_live.next_state = -1;
	334
	335	cur_live.ready = 1;
	336	cur_live.sync = 1;
	337	cur_live.error = 1;
	338	}
	339
	340	void c8050_fdc_t::live_run(const attotime &limit)
	341	{
	342	if(cur_live.state == IDLE || cur_live.next_state != -1)
	343	return;
	344
	345	for(;;) {
	346	switch(cur_live.state) {
	347	case RUNNING: {
	348	bool syncpoint = false;
	349
	350	if (cur_live.tm > limit)
	351	return;
	352
	353	int bit = pll_get_next_bit(cur_live.tm, get_floppy(), limit);
	354	if(bit < 0)
	355	return;
	356
	357	cur_live.shift_reg <<= 1;
	358	cur_live.shift_reg |= bit;
	359	cur_live.shift_reg &= 0x3ff;
	360
	361	// sync
	362	int sync = !((cur_live.shift_reg == 0x3ff) && cur_live.rw_sel);
	363
	364	// bit counter
	365	if (cur_live.rw_sel) {
	366	if (!sync) {
	367	cur_live.bit_counter = 0;
	368	} else if (cur_live.sync) {
	369	cur_live.bit_counter++;
	370	if (cur_live.bit_counter == 10) {
	371	cur_live.bit_counter = 0;
	372	}
	373	}
	374	} else {
	375	cur_live.bit_counter++;
	376	if (cur_live.bit_counter == 10) {
	377	cur_live.bit_counter = 0;
	378	}
	379	}
	380
	381	// GCR decoder
	382	if (cur_live.rw_sel) {
	383	cur_live.i = cur_live.shift_reg;
	384	} else {
	385	cur_live.i = ((cur_live.pi & 0xf0) << 1) | (cur_live.mode_sel << 4) | (cur_live.pi & 0x0f);
	386	}
	387
	388	cur_live.e = m_gcr_rom->base()[cur_live.rw_sel << 10 | cur_live.i];
	389
	390	if (LOG) logerror("%s cyl %u bit %u sync %u bc %u sr %03x i %03x e %02x\n",cur_live.tm.as_string(),get_floppy()->get_cyl(),bit,sync,cur_live.bit_counter,cur_live.shift_reg,cur_live.i,cur_live.e);
	391
	392	// byte ready
	393	int ready = !(cur_live.bit_counter == 9);
	394
	395	// GCR error
	396	int error = !(ready || BIT(cur_live.e, 3));
	397
	398	// write bit
	399	if (!cur_live.rw_sel) { // TODO WPS
	400	int write_bit = BIT(cur_live.shift_reg_write, 9);
	401	if (LOG) logerror("%s writing bit %u sr %03x\n",cur_live.tm.as_string(),write_bit,cur_live.shift_reg_write);
	402	pll_write_next_bit(write_bit, cur_live.tm, get_floppy(), limit);
	403	}
	404
	405	if (!ready) {
	406	// load write shift register
	407	cur_live.shift_reg_write = GCR_ENCODE(cur_live.e, cur_live.i);
	408
	409	if (LOG) logerror("%s load write shift register %03x\n",cur_live.tm.as_string(),cur_live.shift_reg_write);
	410	} else {
	411	// clock write shift register
	412	cur_live.shift_reg_write <<= 1;
	413	cur_live.shift_reg_write &= 0x3ff;
	414	}
	415
	416	if (ready != cur_live.ready) {
	417	if (LOG) logerror("%s READY %u : %02x\n", cur_live.tm.as_string(),ready,GCR_DECODE(cur_live.e, cur_live.i));
	418	cur_live.ready = ready;
	419	syncpoint = true;
	420	}
	421
	422	if (sync != cur_live.sync) {
	423	if (LOG) logerror("%s SYNC %u\n", cur_live.tm.as_string(),sync);
	424	cur_live.sync = sync;
	425	syncpoint = true;
	426	}
	427
	428	if (error != cur_live.error) {
	429	if (LOG) logerror("%s ERROR %u\n", cur_live.tm.as_string(),error);
	430	cur_live.error = error;
	431	syncpoint = true;
	432	}
	433
	434	if (syncpoint) {
	435	live_delay(RUNNING_SYNCPOINT);
	436	return;
	437	}
	438	break;
	439	}
	440
	441	case RUNNING_SYNCPOINT: {
	442	m_write_ready(cur_live.ready);
	443	m_write_sync(cur_live.sync);
	444	m_write_error(cur_live.error);
	445
	446	cur_live.state = RUNNING;
	447	checkpoint();
	448	break;
	449	}
	450	}
	451	}
	452	}
	453
	454	READ8_MEMBER( c8050_fdc_t::read )
	455	{
	456	UINT8 e = checkpoint_live.e;
	457	offs_t i = checkpoint_live.i;
	458
	459	UINT8 data = (BIT(e, 6) << 7) | (BIT(i, 7) << 6) | (e & 0x33) | (BIT(e, 2) << 3) | (i & 0x04);
	460
	461	if (LOG) logerror("%s %s VIA reads data %02x (%03x)\n", machine().time().as_string(), machine().describe_context(), data, checkpoint_live.shift_reg);
	462
	463	return data;
	464	}
	465
	466	WRITE8_MEMBER( c8050_fdc_t::write )
	467	{
	468	if (m_pi != data)
	469	{
	470	live_sync();
	471	m_pi = cur_live.pi = data;
	472	checkpoint();
	473	if (LOG) logerror("%s %s PI %02x\n", machine().time().as_string(), machine().describe_context(), data);
	474	live_run();
	475	}
	476	}
	477
	478	WRITE_LINE_MEMBER( c8050_fdc_t::drv_sel_w )
	479	{
	480	if (m_drv_sel != state)
	481	{
	482	live_sync();
	483	m_drv_sel = cur_live.drv_sel = state;
	484	checkpoint();
	485	if (LOG) logerror("%s %s DRV SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
	486	live_run();
	487	}
	488	}
	489
	490	WRITE_LINE_MEMBER( c8050_fdc_t::mode_sel_w )
	491	{
	492	if (m_mode_sel != state)
	493	{
	494	live_sync();
	495	m_mode_sel = cur_live.mode_sel = state;
	496	checkpoint();
	497	if (LOG) logerror("%s %s MODE SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
	498	live_run();
	499	}
	500	}
	501
	502	WRITE_LINE_MEMBER( c8050_fdc_t::rw_sel_w )
	503	{
	504	if (m_rw_sel != state)
	505	{
	506	live_sync();
	507	m_rw_sel = cur_live.rw_sel = state;
	508	checkpoint();
	509	if (LOG) logerror("%s %s RW SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
	510	if (m_rw_sel) {
	511	pll_stop_writing(get_floppy(), machine().time());
	512	} else {
	513	pll_start_writing(machine().time());
	514	}
	515	live_run();
	516	}
	517	}
	518
	519	WRITE_LINE_MEMBER( c8050_fdc_t::mtr0_w )
	520	{
	521	if (m_mtr0 != state)
	522	{
	523	live_sync();
	524	m_mtr0 = state;
	525	if (LOG) logerror("%s %s MTR0 %u\n", machine().time().as_string(), machine().describe_context(), state);
	526	m_floppy0->mon_w(state);
	527	checkpoint();
	528
	529	if (!m_mtr0 || !m_mtr1) {
	530	if(cur_live.state == IDLE) {
	531	live_start();
	532	}
	533	} else {
	534	live_abort();
	535	}
	536
	537	live_run();
	538	}
	539	}
	540
	541	WRITE_LINE_MEMBER( c8050_fdc_t::mtr1_w )
	542	{
	543	if (m_mtr1 != state)
	544	{
	545	live_sync();
	546	m_mtr1 = state;
	547	if (LOG) logerror("%s %s MTR1 %u\n", machine().time().as_string(), machine().describe_context(), state);
	548	if (m_floppy1) m_floppy1->mon_w(state);
	549	checkpoint();
	550
	551	if (!m_mtr0 || !m_mtr1) {
	552	if(cur_live.state == IDLE) {
	553	live_start();
	554	}
	555	} else {
	556	live_abort();
	557	}
	558
	559	live_run();
	560	}
	561	}
	562
	563	WRITE_LINE_MEMBER( c8050_fdc_t::odd_hd_w )
	564	{
	565	if (m_odd_hd != state)
	566	{
	567	live_sync();
	568	m_odd_hd = cur_live.odd_hd = state;
	569	if (LOG) logerror("%s %s ODD HD %u\n", machine().time().as_string(), machine().describe_context(), state);
	570	m_floppy0->ss_w(!state);
	571	if (m_floppy1) m_floppy1->ss_w(!state);
	572	checkpoint();
	573	live_run();
	574	}
	575	}
	576
	577	WRITE_LINE_MEMBER( c8050_fdc_t::pull_sync_w )
	578	{
	579	// TODO
	580	if (LOG) logerror("%s %s PULL SYNC %u\n", machine().time().as_string(), machine().describe_context(), state);
	581	}

trunk/src/emu/bus/ieee488/c8050fdc.h

r0	r242414
	1	// license:BSD-3-Clause
	2	// copyright-holders:Curt Coder
	3	/**********************************************************************
	4
	5	Commodore 8050 floppy disk controller emulation
	6
	7	Copyright MESS Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	**********************************************************************/
	11
	12	#pragma once
	13
	14	#ifndef __C8050_FLOPPY__
	15	#define __C8050_FLOPPY__
	16
	17	#include "emu.h"
	18	#include "formats/d80_dsk.h"
	19	#include "formats/d82_dsk.h"
	20	#include "imagedev/floppy.h"
	21	#include "machine/fdc_pll.h"
	22
	23
	24
	25	//**************************************************************************
	26	//  INTERFACE CONFIGURATION MACROS
	27	//**************************************************************************
	28
	29	#define MCFG_C8050_SYNC_CALLBACK(_write) \
	30	devcb = &c8050_fdc_t::set_sync_wr_callback(*device, DEVCB_##_write);
	31
	32	#define MCFG_C8050_READY_CALLBACK(_write) \
	33	devcb = &c8050_fdc_t::set_ready_wr_callback(*device, DEVCB_##_write);
	34
	35	#define MCFG_C8050_ERROR_CALLBACK(_write) \
	36	devcb = &c8050_fdc_t::set_error_wr_callback(*device, DEVCB_##_write);
	37
	38
	39
	40	//**************************************************************************
	41	//  TYPE DEFINITIONS
	42	//**************************************************************************
	43
	44	// ======================> c8050_fdc_t
	45
	46	class c8050_fdc_t :  public device_t
	47	{
	48	public:
	49	// construction/destruction
	50	c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	51
	52	template<class _Object> static devcb_base &set_sync_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_sync.set_callback(object); }
	53	template<class _Object> static devcb_base &set_ready_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_ready.set_callback(object); }
	54	template<class _Object> static devcb_base &set_error_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_error.set_callback(object); }
	55
	56	DECLARE_READ8_MEMBER( read );
	57	DECLARE_WRITE8_MEMBER( write );
	58
	59	DECLARE_WRITE_LINE_MEMBER( drv_sel_w );
	60	DECLARE_WRITE_LINE_MEMBER( mode_sel_w );
	61	DECLARE_WRITE_LINE_MEMBER( rw_sel_w );
	62	DECLARE_WRITE_LINE_MEMBER( mtr0_w );
	63	DECLARE_WRITE_LINE_MEMBER( mtr1_w );
	64	DECLARE_WRITE_LINE_MEMBER( odd_hd_w );
	65	DECLARE_WRITE_LINE_MEMBER( pull_sync_w );
	66
	67	DECLARE_READ_LINE_MEMBER( wps_r ) { return checkpoint_live.drv_sel ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); }
	68
	69	void stp0_w(int stp);
	70	void stp1_w(int stp);
	71	void ds_w(int ds);
	72
	73	void set_floppy(floppy_image_device *floppy0, floppy_image_device *floppy1);
	74
	75	protected:
	76	// device-level overrides
	77	virtual void device_start();
	78	virtual void device_reset();
	79	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	80
	81	// optional information overrides
	82	virtual const rom_entry *device_rom_region() const;
	83
	84	void stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp);
	85
	86	enum {
	87	IDLE,
	88	RUNNING,
	89	RUNNING_SYNCPOINT
	90	};
	91
	92	struct live_info {
	93	attotime tm;
	94	int state, next_state;
	95	int sync;
	96	int ready;
	97	int error;
	98	int ds;
	99	int drv_sel;
	100	int mode_sel;
	101	int rw_sel;
	102	int odd_hd;
	103
	104	attotime edge;
	105	UINT16 shift_reg;
	106	int cycle_counter;
	107	int cell_counter;
	108	int bit_counter;
	109	UINT8 e;
	110	offs_t i;
	111
	112	UINT8 pi;
	113	UINT16 shift_reg_write;
	114	};
	115
	116	devcb_write_line m_write_sync;
	117	devcb_write_line m_write_ready;
	118	devcb_write_line m_write_error;
	119
	120	required_memory_region m_gcr_rom;
	121
	122	floppy_image_device *m_floppy0;
	123	floppy_image_device *m_floppy1;
	124
	125	int m_mtr0;
	126	int m_mtr1;
	127	int m_stp0;
	128	int m_stp1;
	129	int m_ds;
	130	int m_drv_sel;
	131	int m_mode_sel;
	132	int m_rw_sel;
	133	int m_odd_hd;
	134	UINT8 m_pi;
	135
	136	live_info cur_live, checkpoint_live;
	137	fdc_pll_t cur_pll, checkpoint_pll;
	138	emu_timer *t_gen;
	139
	140	floppy_image_device* get_floppy();
	141
	142	void live_start();
	143	void checkpoint();
	144	void rollback();
	145	void pll_reset(const attotime &when, const attotime clock);
	146	void pll_start_writing(const attotime &tm);
	147	void pll_commit(floppy_image_device *floppy, const attotime &tm);
	148	void pll_stop_writing(floppy_image_device *floppy, const attotime &tm);
	149	int pll_get_next_bit(attotime &tm, floppy_image_device *floppy, const attotime &limit);
	150	bool pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit);
	151	void pll_save_checkpoint();
	152	void pll_retrieve_checkpoint();
	153	void live_delay(int state);
	154	void live_sync();
	155	void live_abort();
	156	void live_run(const attotime &limit = attotime::never);
	157	};
	158
	159
	160	// device type definition
	161	extern const device_type C8050_FDC;
	162
	163
	164
	165	#endif

trunk/src/emu/bus/isa/cga.c

r242413	r242414
513	513	const rgb_t *palette = m_palette->palette()->entry_list_raw();
514	514	int i;
515	515
516		if ( y == 0 ) CGA_LOG(1,"cga_text_inten_update_row",("\n"));
	516	if ( y == 0 ) CGA_LOG(1,"cga_text_inten_comp_grey_update_row",("\n"));
517	517	for ( i = 0; i < x_count; i++ )
518	518	{
519	519	UINT16 offset = ( ( ma + i ) << 1 ) & 0x3fff;
r242413	r242414
632	632	const rgb_t *palette = m_palette->palette()->entry_list_raw();
633	633	int i;
634	634
635		if ( y == 0 ) CGA_LOG(1,"cga_text_blink_update_row",("\n"));
	635	if ( y == 0 ) CGA_LOG(1,"cga_text_blink_update_row_si",("\n"));
636	636	for ( i = 0; i < x_count; i++ )
637	637	{
638	638	UINT16 offset = ( ( ma + i ) << 1 ) & 0x3fff;

trunk/src/emu/bus/isa/num9rev.c

r242413	r242414
11	11
12	12	const device_type ISA8_NUM_9_REV = &device_creator<isa8_number_9_rev_device>;
13	13
14		static ADDRESS_MAP_START( upd7220_map, AS_0, 8, isa8_number_9_rev_device )
	14	static ADDRESS_MAP_START( upd7220_map, AS_0, 16, isa8_number_9_rev_device )
15	15	AM_RANGE(0x00000, 0x3ffff) AM_NOP
16	16	ADDRESS_MAP_END
17	17
r242413	r242414
22	22	{
23	23	rgb_t color(0);
24	24	UINT16 overlay;
25		if(((address << 3) + 0xc0008) > (1024*1024))
	25	if(((address << 3) + 0xc0016) > (1024*1024))
26	26	return;
27		for(int i = 0; i < 8; i++)
	27	for(int i = 0; i < 16; i++)
28	28	{
29	29	UINT32 addr = (address << 3) + i;
30	30	overlay = m_ram[addr + 0xc0000] << 1;
r242413	r242414
37	37	}
38	38	else
39	39	{
40		if(((address << 3) + 8) > (1024*1024))
	40	if(((address << 3) + 16) > (1024*1024))
41	41	return;
42		for(int i = 0; i < 8; i++)
43		bitmap.pix32(y, x + i) = pal->entry_color(m_ram[(address << 3) + i]);
	42	for(int i = 0; i < 16; i++)
	43	bitmap.pix32(y, x + i) = pal->entry_color(m_ram[(address << 4) + i]);
44	44	}
45	45	}
46	46

trunk/src/emu/bus/pc_kbd/ec1841.c

r242413	r242414
48	48
49	49	ROM_START( ec_1841_keyboard )
50	50	ROM_REGION( 0x400, I8048_TAG, 0 )
51		// XXX add P/N etc
52	51	ROM_LOAD( "1816be48.bin", 0x000, 0x400, CRC(e9abfe44) SHA1(1db430c72c2d007ea0b8ae2514ff15c96baba308) )
53	52	ROM_END
54	53

trunk/src/emu/bus/pc_kbd/ec1841.h

r242413	r242414
15	15	#include "emu.h"
16	16	#include "cpu/mcs48/mcs48.h"
17	17	#include "pc_kbdc.h"
18		#include "machine/rescap.h"
19	18
20	19
21	20
r242413	r242414
81	80	// device type definition
82	81	extern const device_type PC_KBD_EC_1841;
83	82
84
85
86	83	#endif

trunk/src/emu/bus/wangpc/tig.c

r242413	r242414
83	83	//  UPD7220_INTERFACE( hgdc0_intf )
84	84	//-------------------------------------------------
85	85
86		static ADDRESS_MAP_START( upd7220_0_map, AS_0, 8, wangpc_tig_device )
	86	static ADDRESS_MAP_START( upd7220_0_map, AS_0, 16, wangpc_tig_device )
87	87	ADDRESS_MAP_GLOBAL_MASK(0x7fff)
88	88	AM_RANGE(0x0000, 0x0fff) AM_MIRROR(0x1000) AM_RAM // frame buffer
89	89	AM_RANGE(0x4000, 0x7fff) AM_RAM // font memory
r242413	r242414
98	98	//  UPD7220_INTERFACE( hgdc1_intf )
99	99	//-------------------------------------------------
100	100
101		static ADDRESS_MAP_START( upd7220_1_map, AS_0, 8, wangpc_tig_device )
	101	static ADDRESS_MAP_START( upd7220_1_map, AS_0, 16, wangpc_tig_device )
102	102	ADDRESS_MAP_GLOBAL_MASK(0xffff)
103	103	AM_RANGE(0x0000, 0xffff) AM_RAM // graphics memory
104	104	ADDRESS_MAP_END

trunk/src/emu/cpu/arcompact/arcompactdasm.c

r242413	r242414
7	7	#include "emu.h"
8	8	#include <stdarg.h>
9	9
10		static char *output;
	10	#include "arcompactdasm_dispatch.h"
	11	#include "arcompactdasm_ops.h"
11	12
12		static void ATTR_PRINTF(1,2) print(const char *fmt, ...)
13		{
14		va_list vl;
15	13
16		va_start(vl, fmt);
17		vsprintf(output, fmt, vl);
18		va_end(vl);
19		}
20
21	14	/*****************************************************************************/
22	15
23	16
24	17
25	18	/*****************************************************************************/
26	19
27		#define DASM_OPS_16 char *output, offs_t pc, UINT16 op, const UINT8* oprom
28		#define DASM_OPS_32 char *output, offs_t pc, UINT32 op, const UINT8* oprom
29		#define DASM_PARAMS output, pc, op, oprom
30	20
31		#define LIMM_REG 62
32
33		#define GET_LIMM_32 \
34		limm = oprom[6] | (oprom[7] << 8); \
35		limm |= (oprom[4] << 16) | (oprom[5] << 24); \
36
37		int arcompact_handle04_00_dasm(DASM_OPS_32);
38		int arcompact_handle04_01_dasm(DASM_OPS_32);
39		int arcompact_handle04_02_dasm(DASM_OPS_32);
40		int arcompact_handle04_03_dasm(DASM_OPS_32);
41		int arcompact_handle04_04_dasm(DASM_OPS_32);
42		int arcompact_handle04_05_dasm(DASM_OPS_32);
43		int arcompact_handle04_06_dasm(DASM_OPS_32);
44		int arcompact_handle04_07_dasm(DASM_OPS_32);
45		int arcompact_handle04_08_dasm(DASM_OPS_32);
46		int arcompact_handle04_09_dasm(DASM_OPS_32);
47		int arcompact_handle04_0a_dasm(DASM_OPS_32);
48		int arcompact_handle04_0b_dasm(DASM_OPS_32);
49		int arcompact_handle04_0c_dasm(DASM_OPS_32);
50		int arcompact_handle04_0d_dasm(DASM_OPS_32);
51		int arcompact_handle04_0e_dasm(DASM_OPS_32);
52		int arcompact_handle04_0f_dasm(DASM_OPS_32);
53		int arcompact_handle04_10_dasm(DASM_OPS_32);
54		int arcompact_handle04_11_dasm(DASM_OPS_32);
55		int arcompact_handle04_12_dasm(DASM_OPS_32);
56		int arcompact_handle04_13_dasm(DASM_OPS_32);
57		int arcompact_handle04_14_dasm(DASM_OPS_32);
58		int arcompact_handle04_15_dasm(DASM_OPS_32);
59		int arcompact_handle04_16_dasm(DASM_OPS_32);
60		int arcompact_handle04_17_dasm(DASM_OPS_32);
61		int arcompact_handle04_18_dasm(DASM_OPS_32);
62		int arcompact_handle04_19_dasm(DASM_OPS_32);
63		int arcompact_handle04_1a_dasm(DASM_OPS_32);
64		int arcompact_handle04_1b_dasm(DASM_OPS_32);
65		int arcompact_handle04_1c_dasm(DASM_OPS_32);
66		int arcompact_handle04_1d_dasm(DASM_OPS_32);
67		int arcompact_handle04_1e_dasm(DASM_OPS_32);
68		int arcompact_handle04_1f_dasm(DASM_OPS_32);
69		int arcompact_handle04_20_dasm(DASM_OPS_32);
70		int arcompact_handle04_21_dasm(DASM_OPS_32);
71		int arcompact_handle04_22_dasm(DASM_OPS_32);
72		int arcompact_handle04_23_dasm(DASM_OPS_32);
73		int arcompact_handle04_24_dasm(DASM_OPS_32);
74		int arcompact_handle04_25_dasm(DASM_OPS_32);
75		int arcompact_handle04_26_dasm(DASM_OPS_32);
76		int arcompact_handle04_27_dasm(DASM_OPS_32);
77		int arcompact_handle04_28_dasm(DASM_OPS_32);
78		int arcompact_handle04_29_dasm(DASM_OPS_32);
79		int arcompact_handle04_2a_dasm(DASM_OPS_32);
80		int arcompact_handle04_2b_dasm(DASM_OPS_32);
81		int arcompact_handle04_2c_dasm(DASM_OPS_32);
82		int arcompact_handle04_2d_dasm(DASM_OPS_32);
83		int arcompact_handle04_2e_dasm(DASM_OPS_32);
84		int arcompact_handle04_2f_dasm(DASM_OPS_32);
85		int arcompact_handle04_30_dasm(DASM_OPS_32);
86		int arcompact_handle04_31_dasm(DASM_OPS_32);
87		int arcompact_handle04_32_dasm(DASM_OPS_32);
88		int arcompact_handle04_33_dasm(DASM_OPS_32);
89		int arcompact_handle04_34_dasm(DASM_OPS_32);
90		int arcompact_handle04_35_dasm(DASM_OPS_32);
91		int arcompact_handle04_36_dasm(DASM_OPS_32);
92		int arcompact_handle04_37_dasm(DASM_OPS_32);
93		int arcompact_handle04_38_dasm(DASM_OPS_32);
94		int arcompact_handle04_39_dasm(DASM_OPS_32);
95		int arcompact_handle04_3a_dasm(DASM_OPS_32);
96		int arcompact_handle04_3b_dasm(DASM_OPS_32);
97		int arcompact_handle04_3c_dasm(DASM_OPS_32);
98		int arcompact_handle04_3d_dasm(DASM_OPS_32);
99		int arcompact_handle04_3e_dasm(DASM_OPS_32);
100		int arcompact_handle04_3f_dasm(DASM_OPS_32);
101
102		int arcompact_handle04_2f_00_dasm(DASM_OPS_32);
103		int arcompact_handle04_2f_01_dasm(DASM_OPS_32);
104		int arcompact_handle04_2f_02_dasm(DASM_OPS_32);
105		int arcompact_handle04_2f_03_dasm(DASM_OPS_32);
106		int arcompact_handle04_2f_04_dasm(DASM_OPS_32);
107		int arcompact_handle04_2f_05_dasm(DASM_OPS_32);
108		int arcompact_handle04_2f_06_dasm(DASM_OPS_32);
109		int arcompact_handle04_2f_07_dasm(DASM_OPS_32);
110		int arcompact_handle04_2f_08_dasm(DASM_OPS_32);
111		int arcompact_handle04_2f_09_dasm(DASM_OPS_32);
112		int arcompact_handle04_2f_0a_dasm(DASM_OPS_32);
113		int arcompact_handle04_2f_0b_dasm(DASM_OPS_32);
114		int arcompact_handle04_2f_0c_dasm(DASM_OPS_32);
115		int arcompact_handle04_2f_0d_dasm(DASM_OPS_32);
116		int arcompact_handle04_2f_0e_dasm(DASM_OPS_32);
117		int arcompact_handle04_2f_0f_dasm(DASM_OPS_32);
118		int arcompact_handle04_2f_10_dasm(DASM_OPS_32);
119		int arcompact_handle04_2f_11_dasm(DASM_OPS_32);
120		int arcompact_handle04_2f_12_dasm(DASM_OPS_32);
121		int arcompact_handle04_2f_13_dasm(DASM_OPS_32);
122		int arcompact_handle04_2f_14_dasm(DASM_OPS_32);
123		int arcompact_handle04_2f_15_dasm(DASM_OPS_32);
124		int arcompact_handle04_2f_16_dasm(DASM_OPS_32);
125		int arcompact_handle04_2f_17_dasm(DASM_OPS_32);
126		int arcompact_handle04_2f_18_dasm(DASM_OPS_32);
127		int arcompact_handle04_2f_19_dasm(DASM_OPS_32);
128		int arcompact_handle04_2f_1a_dasm(DASM_OPS_32);
129		int arcompact_handle04_2f_1b_dasm(DASM_OPS_32);
130		int arcompact_handle04_2f_1c_dasm(DASM_OPS_32);
131		int arcompact_handle04_2f_1d_dasm(DASM_OPS_32);
132		int arcompact_handle04_2f_1e_dasm(DASM_OPS_32);
133		int arcompact_handle04_2f_1f_dasm(DASM_OPS_32);
134		int arcompact_handle04_2f_20_dasm(DASM_OPS_32);
135		int arcompact_handle04_2f_21_dasm(DASM_OPS_32);
136		int arcompact_handle04_2f_22_dasm(DASM_OPS_32);
137		int arcompact_handle04_2f_23_dasm(DASM_OPS_32);
138		int arcompact_handle04_2f_24_dasm(DASM_OPS_32);
139		int arcompact_handle04_2f_25_dasm(DASM_OPS_32);
140		int arcompact_handle04_2f_26_dasm(DASM_OPS_32);
141		int arcompact_handle04_2f_27_dasm(DASM_OPS_32);
142		int arcompact_handle04_2f_28_dasm(DASM_OPS_32);
143		int arcompact_handle04_2f_29_dasm(DASM_OPS_32);
144		int arcompact_handle04_2f_2a_dasm(DASM_OPS_32);
145		int arcompact_handle04_2f_2b_dasm(DASM_OPS_32);
146		int arcompact_handle04_2f_2c_dasm(DASM_OPS_32);
147		int arcompact_handle04_2f_2d_dasm(DASM_OPS_32);
148		int arcompact_handle04_2f_2e_dasm(DASM_OPS_32);
149		int arcompact_handle04_2f_2f_dasm(DASM_OPS_32);
150		int arcompact_handle04_2f_30_dasm(DASM_OPS_32);
151		int arcompact_handle04_2f_31_dasm(DASM_OPS_32);
152		int arcompact_handle04_2f_32_dasm(DASM_OPS_32);
153		int arcompact_handle04_2f_33_dasm(DASM_OPS_32);
154		int arcompact_handle04_2f_34_dasm(DASM_OPS_32);
155		int arcompact_handle04_2f_35_dasm(DASM_OPS_32);
156		int arcompact_handle04_2f_36_dasm(DASM_OPS_32);
157		int arcompact_handle04_2f_37_dasm(DASM_OPS_32);
158		int arcompact_handle04_2f_38_dasm(DASM_OPS_32);
159		int arcompact_handle04_2f_39_dasm(DASM_OPS_32);
160		int arcompact_handle04_2f_3a_dasm(DASM_OPS_32);
161		int arcompact_handle04_2f_3b_dasm(DASM_OPS_32);
162		int arcompact_handle04_2f_3c_dasm(DASM_OPS_32);
163		int arcompact_handle04_2f_3d_dasm(DASM_OPS_32);
164		int arcompact_handle04_2f_3e_dasm(DASM_OPS_32);
165		int arcompact_handle04_2f_3f_dasm(DASM_OPS_32);
166
167		int arcompact_handle04_2f_3f_00_dasm(DASM_OPS_32);
168		int arcompact_handle04_2f_3f_01_dasm(DASM_OPS_32);
169		int arcompact_handle04_2f_3f_02_dasm(DASM_OPS_32);
170		int arcompact_handle04_2f_3f_03_dasm(DASM_OPS_32);
171		int arcompact_handle04_2f_3f_04_dasm(DASM_OPS_32);
172		int arcompact_handle04_2f_3f_05_dasm(DASM_OPS_32);
173		int arcompact_handle04_2f_3f_06_dasm(DASM_OPS_32);
174		int arcompact_handle04_2f_3f_07_dasm(DASM_OPS_32);
175		int arcompact_handle04_2f_3f_08_dasm(DASM_OPS_32);
176		int arcompact_handle04_2f_3f_09_dasm(DASM_OPS_32);
177		int arcompact_handle04_2f_3f_0a_dasm(DASM_OPS_32);
178		int arcompact_handle04_2f_3f_0b_dasm(DASM_OPS_32);
179		int arcompact_handle04_2f_3f_0c_dasm(DASM_OPS_32);
180		int arcompact_handle04_2f_3f_0d_dasm(DASM_OPS_32);
181		int arcompact_handle04_2f_3f_0e_dasm(DASM_OPS_32);
182		int arcompact_handle04_2f_3f_0f_dasm(DASM_OPS_32);
183		int arcompact_handle04_2f_3f_10_dasm(DASM_OPS_32);
184		int arcompact_handle04_2f_3f_11_dasm(DASM_OPS_32);
185		int arcompact_handle04_2f_3f_12_dasm(DASM_OPS_32);
186		int arcompact_handle04_2f_3f_13_dasm(DASM_OPS_32);
187		int arcompact_handle04_2f_3f_14_dasm(DASM_OPS_32);
188		int arcompact_handle04_2f_3f_15_dasm(DASM_OPS_32);
189		int arcompact_handle04_2f_3f_16_dasm(DASM_OPS_32);
190		int arcompact_handle04_2f_3f_17_dasm(DASM_OPS_32);
191		int arcompact_handle04_2f_3f_18_dasm(DASM_OPS_32);
192		int arcompact_handle04_2f_3f_19_dasm(DASM_OPS_32);
193		int arcompact_handle04_2f_3f_1a_dasm(DASM_OPS_32);
194		int arcompact_handle04_2f_3f_1b_dasm(DASM_OPS_32);
195		int arcompact_handle04_2f_3f_1c_dasm(DASM_OPS_32);
196		int arcompact_handle04_2f_3f_1d_dasm(DASM_OPS_32);
197		int arcompact_handle04_2f_3f_1e_dasm(DASM_OPS_32);
198		int arcompact_handle04_2f_3f_1f_dasm(DASM_OPS_32);
199		int arcompact_handle04_2f_3f_20_dasm(DASM_OPS_32);
200		int arcompact_handle04_2f_3f_21_dasm(DASM_OPS_32);
201		int arcompact_handle04_2f_3f_22_dasm(DASM_OPS_32);
202		int arcompact_handle04_2f_3f_23_dasm(DASM_OPS_32);
203		int arcompact_handle04_2f_3f_24_dasm(DASM_OPS_32);
204		int arcompact_handle04_2f_3f_25_dasm(DASM_OPS_32);
205		int arcompact_handle04_2f_3f_26_dasm(DASM_OPS_32);
206		int arcompact_handle04_2f_3f_27_dasm(DASM_OPS_32);
207		int arcompact_handle04_2f_3f_28_dasm(DASM_OPS_32);
208		int arcompact_handle04_2f_3f_29_dasm(DASM_OPS_32);
209		int arcompact_handle04_2f_3f_2a_dasm(DASM_OPS_32);
210		int arcompact_handle04_2f_3f_2b_dasm(DASM_OPS_32);
211		int arcompact_handle04_2f_3f_2c_dasm(DASM_OPS_32);
212		int arcompact_handle04_2f_3f_2d_dasm(DASM_OPS_32);
213		int arcompact_handle04_2f_3f_2e_dasm(DASM_OPS_32);
214		int arcompact_handle04_2f_3f_2f_dasm(DASM_OPS_32);
215		int arcompact_handle04_2f_3f_30_dasm(DASM_OPS_32);
216		int arcompact_handle04_2f_3f_31_dasm(DASM_OPS_32);
217		int arcompact_handle04_2f_3f_32_dasm(DASM_OPS_32);
218		int arcompact_handle04_2f_3f_33_dasm(DASM_OPS_32);
219		int arcompact_handle04_2f_3f_34_dasm(DASM_OPS_32);
220		int arcompact_handle04_2f_3f_35_dasm(DASM_OPS_32);
221		int arcompact_handle04_2f_3f_36_dasm(DASM_OPS_32);
222		int arcompact_handle04_2f_3f_37_dasm(DASM_OPS_32);
223		int arcompact_handle04_2f_3f_38_dasm(DASM_OPS_32);
224		int arcompact_handle04_2f_3f_39_dasm(DASM_OPS_32);
225		int arcompact_handle04_2f_3f_3a_dasm(DASM_OPS_32);
226		int arcompact_handle04_2f_3f_3b_dasm(DASM_OPS_32);
227		int arcompact_handle04_2f_3f_3c_dasm(DASM_OPS_32);
228		int arcompact_handle04_2f_3f_3d_dasm(DASM_OPS_32);
229		int arcompact_handle04_2f_3f_3e_dasm(DASM_OPS_32);
230		int arcompact_handle04_2f_3f_3f_dasm(DASM_OPS_32);
231
232		int arcompact_handle05_00_dasm(DASM_OPS_32);
233		int arcompact_handle05_01_dasm(DASM_OPS_32);
234		int arcompact_handle05_02_dasm(DASM_OPS_32);
235		int arcompact_handle05_03_dasm(DASM_OPS_32);
236		int arcompact_handle05_04_dasm(DASM_OPS_32);
237		int arcompact_handle05_05_dasm(DASM_OPS_32);
238		int arcompact_handle05_06_dasm(DASM_OPS_32);
239		int arcompact_handle05_07_dasm(DASM_OPS_32);
240		int arcompact_handle05_08_dasm(DASM_OPS_32);
241		int arcompact_handle05_09_dasm(DASM_OPS_32);
242		int arcompact_handle05_0a_dasm(DASM_OPS_32);
243		int arcompact_handle05_0b_dasm(DASM_OPS_32);
244		int arcompact_handle05_0c_dasm(DASM_OPS_32);
245		int arcompact_handle05_0d_dasm(DASM_OPS_32);
246		int arcompact_handle05_0e_dasm(DASM_OPS_32);
247		int arcompact_handle05_0f_dasm(DASM_OPS_32);
248		int arcompact_handle05_10_dasm(DASM_OPS_32);
249		int arcompact_handle05_11_dasm(DASM_OPS_32);
250		int arcompact_handle05_12_dasm(DASM_OPS_32);
251		int arcompact_handle05_13_dasm(DASM_OPS_32);
252		int arcompact_handle05_14_dasm(DASM_OPS_32);
253		int arcompact_handle05_15_dasm(DASM_OPS_32);
254		int arcompact_handle05_16_dasm(DASM_OPS_32);
255		int arcompact_handle05_17_dasm(DASM_OPS_32);
256		int arcompact_handle05_18_dasm(DASM_OPS_32);
257		int arcompact_handle05_19_dasm(DASM_OPS_32);
258		int arcompact_handle05_1a_dasm(DASM_OPS_32);
259		int arcompact_handle05_1b_dasm(DASM_OPS_32);
260		int arcompact_handle05_1c_dasm(DASM_OPS_32);
261		int arcompact_handle05_1d_dasm(DASM_OPS_32);
262		int arcompact_handle05_1e_dasm(DASM_OPS_32);
263		int arcompact_handle05_1f_dasm(DASM_OPS_32);
264		int arcompact_handle05_20_dasm(DASM_OPS_32);
265		int arcompact_handle05_21_dasm(DASM_OPS_32);
266		int arcompact_handle05_22_dasm(DASM_OPS_32);
267		int arcompact_handle05_23_dasm(DASM_OPS_32);
268		int arcompact_handle05_24_dasm(DASM_OPS_32);
269		int arcompact_handle05_25_dasm(DASM_OPS_32);
270		int arcompact_handle05_26_dasm(DASM_OPS_32);
271		int arcompact_handle05_27_dasm(DASM_OPS_32);
272		int arcompact_handle05_28_dasm(DASM_OPS_32);
273		int arcompact_handle05_29_dasm(DASM_OPS_32);
274		int arcompact_handle05_2a_dasm(DASM_OPS_32);
275		int arcompact_handle05_2b_dasm(DASM_OPS_32);
276		int arcompact_handle05_2c_dasm(DASM_OPS_32);
277		int arcompact_handle05_2d_dasm(DASM_OPS_32);
278		int arcompact_handle05_2e_dasm(DASM_OPS_32);
279		int arcompact_handle05_2f_dasm(DASM_OPS_32);
280		int arcompact_handle05_30_dasm(DASM_OPS_32);
281		int arcompact_handle05_31_dasm(DASM_OPS_32);
282		int arcompact_handle05_32_dasm(DASM_OPS_32);
283		int arcompact_handle05_33_dasm(DASM_OPS_32);
284		int arcompact_handle05_34_dasm(DASM_OPS_32);
285		int arcompact_handle05_35_dasm(DASM_OPS_32);
286		int arcompact_handle05_36_dasm(DASM_OPS_32);
287		int arcompact_handle05_37_dasm(DASM_OPS_32);
288		int arcompact_handle05_38_dasm(DASM_OPS_32);
289		int arcompact_handle05_39_dasm(DASM_OPS_32);
290		int arcompact_handle05_3a_dasm(DASM_OPS_32);
291		int arcompact_handle05_3b_dasm(DASM_OPS_32);
292		int arcompact_handle05_3c_dasm(DASM_OPS_32);
293		int arcompact_handle05_3d_dasm(DASM_OPS_32);
294		int arcompact_handle05_3e_dasm(DASM_OPS_32);
295		int arcompact_handle05_3f_dasm(DASM_OPS_32);
296
297
298		int arcompact_handle0c_00_dasm(DASM_OPS_16);
299		int arcompact_handle0c_01_dasm(DASM_OPS_16);
300		int arcompact_handle0c_02_dasm(DASM_OPS_16);
301		int arcompact_handle0c_03_dasm(DASM_OPS_16);
302
303		int arcompact_handle0d_00_dasm(DASM_OPS_16);
304		int arcompact_handle0d_01_dasm(DASM_OPS_16);
305		int arcompact_handle0d_02_dasm(DASM_OPS_16);
306		int arcompact_handle0d_03_dasm(DASM_OPS_16);
307
308		int arcompact_handle0e_00_dasm(DASM_OPS_16);
309		int arcompact_handle0e_01_dasm(DASM_OPS_16);
310		int arcompact_handle0e_02_dasm(DASM_OPS_16);
311		int arcompact_handle0e_03_dasm(DASM_OPS_16);
312
313		int arcompact_handle17_00_dasm(DASM_OPS_16);
314		int arcompact_handle17_01_dasm(DASM_OPS_16);
315		int arcompact_handle17_02_dasm(DASM_OPS_16);
316		int arcompact_handle17_03_dasm(DASM_OPS_16);
317		int arcompact_handle17_04_dasm(DASM_OPS_16);
318		int arcompact_handle17_05_dasm(DASM_OPS_16);
319		int arcompact_handle17_06_dasm(DASM_OPS_16);
320		int arcompact_handle17_07_dasm(DASM_OPS_16);
321
322		int arcompact_handle18_00_dasm(DASM_OPS_16);
323		int arcompact_handle18_01_dasm(DASM_OPS_16);
324		int arcompact_handle18_02_dasm(DASM_OPS_16);
325		int arcompact_handle18_03_dasm(DASM_OPS_16);
326		int arcompact_handle18_04_dasm(DASM_OPS_16);
327
328		int arcompact_handle18_05_dasm(DASM_OPS_16);
329		int arcompact_handle18_05_00_dasm(DASM_OPS_16);
330		int arcompact_handle18_05_01_dasm(DASM_OPS_16);
331		int arcompact_handle18_05_02_dasm(DASM_OPS_16);
332		int arcompact_handle18_05_03_dasm(DASM_OPS_16);
333		int arcompact_handle18_05_04_dasm(DASM_OPS_16);
334		int arcompact_handle18_05_05_dasm(DASM_OPS_16);
335		int arcompact_handle18_05_06_dasm(DASM_OPS_16);
336		int arcompact_handle18_05_07_dasm(DASM_OPS_16);
337
338		int arcompact_handle18_06_dasm(DASM_OPS_16);
339		int arcompact_handle18_06_00_dasm(DASM_OPS_16);
340		int arcompact_handle18_06_01_dasm(DASM_OPS_16);
341		int arcompact_handle18_06_02_dasm(DASM_OPS_16);
342		int arcompact_handle18_06_03_dasm(DASM_OPS_16);
343		int arcompact_handle18_06_04_dasm(DASM_OPS_16);
344		int arcompact_handle18_06_05_dasm(DASM_OPS_16);
345		int arcompact_handle18_06_06_dasm(DASM_OPS_16);
346		int arcompact_handle18_06_07_dasm(DASM_OPS_16);
347		int arcompact_handle18_06_08_dasm(DASM_OPS_16);
348		int arcompact_handle18_06_09_dasm(DASM_OPS_16);
349		int arcompact_handle18_06_0a_dasm(DASM_OPS_16);
350		int arcompact_handle18_06_0b_dasm(DASM_OPS_16);
351		int arcompact_handle18_06_0c_dasm(DASM_OPS_16);
352		int arcompact_handle18_06_0d_dasm(DASM_OPS_16);
353		int arcompact_handle18_06_0e_dasm(DASM_OPS_16);
354		int arcompact_handle18_06_0f_dasm(DASM_OPS_16);
355		int arcompact_handle18_06_10_dasm(DASM_OPS_16);
356		int arcompact_handle18_06_11_dasm(DASM_OPS_16);
357		int arcompact_handle18_06_12_dasm(DASM_OPS_16);
358		int arcompact_handle18_06_13_dasm(DASM_OPS_16);
359		int arcompact_handle18_06_14_dasm(DASM_OPS_16);
360		int arcompact_handle18_06_15_dasm(DASM_OPS_16);
361		int arcompact_handle18_06_16_dasm(DASM_OPS_16);
362		int arcompact_handle18_06_17_dasm(DASM_OPS_16);
363		int arcompact_handle18_06_18_dasm(DASM_OPS_16);
364		int arcompact_handle18_06_19_dasm(DASM_OPS_16);
365		int arcompact_handle18_06_1a_dasm(DASM_OPS_16);
366		int arcompact_handle18_06_1b_dasm(DASM_OPS_16);
367		int arcompact_handle18_06_1c_dasm(DASM_OPS_16);
368		int arcompact_handle18_06_1d_dasm(DASM_OPS_16);
369		int arcompact_handle18_06_1e_dasm(DASM_OPS_16);
370		int arcompact_handle18_06_1f_dasm(DASM_OPS_16);
371
372		int arcompact_handle18_07_dasm(DASM_OPS_16);
373		int arcompact_handle18_07_00_dasm(DASM_OPS_16);
374		int arcompact_handle18_07_01_dasm(DASM_OPS_16);
375		int arcompact_handle18_07_02_dasm(DASM_OPS_16);
376		int arcompact_handle18_07_03_dasm(DASM_OPS_16);
377		int arcompact_handle18_07_04_dasm(DASM_OPS_16);
378		int arcompact_handle18_07_05_dasm(DASM_OPS_16);
379		int arcompact_handle18_07_06_dasm(DASM_OPS_16);
380		int arcompact_handle18_07_07_dasm(DASM_OPS_16);
381		int arcompact_handle18_07_08_dasm(DASM_OPS_16);
382		int arcompact_handle18_07_09_dasm(DASM_OPS_16);
383		int arcompact_handle18_07_0a_dasm(DASM_OPS_16);
384		int arcompact_handle18_07_0b_dasm(DASM_OPS_16);
385		int arcompact_handle18_07_0c_dasm(DASM_OPS_16);
386		int arcompact_handle18_07_0d_dasm(DASM_OPS_16);
387		int arcompact_handle18_07_0e_dasm(DASM_OPS_16);
388		int arcompact_handle18_07_0f_dasm(DASM_OPS_16);
389		int arcompact_handle18_07_10_dasm(DASM_OPS_16);
390		int arcompact_handle18_07_11_dasm(DASM_OPS_16);
391		int arcompact_handle18_07_12_dasm(DASM_OPS_16);
392		int arcompact_handle18_07_13_dasm(DASM_OPS_16);
393		int arcompact_handle18_07_14_dasm(DASM_OPS_16);
394		int arcompact_handle18_07_15_dasm(DASM_OPS_16);
395		int arcompact_handle18_07_16_dasm(DASM_OPS_16);
396		int arcompact_handle18_07_17_dasm(DASM_OPS_16);
397		int arcompact_handle18_07_18_dasm(DASM_OPS_16);
398		int arcompact_handle18_07_19_dasm(DASM_OPS_16);
399		int arcompact_handle18_07_1a_dasm(DASM_OPS_16);
400		int arcompact_handle18_07_1b_dasm(DASM_OPS_16);
401		int arcompact_handle18_07_1c_dasm(DASM_OPS_16);
402		int arcompact_handle18_07_1d_dasm(DASM_OPS_16);
403		int arcompact_handle18_07_1e_dasm(DASM_OPS_16);
404		int arcompact_handle18_07_1f_dasm(DASM_OPS_16);
405
406		int arcompact_handle19_00_dasm(DASM_OPS_16);
407		int arcompact_handle19_01_dasm(DASM_OPS_16);
408		int arcompact_handle19_02_dasm(DASM_OPS_16);
409		int arcompact_handle19_03_dasm(DASM_OPS_16);
410
411		int arcompact_handle1c_00_dasm(DASM_OPS_16);
412		int arcompact_handle1c_01_dasm(DASM_OPS_16);
413
414		int arcompact_handle1d_00_dasm(DASM_OPS_16);
415		int arcompact_handle1d_01_dasm(DASM_OPS_16);
416
417		int arcompact_handle1e_00_dasm(DASM_OPS_16);
418		int arcompact_handle1e_01_dasm(DASM_OPS_16);
419		int arcompact_handle1e_02_dasm(DASM_OPS_16);
420		int arcompact_handle1e_03_dasm(DASM_OPS_16);
421
422		int arcompact_handle1e_03_00_dasm(DASM_OPS_16);
423		int arcompact_handle1e_03_01_dasm(DASM_OPS_16);
424		int arcompact_handle1e_03_02_dasm(DASM_OPS_16);
425		int arcompact_handle1e_03_03_dasm(DASM_OPS_16);
426		int arcompact_handle1e_03_04_dasm(DASM_OPS_16);
427		int arcompact_handle1e_03_05_dasm(DASM_OPS_16);
428		int arcompact_handle1e_03_06_dasm(DASM_OPS_16);
429		int arcompact_handle1e_03_07_dasm(DASM_OPS_16);
430
431
432
433		// condition codes (basic ones are the same as arc
434		static const char *conditions[0x20] =
435		{
436		/* 00 */ "AL", // (aka RA         - Always)
437		/* 01 */ "EQ", // (aka Z          - Zero
438		/* 02 */ "NE", // (aka NZ         - Non-Zero)
439		/* 03 */ "PL", // (aka P          - Positive)
440		/* 04 */ "MI", // (aka N          - Negative)
441		/* 05 */ "CS", // (aka C,  LO     - Carry set / Lower than) (unsigned)
442		/* 06 */ "CC", // (aka CC, NC, HS - Carry Clear / Higher or Same) (unsigned)
443		/* 07 */ "VS", // (aka V          - Overflow set)
444		/* 08 */ "VC", // (aka NV         - Overflow clear)
445		/* 09 */ "GT", // (               - Greater than) (signed)
446		/* 0a */ "GE", // (               - Greater than or Equal) (signed)
447		/* 0b */ "LT", // (               - Less than) (signed)
448		/* 0c */ "LE", // (               - Less than or Equal) (signed)
449		/* 0d */ "HI", // (               - Higher than) (unsigned)
450		/* 0e */ "LS", // (               - Lower or Same) (unsigned)
451		/* 0f */ "PNZ",// (               - Positive non-0 value)
452		/* 10 */ "0x10 Reserved", // possible CPU implementation specifics
453		/* 11 */ "0x11 Reserved",
454		/* 12 */ "0x12 Reserved",
455		/* 13 */ "0x13 Reserved",
456		/* 14 */ "0x14 Reserved",
457		/* 15 */ "0x15 Reserved",
458		/* 16 */ "0x16 Reserved",
459		/* 17 */ "0x17 Reserved",
460		/* 18 */ "0x18 Reserved",
461		/* 19 */ "0x19 Reserved",
462		/* 1a */ "0x1a Reserved",
463		/* 1b */ "0x1b Reserved",
464		/* 1c */ "0x1c Reserved",
465		/* 1d */ "0x1d Reserved",
466		/* 1e */ "0x1e Reserved",
467		/* 1f */ "0x1f Reserved"
468		};
469
470		static const char *table01_01_0x[0x10] =
471		{
472		/* 00 */ "BREQ",
473		/* 01 */ "BRNE",
474		/* 02 */ "BRLT",
475		/* 03 */ "BRGE",
476		/* 04 */ "BRLO",
477		/* 05 */ "BRHS",
478		/* 06 */ "<reserved>",
479		/* 07 */ "<reserved>",
480		/* 08 */ "<reserved>",
481		/* 09 */ "<reserved>",
482		/* 0a */ "<reserved>",
483		/* 0b */ "<reserved>",
484		/* 0c */ "<reserved>",
485		/* 0d */ "<reserved>",
486		/* 0e */ "<BBIT0>",
487		/* 0f */ "<BBIT1>"
488		};
489
490
491
492
493
494		static const char *table0f[0x20] =
495		{
496		/* 00 */ "SOPs", // Sub Operation (another table..) ( table0f_00 )
497		/* 01 */ "0x01 <illegal>",
498		/* 02 */ "SUB_S",
499		/* 03 */ "0x03 <illegal>",
500		/* 04 */ "AND_S",
501		/* 05 */ "OR_S",
502		/* 06 */ "BIC_S",
503		/* 07 */ "XOR_S",
504		/* 08 */ "0x08 <illegal>",
505		/* 09 */ "0x09 <illegal>",
506		/* 0a */ "0x0a <illegal>",
507		/* 0b */ "TST_S",
508		/* 0c */ "MUL64_S",
509		/* 0d */ "SEXB_S",
510		/* 0e */ "SEXW_S",
511		/* 0f */ "EXTB_S",
512		/* 10 */ "EXTW_S",
513		/* 11 */ "ABS_S",
514		/* 12 */ "NOT_S",
515		/* 13 */ "NEG_S",
516		/* 14 */ "ADD1_S",
517		/* 15 */ "ADD2_S>",
518		/* 16 */ "ADD3_S",
519		/* 17 */ "0x17 <illegal>",
520		/* 18 */ "ASL_S (multiple)",
521		/* 19 */ "LSR_S (multiple)",
522		/* 1a */ "ASR_S (multiple)",
523		/* 1b */ "ASL_S (single)",
524		/* 1c */ "LSR_S (single)",
525		/* 1d */ "ASR_S (single)",
526		/* 1e */ "TRAP (not a5?)",
527		/* 1f */ "BRK_S" // 0x7fff only?
528		};
529
530		static const char *table0f_00[0x8] =
531		{
532		/* 00 */ "J_S",
533		/* 01 */ "J_S.D",
534		/* 02 */ "JL_S",
535		/* 03 */ "JL_S.D",
536		/* 04 */ "0x04 <illegal>",
537		/* 05 */ "0x05 <illegal>",
538		/* 06 */ "SUB_S.NE",
539		/* 07 */ "ZOPs", // Sub Operations (yet another table..) ( table0f_00_07 )
540		};
541
542		static const char *table0f_00_07[0x8] =
543		{
544		/* 00 */ "NOP_S",
545		/* 01 */ "UNIMP_S", // unimplemented (not a5?)
546		/* 02 */ "0x02 <illegal>",
547		/* 03 */ "0x03 <illegal>",
548		/* 04 */ "JEQ_S [BLINK]",
549		/* 05 */ "JNE_S [BLINK]",
550		/* 06 */ "J_S [BLINK]",
551		/* 07 */ "J_S.D [BLINK]",
552		};
553
554	21	#define ARCOMPACT_OPERATION ((op & 0xf800) >> 11)
555	22
	23	extern char *output;;
556	24
557		int arcompact_handle00_dasm(DASM_OPS_32)
558		{
559		if (op & 0x00010000)
560		{ // Branch Unconditionally Far
561		// 00000 ssssssssss 1  SSSSSSSSSS N R TTTT
562		INT32 address = (op & 0x07fe0000) >> 17;
563		address |= ((op & 0x0000ffc0) >> 6) << 10;
564		address |= ((op & 0x0000000f) >> 0) << 20;
565		if (address & 0x800000) address = -(address & 0x7fffff);
566
567		print("B %08x (%08x)", pc + (address * 2) + 2, op & ~0xffffffcf);
568		}
569		else
570		{ // Branch Conditionally
571		// 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ
572		INT32 address = (op & 0x07fe0000) >> 17;
573		address |= ((op & 0x0000ffc0) >> 6) << 10;
574		if (address & 0x800000) address = -(address & 0x7fffff);
575
576		UINT8 condition = op & 0x0000001f;
577
578		print("B(%s) %08x (%08x)", conditions[condition], pc + (address * 2) + 2, op & ~0xffffffdf);
579		}
580		return 4;
581		}
582
583		int arcompact_handle01_dasm(DASM_OPS_32)
584		{
585		int size = 4;
586
587		if (op & 0x00010000)
588		{
589		if (op & 0x00000010)
590		{ // Branch on Compare / Bit Test - Register-Immediate
591		// 00001 bbb sssssss 1 S BBB UUUUUU N 1 iiii
592		UINT8 subinstr = op & 0x0000000f;
593		INT32 address = (op & 0x00fe0000) >> 17;
594		address |= ((op & 0x00008000) >> 15) << 7;
595		if (address & 0x80) address = -(address & 0x7f);
596
597
598		print("%s (reg-imm) %08x (%08x)", table01_01_0x[subinstr], pc + (address * 2) + 4, op & ~0xf8fe800f);
599
600
601		}
602		else
603		{
604		// Branch on Compare / Bit Test - Register-Register
605		// 00001 bbb sssssss 1 S BBB CCCCCC N 0 iiii
606		UINT8 subinstr = op & 0x0000000f;
607		INT32 address = (op & 0x00fe0000) >> 17;
608		address |= ((op & 0x00008000) >> 15) << 7;
609		if (address & 0x80) address = -(address & 0x7f);
610
611		int c = (op & 0x00000fc0)>> 6;
612		int b = (op & 0x07000000) >> 24;
613		b |=   ((op & 0x00007000) >> 12) << 3;
614
615		op &= ~0x07007fe0;
616
617		if ((b != LIMM_REG) && (c != LIMM_REG))
618		{
619		print("%s (reg-reg) (r%d) (r%d) %08x (%08x)", table01_01_0x[subinstr], b, c, pc + (address * 2) + 4, op & ~0xf8fe800f);
620		}
621		else
622		{
623		UINT32 limm;
624		GET_LIMM_32;
625		size = 8;
626
627		if ((b == LIMM_REG) && (c != LIMM_REG))
628		{
629		print("%s (reg-reg) (%08x) (r%d) %08x (%08x)", table01_01_0x[subinstr], limm, c, pc + (address * 2) + 4, op & ~0xf8fe800f);
630		}
631		else if ((c == LIMM_REG) && (b != LIMM_REG))
632		{
633		print("%s (reg-reg) (r%d) (%08x) %08x (%08x)", table01_01_0x[subinstr], b, limm, pc + (address * 2) + 4, op & ~0xf8fe800f);
634		}
635		else
636		{
637		// b and c are LIMM? invalid??
638		print("%s (reg-reg) (%08x) (%08x) (illegal?) %08x (%08x)", table01_01_0x[subinstr], limm, limm, pc + (address * 2) + 4, op & ~0xf8fe800f);
639
640		}
641		}
642
643		}
644
645		}
646		else
647		{
648		if (op & 0x00020000)
649		{ // Branch and Link Unconditionally Far
650		// 00001 sssssssss 10  SSSSSSSSSS N R TTTT
651		INT32 address =   (op & 0x07fc0000) >> 17;
652		address |=        ((op & 0x0000ffc0) >> 6) << 10;
653		address |=        ((op & 0x0000000f) >> 0) << 20;
654		if (address & 0x800000) address = -(address&0x7fffff);
655
656		print("BL %08x (%08x)",  pc + (address *2) + 2, op & ~0xffffffcf );
657		}
658		else
659		{ // Branch and Link Conditionally
660		// 00001 sssssssss 00 SSSSSSSSSS N QQQQQ
661		INT32 address =   (op & 0x07fc0000) >> 17;
662		address |=        ((op & 0x0000ffc0) >> 6) << 10;
663		if (address & 0x800000) address = -(address&0x7fffff);
664
665		UINT8 condition = op & 0x0000001f;
666
667		print("BL(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 2, op & ~0xffffffdf );
668
669		}
670
671		}
672		return size;
673		}
674
675		int arcompact_handle02_dasm(DASM_OPS_32)
676		{
677		// bitpos
678		// 11111 111 11111111 0 000 0 00 00 0 000000
679		// fedcb a98 76543210 f edc b a9 87 6 543210
680		// fields
681		// 00010 bbb ssssssss S BBB D aa ZZ X AAAAAA
682		#if 0
683		int A = (op & 0x0000003f >> 0);  op &= ~0x0000003f;
684		int X = (op & 0x00000040 >> 6);  op &= ~0x00000040;
685		int Z = (op & 0x00000180 >> 7);  op &= ~0x00000180;
686		int a = (op & 0x00000600 >> 9);  op &= ~0x00000600;
687		int D = (op & 0x00000800 >> 11); op &= ~0x00000800;
688		int B = (op & 0x00007000 >> 12); op &= ~0x00007000;
689		int S = (op & 0x00008000 >> 15); op &= ~0x00008000;
690		int s = (op & 0x00ff0000 >> 16); op &= ~0x00ff0000;
691		int b = (op & 0x07000000 >> 24); op &= ~0x07000000;
692		#endif
693
694		print("LD r+o (%08x)", op );
695		return 4;
696		}
697
698		int arcompact_handle03_dasm(DASM_OPS_32)
699		{
700		// bitpos
701		// 11111 111 11111111 0 000 000000 0 00 00 0
702		// fedcb a98 76543210 f edc ba9876 5 43 21 0
703		// fields
704		// 00011 bbb ssssssss S BBB CCCCCC D aa ZZ R
705
706		print("ST r+o (%08x)", op );
707		return 4;
708		}
709
710		int arcompact_handle04_dasm(DASM_OPS_32)
711		{
712		int size = 4;
713		// General Operations
714
715		// bitpos
716		// 11111 111 11 111111 0 000 000000 0 00000
717		// fedcb a98 76 543210 f edc ba9876 5 43210
718		//
719		// 00100 bbb 00 iiiiii F BBB CCCCCC A AAAAA   General Operations *UN*Conditional Register to Register
720		// 00100 bbb 01 iiiiii F BBB UUUUUU A AAAAA   General Operations *UN*Conditional Register (Unsigned 6-bit IMM)
721		// 00100 bbb 10 iiiiii F BBB ssssss S SSSSS   General Operations *UN*Conditional Register (Signed 12-bit IMM)
722
723		// 00100 bbb 11 iiiiii F BBB CCCCCC 0 QQQQQ   General Operations Conditional Register
724		// 00100 bbb 11 iiiiii F BBB UUUUUU 1 QQQQQ   General Operations Conditional Register (Unsigned 6-bit IMM)
725		UINT8 subinstr = (op & 0x003f0000) >> 16;
726		op &= ~0x003f0000;
727
728		switch (subinstr)
729		{
730		case 0x00: size = arcompact_handle04_00_dasm(DASM_PARAMS); break; // ADD
731		case 0x01: size = arcompact_handle04_01_dasm(DASM_PARAMS); break; // ADC
732		case 0x02: size = arcompact_handle04_02_dasm(DASM_PARAMS); break; // SUB
733		case 0x03: size = arcompact_handle04_03_dasm(DASM_PARAMS); break; // SBC
734		case 0x04: size = arcompact_handle04_04_dasm(DASM_PARAMS); break; // AND
735		case 0x05: size = arcompact_handle04_05_dasm(DASM_PARAMS); break; // OR
736		case 0x06: size = arcompact_handle04_06_dasm(DASM_PARAMS); break; // BIC
737		case 0x07: size = arcompact_handle04_07_dasm(DASM_PARAMS); break; // XOR
738		case 0x08: size = arcompact_handle04_08_dasm(DASM_PARAMS); break; // MAX
739		case 0x09: size = arcompact_handle04_09_dasm(DASM_PARAMS); break; // MIN
740		case 0x0a: size = arcompact_handle04_0a_dasm(DASM_PARAMS); break; // MOV
741		case 0x0b: size = arcompact_handle04_0b_dasm(DASM_PARAMS); break; // TST
742		case 0x0c: size = arcompact_handle04_0c_dasm(DASM_PARAMS); break; // CMP
743		case 0x0d: size = arcompact_handle04_0d_dasm(DASM_PARAMS); break; // RCMP
744		case 0x0e: size = arcompact_handle04_0e_dasm(DASM_PARAMS); break; // RSUB
745		case 0x0f: size = arcompact_handle04_0f_dasm(DASM_PARAMS); break; // BSET
746		case 0x10: size = arcompact_handle04_10_dasm(DASM_PARAMS); break; // BCLR
747		case 0x11: size = arcompact_handle04_11_dasm(DASM_PARAMS); break; // BTST
748		case 0x12: size = arcompact_handle04_12_dasm(DASM_PARAMS); break; // BXOR
749		case 0x13: size = arcompact_handle04_13_dasm(DASM_PARAMS); break; // BMSK
750		case 0x14: size = arcompact_handle04_14_dasm(DASM_PARAMS); break; // ADD1
751		case 0x15: size = arcompact_handle04_15_dasm(DASM_PARAMS); break; // ADD2
752		case 0x16: size = arcompact_handle04_16_dasm(DASM_PARAMS); break; // ADD3
753		case 0x17: size = arcompact_handle04_17_dasm(DASM_PARAMS); break; // SUB1
754		case 0x18: size = arcompact_handle04_18_dasm(DASM_PARAMS); break; // SUB2
755		case 0x19: size = arcompact_handle04_19_dasm(DASM_PARAMS); break; // SUB3
756		case 0x1a: size = arcompact_handle04_1a_dasm(DASM_PARAMS); break; // MPY *
757		case 0x1b: size = arcompact_handle04_1b_dasm(DASM_PARAMS); break; // MPYH *
758		case 0x1c: size = arcompact_handle04_1c_dasm(DASM_PARAMS); break; // MPYHU *
759		case 0x1d: size = arcompact_handle04_1d_dasm(DASM_PARAMS); break; // MPYU *
760		case 0x1e: size = arcompact_handle04_1e_dasm(DASM_PARAMS); break; // illegal
761		case 0x1f: size = arcompact_handle04_1f_dasm(DASM_PARAMS); break; // illegal
762		case 0x20: size = arcompact_handle04_20_dasm(DASM_PARAMS); break; // Jcc
763		case 0x21: size = arcompact_handle04_21_dasm(DASM_PARAMS); break; // Jcc.D
764		case 0x22: size = arcompact_handle04_22_dasm(DASM_PARAMS); break; // JLcc
765		case 0x23: size = arcompact_handle04_23_dasm(DASM_PARAMS); break; // JLcc.D
766		case 0x24: size = arcompact_handle04_24_dasm(DASM_PARAMS); break; // illegal
767		case 0x25: size = arcompact_handle04_25_dasm(DASM_PARAMS); break; // illegal
768		case 0x26: size = arcompact_handle04_26_dasm(DASM_PARAMS); break; // illegal
769		case 0x27: size = arcompact_handle04_27_dasm(DASM_PARAMS); break; // illegal
770		case 0x28: size = arcompact_handle04_28_dasm(DASM_PARAMS); break; // LPcc
771		case 0x29: size = arcompact_handle04_29_dasm(DASM_PARAMS); break; // FLAG
772		case 0x2a: size = arcompact_handle04_2a_dasm(DASM_PARAMS); break; // LR
773		case 0x2b: size = arcompact_handle04_2b_dasm(DASM_PARAMS); break; // SR
774		case 0x2c: size = arcompact_handle04_2c_dasm(DASM_PARAMS); break; // illegal
775		case 0x2d: size = arcompact_handle04_2d_dasm(DASM_PARAMS); break; // illegal
776		case 0x2e: size = arcompact_handle04_2e_dasm(DASM_PARAMS); break; // illegal
777		case 0x2f: size = arcompact_handle04_2f_dasm(DASM_PARAMS); break; // Sub Opcode
778		case 0x30: size = arcompact_handle04_30_dasm(DASM_PARAMS); break; // LD r-r
779		case 0x31: size = arcompact_handle04_31_dasm(DASM_PARAMS); break; // LD r-r
780		case 0x32: size = arcompact_handle04_32_dasm(DASM_PARAMS); break; // LD r-r
781		case 0x33: size = arcompact_handle04_33_dasm(DASM_PARAMS); break; // LD r-r
782		case 0x34: size = arcompact_handle04_34_dasm(DASM_PARAMS); break; // LD r-r
783		case 0x35: size = arcompact_handle04_35_dasm(DASM_PARAMS); break; // LD r-r
784		case 0x36: size = arcompact_handle04_36_dasm(DASM_PARAMS); break; // LD r-r
785		case 0x37: size = arcompact_handle04_37_dasm(DASM_PARAMS); break; // LD r-r
786		case 0x38: size = arcompact_handle04_38_dasm(DASM_PARAMS); break; // illegal
787		case 0x39: size = arcompact_handle04_39_dasm(DASM_PARAMS); break; // illegal
788		case 0x3a: size = arcompact_handle04_3a_dasm(DASM_PARAMS); break; // illegal
789		case 0x3b: size = arcompact_handle04_3b_dasm(DASM_PARAMS); break; // illegal
790		case 0x3c: size = arcompact_handle04_3c_dasm(DASM_PARAMS); break; // illegal
791		case 0x3d: size = arcompact_handle04_3d_dasm(DASM_PARAMS); break; // illegal
792		case 0x3e: size = arcompact_handle04_3e_dasm(DASM_PARAMS); break; // illegal
793		case 0x3f: size = arcompact_handle04_3f_dasm(DASM_PARAMS); break; // illegal
794		}
795
796		return size;
797		}
798
799		int arcompact_handle04_00_dasm(DASM_OPS_32)  { print("ADD (%08x)", op); return 4;}
800		int arcompact_handle04_01_dasm(DASM_OPS_32)  { print("ADC (%08x)", op); return 4;}
801		int arcompact_handle04_02_dasm(DASM_OPS_32)  { print("SUB (%08x)", op); return 4;}
802		int arcompact_handle04_03_dasm(DASM_OPS_32)  { print("SBC (%08x)", op); return 4;}
803		int arcompact_handle04_04_dasm(DASM_OPS_32)  { print("AND (%08x)", op); return 4;}
804		int arcompact_handle04_05_dasm(DASM_OPS_32)  { print("OR (%08x)", op); return 4;}
805		int arcompact_handle04_06_dasm(DASM_OPS_32)  { print("BIC (%08x)", op); return 4;}
806		int arcompact_handle04_07_dasm(DASM_OPS_32)  { print("XOR (%08x)", op); return 4;}
807		int arcompact_handle04_08_dasm(DASM_OPS_32)  { print("MAX (%08x)", op); return 4;}
808		int arcompact_handle04_09_dasm(DASM_OPS_32)  { print("MIN (%08x)", op); return 4;}
809		int arcompact_handle04_0a_dasm(DASM_OPS_32)  { print("MOV (%08x)", op); return 4;}
810		int arcompact_handle04_0b_dasm(DASM_OPS_32)  { print("TST (%08x)", op); return 4;}
811		int arcompact_handle04_0c_dasm(DASM_OPS_32)  { print("CMP (%08x)", op); return 4;}
812		int arcompact_handle04_0d_dasm(DASM_OPS_32)  { print("RCMP (%08x)", op); return 4;}
813		int arcompact_handle04_0e_dasm(DASM_OPS_32)  { print("RSUB (%08x)", op); return 4;}
814		int arcompact_handle04_0f_dasm(DASM_OPS_32)  { print("BSET (%08x)", op); return 4;}
815		int arcompact_handle04_10_dasm(DASM_OPS_32)  { print("BCLR (%08x)", op); return 4;}
816		int arcompact_handle04_11_dasm(DASM_OPS_32)  { print("BTST (%08x)", op); return 4;}
817		int arcompact_handle04_12_dasm(DASM_OPS_32)  { print("BXOR (%08x)", op); return 4;}
818		int arcompact_handle04_13_dasm(DASM_OPS_32)  { print("BMSK (%08x)", op); return 4;}
819		int arcompact_handle04_14_dasm(DASM_OPS_32)  { print("ADD1 (%08x)", op); return 4;}
820		int arcompact_handle04_15_dasm(DASM_OPS_32)  { print("ADD2 (%08x)", op); return 4;}
821		int arcompact_handle04_16_dasm(DASM_OPS_32)  { print("ADD3 (%08x)", op); return 4;}
822		int arcompact_handle04_17_dasm(DASM_OPS_32)  { print("SUB1 (%08x)", op); return 4;}
823		int arcompact_handle04_18_dasm(DASM_OPS_32)  { print("SUB2 (%08x)", op); return 4;}
824		int arcompact_handle04_19_dasm(DASM_OPS_32)  { print("SUB3 (%08x)", op); return 4;}
825		int arcompact_handle04_1a_dasm(DASM_OPS_32)  { print("MPY (%08x)", op); return 4;} // *
826		int arcompact_handle04_1b_dasm(DASM_OPS_32)  { print("MPYH (%08x)", op); return 4;} // *
827		int arcompact_handle04_1c_dasm(DASM_OPS_32)  { print("MPYHU (%08x)", op); return 4;} // *
828		int arcompact_handle04_1d_dasm(DASM_OPS_32)  { print("MPYU (%08x)", op); return 4;} // *
829		int arcompact_handle04_1e_dasm(DASM_OPS_32)  { print("<illegal 0x04_1e> (%08x)", op); return 4;}
830		int arcompact_handle04_1f_dasm(DASM_OPS_32)  { print("<illegal 0x04_1f> (%08x)", op); return 4;}
831
832
833
834		int arcompact_handle04_20_dasm(DASM_OPS_32)
835		{
836		// todo, other bits (in none long immediate mode at least)
837
838		int size = 4;
839		int C = (op & 0x00000fc0) >> 6;
840		UINT8 condition = op & 0x0000001f;
841
842		op &= ~0x00000fc0;
843
844		if (C == LIMM_REG)
845		{
846		UINT32 limm;
847		GET_LIMM_32;
848		size = 8;
849
850		print("J(%s) %08x (%08x)", conditions[condition], limm, op);
851		}
852		else
853		{
854		print("J(%s) (r%d) (%08x)", conditions[condition], C, op);
855		}
856
857		return size;
858		}
859
860
861
862		int arcompact_handle04_21_dasm(DASM_OPS_32)  { print("Jcc.D (%08x)", op); return 4;}
863		int arcompact_handle04_22_dasm(DASM_OPS_32)  { print("JLcc (%08x)", op); return 4;}
864		int arcompact_handle04_23_dasm(DASM_OPS_32)  { print("JLcc.D (%08x)", op); return 4;}
865		int arcompact_handle04_24_dasm(DASM_OPS_32)  { print("<illegal 0x04_24> (%08x)", op); return 4;}
866		int arcompact_handle04_25_dasm(DASM_OPS_32)  { print("<illegal 0x04_25> (%08x)", op); return 4;}
867		int arcompact_handle04_26_dasm(DASM_OPS_32)  { print("<illegal 0x04_26> (%08x)", op); return 4;}
868		int arcompact_handle04_27_dasm(DASM_OPS_32)  { print("<illegal 0x04_27> (%08x)", op); return 4;}
869		int arcompact_handle04_28_dasm(DASM_OPS_32)  { print("LPcc (%08x)", op); return 4;}
870		int arcompact_handle04_29_dasm(DASM_OPS_32)  { print("FLAG (%08x)", op); return 4;}
871		int arcompact_handle04_2a_dasm(DASM_OPS_32)  { print("LR (%08x)", op); return 4;}
872		int arcompact_handle04_2b_dasm(DASM_OPS_32)  { print("SR (%08x)", op); return 4;}
873		int arcompact_handle04_2c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2c> (%08x)", op); return 4;}
874		int arcompact_handle04_2d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2d> (%08x)", op); return 4;}
875		int arcompact_handle04_2e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2e> (%08x)", op); return 4;}
876
877		int arcompact_handle04_2f_dasm(DASM_OPS_32)
878		{
879		int size = 4;
880		UINT8 subinstr2 = (op & 0x0000003f) >> 0;
881		op &= ~0x0000003f;
882
883		switch (subinstr2)
884		{
885		case 0x00: size = arcompact_handle04_2f_00_dasm(DASM_PARAMS); break; // ASL
886		case 0x01: size = arcompact_handle04_2f_01_dasm(DASM_PARAMS); break; // ASR
887		case 0x02: size = arcompact_handle04_2f_02_dasm(DASM_PARAMS); break; // LSR
888		case 0x03: size = arcompact_handle04_2f_03_dasm(DASM_PARAMS); break; // ROR
889		case 0x04: size = arcompact_handle04_2f_04_dasm(DASM_PARAMS); break; // RCC
890		case 0x05: size = arcompact_handle04_2f_05_dasm(DASM_PARAMS); break; // SEXB
891		case 0x06: size = arcompact_handle04_2f_06_dasm(DASM_PARAMS); break; // SEXW
892		case 0x07: size = arcompact_handle04_2f_07_dasm(DASM_PARAMS); break; // EXTB
893		case 0x08: size = arcompact_handle04_2f_08_dasm(DASM_PARAMS); break; // EXTW
894		case 0x09: size = arcompact_handle04_2f_09_dasm(DASM_PARAMS); break; // ABS
895		case 0x0a: size = arcompact_handle04_2f_0a_dasm(DASM_PARAMS); break; // NOT
896		case 0x0b: size = arcompact_handle04_2f_0b_dasm(DASM_PARAMS); break; // RLC
897		case 0x0c: size = arcompact_handle04_2f_0c_dasm(DASM_PARAMS); break; // EX
898		case 0x0d: size = arcompact_handle04_2f_0d_dasm(DASM_PARAMS); break; // illegal
899		case 0x0e: size = arcompact_handle04_2f_0e_dasm(DASM_PARAMS); break; // illegal
900		case 0x0f: size = arcompact_handle04_2f_0f_dasm(DASM_PARAMS); break; // illegal
901		case 0x10: size = arcompact_handle04_2f_10_dasm(DASM_PARAMS); break; // illegal
902		case 0x11: size = arcompact_handle04_2f_11_dasm(DASM_PARAMS); break; // illegal
903		case 0x12: size = arcompact_handle04_2f_12_dasm(DASM_PARAMS); break; // illegal
904		case 0x13: size = arcompact_handle04_2f_13_dasm(DASM_PARAMS); break; // illegal
905		case 0x14: size = arcompact_handle04_2f_14_dasm(DASM_PARAMS); break; // illegal
906		case 0x15: size = arcompact_handle04_2f_15_dasm(DASM_PARAMS); break; // illegal
907		case 0x16: size = arcompact_handle04_2f_16_dasm(DASM_PARAMS); break; // illegal
908		case 0x17: size = arcompact_handle04_2f_17_dasm(DASM_PARAMS); break; // illegal
909		case 0x18: size = arcompact_handle04_2f_18_dasm(DASM_PARAMS); break; // illegal
910		case 0x19: size = arcompact_handle04_2f_19_dasm(DASM_PARAMS); break; // illegal
911		case 0x1a: size = arcompact_handle04_2f_1a_dasm(DASM_PARAMS); break; // illegal
912		case 0x1b: size = arcompact_handle04_2f_1b_dasm(DASM_PARAMS); break; // illegal
913		case 0x1c: size = arcompact_handle04_2f_1c_dasm(DASM_PARAMS); break; // illegal
914		case 0x1d: size = arcompact_handle04_2f_1d_dasm(DASM_PARAMS); break; // illegal
915		case 0x1e: size = arcompact_handle04_2f_1e_dasm(DASM_PARAMS); break; // illegal
916		case 0x1f: size = arcompact_handle04_2f_1f_dasm(DASM_PARAMS); break; // illegal
917		case 0x20: size = arcompact_handle04_2f_20_dasm(DASM_PARAMS); break; // illegal
918		case 0x21: size = arcompact_handle04_2f_21_dasm(DASM_PARAMS); break; // illegal
919		case 0x22: size = arcompact_handle04_2f_22_dasm(DASM_PARAMS); break; // illegal
920		case 0x23: size = arcompact_handle04_2f_23_dasm(DASM_PARAMS); break; // illegal
921		case 0x24: size = arcompact_handle04_2f_24_dasm(DASM_PARAMS); break; // illegal
922		case 0x25: size = arcompact_handle04_2f_25_dasm(DASM_PARAMS); break; // illegal
923		case 0x26: size = arcompact_handle04_2f_26_dasm(DASM_PARAMS); break; // illegal
924		case 0x27: size = arcompact_handle04_2f_27_dasm(DASM_PARAMS); break; // illegal
925		case 0x28: size = arcompact_handle04_2f_28_dasm(DASM_PARAMS); break; // illegal
926		case 0x29: size = arcompact_handle04_2f_29_dasm(DASM_PARAMS); break; // illegal
927		case 0x2a: size = arcompact_handle04_2f_2a_dasm(DASM_PARAMS); break; // illegal
928		case 0x2b: size = arcompact_handle04_2f_2b_dasm(DASM_PARAMS); break; // illegal
929		case 0x2c: size = arcompact_handle04_2f_2c_dasm(DASM_PARAMS); break; // illegal
930		case 0x2d: size = arcompact_handle04_2f_2d_dasm(DASM_PARAMS); break; // illegal
931		case 0x2e: size = arcompact_handle04_2f_2e_dasm(DASM_PARAMS); break; // illegal
932		case 0x2f: size = arcompact_handle04_2f_2f_dasm(DASM_PARAMS); break; // illegal
933		case 0x30: size = arcompact_handle04_2f_30_dasm(DASM_PARAMS); break; // illegal
934		case 0x31: size = arcompact_handle04_2f_31_dasm(DASM_PARAMS); break; // illegal
935		case 0x32: size = arcompact_handle04_2f_32_dasm(DASM_PARAMS); break; // illegal
936		case 0x33: size = arcompact_handle04_2f_33_dasm(DASM_PARAMS); break; // illegal
937		case 0x34: size = arcompact_handle04_2f_34_dasm(DASM_PARAMS); break; // illegal
938		case 0x35: size = arcompact_handle04_2f_35_dasm(DASM_PARAMS); break; // illegal
939		case 0x36: size = arcompact_handle04_2f_36_dasm(DASM_PARAMS); break; // illegal
940		case 0x37: size = arcompact_handle04_2f_37_dasm(DASM_PARAMS); break; // illegal
941		case 0x38: size = arcompact_handle04_2f_38_dasm(DASM_PARAMS); break; // illegal
942		case 0x39: size = arcompact_handle04_2f_39_dasm(DASM_PARAMS); break; // illegal
943		case 0x3a: size = arcompact_handle04_2f_3a_dasm(DASM_PARAMS); break; // illegal
944		case 0x3b: size = arcompact_handle04_2f_3b_dasm(DASM_PARAMS); break; // illegal
945		case 0x3c: size = arcompact_handle04_2f_3c_dasm(DASM_PARAMS); break; // illegal
946		case 0x3d: size = arcompact_handle04_2f_3d_dasm(DASM_PARAMS); break; // illegal
947		case 0x3e: size = arcompact_handle04_2f_3e_dasm(DASM_PARAMS); break; // illegal
948		case 0x3f: size = arcompact_handle04_2f_3f_dasm(DASM_PARAMS); break; // ZOPs (Zero Operand Opcodes)
949		}
950
951		return size;
952		}
953
954
955		int arcompact_handle04_2f_00_dasm(DASM_OPS_32)  { print("ASL (%08x)", op); return 4;} // ASL
956		int arcompact_handle04_2f_01_dasm(DASM_OPS_32)  { print("ASR (%08x)", op); return 4;} // ASR
957		int arcompact_handle04_2f_02_dasm(DASM_OPS_32)  { print("LSR (%08x)", op); return 4;} // LSR
958		int arcompact_handle04_2f_03_dasm(DASM_OPS_32)  { print("ROR (%08x)", op); return 4;} // ROR
959		int arcompact_handle04_2f_04_dasm(DASM_OPS_32)  { print("RCC (%08x)", op); return 4;} // RCC
960		int arcompact_handle04_2f_05_dasm(DASM_OPS_32)  { print("SEXB (%08x)", op); return 4;} // SEXB
961		int arcompact_handle04_2f_06_dasm(DASM_OPS_32)  { print("SEXW (%08x)", op); return 4;} // SEXW
962		int arcompact_handle04_2f_07_dasm(DASM_OPS_32)  { print("EXTB (%08x)", op); return 4;} // EXTB
963		int arcompact_handle04_2f_08_dasm(DASM_OPS_32)  { print("EXTW (%08x)", op); return 4;} // EXTW
964		int arcompact_handle04_2f_09_dasm(DASM_OPS_32)  { print("ABS (%08x)", op); return 4;} // ABS
965		int arcompact_handle04_2f_0a_dasm(DASM_OPS_32)  { print("NOT (%08x)", op); return 4;} // NOT
966		int arcompact_handle04_2f_0b_dasm(DASM_OPS_32)  { print("RLC (%08x)", op); return 4;} // RLC
967		int arcompact_handle04_2f_0c_dasm(DASM_OPS_32)  { print("EX (%08x)", op); return 4;} // EX
968		int arcompact_handle04_2f_0d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_0d> (%08x)", op); return 4;}
969		int arcompact_handle04_2f_0e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_0e> (%08x)", op); return 4;}
970		int arcompact_handle04_2f_0f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_0f> (%08x)", op); return 4;}
971		int arcompact_handle04_2f_10_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_10> (%08x)", op); return 4;}
972		int arcompact_handle04_2f_11_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_11> (%08x)", op); return 4;}
973		int arcompact_handle04_2f_12_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_12> (%08x)", op); return 4;}
974		int arcompact_handle04_2f_13_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_13> (%08x)", op); return 4;}
975		int arcompact_handle04_2f_14_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_14> (%08x)", op); return 4;}
976		int arcompact_handle04_2f_15_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_15> (%08x)", op); return 4;}
977		int arcompact_handle04_2f_16_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_16> (%08x)", op); return 4;}
978		int arcompact_handle04_2f_17_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_17> (%08x)", op); return 4;}
979		int arcompact_handle04_2f_18_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_18> (%08x)", op); return 4;}
980		int arcompact_handle04_2f_19_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_19> (%08x)", op); return 4;}
981		int arcompact_handle04_2f_1a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1a> (%08x)", op); return 4;}
982		int arcompact_handle04_2f_1b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1b> (%08x)", op); return 4;}
983		int arcompact_handle04_2f_1c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1c> (%08x)", op); return 4;}
984		int arcompact_handle04_2f_1d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1d> (%08x)", op); return 4;}
985		int arcompact_handle04_2f_1e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1e> (%08x)", op); return 4;}
986		int arcompact_handle04_2f_1f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1f> (%08x)", op); return 4;}
987		int arcompact_handle04_2f_20_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_20> (%08x)", op); return 4;}
988		int arcompact_handle04_2f_21_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_21> (%08x)", op); return 4;}
989		int arcompact_handle04_2f_22_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_22> (%08x)", op); return 4;}
990		int arcompact_handle04_2f_23_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_23> (%08x)", op); return 4;}
991		int arcompact_handle04_2f_24_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_24> (%08x)", op); return 4;}
992		int arcompact_handle04_2f_25_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_25> (%08x)", op); return 4;}
993		int arcompact_handle04_2f_26_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_26> (%08x)", op); return 4;}
994		int arcompact_handle04_2f_27_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_27> (%08x)", op); return 4;}
995		int arcompact_handle04_2f_28_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_28> (%08x)", op); return 4;}
996		int arcompact_handle04_2f_29_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_29> (%08x)", op); return 4;}
997		int arcompact_handle04_2f_2a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2a> (%08x)", op); return 4;}
998		int arcompact_handle04_2f_2b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2b> (%08x)", op); return 4;}
999		int arcompact_handle04_2f_2c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2c> (%08x)", op); return 4;}
1000		int arcompact_handle04_2f_2d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2d> (%08x)", op); return 4;}
1001		int arcompact_handle04_2f_2e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2e> (%08x)", op); return 4;}
1002		int arcompact_handle04_2f_2f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2f> (%08x)", op); return 4;}
1003		int arcompact_handle04_2f_30_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_30> (%08x)", op); return 4;}
1004		int arcompact_handle04_2f_31_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_31> (%08x)", op); return 4;}
1005		int arcompact_handle04_2f_32_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_32> (%08x)", op); return 4;}
1006		int arcompact_handle04_2f_33_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_33> (%08x)", op); return 4;}
1007		int arcompact_handle04_2f_34_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_34> (%08x)", op); return 4;}
1008		int arcompact_handle04_2f_35_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_35> (%08x)", op); return 4;}
1009		int arcompact_handle04_2f_36_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_36> (%08x)", op); return 4;}
1010		int arcompact_handle04_2f_37_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_37> (%08x)", op); return 4;}
1011		int arcompact_handle04_2f_38_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_38> (%08x)", op); return 4;}
1012		int arcompact_handle04_2f_39_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_39> (%08x)", op); return 4;}
1013		int arcompact_handle04_2f_3a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3a> (%08x)", op); return 4;}
1014		int arcompact_handle04_2f_3b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3b> (%08x)", op); return 4;}
1015		int arcompact_handle04_2f_3c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3c> (%08x)", op); return 4;}
1016		int arcompact_handle04_2f_3d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3d> (%08x)", op); return 4;}
1017		int arcompact_handle04_2f_3e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3e> (%08x)", op); return 4;}
1018
1019		int arcompact_handle04_2f_3f_dasm(DASM_OPS_32)
1020		{
1021		int size = 4;
1022		UINT8 subinstr3 = (op & 0x07000000) >> 24;
1023		subinstr3 |= ((op & 0x00007000) >> 12) << 3;
1024
1025		op &= ~0x07007000;
1026
1027		switch (subinstr3)
1028		{
1029		case 0x00: size = arcompact_handle04_2f_3f_00_dasm(DASM_PARAMS); break; // illegal
1030		case 0x01: size = arcompact_handle04_2f_3f_01_dasm(DASM_PARAMS); break; // SLEEP
1031		case 0x02: size = arcompact_handle04_2f_3f_02_dasm(DASM_PARAMS); break; // SWI / TRAP9
1032		case 0x03: size = arcompact_handle04_2f_3f_03_dasm(DASM_PARAMS); break; // SYNC
1033		case 0x04: size = arcompact_handle04_2f_3f_04_dasm(DASM_PARAMS); break; // RTIE
1034		case 0x05: size = arcompact_handle04_2f_3f_05_dasm(DASM_PARAMS); break; // BRK
1035		case 0x06: size = arcompact_handle04_2f_3f_06_dasm(DASM_PARAMS); break; // illegal
1036		case 0x07: size = arcompact_handle04_2f_3f_07_dasm(DASM_PARAMS); break; // illegal
1037		case 0x08: size = arcompact_handle04_2f_3f_08_dasm(DASM_PARAMS); break; // illegal
1038		case 0x09: size = arcompact_handle04_2f_3f_09_dasm(DASM_PARAMS); break; // illegal
1039		case 0x0a: size = arcompact_handle04_2f_3f_0a_dasm(DASM_PARAMS); break; // illegal
1040		case 0x0b: size = arcompact_handle04_2f_3f_0b_dasm(DASM_PARAMS); break; // illegal
1041		case 0x0c: size = arcompact_handle04_2f_3f_0c_dasm(DASM_PARAMS); break; // illegal
1042		case 0x0d: size = arcompact_handle04_2f_3f_0d_dasm(DASM_PARAMS); break; // illegal
1043		case 0x0e: size = arcompact_handle04_2f_3f_0e_dasm(DASM_PARAMS); break; // illegal
1044		case 0x0f: size = arcompact_handle04_2f_3f_0f_dasm(DASM_PARAMS); break; // illegal
1045		case 0x10: size = arcompact_handle04_2f_3f_10_dasm(DASM_PARAMS); break; // illegal
1046		case 0x11: size = arcompact_handle04_2f_3f_11_dasm(DASM_PARAMS); break; // illegal
1047		case 0x12: size = arcompact_handle04_2f_3f_12_dasm(DASM_PARAMS); break; // illegal
1048		case 0x13: size = arcompact_handle04_2f_3f_13_dasm(DASM_PARAMS); break; // illegal
1049		case 0x14: size = arcompact_handle04_2f_3f_14_dasm(DASM_PARAMS); break; // illegal
1050		case 0x15: size = arcompact_handle04_2f_3f_15_dasm(DASM_PARAMS); break; // illegal
1051		case 0x16: size = arcompact_handle04_2f_3f_16_dasm(DASM_PARAMS); break; // illegal
1052		case 0x17: size = arcompact_handle04_2f_3f_17_dasm(DASM_PARAMS); break; // illegal
1053		case 0x18: size = arcompact_handle04_2f_3f_18_dasm(DASM_PARAMS); break; // illegal
1054		case 0x19: size = arcompact_handle04_2f_3f_19_dasm(DASM_PARAMS); break; // illegal
1055		case 0x1a: size = arcompact_handle04_2f_3f_1a_dasm(DASM_PARAMS); break; // illegal
1056		case 0x1b: size = arcompact_handle04_2f_3f_1b_dasm(DASM_PARAMS); break; // illegal
1057		case 0x1c: size = arcompact_handle04_2f_3f_1c_dasm(DASM_PARAMS); break; // illegal
1058		case 0x1d: size = arcompact_handle04_2f_3f_1d_dasm(DASM_PARAMS); break; // illegal
1059		case 0x1e: size = arcompact_handle04_2f_3f_1e_dasm(DASM_PARAMS); break; // illegal
1060		case 0x1f: size = arcompact_handle04_2f_3f_1f_dasm(DASM_PARAMS); break; // illegal
1061		case 0x20: size = arcompact_handle04_2f_3f_20_dasm(DASM_PARAMS); break; // illegal
1062		case 0x21: size = arcompact_handle04_2f_3f_21_dasm(DASM_PARAMS); break; // illegal
1063		case 0x22: size = arcompact_handle04_2f_3f_22_dasm(DASM_PARAMS); break; // illegal
1064		case 0x23: size = arcompact_handle04_2f_3f_23_dasm(DASM_PARAMS); break; // illegal
1065		case 0x24: size = arcompact_handle04_2f_3f_24_dasm(DASM_PARAMS); break; // illegal
1066		case 0x25: size = arcompact_handle04_2f_3f_25_dasm(DASM_PARAMS); break; // illegal
1067		case 0x26: size = arcompact_handle04_2f_3f_26_dasm(DASM_PARAMS); break; // illegal
1068		case 0x27: size = arcompact_handle04_2f_3f_27_dasm(DASM_PARAMS); break; // illegal
1069		case 0x28: size = arcompact_handle04_2f_3f_28_dasm(DASM_PARAMS); break; // illegal
1070		case 0x29: size = arcompact_handle04_2f_3f_29_dasm(DASM_PARAMS); break; // illegal
1071		case 0x2a: size = arcompact_handle04_2f_3f_2a_dasm(DASM_PARAMS); break; // illegal
1072		case 0x2b: size = arcompact_handle04_2f_3f_2b_dasm(DASM_PARAMS); break; // illegal
1073		case 0x2c: size = arcompact_handle04_2f_3f_2c_dasm(DASM_PARAMS); break; // illegal
1074		case 0x2d: size = arcompact_handle04_2f_3f_2d_dasm(DASM_PARAMS); break; // illegal
1075		case 0x2e: size = arcompact_handle04_2f_3f_2e_dasm(DASM_PARAMS); break; // illegal
1076		case 0x2f: size = arcompact_handle04_2f_3f_2f_dasm(DASM_PARAMS); break; // illegal
1077		case 0x30: size = arcompact_handle04_2f_3f_30_dasm(DASM_PARAMS); break; // illegal
1078		case 0x31: size = arcompact_handle04_2f_3f_31_dasm(DASM_PARAMS); break; // illegal
1079		case 0x32: size = arcompact_handle04_2f_3f_32_dasm(DASM_PARAMS); break; // illegal
1080		case 0x33: size = arcompact_handle04_2f_3f_33_dasm(DASM_PARAMS); break; // illegal
1081		case 0x34: size = arcompact_handle04_2f_3f_34_dasm(DASM_PARAMS); break; // illegal
1082		case 0x35: size = arcompact_handle04_2f_3f_35_dasm(DASM_PARAMS); break; // illegal
1083		case 0x36: size = arcompact_handle04_2f_3f_36_dasm(DASM_PARAMS); break; // illegal
1084		case 0x37: size = arcompact_handle04_2f_3f_37_dasm(DASM_PARAMS); break; // illegal
1085		case 0x38: size = arcompact_handle04_2f_3f_38_dasm(DASM_PARAMS); break; // illegal
1086		case 0x39: size = arcompact_handle04_2f_3f_39_dasm(DASM_PARAMS); break; // illegal
1087		case 0x3a: size = arcompact_handle04_2f_3f_3a_dasm(DASM_PARAMS); break; // illegal
1088		case 0x3b: size = arcompact_handle04_2f_3f_3b_dasm(DASM_PARAMS); break; // illegal
1089		case 0x3c: size = arcompact_handle04_2f_3f_3c_dasm(DASM_PARAMS); break; // illegal
1090		case 0x3d: size = arcompact_handle04_2f_3f_3d_dasm(DASM_PARAMS); break; // illegal
1091		case 0x3e: size = arcompact_handle04_2f_3f_3e_dasm(DASM_PARAMS); break; // illegal
1092		case 0x3f: size = arcompact_handle04_2f_3f_3f_dasm(DASM_PARAMS); break; // illegal
1093		}
1094
1095		return size;
1096		}
1097
1098		int arcompact_handle04_2f_3f_00_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_00> (%08x)", op); return 4;}
1099		int arcompact_handle04_2f_3f_01_dasm(DASM_OPS_32)  { print("SLEEP (%08x)", op); return 4;}
1100		int arcompact_handle04_2f_3f_02_dasm(DASM_OPS_32)  { print("SWI / TRAP0 (%08x)", op); return 4;}
1101		int arcompact_handle04_2f_3f_03_dasm(DASM_OPS_32)  { print("SYNC (%08x)", op); return 4;}
1102		int arcompact_handle04_2f_3f_04_dasm(DASM_OPS_32)  { print("RTIE (%08x)", op); return 4;}
1103		int arcompact_handle04_2f_3f_05_dasm(DASM_OPS_32)  { print("BRK (%08x)", op); return 4;}
1104		int arcompact_handle04_2f_3f_06_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_06> (%08x)", op); return 4;}
1105		int arcompact_handle04_2f_3f_07_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_07> (%08x)", op); return 4;}
1106		int arcompact_handle04_2f_3f_08_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_08> (%08x)", op); return 4;}
1107		int arcompact_handle04_2f_3f_09_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_09> (%08x)", op); return 4;}
1108		int arcompact_handle04_2f_3f_0a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0a> (%08x)", op); return 4;}
1109		int arcompact_handle04_2f_3f_0b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0b> (%08x)", op); return 4;}
1110		int arcompact_handle04_2f_3f_0c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0c> (%08x)", op); return 4;}
1111		int arcompact_handle04_2f_3f_0d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0d> (%08x)", op); return 4;}
1112		int arcompact_handle04_2f_3f_0e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0e> (%08x)", op); return 4;}
1113		int arcompact_handle04_2f_3f_0f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0f> (%08x)", op); return 4;}
1114		int arcompact_handle04_2f_3f_10_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_10> (%08x)", op); return 4;}
1115		int arcompact_handle04_2f_3f_11_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_11> (%08x)", op); return 4;}
1116		int arcompact_handle04_2f_3f_12_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_12> (%08x)", op); return 4;}
1117		int arcompact_handle04_2f_3f_13_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_13> (%08x)", op); return 4;}
1118		int arcompact_handle04_2f_3f_14_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_14> (%08x)", op); return 4;}
1119		int arcompact_handle04_2f_3f_15_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_15> (%08x)", op); return 4;}
1120		int arcompact_handle04_2f_3f_16_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_16> (%08x)", op); return 4;}
1121		int arcompact_handle04_2f_3f_17_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_17> (%08x)", op); return 4;}
1122		int arcompact_handle04_2f_3f_18_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_18> (%08x)", op); return 4;}
1123		int arcompact_handle04_2f_3f_19_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_19> (%08x)", op); return 4;}
1124		int arcompact_handle04_2f_3f_1a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1a> (%08x)", op); return 4;}
1125		int arcompact_handle04_2f_3f_1b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1b> (%08x)", op); return 4;}
1126		int arcompact_handle04_2f_3f_1c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1c> (%08x)", op); return 4;}
1127		int arcompact_handle04_2f_3f_1d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1d> (%08x)", op); return 4;}
1128		int arcompact_handle04_2f_3f_1e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1e> (%08x)", op); return 4;}
1129		int arcompact_handle04_2f_3f_1f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1f> (%08x)", op); return 4;}
1130		int arcompact_handle04_2f_3f_20_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_20> (%08x)", op); return 4;}
1131		int arcompact_handle04_2f_3f_21_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_21> (%08x)", op); return 4;}
1132		int arcompact_handle04_2f_3f_22_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_22> (%08x)", op); return 4;}
1133		int arcompact_handle04_2f_3f_23_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_23> (%08x)", op); return 4;}
1134		int arcompact_handle04_2f_3f_24_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_24> (%08x)", op); return 4;}
1135		int arcompact_handle04_2f_3f_25_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_25> (%08x)", op); return 4;}
1136		int arcompact_handle04_2f_3f_26_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_26> (%08x)", op); return 4;}
1137		int arcompact_handle04_2f_3f_27_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_27> (%08x)", op); return 4;}
1138		int arcompact_handle04_2f_3f_28_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_28> (%08x)", op); return 4;}
1139		int arcompact_handle04_2f_3f_29_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_29> (%08x)", op); return 4;}
1140		int arcompact_handle04_2f_3f_2a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2a> (%08x)", op); return 4;}
1141		int arcompact_handle04_2f_3f_2b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2b> (%08x)", op); return 4;}
1142		int arcompact_handle04_2f_3f_2c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2c> (%08x)", op); return 4;}
1143		int arcompact_handle04_2f_3f_2d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2d> (%08x)", op); return 4;}
1144		int arcompact_handle04_2f_3f_2e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2e> (%08x)", op); return 4;}
1145		int arcompact_handle04_2f_3f_2f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2f> (%08x)", op); return 4;}
1146		int arcompact_handle04_2f_3f_30_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_30> (%08x)", op); return 4;}
1147		int arcompact_handle04_2f_3f_31_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_31> (%08x)", op); return 4;}
1148		int arcompact_handle04_2f_3f_32_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_32> (%08x)", op); return 4;}
1149		int arcompact_handle04_2f_3f_33_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_33> (%08x)", op); return 4;}
1150		int arcompact_handle04_2f_3f_34_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_34> (%08x)", op); return 4;}
1151		int arcompact_handle04_2f_3f_35_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_35> (%08x)", op); return 4;}
1152		int arcompact_handle04_2f_3f_36_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_36> (%08x)", op); return 4;}
1153		int arcompact_handle04_2f_3f_37_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_37> (%08x)", op); return 4;}
1154		int arcompact_handle04_2f_3f_38_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_38> (%08x)", op); return 4;}
1155		int arcompact_handle04_2f_3f_39_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_39> (%08x)", op); return 4;}
1156		int arcompact_handle04_2f_3f_3a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3a> (%08x)", op); return 4;}
1157		int arcompact_handle04_2f_3f_3b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3b> (%08x)", op); return 4;}
1158		int arcompact_handle04_2f_3f_3c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3c> (%08x)", op); return 4;}
1159		int arcompact_handle04_2f_3f_3d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3d> (%08x)", op); return 4;}
1160		int arcompact_handle04_2f_3f_3e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3e> (%08x)", op); return 4;}
1161		int arcompact_handle04_2f_3f_3f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3f> (%08x)", op); return 4;}
1162
1163
1164
1165
1166
1167
1168
1169
1170		int arcompact_handle04_30_dasm(DASM_OPS_32)  { print("LD r-r (basecase 0x30) (%08x)", op); return 4;}
1171		int arcompact_handle04_31_dasm(DASM_OPS_32)  { print("LD r-r (basecase 0x31) (%08x)", op); return 4;}
1172		int arcompact_handle04_32_dasm(DASM_OPS_32)  { print("LD r-r (basecase 0x32) (%08x)", op); return 4;}
1173		int arcompact_handle04_33_dasm(DASM_OPS_32)  { print("LD r-r (basecase 0x33) (%08x)", op); return 4;}
1174		int arcompact_handle04_34_dasm(DASM_OPS_32)  { print("LD r-r (basecase 0x34) (%08x)", op); return 4;}
1175		int arcompact_handle04_35_dasm(DASM_OPS_32)  { print("LD r-r (basecase 0x35) (%08x)", op); return 4;}
1176		int arcompact_handle04_36_dasm(DASM_OPS_32)  { print("LD r-r (basecase 0x36) (%08x)", op); return 4;}
1177		int arcompact_handle04_37_dasm(DASM_OPS_32)  { print("LD r-r (basecase 0x37) (%08x)", op); return 4;}
1178		int arcompact_handle04_38_dasm(DASM_OPS_32)  { print("<illegal 0x04_38> (%08x)", op); return 4;}
1179		int arcompact_handle04_39_dasm(DASM_OPS_32)  { print("<illegal 0x04_39> (%08x)", op); return 4;}
1180		int arcompact_handle04_3a_dasm(DASM_OPS_32)  { print("<illegal 0x04_3a> (%08x)", op); return 4;}
1181		int arcompact_handle04_3b_dasm(DASM_OPS_32)  { print("<illegal 0x04_3b> (%08x)", op); return 4;}
1182		int arcompact_handle04_3c_dasm(DASM_OPS_32)  { print("<illegal 0x04_3c> (%08x)", op); return 4;}
1183		int arcompact_handle04_3d_dasm(DASM_OPS_32)  { print("<illegal 0x04_3d> (%08x)", op); return 4;}
1184		int arcompact_handle04_3e_dasm(DASM_OPS_32)  { print("<illegal 0x04_3e> (%08x)", op); return 4;}
1185		int arcompact_handle04_3f_dasm(DASM_OPS_32)  { print("<illegal 0x04_3f> (%08x)", op); return 4;}
1186
1187
1188
1189
1190
1191		// this is an Extension ALU group, maybe optional on some CPUs?
1192		int arcompact_handle05_dasm(DASM_OPS_32)
1193		{
1194		int size = 4;
1195		UINT8 subinstr = (op & 0x003f0000) >> 16;
1196		op &= ~0x003f0000;
1197
1198		switch (subinstr)
1199		{
1200		case 0x00: size = arcompact_handle05_00_dasm(DASM_PARAMS); break; // ASL
1201		case 0x01: size = arcompact_handle05_01_dasm(DASM_PARAMS); break; // LSR
1202		case 0x02: size = arcompact_handle05_02_dasm(DASM_PARAMS); break; // ASR
1203		case 0x03: size = arcompact_handle05_03_dasm(DASM_PARAMS); break; // ROR
1204		case 0x04: size = arcompact_handle05_04_dasm(DASM_PARAMS); break; // MUL64
1205		case 0x05: size = arcompact_handle05_05_dasm(DASM_PARAMS); break; // MULU64
1206		case 0x06: size = arcompact_handle05_06_dasm(DASM_PARAMS); break; // ADDS
1207		case 0x07: size = arcompact_handle05_07_dasm(DASM_PARAMS); break; // SUBS
1208		case 0x08: size = arcompact_handle05_08_dasm(DASM_PARAMS); break; // DIVAW
1209		case 0x09: size = arcompact_handle05_09_dasm(DASM_PARAMS); break; // illegal
1210		case 0x0a: size = arcompact_handle05_0a_dasm(DASM_PARAMS); break; // ASLS
1211		case 0x0b: size = arcompact_handle05_0b_dasm(DASM_PARAMS); break; // ASRS
1212		case 0x0c: size = arcompact_handle05_0c_dasm(DASM_PARAMS); break; // illegal
1213		case 0x0d: size = arcompact_handle05_0d_dasm(DASM_PARAMS); break; // illegal
1214		case 0x0e: size = arcompact_handle05_0e_dasm(DASM_PARAMS); break; // illegal
1215		case 0x0f: size = arcompact_handle05_0f_dasm(DASM_PARAMS); break; // illegal
1216		case 0x10: size = arcompact_handle05_10_dasm(DASM_PARAMS); break; // illegal
1217		case 0x11: size = arcompact_handle05_11_dasm(DASM_PARAMS); break; // illegal
1218		case 0x12: size = arcompact_handle05_12_dasm(DASM_PARAMS); break; // illegal
1219		case 0x13: size = arcompact_handle05_13_dasm(DASM_PARAMS); break; // illegal
1220		case 0x14: size = arcompact_handle05_14_dasm(DASM_PARAMS); break; // illegal
1221		case 0x15: size = arcompact_handle05_15_dasm(DASM_PARAMS); break; // illegal
1222		case 0x16: size = arcompact_handle05_16_dasm(DASM_PARAMS); break; // illegal
1223		case 0x17: size = arcompact_handle05_17_dasm(DASM_PARAMS); break; // illegal
1224		case 0x18: size = arcompact_handle05_18_dasm(DASM_PARAMS); break; // illegal
1225		case 0x19: size = arcompact_handle05_19_dasm(DASM_PARAMS); break; // illegal
1226		case 0x1a: size = arcompact_handle05_1a_dasm(DASM_PARAMS); break; // illegal
1227		case 0x1b: size = arcompact_handle05_1b_dasm(DASM_PARAMS); break; // illegal
1228		case 0x1c: size = arcompact_handle05_1c_dasm(DASM_PARAMS); break; // illegal
1229		case 0x1d: size = arcompact_handle05_1d_dasm(DASM_PARAMS); break; // illegal
1230		case 0x1e: size = arcompact_handle05_1e_dasm(DASM_PARAMS); break; // illegal
1231		case 0x1f: size = arcompact_handle05_1f_dasm(DASM_PARAMS); break; // illegal
1232		case 0x20: size = arcompact_handle05_20_dasm(DASM_PARAMS); break; // illegal
1233		case 0x21: size = arcompact_handle05_21_dasm(DASM_PARAMS); break; // illegal
1234		case 0x22: size = arcompact_handle05_22_dasm(DASM_PARAMS); break; // illegal
1235		case 0x23: size = arcompact_handle05_23_dasm(DASM_PARAMS); break; // illegal
1236		case 0x24: size = arcompact_handle05_24_dasm(DASM_PARAMS); break; // illegal
1237		case 0x25: size = arcompact_handle05_25_dasm(DASM_PARAMS); break; // illegal
1238		case 0x26: size = arcompact_handle05_26_dasm(DASM_PARAMS); break; // illegal
1239		case 0x27: size = arcompact_handle05_27_dasm(DASM_PARAMS); break; // illegal
1240		case 0x28: size = arcompact_handle05_28_dasm(DASM_PARAMS); break; // ADDSDW
1241		case 0x29: size = arcompact_handle05_29_dasm(DASM_PARAMS); break; // SUBSDW
1242		case 0x2a: size = arcompact_handle05_2a_dasm(DASM_PARAMS); break; // illegal
1243		case 0x2b: size = arcompact_handle05_2b_dasm(DASM_PARAMS); break; // illegal
1244		case 0x2c: size = arcompact_handle05_2c_dasm(DASM_PARAMS); break; // illegal
1245		case 0x2d: size = arcompact_handle05_2d_dasm(DASM_PARAMS); break; // illegal
1246		case 0x2e: size = arcompact_handle05_2e_dasm(DASM_PARAMS); break; // illegal
1247		case 0x2f: size = arcompact_handle05_2f_dasm(DASM_PARAMS); break; // SOPs
1248		case 0x30: size = arcompact_handle05_30_dasm(DASM_PARAMS); break; // illegal
1249		case 0x31: size = arcompact_handle05_31_dasm(DASM_PARAMS); break; // illegal
1250		case 0x32: size = arcompact_handle05_32_dasm(DASM_PARAMS); break; // illegal
1251		case 0x33: size = arcompact_handle05_33_dasm(DASM_PARAMS); break; // illegal
1252		case 0x34: size = arcompact_handle05_34_dasm(DASM_PARAMS); break; // illegal
1253		case 0x35: size = arcompact_handle05_35_dasm(DASM_PARAMS); break; // illegal
1254		case 0x36: size = arcompact_handle05_36_dasm(DASM_PARAMS); break; // illegal
1255		case 0x37: size = arcompact_handle05_37_dasm(DASM_PARAMS); break; // illegal
1256		case 0x38: size = arcompact_handle05_38_dasm(DASM_PARAMS); break; // illegal
1257		case 0x39: size = arcompact_handle05_39_dasm(DASM_PARAMS); break; // illegal
1258		case 0x3a: size = arcompact_handle05_3a_dasm(DASM_PARAMS); break; // illegal
1259		case 0x3b: size = arcompact_handle05_3b_dasm(DASM_PARAMS); break; // illegal
1260		case 0x3c: size = arcompact_handle05_3c_dasm(DASM_PARAMS); break; // illegal
1261		case 0x3d: size = arcompact_handle05_3d_dasm(DASM_PARAMS); break; // illegal
1262		case 0x3e: size = arcompact_handle05_3e_dasm(DASM_PARAMS); break; // illegal
1263		case 0x3f: size = arcompact_handle05_3f_dasm(DASM_PARAMS); break; // illegal
1264		}
1265
1266		return size;
1267		}
1268
1269		int arcompact_handle05_00_dasm(DASM_OPS_32)  { print("ASL a <- b asl c (%08x)", op); return 4;}
1270		int arcompact_handle05_01_dasm(DASM_OPS_32)  { print("LSR a <- b lsr c (%08x)", op); return 4;}
1271		int arcompact_handle05_02_dasm(DASM_OPS_32)  { print("ASR a <- b asr c (%08x)", op); return 4;}
1272		int arcompact_handle05_03_dasm(DASM_OPS_32)  { print("ROR a <- b ror c (%08x)", op); return 4;}
1273		int arcompact_handle05_04_dasm(DASM_OPS_32)  { print("MUL64 mulres <- b * c (%08x)", op); return 4;}
1274		int arcompact_handle05_05_dasm(DASM_OPS_32)  { print("MULU64 mulres <- b * c (%08x)", op); return 4;}
1275		int arcompact_handle05_06_dasm(DASM_OPS_32)  { print("ADDS a <- sat32 (b + c) (%08x)", op); return 4;}
1276		int arcompact_handle05_07_dasm(DASM_OPS_32)  { print("SUBS a <- sat32 (b + c) (%08x)", op); return 4;}
1277		int arcompact_handle05_08_dasm(DASM_OPS_32)  { print("DIVAW (%08x)", op); return 4;}
1278		int arcompact_handle05_09_dasm(DASM_OPS_32)  { print("<illegal 0x05_09> (%08x)", op); return 4;}
1279		int arcompact_handle05_0a_dasm(DASM_OPS_32)  { print("ASLS a <- sat32 (b << c) (%08x)", op); return 4;}
1280		int arcompact_handle05_0b_dasm(DASM_OPS_32)  { print("ASRS a ,- sat32 (b >> c) (%08x)", op); return 4;}
1281		int arcompact_handle05_0c_dasm(DASM_OPS_32)  { print("<illegal 0x05_0c> (%08x)", op); return 4;}
1282		int arcompact_handle05_0d_dasm(DASM_OPS_32)  { print("<illegal 0x05_0d> (%08x)", op); return 4;}
1283		int arcompact_handle05_0e_dasm(DASM_OPS_32)  { print("<illegal 0x05_0e> (%08x)", op); return 4;}
1284		int arcompact_handle05_0f_dasm(DASM_OPS_32)  { print("<illegal 0x05_0f> (%08x)", op); return 4;}
1285		int arcompact_handle05_10_dasm(DASM_OPS_32)  { print("<illegal 0x05_10> (%08x)", op); return 4;}
1286		int arcompact_handle05_11_dasm(DASM_OPS_32)  { print("<illegal 0x05_11> (%08x)", op); return 4;}
1287		int arcompact_handle05_12_dasm(DASM_OPS_32)  { print("<illegal 0x05_12> (%08x)", op); return 4;}
1288		int arcompact_handle05_13_dasm(DASM_OPS_32)  { print("<illegal 0x05_13> (%08x)", op); return 4;}
1289		int arcompact_handle05_14_dasm(DASM_OPS_32)  { print("<illegal 0x05_14> (%08x)", op); return 4;}
1290		int arcompact_handle05_15_dasm(DASM_OPS_32)  { print("<illegal 0x05_15> (%08x)", op); return 4;}
1291		int arcompact_handle05_16_dasm(DASM_OPS_32)  { print("<illegal 0x05_16> (%08x)", op); return 4;}
1292		int arcompact_handle05_17_dasm(DASM_OPS_32)  { print("<illegal 0x05_17> (%08x)", op); return 4;}
1293		int arcompact_handle05_18_dasm(DASM_OPS_32)  { print("<illegal 0x05_18> (%08x)", op); return 4;}
1294		int arcompact_handle05_19_dasm(DASM_OPS_32)  { print("<illegal 0x05_19> (%08x)", op); return 4;}
1295		int arcompact_handle05_1a_dasm(DASM_OPS_32)  { print("<illegal 0x05_1a> (%08x)", op); return 4;}
1296		int arcompact_handle05_1b_dasm(DASM_OPS_32)  { print("<illegal 0x05_1b> (%08x)", op); return 4;}
1297		int arcompact_handle05_1c_dasm(DASM_OPS_32)  { print("<illegal 0x05_1c> (%08x)", op); return 4;}
1298		int arcompact_handle05_1d_dasm(DASM_OPS_32)  { print("<illegal 0x05_1d> (%08x)", op); return 4;}
1299		int arcompact_handle05_1e_dasm(DASM_OPS_32)  { print("<illegal 0x05_1e> (%08x)", op); return 4;}
1300		int arcompact_handle05_1f_dasm(DASM_OPS_32)  { print("<illegal 0x05_1f> (%08x)", op); return 4;}
1301		int arcompact_handle05_20_dasm(DASM_OPS_32)  { print("<illegal 0x05_20> (%08x)", op); return 4;}
1302		int arcompact_handle05_21_dasm(DASM_OPS_32)  { print("<illegal 0x05_21> (%08x)", op); return 4;}
1303		int arcompact_handle05_22_dasm(DASM_OPS_32)  { print("<illegal 0x05_22> (%08x)", op); return 4;}
1304		int arcompact_handle05_23_dasm(DASM_OPS_32)  { print("<illegal 0x05_23> (%08x)", op); return 4;}
1305		int arcompact_handle05_24_dasm(DASM_OPS_32)  { print("<illegal 0x05_24> (%08x)", op); return 4;}
1306		int arcompact_handle05_25_dasm(DASM_OPS_32)  { print("<illegal 0x05_25> (%08x)", op); return 4;}
1307		int arcompact_handle05_26_dasm(DASM_OPS_32)  { print("<illegal 0x05_26> (%08x)", op); return 4;}
1308		int arcompact_handle05_27_dasm(DASM_OPS_32)  { print("<illegal 0x05_27> (%08x)", op); return 4;}
1309		int arcompact_handle05_28_dasm(DASM_OPS_32)  { print("ADDSDW (%08x)", op); return 4;}
1310		int arcompact_handle05_29_dasm(DASM_OPS_32)  { print("SUBSDW (%08x)", op); return 4;}
1311		int arcompact_handle05_2a_dasm(DASM_OPS_32)  { print("<illegal 0x05_2a> (%08x)", op); return 4;}
1312		int arcompact_handle05_2b_dasm(DASM_OPS_32)  { print("<illegal 0x05_2b> (%08x)", op); return 4;}
1313		int arcompact_handle05_2c_dasm(DASM_OPS_32)  { print("<illegal 0x05_2c> (%08x)", op); return 4;}
1314		int arcompact_handle05_2d_dasm(DASM_OPS_32)  { print("<illegal 0x05_2d> (%08x)", op); return 4;}
1315		int arcompact_handle05_2e_dasm(DASM_OPS_32)  { print("<illegal 0x05_2e> (%08x)", op); return 4;}
1316		int arcompact_handle05_2f_dasm(DASM_OPS_32)  { print("SOP (another table) (%08x)", op); return 4;}
1317		int arcompact_handle05_30_dasm(DASM_OPS_32)  { print("<illegal 0x05_30> (%08x)", op); return 4;}
1318		int arcompact_handle05_31_dasm(DASM_OPS_32)  { print("<illegal 0x05_31> (%08x)", op); return 4;}
1319		int arcompact_handle05_32_dasm(DASM_OPS_32)  { print("<illegal 0x05_32> (%08x)", op); return 4;}
1320		int arcompact_handle05_33_dasm(DASM_OPS_32)  { print("<illegal 0x05_33> (%08x)", op); return 4;}
1321		int arcompact_handle05_34_dasm(DASM_OPS_32)  { print("<illegal 0x05_34> (%08x)", op); return 4;}
1322		int arcompact_handle05_35_dasm(DASM_OPS_32)  { print("<illegal 0x05_35> (%08x)", op); return 4;}
1323		int arcompact_handle05_36_dasm(DASM_OPS_32)  { print("<illegal 0x05_36> (%08x)", op); return 4;}
1324		int arcompact_handle05_37_dasm(DASM_OPS_32)  { print("<illegal 0x05_37> (%08x)", op); return 4;}
1325		int arcompact_handle05_38_dasm(DASM_OPS_32)  { print("<illegal 0x05_38> (%08x)", op); return 4;}
1326		int arcompact_handle05_39_dasm(DASM_OPS_32)  { print("<illegal 0x05_39> (%08x)", op); return 4;}
1327		int arcompact_handle05_3a_dasm(DASM_OPS_32)  { print("<illegal 0x05_3a> (%08x)", op); return 4;}
1328		int arcompact_handle05_3b_dasm(DASM_OPS_32)  { print("<illegal 0x05_3b> (%08x)", op); return 4;}
1329		int arcompact_handle05_3c_dasm(DASM_OPS_32)  { print("<illegal 0x05_3c> (%08x)", op); return 4;}
1330		int arcompact_handle05_3d_dasm(DASM_OPS_32)  { print("<illegal 0x05_3d> (%08x)", op); return 4;}
1331		int arcompact_handle05_3e_dasm(DASM_OPS_32)  { print("<illegal 0x05_3e> (%08x)", op); return 4;}
1332		int arcompact_handle05_3f_dasm(DASM_OPS_32)  { print("<illegal 0x05_3f> (%08x)", op); return 4;}
1333
1334
1335
1336		int arcompact_handle06_dasm(DASM_OPS_32)
1337		{
1338		print("op a,b,c (06 ARC ext) (%08x)", op );
1339		return 4;
1340		}
1341
1342		int arcompact_handle07_dasm(DASM_OPS_32)
1343		{
1344		print("op a,b,c (07 User ext) (%08x)", op );
1345		return 4;
1346		}
1347
1348		int arcompact_handle08_dasm(DASM_OPS_32)
1349		{
1350		print("op a,b,c (08 User ext) (%08x)", op );
1351		return 4;
1352		}
1353
1354		int arcompact_handle09_dasm(DASM_OPS_32)
1355		{
1356		print("op a,b,c (09 Market ext) (%08x)", op );
1357		return 4;
1358		}
1359
1360		int arcompact_handle0a_dasm(DASM_OPS_32)
1361		{
1362		print("op a,b,c (0a Market ext) (%08x)",  op );
1363		return 4;
1364		}
1365
1366		int arcompact_handle0b_dasm(DASM_OPS_32)
1367		{
1368		print("op a,b,c (0b Market ext) (%08x)",  op );
1369		return 4;
1370		}
1371
1372
1373
1374
1375		int arcompact_handle0c_dasm(DASM_OPS_16)
1376		{
1377		int size = 2;
1378		UINT8 subinstr = (op & 0x0018) >> 3;
1379		op &= ~0x0018;
1380
1381		switch (subinstr)
1382		{
1383		case 0x00: size = arcompact_handle0c_00_dasm(DASM_PARAMS); break; // LD_S
1384		case 0x01: size = arcompact_handle0c_01_dasm(DASM_PARAMS); break; // LDB_S
1385		case 0x02: size = arcompact_handle0c_02_dasm(DASM_PARAMS); break; // LDW_S
1386		case 0x03: size = arcompact_handle0c_03_dasm(DASM_PARAMS); break; // ADD_S
1387		}
1388		return size;
1389		}
1390
1391
1392		int arcompact_handle0c_00_dasm(DASM_OPS_16)
1393		{
1394		int size = 2;
1395		print("LD_S a <- m[b + c].long (%04x)", op);
1396		return size;
1397		}
1398
1399		int arcompact_handle0c_01_dasm(DASM_OPS_16)
1400		{
1401		int size = 2;
1402		print("LDB_S a <- m[b + c].byte (%04x)", op);
1403		return size;
1404		}
1405
1406		int arcompact_handle0c_02_dasm(DASM_OPS_16)
1407		{
1408		int size = 2;
1409		print("LDW_S a <- m[b + c].word (%04x)", op);
1410		return size;
1411		}
1412
1413		int arcompact_handle0c_03_dasm(DASM_OPS_16)
1414		{
1415		int size = 2;
1416		print("ADD_S a <- b + c (%04x)", op);
1417		return size;
1418		}
1419
1420
1421		int arcompact_handle0d_dasm(DASM_OPS_16)
1422		{
1423		int size = 2;
1424		UINT8 subinstr = (op & 0x0018) >> 3;
1425		op &= ~0x0018;
1426
1427		switch (subinstr)
1428		{
1429		case 0x00: size = arcompact_handle0d_00_dasm(DASM_PARAMS); break; // ADD_S
1430		case 0x01: size = arcompact_handle0d_01_dasm(DASM_PARAMS); break; // SUB_S
1431		case 0x02: size = arcompact_handle0d_02_dasm(DASM_PARAMS); break; // ASL_S
1432		case 0x03: size = arcompact_handle0d_03_dasm(DASM_PARAMS); break; // ASR_S
1433		}
1434		return size;
1435		}
1436
1437		int arcompact_handle0d_00_dasm(DASM_OPS_16)
1438		{
1439		int size = 2;
1440		print("ADD_S c <- b + u3 (%04x)", op);
1441		return size;
1442		}
1443
1444		int arcompact_handle0d_01_dasm(DASM_OPS_16)
1445		{
1446		int size = 2;
1447		print("SUB_S c <- b - u3 (%04x)", op);
1448		return size;
1449		}
1450
1451		int arcompact_handle0d_02_dasm(DASM_OPS_16)
1452		{
1453		int size = 2;
1454		print("ASL_S c <- b asl u3 (%04x)", op);
1455		return size;
1456		}
1457
1458		int arcompact_handle0d_03_dasm(DASM_OPS_16)
1459		{
1460		int size = 2;
1461		print("ASL_S c <- b asr u3 (%04x)", op);
1462		return size;
1463		}
1464
1465
1466		int arcompact_handle0e_dasm(DASM_OPS_16)
1467		{
1468		int size = 2;
1469		UINT8 subinstr = (op & 0x0018) >> 3;
1470		op &= ~0x0018;
1471
1472		switch (subinstr)
1473		{
1474		case 0x00: size = arcompact_handle0e_00_dasm(DASM_PARAMS); break; // ADD_S
1475		case 0x01: size = arcompact_handle0e_01_dasm(DASM_PARAMS); break; // MOV_S
1476		case 0x02: size = arcompact_handle0e_02_dasm(DASM_PARAMS); break; // CMP_S
1477		case 0x03: size = arcompact_handle0e_03_dasm(DASM_PARAMS); break; // MOV_S
1478		}
1479		return size;
1480		}
1481
1482
1483
1484
1485		#define GROUP_0e_GET_h \
1486		h =  ((op & 0x0007) << 3); \
1487		h |= ((op & 0x00e0) >> 5); \
1488
1489		// this is as messed up as the rest of the 16-bit alignment in LE mode...
1490
1491		#define GET_LIMM \
1492		limm = oprom[4] | (oprom[5] << 8); \
1493		limm |= (oprom[2] << 16) | (oprom[3] << 24); \
1494
1495
1496		int arcompact_handle0e_00_dasm(DASM_OPS_16)
1497		{
1498		int h;
1499		int size = 2;
1500
1501		GROUP_0e_GET_h;
1502
1503		if (h == LIMM_REG)
1504		{
1505		UINT32 limm;
1506		GET_LIMM;
1507		size = 6;
1508		print("ADD_S b <- b + (%08x) (%04x)", limm, op);
1509		}
1510		else
1511		{
1512
1513		print("ADD_S b <- b + (r%d) (%04x)", h, op);
1514		}
1515
1516		return size;
1517		}
1518
1519		int arcompact_handle0e_01_dasm(DASM_OPS_16)
1520		{
1521		int h;
1522		int size = 2;
1523		GROUP_0e_GET_h;
1524
1525		if (h == LIMM_REG)
1526		{
1527		UINT32 limm;
1528		GET_LIMM;
1529		size = 6;
1530		print("MOV_S b <- (%08x)  (%04x)", limm, op);
1531		}
1532		else
1533		{
1534		print("MOV_S b <- (r%d)  (%04x)", h, op);
1535		}
1536		return size;
1537		}
1538
1539		int arcompact_handle0e_02_dasm(DASM_OPS_16)
1540		{
1541		int h;
1542		int size = 2;
1543		GROUP_0e_GET_h;
1544
1545		if (h == LIMM_REG)
1546		{
1547		UINT32 limm;
1548		GET_LIMM;
1549		size = 6;
1550		print("CMP_S b - (%08x) (%04x)", limm, op);
1551		}
1552		else
1553		{
1554		print("CMP_S b - (r%d) (%04x)", h, op);
1555		}
1556		return size;
1557		}
1558
1559		int arcompact_handle0e_03_dasm(DASM_OPS_16)
1560		{
1561		int h;
1562		int size = 2;
1563		GROUP_0e_GET_h;
1564
1565		if (h == LIMM_REG)
1566		{
1567		UINT32 limm;
1568		GET_LIMM;
1569		size = 6;
1570		print("MOV_S (%08x) <- b (%04x)", limm, op);
1571		}
1572		else
1573		{
1574		print("MOV_S (r%d) <- b (%04x)", h, op);
1575		}
1576
1577		return size;
1578		}
1579
1580
1581
1582		int arcompact_handle0f_dasm(DASM_OPS_16)
1583		{
1584		// General Register Instructions (16-bit)
1585		// 01111 bbb ccc iiiii
1586		UINT8 subinstr = (op & 0x01f) >> 0;
1587		//print("%s (%04x)", table0f[subinstr], op & ~0xf81f);
1588
1589		switch (subinstr)
1590		{
1591
1592		default:
1593		print("%s (%04x)", table0f[subinstr], op & ~0xf81f);
1594		break;
1595
1596		case 0x00:
1597		{
1598		// General Operations w/ Register
1599		// 01111 bbb iii 00000
1600		UINT8 subinstr2 = (op & 0x00e0) >> 5;
1601
1602		switch (subinstr2)
1603		{
1604		default:
1605		print("%s (%04x)", table0f_00[subinstr2], op & ~0xf8ff);
1606		return 2;
1607
1608		case 0x7:
1609		{
1610		// General Operations w/o Register
1611		// 01111 iii 111 00000
1612		UINT8 subinstr3 = (op & 0x0700) >> 8;
1613
1614		print("%s (%04x)", table0f_00_07[subinstr3], op & ~0xffff);
1615
1616		return 2;
1617		}
1618		}
1619		}
1620		}
1621
1622		return 2;
1623		}
1624
1625		int arcompact_handle10_dasm(DASM_OPS_16)
1626		{
1627		print("LD_S (%04x)",  op);
1628		return 2;
1629		}
1630
1631		int arcompact_handle11_dasm(DASM_OPS_16)
1632		{
1633		print("LDB_S (%04x)", op);
1634		return 2;
1635		}
1636
1637		int arcompact_handle12_dasm(DASM_OPS_16)
1638		{
1639		print("LDW_S (%04x)", op);
1640		return 2;
1641		}
1642
1643		int arcompact_handle13_dasm(DASM_OPS_16)
1644		{
1645		print("LSW_S.X (%04x)", op);
1646		return 2;
1647		}
1648
1649		int arcompact_handle14_dasm(DASM_OPS_16)
1650		{
1651		print("ST_S (%04x)", op);
1652		return 2;
1653		}
1654
1655		int arcompact_handle15_dasm(DASM_OPS_16)
1656		{
1657		print("STB_S (%04x)", op);
1658		return 2;
1659		}
1660
1661		int arcompact_handle16_dasm(DASM_OPS_16)
1662		{
1663		print("STW_S (%04x)",  op);
1664		return 2;
1665		}
1666
1667		int arcompact_handle17_dasm(DASM_OPS_16)
1668		{
1669		int size = 2;
1670		UINT8 subinstr = (op & 0x00e0) >> 5;
1671		op &= ~0x00e0;
1672
1673		switch (subinstr)
1674		{
1675		case 0x00: size = arcompact_handle17_00_dasm(DASM_PARAMS); break; // ASL_S
1676		case 0x01: size = arcompact_handle17_01_dasm(DASM_PARAMS); break; // LSR_S
1677		case 0x02: size = arcompact_handle17_02_dasm(DASM_PARAMS); break; // ASR_S
1678		case 0x03: size = arcompact_handle17_03_dasm(DASM_PARAMS); break; // SUB_S
1679		case 0x04: size = arcompact_handle17_04_dasm(DASM_PARAMS); break; // BSET_S
1680		case 0x05: size = arcompact_handle17_05_dasm(DASM_PARAMS); break; // BCLR_S
1681		case 0x06: size = arcompact_handle17_06_dasm(DASM_PARAMS); break; // BMSK_S
1682		case 0x07: size = arcompact_handle17_07_dasm(DASM_PARAMS); break; // BTST_S
1683		}
1684
1685		return size;
1686		}
1687
1688		int arcompact_handle17_00_dasm(DASM_OPS_16)
1689		{
1690		int size = 2;
1691		print("ASL_S b <- b asl u5 (%04x)",  op);
1692		return size;
1693		}
1694
1695		int arcompact_handle17_01_dasm(DASM_OPS_16)
1696		{
1697		int size = 2;
1698		print("LSR_S b <- b lsr u5 (%04x)",  op);
1699		return size;
1700		}
1701
1702		int arcompact_handle17_02_dasm(DASM_OPS_16)
1703		{
1704		int size = 2;
1705		print("ASR_S b <- b asr u5 (%04x)",  op);
1706		return size;
1707		}
1708
1709		int arcompact_handle17_03_dasm(DASM_OPS_16)
1710		{
1711		int size = 2;
1712		print("SUB_S b <- b - u5 (%04x)",  op);
1713		return size;
1714		}
1715
1716		int arcompact_handle17_04_dasm(DASM_OPS_16)
1717		{
1718		int size = 2;
1719		print("BSET_S b <- b | (1 << u5) (%04x)",  op);
1720		return size;
1721		}
1722
1723		int arcompact_handle17_05_dasm(DASM_OPS_16)
1724		{
1725		int size = 2;
1726		print("BCLR_S b <- b & !(1 << u5) (%04x)",  op);
1727		return size;
1728		}
1729
1730		int arcompact_handle17_06_dasm(DASM_OPS_16)
1731		{
1732		int size = 2;
1733		print("BMSK_S (%04x)",  op);
1734		return size;
1735		}
1736
1737		int arcompact_handle17_07_dasm(DASM_OPS_16)
1738		{
1739		int size = 2;
1740		print("BTST_S (%04x)",  op);
1741		return size;
1742		}
1743
1744		int arcompact_handle18_dasm(DASM_OPS_16)
1745		{
1746		int size = 2;
1747		// Stack Pointer Based Instructions (16-bit)
1748		// 11000 bbb iii uuuuu
1749		UINT8 subinstr = (op & 0x00e0) >> 5;
1750		op &= ~0x00e0;
1751
1752		switch (subinstr)
1753		{
1754		case 0x00: size = arcompact_handle18_00_dasm(DASM_PARAMS); break; // LD_S (SP)
1755		case 0x01: size = arcompact_handle18_01_dasm(DASM_PARAMS); break; // LDB_S (SP)
1756		case 0x02: size = arcompact_handle18_02_dasm(DASM_PARAMS); break; // ST_S (SP)
1757		case 0x03: size = arcompact_handle18_03_dasm(DASM_PARAMS); break; // STB_S (SP)
1758		case 0x04: size = arcompact_handle18_04_dasm(DASM_PARAMS); break; // ADD_S (SP)
1759		case 0x05: size = arcompact_handle18_05_dasm(DASM_PARAMS); break; // subtable 18_05
1760		case 0x06: size = arcompact_handle18_06_dasm(DASM_PARAMS); break; // subtable 18_06
1761		case 0x07: size = arcompact_handle18_07_dasm(DASM_PARAMS); break; // subtable 18_07
1762		}
1763
1764		return size;
1765		}
1766
1767		// op bits remaining for 0x18_xx subgroups 0x071f
1768
1769		int arcompact_handle18_00_dasm(DASM_OPS_16)
1770		{
1771		print("LD_S (SP) (%04x)",  op);
1772		return 2;
1773		}
1774
1775		int arcompact_handle18_01_dasm(DASM_OPS_16)
1776		{
1777		print("LDB_S (SP) (%04x)",  op);
1778		return 2;
1779		}
1780
1781		int arcompact_handle18_02_dasm(DASM_OPS_16)
1782		{
1783		print("ST_S (SP) (%04x)",  op);
1784		return 2;
1785		}
1786
1787		int arcompact_handle18_03_dasm(DASM_OPS_16)
1788		{
1789		print("STB_S (SP) (%04x)",  op);
1790		return 2;
1791		}
1792
1793		int arcompact_handle18_04_dasm(DASM_OPS_16)
1794		{
1795		print("ADD_S (SP) (%04x)",  op);
1796		return 2;
1797		}
1798
1799
1800
1801
1802
1803		int arcompact_handle18_05_dasm(DASM_OPS_16)
1804		{
1805		int size = 2;
1806		UINT8 subinstr2 = (op & 0x0700) >> 8;
1807		op &= ~0x001f;
1808
1809		switch (subinstr2)
1810		{
1811		case 0x00: size = arcompact_handle18_05_00_dasm(DASM_PARAMS); break; // ADD_S (SP)
1812		case 0x01: size = arcompact_handle18_05_01_dasm(DASM_PARAMS); break; // SUB_S (SP)
1813		case 0x02: size = arcompact_handle18_05_02_dasm(DASM_PARAMS); break; // <illegal 0x18_05_02>
1814		case 0x03: size = arcompact_handle18_05_03_dasm(DASM_PARAMS); break; // <illegal 0x18_05_03>
1815		case 0x04: size = arcompact_handle18_05_04_dasm(DASM_PARAMS); break; // <illegal 0x18_05_04>
1816		case 0x05: size = arcompact_handle18_05_05_dasm(DASM_PARAMS); break; // <illegal 0x18_05_05>
1817		case 0x06: size = arcompact_handle18_05_06_dasm(DASM_PARAMS); break; // <illegal 0x18_05_06>
1818		case 0x07: size = arcompact_handle18_05_07_dasm(DASM_PARAMS); break; // <illegal 0x18_05_07>
1819		}
1820
1821		return size;
1822		}
1823		// op bits remaining for 0x18_05_xx subgroups 0x001f
1824		int arcompact_handle18_05_00_dasm(DASM_OPS_16)
1825		{
1826		int u = op & 0x001f;
1827		op &= ~0x001f; // all bits now used
1828
1829		print("ADD_S %02x (SP)", u);
1830		return 2;
1831
1832		}
1833
1834		int arcompact_handle18_05_01_dasm(DASM_OPS_16)
1835		{
1836		int u = op & 0x001f;
1837		op &= ~0x001f; // all bits now used
1838
1839		print("SUB_S %02x (SP)", u);
1840		return 2;
1841		}
1842
1843
1844		int arcompact_handle18_05_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_02> (%04x)", op); return 2;}
1845		int arcompact_handle18_05_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_03> (%04x)", op); return 2;}
1846		int arcompact_handle18_05_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_04> (%04x)", op); return 2;}
1847		int arcompact_handle18_05_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_05> (%04x)", op); return 2;}
1848		int arcompact_handle18_05_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_06> (%04x)", op); return 2;}
1849		int arcompact_handle18_05_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_07> (%04x)", op); return 2;}
1850
1851
1852		int arcompact_handle18_06_dasm(DASM_OPS_16)
1853		{
1854		int size = 2;
1855		UINT8 subinstr2 = (op & 0x001f) >> 0;
1856		op &= ~0x001f;
1857
1858		switch (subinstr2)
1859		{
1860		case 0x00: size = arcompact_handle18_06_00_dasm(DASM_PARAMS); break; // <illegal 0x18_06_00>
1861		case 0x01: size = arcompact_handle18_06_01_dasm(DASM_PARAMS); break; // POP_S b
1862		case 0x02: size = arcompact_handle18_06_02_dasm(DASM_PARAMS); break; // <illegal 0x18_06_02>
1863		case 0x03: size = arcompact_handle18_06_03_dasm(DASM_PARAMS); break; // <illegal 0x18_06_03>
1864		case 0x04: size = arcompact_handle18_06_04_dasm(DASM_PARAMS); break; // <illegal 0x18_06_04>
1865		case 0x05: size = arcompact_handle18_06_05_dasm(DASM_PARAMS); break; // <illegal 0x18_06_05>
1866		case 0x06: size = arcompact_handle18_06_06_dasm(DASM_PARAMS); break; // <illegal 0x18_06_06>
1867		case 0x07: size = arcompact_handle18_06_07_dasm(DASM_PARAMS); break; // <illegal 0x18_06_07>
1868		case 0x08: size = arcompact_handle18_06_08_dasm(DASM_PARAMS); break; // <illegal 0x18_06_08>
1869		case 0x09: size = arcompact_handle18_06_09_dasm(DASM_PARAMS); break; // <illegal 0x18_06_09>
1870		case 0x0a: size = arcompact_handle18_06_0a_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0a>
1871		case 0x0b: size = arcompact_handle18_06_0b_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0b>
1872		case 0x0c: size = arcompact_handle18_06_0c_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0c>
1873		case 0x0d: size = arcompact_handle18_06_0d_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0d>
1874		case 0x0e: size = arcompact_handle18_06_0e_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0e>
1875		case 0x0f: size = arcompact_handle18_06_0f_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0f>
1876		case 0x10: size = arcompact_handle18_06_10_dasm(DASM_PARAMS); break; // <illegal 0x18_06_10>
1877		case 0x11: size = arcompact_handle18_06_11_dasm(DASM_PARAMS); break; // POP_S blink
1878		case 0x12: size = arcompact_handle18_06_12_dasm(DASM_PARAMS); break; // <illegal 0x18_06_12>
1879		case 0x13: size = arcompact_handle18_06_13_dasm(DASM_PARAMS); break; // <illegal 0x18_06_13>
1880		case 0x14: size = arcompact_handle18_06_14_dasm(DASM_PARAMS); break; // <illegal 0x18_06_14>
1881		case 0x15: size = arcompact_handle18_06_15_dasm(DASM_PARAMS); break; // <illegal 0x18_06_15>
1882		case 0x16: size = arcompact_handle18_06_16_dasm(DASM_PARAMS); break; // <illegal 0x18_06_16>
1883		case 0x17: size = arcompact_handle18_06_17_dasm(DASM_PARAMS); break; // <illegal 0x18_06_17>
1884		case 0x18: size = arcompact_handle18_06_18_dasm(DASM_PARAMS); break; // <illegal 0x18_06_18>
1885		case 0x19: size = arcompact_handle18_06_19_dasm(DASM_PARAMS); break; // <illegal 0x18_06_19>
1886		case 0x1a: size = arcompact_handle18_06_1a_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1a>
1887		case 0x1b: size = arcompact_handle18_06_1b_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1b>
1888		case 0x1c: size = arcompact_handle18_06_1c_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1c>
1889		case 0x1d: size = arcompact_handle18_06_1d_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1d>
1890		case 0x1e: size = arcompact_handle18_06_1e_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1e>
1891		case 0x1f: size = arcompact_handle18_06_1f_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1f>
1892		}
1893
1894		return size;
1895		}
1896
1897
1898		// op bits remaining for 0x18_06_xx subgroups 0x0700
1899		int arcompact_handle18_06_00_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_00> (%04x)",  op); return 2;}
1900
1901		int arcompact_handle18_06_01_dasm(DASM_OPS_16)
1902		{
1903		int b = (op & 0x0700) >> 8;
1904		op &= ~0x0700; // all bits now used
1905
1906		print("POP_S [%02x]", b);
1907
1908		return 2;
1909		}
1910
1911		int arcompact_handle18_06_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_02> (%04x)", op); return 2;}
1912		int arcompact_handle18_06_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_03> (%04x)", op); return 2;}
1913		int arcompact_handle18_06_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_04> (%04x)", op); return 2;}
1914		int arcompact_handle18_06_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_05> (%04x)", op); return 2;}
1915		int arcompact_handle18_06_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_06> (%04x)", op); return 2;}
1916		int arcompact_handle18_06_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_07> (%04x)", op); return 2;}
1917		int arcompact_handle18_06_08_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_08> (%04x)", op); return 2;}
1918		int arcompact_handle18_06_09_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_09> (%04x)", op); return 2;}
1919		int arcompact_handle18_06_0a_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0a> (%04x)", op); return 2;}
1920		int arcompact_handle18_06_0b_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0b> (%04x)", op); return 2;}
1921		int arcompact_handle18_06_0c_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0c> (%04x)", op); return 2;}
1922		int arcompact_handle18_06_0d_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0d> (%04x)", op); return 2;}
1923		int arcompact_handle18_06_0e_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0e> (%04x)", op); return 2;}
1924		int arcompact_handle18_06_0f_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0f> (%04x)", op); return 2;}
1925		int arcompact_handle18_06_10_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_10> (%04x)", op); return 2;}
1926
1927		int arcompact_handle18_06_11_dasm(DASM_OPS_16)
1928		{
1929		int res = (op & 0x0700) >> 8;
1930		op &= ~0x0700; // all bits now used
1931
1932		if (res)
1933		print("POP_S [BLINK] (Reserved Bits set %04x)", op);
1934		else
1935		print("POP_S [BLINK]");
1936
1937		return 2;
1938		}
1939
1940		int arcompact_handle18_06_12_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_12> (%04x)",  op); return 2;}
1941		int arcompact_handle18_06_13_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_13> (%04x)",  op); return 2;}
1942		int arcompact_handle18_06_14_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_14> (%04x)",  op); return 2;}
1943		int arcompact_handle18_06_15_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_15> (%04x)",  op); return 2;}
1944		int arcompact_handle18_06_16_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_16> (%04x)",  op); return 2;}
1945		int arcompact_handle18_06_17_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_17> (%04x)",  op); return 2;}
1946		int arcompact_handle18_06_18_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_18> (%04x)",  op); return 2;}
1947		int arcompact_handle18_06_19_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_19> (%04x)",  op); return 2;}
1948		int arcompact_handle18_06_1a_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1a> (%04x)",  op); return 2;}
1949		int arcompact_handle18_06_1b_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1b> (%04x)",  op); return 2;}
1950		int arcompact_handle18_06_1c_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1c> (%04x)",  op); return 2;}
1951		int arcompact_handle18_06_1d_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1d> (%04x)",  op); return 2;}
1952		int arcompact_handle18_06_1e_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1e> (%04x)",  op); return 2;}
1953		int arcompact_handle18_06_1f_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1f> (%04x)",  op); return 2;}
1954
1955
1956
1957
1958		int arcompact_handle18_07_dasm(DASM_OPS_16)
1959		{
1960		int size = 2;
1961		UINT8 subinstr2 = (op & 0x001f) >> 0;
1962		op &= ~0x001f;
1963
1964		switch (subinstr2)
1965		{
1966		case 0x00: size = arcompact_handle18_07_00_dasm(DASM_PARAMS); break; // <illegal 0x18_07_00>
1967		case 0x01: size = arcompact_handle18_07_01_dasm(DASM_PARAMS); break; // PUSH_S b
1968		case 0x02: size = arcompact_handle18_07_02_dasm(DASM_PARAMS); break; // <illegal 0x18_07_02>
1969		case 0x03: size = arcompact_handle18_07_03_dasm(DASM_PARAMS); break; // <illegal 0x18_07_03>
1970		case 0x04: size = arcompact_handle18_07_04_dasm(DASM_PARAMS); break; // <illegal 0x18_07_04>
1971		case 0x05: size = arcompact_handle18_07_05_dasm(DASM_PARAMS); break; // <illegal 0x18_07_05>
1972		case 0x06: size = arcompact_handle18_07_06_dasm(DASM_PARAMS); break; // <illegal 0x18_07_06>
1973		case 0x07: size = arcompact_handle18_07_07_dasm(DASM_PARAMS); break; // <illegal 0x18_07_07>
1974		case 0x08: size = arcompact_handle18_07_08_dasm(DASM_PARAMS); break; // <illegal 0x18_07_08>
1975		case 0x09: size = arcompact_handle18_07_09_dasm(DASM_PARAMS); break; // <illegal 0x18_07_09>
1976		case 0x0a: size = arcompact_handle18_07_0a_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0a>
1977		case 0x0b: size = arcompact_handle18_07_0b_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0b>
1978		case 0x0c: size = arcompact_handle18_07_0c_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0c>
1979		case 0x0d: size = arcompact_handle18_07_0d_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0d>
1980		case 0x0e: size = arcompact_handle18_07_0e_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0e>
1981		case 0x0f: size = arcompact_handle18_07_0f_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0f>
1982		case 0x10: size = arcompact_handle18_07_10_dasm(DASM_PARAMS); break; // <illegal 0x18_07_10>
1983		case 0x11: size = arcompact_handle18_07_11_dasm(DASM_PARAMS); break; // PUSH_S blink
1984		case 0x12: size = arcompact_handle18_07_12_dasm(DASM_PARAMS); break; // <illegal 0x18_07_12>
1985		case 0x13: size = arcompact_handle18_07_13_dasm(DASM_PARAMS); break; // <illegal 0x18_07_13>
1986		case 0x14: size = arcompact_handle18_07_14_dasm(DASM_PARAMS); break; // <illegal 0x18_07_14>
1987		case 0x15: size = arcompact_handle18_07_15_dasm(DASM_PARAMS); break; // <illegal 0x18_07_15>
1988		case 0x16: size = arcompact_handle18_07_16_dasm(DASM_PARAMS); break; // <illegal 0x18_07_16>
1989		case 0x17: size = arcompact_handle18_07_17_dasm(DASM_PARAMS); break; // <illegal 0x18_07_17>
1990		case 0x18: size = arcompact_handle18_07_18_dasm(DASM_PARAMS); break; // <illegal 0x18_07_18>
1991		case 0x19: size = arcompact_handle18_07_19_dasm(DASM_PARAMS); break; // <illegal 0x18_07_19>
1992		case 0x1a: size = arcompact_handle18_07_1a_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1a>
1993		case 0x1b: size = arcompact_handle18_07_1b_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1b>
1994		case 0x1c: size = arcompact_handle18_07_1c_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1c>
1995		case 0x1d: size = arcompact_handle18_07_1d_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1d>
1996		case 0x1e: size = arcompact_handle18_07_1e_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1e>
1997		case 0x1f: size = arcompact_handle18_07_1f_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1f>
1998		}
1999
2000		return size;
2001		}
2002
2003
2004		// op bits remaining for 0x18_07_xx subgroups 0x0700
2005		int arcompact_handle18_07_00_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_00> (%04x)",  op); return 2;}
2006
2007		int arcompact_handle18_07_01_dasm(DASM_OPS_16)
2008		{
2009		int b = (op & 0x0700) >> 8;
2010		op &= ~0x0700; // all bits now used
2011
2012		print("PUSH_S [%02x]", b);
2013
2014		return 2;
2015		}
2016
2017		int arcompact_handle18_07_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_02> (%04x)", op); return 2;}
2018		int arcompact_handle18_07_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_03> (%04x)", op); return 2;}
2019		int arcompact_handle18_07_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_04> (%04x)", op); return 2;}
2020		int arcompact_handle18_07_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_05> (%04x)", op); return 2;}
2021		int arcompact_handle18_07_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_06> (%04x)", op); return 2;}
2022		int arcompact_handle18_07_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_07> (%04x)", op); return 2;}
2023		int arcompact_handle18_07_08_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_08> (%04x)", op); return 2;}
2024		int arcompact_handle18_07_09_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_09> (%04x)", op); return 2;}
2025		int arcompact_handle18_07_0a_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0a> (%04x)", op); return 2;}
2026		int arcompact_handle18_07_0b_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0b> (%04x)", op); return 2;}
2027		int arcompact_handle18_07_0c_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0c> (%04x)", op); return 2;}
2028		int arcompact_handle18_07_0d_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0d> (%04x)", op); return 2;}
2029		int arcompact_handle18_07_0e_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0e> (%04x)", op); return 2;}
2030		int arcompact_handle18_07_0f_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0f> (%04x)", op); return 2;}
2031		int arcompact_handle18_07_10_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_10> (%04x)", op); return 2;}
2032
2033		int arcompact_handle18_07_11_dasm(DASM_OPS_16)
2034		{
2035		int res = (op & 0x0700) >> 8;
2036		op &= ~0x0700; // all bits now used
2037
2038		if (res)
2039		print("PUSH_S [BLINK] (Reserved Bits set %04x)", op);
2040		else
2041		print("PUSH_S [BLINK]");
2042
2043		return 2;
2044		}
2045
2046		int arcompact_handle18_07_12_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_12> (%04x)",  op); return 2;}
2047		int arcompact_handle18_07_13_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_13> (%04x)",  op); return 2;}
2048		int arcompact_handle18_07_14_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_14> (%04x)",  op); return 2;}
2049		int arcompact_handle18_07_15_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_15> (%04x)",  op); return 2;}
2050		int arcompact_handle18_07_16_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_16> (%04x)",  op); return 2;}
2051		int arcompact_handle18_07_17_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_17> (%04x)",  op); return 2;}
2052		int arcompact_handle18_07_18_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_18> (%04x)",  op); return 2;}
2053		int arcompact_handle18_07_19_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_19> (%04x)",  op); return 2;}
2054		int arcompact_handle18_07_1a_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1a> (%04x)",  op); return 2;}
2055		int arcompact_handle18_07_1b_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1b> (%04x)",  op); return 2;}
2056		int arcompact_handle18_07_1c_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1c> (%04x)",  op); return 2;}
2057		int arcompact_handle18_07_1d_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1d> (%04x)",  op); return 2;}
2058		int arcompact_handle18_07_1e_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1e> (%04x)",  op); return 2;}
2059		int arcompact_handle18_07_1f_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1f> (%04x)",  op); return 2;}
2060
2061
2062		int arcompact_handle19_dasm(DASM_OPS_16)
2063		{
2064		int size = 2;
2065		UINT8 subinstr = (op & 0x0600) >> 9;
2066		op &= ~0x0600;
2067
2068		switch (subinstr)
2069		{
2070		case 0x00: size = arcompact_handle19_00_dasm(DASM_PARAMS); break; // LD_S (GP)
2071		case 0x01: size = arcompact_handle19_01_dasm(DASM_PARAMS); break; // LDB_S (GP)
2072		case 0x02: size = arcompact_handle19_02_dasm(DASM_PARAMS); break; // LDW_S (GP)
2073		case 0x03: size = arcompact_handle19_03_dasm(DASM_PARAMS); break; // ADD_S (GP)
2074		}
2075		return size;
2076		}
2077
2078		int arcompact_handle19_00_dasm(DASM_OPS_16)  { print("LD_S r0 <- m[GP + s11].long (%04x)",  op); return 2;}
2079		int arcompact_handle19_01_dasm(DASM_OPS_16)  { print("LDB_S r0 <- m[GP + s9].byte (%04x)",  op); return 2;}
2080		int arcompact_handle19_02_dasm(DASM_OPS_16)  { print("LDW_S r0 <- m[GP + s10].word (%04x)",  op); return 2;}
2081		int arcompact_handle19_03_dasm(DASM_OPS_16)  { print("ADD_S r0 <- GP + s11 (%04x)",  op); return 2;}
2082
2083
2084
2085		int arcompact_handle1a_dasm(DASM_OPS_16)
2086		{
2087		print("PCL Instr (%04x)", op);
2088		return 2;
2089		}
2090
2091		int arcompact_handle1b_dasm(DASM_OPS_16)
2092		{
2093		print("MOV_S (%04x)", op);
2094		return 2;
2095		}
2096
2097		int arcompact_handle1c_dasm(DASM_OPS_16)
2098		{
2099		int size = 2;
2100		UINT8 subinstr = (op & 0x0080) >> 7;
2101		op &= ~0x0080;
2102
2103		switch (subinstr)
2104		{
2105		case 0x00: size = arcompact_handle1c_00_dasm(DASM_PARAMS); break; // ADD_S
2106		case 0x01: size = arcompact_handle1c_01_dasm(DASM_PARAMS); break; // CMP_S
2107		}
2108		return size;
2109		}
2110
2111		int arcompact_handle1c_00_dasm(DASM_OPS_16)  { print("ADD_S b <- b + u7 (%04x)",  op); return 2;}
2112		int arcompact_handle1c_01_dasm(DASM_OPS_16)  { print("CMP_S b - u7 (%04x)",  op); return 2;}
2113
2114
2115		int arcompact_handle1d_dasm(DASM_OPS_16)
2116		{
2117		int size = 2;
2118		UINT8 subinstr = (op & 0x0080) >> 7;
2119		op &= ~0x0080;
2120
2121		switch (subinstr)
2122		{
2123		case 0x00: size = arcompact_handle1d_00_dasm(DASM_PARAMS); break; // BREQ_S
2124		case 0x01: size = arcompact_handle1d_01_dasm(DASM_PARAMS); break; // BRNE_S
2125		}
2126		return size;
2127		}
2128
2129		int arcompact_handle1d_00_dasm(DASM_OPS_16)  { print("BREQ_S (%04x)",  op); return 2;}
2130		int arcompact_handle1d_01_dasm(DASM_OPS_16)  { print("BRNE_S (%04x)",  op); return 2;}
2131
2132
2133		int arcompact_handle1e_dasm(DASM_OPS_16)
2134		{
2135		int size = 2;
2136		UINT8 subinstr = (op & 0x0600) >> 9;
2137		op &= ~0x0600;
2138
2139		switch (subinstr)
2140		{
2141		case 0x00: size = arcompact_handle1e_00_dasm(DASM_PARAMS); break; // B_S
2142		case 0x01: size = arcompact_handle1e_01_dasm(DASM_PARAMS); break; // BEQ_S
2143		case 0x02: size = arcompact_handle1e_02_dasm(DASM_PARAMS); break; // BNE_S
2144		case 0x03: size = arcompact_handle1e_03_dasm(DASM_PARAMS); break; // Bcc_S
2145		}
2146		return size;
2147		}
2148
2149		int arcompact_handle1e_00_dasm(DASM_OPS_16)  { print("B_S (%04x)",  op); return 2;}
2150		int arcompact_handle1e_01_dasm(DASM_OPS_16)  { print("BEQ_S (%04x)",  op); return 2;}
2151		int arcompact_handle1e_02_dasm(DASM_OPS_16)  { print("BNE_S (%04x)",  op); return 2;}
2152
2153
2154		int arcompact_handle1e_03_dasm(DASM_OPS_16)
2155		{
2156
2157		int size = 2;
2158		UINT8 subinstr2 = (op & 0x01c0) >> 6;
2159		op &= ~0x01c0;
2160
2161		switch (subinstr2)
2162		{
2163		case 0x00: size = arcompact_handle1e_03_00_dasm(DASM_PARAMS); break; // BGT_S
2164		case 0x01: size = arcompact_handle1e_03_01_dasm(DASM_PARAMS); break; // BGE_S
2165		case 0x02: size = arcompact_handle1e_03_02_dasm(DASM_PARAMS); break; // BLT_S
2166		case 0x03: size = arcompact_handle1e_03_03_dasm(DASM_PARAMS); break; // BLE_S
2167		case 0x04: size = arcompact_handle1e_03_04_dasm(DASM_PARAMS); break; // BHI_S
2168		case 0x05: size = arcompact_handle1e_03_05_dasm(DASM_PARAMS); break; // BHS_S
2169		case 0x06: size = arcompact_handle1e_03_06_dasm(DASM_PARAMS); break; // BLO_S
2170		case 0x07: size = arcompact_handle1e_03_07_dasm(DASM_PARAMS); break; // BLS_S
2171		}
2172		return size;
2173
2174		}
2175
2176		int arcompact_handle1e_03_00_dasm(DASM_OPS_16)  { print("BGT_S (%04x)",  op); return 2;}
2177		int arcompact_handle1e_03_01_dasm(DASM_OPS_16)  { print("BGE_S (%04x)",  op); return 2;}
2178		int arcompact_handle1e_03_02_dasm(DASM_OPS_16)  { print("BLT_S (%04x)",  op); return 2;}
2179		int arcompact_handle1e_03_03_dasm(DASM_OPS_16)  { print("BLE_S (%04x)",  op); return 2;}
2180		int arcompact_handle1e_03_04_dasm(DASM_OPS_16)  { print("BHI_S (%04x)",  op); return 2;}
2181		int arcompact_handle1e_03_05_dasm(DASM_OPS_16)  { print("BHS_S (%04x)",  op); return 2;}
2182		int arcompact_handle1e_03_06_dasm(DASM_OPS_16)  { print("BLO_S (%04x)",  op); return 2;}
2183		int arcompact_handle1e_03_07_dasm(DASM_OPS_16)  { print("BLS_S (%04x)",  op); return 2;}
2184
2185
2186
2187		int arcompact_handle1f_dasm(DASM_OPS_16)
2188		{
2189		print("BL_S (%04x)", op);
2190		return 2;
2191		}
2192
2193	25	CPU_DISASSEMBLE(arcompact)
2194	26	{
2195	27	int size = 2;

trunk/src/emu/cpu/arcompact/arcompactdasm_dispatch.c

r0	r242414
	1	/*********************************\
	2
	3	ARCompact disassembler
	4
	5	\*********************************/
	6
	7	#include "emu.h"
	8	#include <stdarg.h>
	9
	10	#include "arcompactdasm_dispatch.h"
	11	#include "arcompactdasm_ops.h"
	12
	13	int arcompact_handle00_dasm(DASM_OPS_32)
	14	{
	15	int size = 4;
	16	UINT8 subinstr = (op & 0x00010000) >> 16;
	17	op &= ~0x00010000;
	18
	19	switch (subinstr)
	20	{
	21	case 0x00: size = arcompact_handle00_00_dasm(DASM_PARAMS); break; // Branch Conditionally
	22	case 0x01: size = arcompact_handle00_01_dasm(DASM_PARAMS); break; // Branch Unconditionally Far
	23	}
	24
	25	return size;
	26	}
	27
	28	int arcompact_handle01_dasm(DASM_OPS_32)
	29	{
	30	int size = 4;
	31	UINT8 subinstr = (op & 0x00010000) >> 16;
	32	op &= ~0x00010000;
	33
	34	switch (subinstr)
	35	{
	36	case 0x00: size = arcompact_handle01_00_dasm(DASM_PARAMS); break; // Branh & Link
	37	case 0x01: size = arcompact_handle01_01_dasm(DASM_PARAMS); break; // Branch on Compare
	38	}
	39
	40	return size;
	41	}
	42
	43	int arcompact_handle01_00_dasm(DASM_OPS_32)
	44	{
	45	int size = 4;
	46	UINT8 subinstr2 = (op & 0x00020000) >> 17;
	47	op &= ~0x00020000;
	48
	49	switch (subinstr2)
	50	{
	51	case 0x00: size = arcompact_handle01_00_00dasm(DASM_PARAMS); break; // Branch and Link Conditionally
	52	case 0x01: size = arcompact_handle01_00_01dasm(DASM_PARAMS); break; // Branch and Link Unconditional Far
	53	}
	54
	55	return size;
	56	}
	57
	58	int arcompact_handle01_01_dasm(DASM_OPS_32)
	59	{
	60	int size = 4;
	61
	62	UINT8 subinstr2 = (op & 0x00000010) >> 4;
	63	op &= ~0x00000010;
	64
	65	switch (subinstr2)
	66	{
	67	case 0x00: size = arcompact_handle01_01_00_dasm(DASM_PARAMS); break; // Branch on Compare Register-Register
	68	case 0x01: size = arcompact_handle01_01_01_dasm(DASM_PARAMS); break; // Branch on Compare/Bit Test Register-Immediate
	69	}
	70
	71	return size;
	72	}
	73
	74	int arcompact_handle01_01_00_dasm(DASM_OPS_32)
	75	{
	76	int size = 4;
	77	UINT8 subinstr3 = (op & 0x0000000f) >> 0;
	78	op &= ~0x0000000f;
	79
	80	switch (subinstr3)
	81	{
	82	case 0x00: size = arcompact_handle01_01_00_00_dasm(DASM_PARAMS); break; // BREQ (reg-reg)
	83	case 0x01: size = arcompact_handle01_01_00_01_dasm(DASM_PARAMS); break; // BRNE (reg-reg)
	84	case 0x02: size = arcompact_handle01_01_00_02_dasm(DASM_PARAMS); break; // BRLT (reg-reg)
	85	case 0x03: size = arcompact_handle01_01_00_03_dasm(DASM_PARAMS); break; // BRGE (reg-reg)
	86	case 0x04: size = arcompact_handle01_01_00_04_dasm(DASM_PARAMS); break; // BRLO (reg-reg)
	87	case 0x05: size = arcompact_handle01_01_00_05_dasm(DASM_PARAMS); break; // BRHS (reg-reg)
	88	case 0x06: size = arcompact_handle01_01_00_06_dasm(DASM_PARAMS); break; // reserved
	89	case 0x07: size = arcompact_handle01_01_00_07_dasm(DASM_PARAMS); break; // reserved
	90	case 0x08: size = arcompact_handle01_01_00_08_dasm(DASM_PARAMS); break; // reserved
	91	case 0x09: size = arcompact_handle01_01_00_09_dasm(DASM_PARAMS); break; // reserved
	92	case 0x0a: size = arcompact_handle01_01_00_0a_dasm(DASM_PARAMS); break; // reserved
	93	case 0x0b: size = arcompact_handle01_01_00_0b_dasm(DASM_PARAMS); break; // reserved
	94	case 0x0c: size = arcompact_handle01_01_00_0c_dasm(DASM_PARAMS); break; // reserved
	95	case 0x0d: size = arcompact_handle01_01_00_0d_dasm(DASM_PARAMS); break; // reserved
	96	case 0x0e: size = arcompact_handle01_01_00_0e_dasm(DASM_PARAMS); break; // BBIT0 (reg-reg)
	97	case 0x0f: size = arcompact_handle01_01_00_0f_dasm(DASM_PARAMS); break; // BBIT1 (reg-reg)
	98	}
	99
	100	return size;
	101	}
	102
	103	int arcompact_handle01_01_01_dasm(DASM_OPS_32) //  Branch on Compare/Bit Test Register-Immediate
	104	{
	105	int size = 4;
	106	UINT8 subinstr3 = (op & 0x0000000f) >> 0;
	107	op &= ~0x0000000f;
	108
	109	switch (subinstr3)
	110	{
	111	case 0x00: size = arcompact_handle01_01_01_00_dasm(DASM_PARAMS); break; // BREQ (reg-imm)
	112	case 0x01: size = arcompact_handle01_01_01_01_dasm(DASM_PARAMS); break; // BRNE (reg-imm)
	113	case 0x02: size = arcompact_handle01_01_01_02_dasm(DASM_PARAMS); break; // BRLT (reg-imm)
	114	case 0x03: size = arcompact_handle01_01_01_03_dasm(DASM_PARAMS); break; // BRGE (reg-imm)
	115	case 0x04: size = arcompact_handle01_01_01_04_dasm(DASM_PARAMS); break; // BRLO (reg-imm)
	116	case 0x05: size = arcompact_handle01_01_01_05_dasm(DASM_PARAMS); break; // BRHS (reg-imm)
	117	case 0x06: size = arcompact_handle01_01_01_06_dasm(DASM_PARAMS); break; // reserved
	118	case 0x07: size = arcompact_handle01_01_01_07_dasm(DASM_PARAMS); break; // reserved
	119	case 0x08: size = arcompact_handle01_01_01_08_dasm(DASM_PARAMS); break; // reserved
	120	case 0x09: size = arcompact_handle01_01_01_09_dasm(DASM_PARAMS); break; // reserved
	121	case 0x0a: size = arcompact_handle01_01_01_0a_dasm(DASM_PARAMS); break; // reserved
	122	case 0x0b: size = arcompact_handle01_01_01_0b_dasm(DASM_PARAMS); break; // reserved
	123	case 0x0c: size = arcompact_handle01_01_01_0c_dasm(DASM_PARAMS); break; // reserved
	124	case 0x0d: size = arcompact_handle01_01_01_0d_dasm(DASM_PARAMS); break; // reserved
	125	case 0x0e: size = arcompact_handle01_01_01_0e_dasm(DASM_PARAMS); break; // BBIT0 (reg-imm)
	126	case 0x0f: size = arcompact_handle01_01_01_0f_dasm(DASM_PARAMS); break; // BBIT1 (reg-imm)
	127	}
	128
	129	return size;
	130	}
	131
	132	int arcompact_handle04_dasm(DASM_OPS_32)
	133	{
	134	int size = 4;
	135	// General Operations
	136
	137	// bitpos
	138	// 11111 111 11 111111 0 000 000000 0 00000
	139	// fedcb a98 76 543210 f edc ba9876 5 43210
	140	//
	141	// 00100 bbb 00 iiiiii F BBB CCCCCC A AAAAA   General Operations *UN*Conditional Register to Register
	142	// 00100 bbb 01 iiiiii F BBB UUUUUU A AAAAA   General Operations *UN*Conditional Register (Unsigned 6-bit IMM)
	143	// 00100 bbb 10 iiiiii F BBB ssssss S SSSSS   General Operations *UN*Conditional Register (Signed 12-bit IMM)
	144
	145	// 00100 bbb 11 iiiiii F BBB CCCCCC 0 QQQQQ   General Operations Conditional Register
	146	// 00100 bbb 11 iiiiii F BBB UUUUUU 1 QQQQQ   General Operations Conditional Register (Unsigned 6-bit IMM)
	147	UINT8 subinstr = (op & 0x003f0000) >> 16;
	148	op &= ~0x003f0000;
	149
	150	switch (subinstr)
	151	{
	152	case 0x00: size = arcompact_handle04_00_dasm(DASM_PARAMS); break; // ADD
	153	case 0x01: size = arcompact_handle04_01_dasm(DASM_PARAMS); break; // ADC
	154	case 0x02: size = arcompact_handle04_02_dasm(DASM_PARAMS); break; // SUB
	155	case 0x03: size = arcompact_handle04_03_dasm(DASM_PARAMS); break; // SBC
	156	case 0x04: size = arcompact_handle04_04_dasm(DASM_PARAMS); break; // AND
	157	case 0x05: size = arcompact_handle04_05_dasm(DASM_PARAMS); break; // OR
	158	case 0x06: size = arcompact_handle04_06_dasm(DASM_PARAMS); break; // BIC
	159	case 0x07: size = arcompact_handle04_07_dasm(DASM_PARAMS); break; // XOR
	160	case 0x08: size = arcompact_handle04_08_dasm(DASM_PARAMS); break; // MAX
	161	case 0x09: size = arcompact_handle04_09_dasm(DASM_PARAMS); break; // MIN
	162	case 0x0a: size = arcompact_handle04_0a_dasm(DASM_PARAMS); break; // MOV
	163	case 0x0b: size = arcompact_handle04_0b_dasm(DASM_PARAMS); break; // TST
	164	case 0x0c: size = arcompact_handle04_0c_dasm(DASM_PARAMS); break; // CMP
	165	case 0x0d: size = arcompact_handle04_0d_dasm(DASM_PARAMS); break; // RCMP
	166	case 0x0e: size = arcompact_handle04_0e_dasm(DASM_PARAMS); break; // RSUB
	167	case 0x0f: size = arcompact_handle04_0f_dasm(DASM_PARAMS); break; // BSET
	168	case 0x10: size = arcompact_handle04_10_dasm(DASM_PARAMS); break; // BCLR
	169	case 0x11: size = arcompact_handle04_11_dasm(DASM_PARAMS); break; // BTST
	170	case 0x12: size = arcompact_handle04_12_dasm(DASM_PARAMS); break; // BXOR
	171	case 0x13: size = arcompact_handle04_13_dasm(DASM_PARAMS); break; // BMSK
	172	case 0x14: size = arcompact_handle04_14_dasm(DASM_PARAMS); break; // ADD1
	173	case 0x15: size = arcompact_handle04_15_dasm(DASM_PARAMS); break; // ADD2
	174	case 0x16: size = arcompact_handle04_16_dasm(DASM_PARAMS); break; // ADD3
	175	case 0x17: size = arcompact_handle04_17_dasm(DASM_PARAMS); break; // SUB1
	176	case 0x18: size = arcompact_handle04_18_dasm(DASM_PARAMS); break; // SUB2
	177	case 0x19: size = arcompact_handle04_19_dasm(DASM_PARAMS); break; // SUB3
	178	case 0x1a: size = arcompact_handle04_1a_dasm(DASM_PARAMS); break; // MPY *
	179	case 0x1b: size = arcompact_handle04_1b_dasm(DASM_PARAMS); break; // MPYH *
	180	case 0x1c: size = arcompact_handle04_1c_dasm(DASM_PARAMS); break; // MPYHU *
	181	case 0x1d: size = arcompact_handle04_1d_dasm(DASM_PARAMS); break; // MPYU *
	182	case 0x1e: size = arcompact_handle04_1e_dasm(DASM_PARAMS); break; // illegal
	183	case 0x1f: size = arcompact_handle04_1f_dasm(DASM_PARAMS); break; // illegal
	184	case 0x20: size = arcompact_handle04_20_dasm(DASM_PARAMS); break; // Jcc
	185	case 0x21: size = arcompact_handle04_21_dasm(DASM_PARAMS); break; // Jcc.D
	186	case 0x22: size = arcompact_handle04_22_dasm(DASM_PARAMS); break; // JLcc
	187	case 0x23: size = arcompact_handle04_23_dasm(DASM_PARAMS); break; // JLcc.D
	188	case 0x24: size = arcompact_handle04_24_dasm(DASM_PARAMS); break; // illegal
	189	case 0x25: size = arcompact_handle04_25_dasm(DASM_PARAMS); break; // illegal
	190	case 0x26: size = arcompact_handle04_26_dasm(DASM_PARAMS); break; // illegal
	191	case 0x27: size = arcompact_handle04_27_dasm(DASM_PARAMS); break; // illegal
	192	case 0x28: size = arcompact_handle04_28_dasm(DASM_PARAMS); break; // LPcc
	193	case 0x29: size = arcompact_handle04_29_dasm(DASM_PARAMS); break; // FLAG
	194	case 0x2a: size = arcompact_handle04_2a_dasm(DASM_PARAMS); break; // LR
	195	case 0x2b: size = arcompact_handle04_2b_dasm(DASM_PARAMS); break; // SR
	196	case 0x2c: size = arcompact_handle04_2c_dasm(DASM_PARAMS); break; // illegal
	197	case 0x2d: size = arcompact_handle04_2d_dasm(DASM_PARAMS); break; // illegal
	198	case 0x2e: size = arcompact_handle04_2e_dasm(DASM_PARAMS); break; // illegal
	199	case 0x2f: size = arcompact_handle04_2f_dasm(DASM_PARAMS); break; // Sub Opcode
	200	case 0x30: size = arcompact_handle04_30_dasm(DASM_PARAMS); break; // LD r-r
	201	case 0x31: size = arcompact_handle04_31_dasm(DASM_PARAMS); break; // LD r-r
	202	case 0x32: size = arcompact_handle04_32_dasm(DASM_PARAMS); break; // LD r-r
	203	case 0x33: size = arcompact_handle04_33_dasm(DASM_PARAMS); break; // LD r-r
	204	case 0x34: size = arcompact_handle04_34_dasm(DASM_PARAMS); break; // LD r-r
	205	case 0x35: size = arcompact_handle04_35_dasm(DASM_PARAMS); break; // LD r-r
	206	case 0x36: size = arcompact_handle04_36_dasm(DASM_PARAMS); break; // LD r-r
	207	case 0x37: size = arcompact_handle04_37_dasm(DASM_PARAMS); break; // LD r-r
	208	case 0x38: size = arcompact_handle04_38_dasm(DASM_PARAMS); break; // illegal
	209	case 0x39: size = arcompact_handle04_39_dasm(DASM_PARAMS); break; // illegal
	210	case 0x3a: size = arcompact_handle04_3a_dasm(DASM_PARAMS); break; // illegal
	211	case 0x3b: size = arcompact_handle04_3b_dasm(DASM_PARAMS); break; // illegal
	212	case 0x3c: size = arcompact_handle04_3c_dasm(DASM_PARAMS); break; // illegal
	213	case 0x3d: size = arcompact_handle04_3d_dasm(DASM_PARAMS); break; // illegal
	214	case 0x3e: size = arcompact_handle04_3e_dasm(DASM_PARAMS); break; // illegal
	215	case 0x3f: size = arcompact_handle04_3f_dasm(DASM_PARAMS); break; // illegal
	216	}
	217
	218	return size;
	219	}
	220
	221	int arcompact_handle04_2f_dasm(DASM_OPS_32)
	222	{
	223	int size = 4;
	224	UINT8 subinstr2 = (op & 0x0000003f) >> 0;
	225	op &= ~0x0000003f;
	226
	227	switch (subinstr2)
	228	{
	229	case 0x00: size = arcompact_handle04_2f_00_dasm(DASM_PARAMS); break; // ASL
	230	case 0x01: size = arcompact_handle04_2f_01_dasm(DASM_PARAMS); break; // ASR
	231	case 0x02: size = arcompact_handle04_2f_02_dasm(DASM_PARAMS); break; // LSR
	232	case 0x03: size = arcompact_handle04_2f_03_dasm(DASM_PARAMS); break; // ROR
	233	case 0x04: size = arcompact_handle04_2f_04_dasm(DASM_PARAMS); break; // RCC
	234	case 0x05: size = arcompact_handle04_2f_05_dasm(DASM_PARAMS); break; // SEXB
	235	case 0x06: size = arcompact_handle04_2f_06_dasm(DASM_PARAMS); break; // SEXW
	236	case 0x07: size = arcompact_handle04_2f_07_dasm(DASM_PARAMS); break; // EXTB
	237	case 0x08: size = arcompact_handle04_2f_08_dasm(DASM_PARAMS); break; // EXTW
	238	case 0x09: size = arcompact_handle04_2f_09_dasm(DASM_PARAMS); break; // ABS
	239	case 0x0a: size = arcompact_handle04_2f_0a_dasm(DASM_PARAMS); break; // NOT
	240	case 0x0b: size = arcompact_handle04_2f_0b_dasm(DASM_PARAMS); break; // RLC
	241	case 0x0c: size = arcompact_handle04_2f_0c_dasm(DASM_PARAMS); break; // EX
	242	case 0x0d: size = arcompact_handle04_2f_0d_dasm(DASM_PARAMS); break; // illegal
	243	case 0x0e: size = arcompact_handle04_2f_0e_dasm(DASM_PARAMS); break; // illegal
	244	case 0x0f: size = arcompact_handle04_2f_0f_dasm(DASM_PARAMS); break; // illegal
	245	case 0x10: size = arcompact_handle04_2f_10_dasm(DASM_PARAMS); break; // illegal
	246	case 0x11: size = arcompact_handle04_2f_11_dasm(DASM_PARAMS); break; // illegal
	247	case 0x12: size = arcompact_handle04_2f_12_dasm(DASM_PARAMS); break; // illegal
	248	case 0x13: size = arcompact_handle04_2f_13_dasm(DASM_PARAMS); break; // illegal
	249	case 0x14: size = arcompact_handle04_2f_14_dasm(DASM_PARAMS); break; // illegal
	250	case 0x15: size = arcompact_handle04_2f_15_dasm(DASM_PARAMS); break; // illegal
	251	case 0x16: size = arcompact_handle04_2f_16_dasm(DASM_PARAMS); break; // illegal
	252	case 0x17: size = arcompact_handle04_2f_17_dasm(DASM_PARAMS); break; // illegal
	253	case 0x18: size = arcompact_handle04_2f_18_dasm(DASM_PARAMS); break; // illegal
	254	case 0x19: size = arcompact_handle04_2f_19_dasm(DASM_PARAMS); break; // illegal
	255	case 0x1a: size = arcompact_handle04_2f_1a_dasm(DASM_PARAMS); break; // illegal
	256	case 0x1b: size = arcompact_handle04_2f_1b_dasm(DASM_PARAMS); break; // illegal
	257	case 0x1c: size = arcompact_handle04_2f_1c_dasm(DASM_PARAMS); break; // illegal
	258	case 0x1d: size = arcompact_handle04_2f_1d_dasm(DASM_PARAMS); break; // illegal
	259	case 0x1e: size = arcompact_handle04_2f_1e_dasm(DASM_PARAMS); break; // illegal
	260	case 0x1f: size = arcompact_handle04_2f_1f_dasm(DASM_PARAMS); break; // illegal
	261	case 0x20: size = arcompact_handle04_2f_20_dasm(DASM_PARAMS); break; // illegal
	262	case 0x21: size = arcompact_handle04_2f_21_dasm(DASM_PARAMS); break; // illegal
	263	case 0x22: size = arcompact_handle04_2f_22_dasm(DASM_PARAMS); break; // illegal
	264	case 0x23: size = arcompact_handle04_2f_23_dasm(DASM_PARAMS); break; // illegal
	265	case 0x24: size = arcompact_handle04_2f_24_dasm(DASM_PARAMS); break; // illegal
	266	case 0x25: size = arcompact_handle04_2f_25_dasm(DASM_PARAMS); break; // illegal
	267	case 0x26: size = arcompact_handle04_2f_26_dasm(DASM_PARAMS); break; // illegal
	268	case 0x27: size = arcompact_handle04_2f_27_dasm(DASM_PARAMS); break; // illegal
	269	case 0x28: size = arcompact_handle04_2f_28_dasm(DASM_PARAMS); break; // illegal
	270	case 0x29: size = arcompact_handle04_2f_29_dasm(DASM_PARAMS); break; // illegal
	271	case 0x2a: size = arcompact_handle04_2f_2a_dasm(DASM_PARAMS); break; // illegal
	272	case 0x2b: size = arcompact_handle04_2f_2b_dasm(DASM_PARAMS); break; // illegal
	273	case 0x2c: size = arcompact_handle04_2f_2c_dasm(DASM_PARAMS); break; // illegal
	274	case 0x2d: size = arcompact_handle04_2f_2d_dasm(DASM_PARAMS); break; // illegal
	275	case 0x2e: size = arcompact_handle04_2f_2e_dasm(DASM_PARAMS); break; // illegal
	276	case 0x2f: size = arcompact_handle04_2f_2f_dasm(DASM_PARAMS); break; // illegal
	277	case 0x30: size = arcompact_handle04_2f_30_dasm(DASM_PARAMS); break; // illegal
	278	case 0x31: size = arcompact_handle04_2f_31_dasm(DASM_PARAMS); break; // illegal
	279	case 0x32: size = arcompact_handle04_2f_32_dasm(DASM_PARAMS); break; // illegal
	280	case 0x33: size = arcompact_handle04_2f_33_dasm(DASM_PARAMS); break; // illegal
	281	case 0x34: size = arcompact_handle04_2f_34_dasm(DASM_PARAMS); break; // illegal
	282	case 0x35: size = arcompact_handle04_2f_35_dasm(DASM_PARAMS); break; // illegal
	283	case 0x36: size = arcompact_handle04_2f_36_dasm(DASM_PARAMS); break; // illegal
	284	case 0x37: size = arcompact_handle04_2f_37_dasm(DASM_PARAMS); break; // illegal
	285	case 0x38: size = arcompact_handle04_2f_38_dasm(DASM_PARAMS); break; // illegal
	286	case 0x39: size = arcompact_handle04_2f_39_dasm(DASM_PARAMS); break; // illegal
	287	case 0x3a: size = arcompact_handle04_2f_3a_dasm(DASM_PARAMS); break; // illegal
	288	case 0x3b: size = arcompact_handle04_2f_3b_dasm(DASM_PARAMS); break; // illegal
	289	case 0x3c: size = arcompact_handle04_2f_3c_dasm(DASM_PARAMS); break; // illegal
	290	case 0x3d: size = arcompact_handle04_2f_3d_dasm(DASM_PARAMS); break; // illegal
	291	case 0x3e: size = arcompact_handle04_2f_3e_dasm(DASM_PARAMS); break; // illegal
	292	case 0x3f: size = arcompact_handle04_2f_3f_dasm(DASM_PARAMS); break; // ZOPs (Zero Operand Opcodes)
	293	}
	294
	295	return size;
	296	}
	297
	298	int arcompact_handle04_2f_3f_dasm(DASM_OPS_32)
	299	{
	300	int size = 4;
	301	UINT8 subinstr3 = (op & 0x07000000) >> 24;
	302	subinstr3 |= ((op & 0x00007000) >> 12) << 3;
	303
	304	op &= ~0x07007000;
	305
	306	switch (subinstr3)
	307	{
	308	case 0x00: size = arcompact_handle04_2f_3f_00_dasm(DASM_PARAMS); break; // illegal
	309	case 0x01: size = arcompact_handle04_2f_3f_01_dasm(DASM_PARAMS); break; // SLEEP
	310	case 0x02: size = arcompact_handle04_2f_3f_02_dasm(DASM_PARAMS); break; // SWI / TRAP9
	311	case 0x03: size = arcompact_handle04_2f_3f_03_dasm(DASM_PARAMS); break; // SYNC
	312	case 0x04: size = arcompact_handle04_2f_3f_04_dasm(DASM_PARAMS); break; // RTIE
	313	case 0x05: size = arcompact_handle04_2f_3f_05_dasm(DASM_PARAMS); break; // BRK
	314	case 0x06: size = arcompact_handle04_2f_3f_06_dasm(DASM_PARAMS); break; // illegal
	315	case 0x07: size = arcompact_handle04_2f_3f_07_dasm(DASM_PARAMS); break; // illegal
	316	case 0x08: size = arcompact_handle04_2f_3f_08_dasm(DASM_PARAMS); break; // illegal
	317	case 0x09: size = arcompact_handle04_2f_3f_09_dasm(DASM_PARAMS); break; // illegal
	318	case 0x0a: size = arcompact_handle04_2f_3f_0a_dasm(DASM_PARAMS); break; // illegal
	319	case 0x0b: size = arcompact_handle04_2f_3f_0b_dasm(DASM_PARAMS); break; // illegal
	320	case 0x0c: size = arcompact_handle04_2f_3f_0c_dasm(DASM_PARAMS); break; // illegal
	321	case 0x0d: size = arcompact_handle04_2f_3f_0d_dasm(DASM_PARAMS); break; // illegal
	322	case 0x0e: size = arcompact_handle04_2f_3f_0e_dasm(DASM_PARAMS); break; // illegal
	323	case 0x0f: size = arcompact_handle04_2f_3f_0f_dasm(DASM_PARAMS); break; // illegal
	324	case 0x10: size = arcompact_handle04_2f_3f_10_dasm(DASM_PARAMS); break; // illegal
	325	case 0x11: size = arcompact_handle04_2f_3f_11_dasm(DASM_PARAMS); break; // illegal
	326	case 0x12: size = arcompact_handle04_2f_3f_12_dasm(DASM_PARAMS); break; // illegal
	327	case 0x13: size = arcompact_handle04_2f_3f_13_dasm(DASM_PARAMS); break; // illegal
	328	case 0x14: size = arcompact_handle04_2f_3f_14_dasm(DASM_PARAMS); break; // illegal
	329	case 0x15: size = arcompact_handle04_2f_3f_15_dasm(DASM_PARAMS); break; // illegal
	330	case 0x16: size = arcompact_handle04_2f_3f_16_dasm(DASM_PARAMS); break; // illegal
	331	case 0x17: size = arcompact_handle04_2f_3f_17_dasm(DASM_PARAMS); break; // illegal
	332	case 0x18: size = arcompact_handle04_2f_3f_18_dasm(DASM_PARAMS); break; // illegal
	333	case 0x19: size = arcompact_handle04_2f_3f_19_dasm(DASM_PARAMS); break; // illegal
	334	case 0x1a: size = arcompact_handle04_2f_3f_1a_dasm(DASM_PARAMS); break; // illegal
	335	case 0x1b: size = arcompact_handle04_2f_3f_1b_dasm(DASM_PARAMS); break; // illegal
	336	case 0x1c: size = arcompact_handle04_2f_3f_1c_dasm(DASM_PARAMS); break; // illegal
	337	case 0x1d: size = arcompact_handle04_2f_3f_1d_dasm(DASM_PARAMS); break; // illegal
	338	case 0x1e: size = arcompact_handle04_2f_3f_1e_dasm(DASM_PARAMS); break; // illegal
	339	case 0x1f: size = arcompact_handle04_2f_3f_1f_dasm(DASM_PARAMS); break; // illegal
	340	case 0x20: size = arcompact_handle04_2f_3f_20_dasm(DASM_PARAMS); break; // illegal
	341	case 0x21: size = arcompact_handle04_2f_3f_21_dasm(DASM_PARAMS); break; // illegal
	342	case 0x22: size = arcompact_handle04_2f_3f_22_dasm(DASM_PARAMS); break; // illegal
	343	case 0x23: size = arcompact_handle04_2f_3f_23_dasm(DASM_PARAMS); break; // illegal
	344	case 0x24: size = arcompact_handle04_2f_3f_24_dasm(DASM_PARAMS); break; // illegal
	345	case 0x25: size = arcompact_handle04_2f_3f_25_dasm(DASM_PARAMS); break; // illegal
	346	case 0x26: size = arcompact_handle04_2f_3f_26_dasm(DASM_PARAMS); break; // illegal
	347	case 0x27: size = arcompact_handle04_2f_3f_27_dasm(DASM_PARAMS); break; // illegal
	348	case 0x28: size = arcompact_handle04_2f_3f_28_dasm(DASM_PARAMS); break; // illegal
	349	case 0x29: size = arcompact_handle04_2f_3f_29_dasm(DASM_PARAMS); break; // illegal
	350	case 0x2a: size = arcompact_handle04_2f_3f_2a_dasm(DASM_PARAMS); break; // illegal
	351	case 0x2b: size = arcompact_handle04_2f_3f_2b_dasm(DASM_PARAMS); break; // illegal
	352	case 0x2c: size = arcompact_handle04_2f_3f_2c_dasm(DASM_PARAMS); break; // illegal
	353	case 0x2d: size = arcompact_handle04_2f_3f_2d_dasm(DASM_PARAMS); break; // illegal
	354	case 0x2e: size = arcompact_handle04_2f_3f_2e_dasm(DASM_PARAMS); break; // illegal
	355	case 0x2f: size = arcompact_handle04_2f_3f_2f_dasm(DASM_PARAMS); break; // illegal
	356	case 0x30: size = arcompact_handle04_2f_3f_30_dasm(DASM_PARAMS); break; // illegal
	357	case 0x31: size = arcompact_handle04_2f_3f_31_dasm(DASM_PARAMS); break; // illegal
	358	case 0x32: size = arcompact_handle04_2f_3f_32_dasm(DASM_PARAMS); break; // illegal
	359	case 0x33: size = arcompact_handle04_2f_3f_33_dasm(DASM_PARAMS); break; // illegal
	360	case 0x34: size = arcompact_handle04_2f_3f_34_dasm(DASM_PARAMS); break; // illegal
	361	case 0x35: size = arcompact_handle04_2f_3f_35_dasm(DASM_PARAMS); break; // illegal
	362	case 0x36: size = arcompact_handle04_2f_3f_36_dasm(DASM_PARAMS); break; // illegal
	363	case 0x37: size = arcompact_handle04_2f_3f_37_dasm(DASM_PARAMS); break; // illegal
	364	case 0x38: size = arcompact_handle04_2f_3f_38_dasm(DASM_PARAMS); break; // illegal
	365	case 0x39: size = arcompact_handle04_2f_3f_39_dasm(DASM_PARAMS); break; // illegal
	366	case 0x3a: size = arcompact_handle04_2f_3f_3a_dasm(DASM_PARAMS); break; // illegal
	367	case 0x3b: size = arcompact_handle04_2f_3f_3b_dasm(DASM_PARAMS); break; // illegal
	368	case 0x3c: size = arcompact_handle04_2f_3f_3c_dasm(DASM_PARAMS); break; // illegal
	369	case 0x3d: size = arcompact_handle04_2f_3f_3d_dasm(DASM_PARAMS); break; // illegal
	370	case 0x3e: size = arcompact_handle04_2f_3f_3e_dasm(DASM_PARAMS); break; // illegal
	371	case 0x3f: size = arcompact_handle04_2f_3f_3f_dasm(DASM_PARAMS); break; // illegal
	372	}
	373
	374	return size;
	375	}
	376
	377	// this is an Extension ALU group, maybe optional on some CPUs?
	378	int arcompact_handle05_dasm(DASM_OPS_32)
	379	{
	380	int size = 4;
	381	UINT8 subinstr = (op & 0x003f0000) >> 16;
	382	op &= ~0x003f0000;
	383
	384	switch (subinstr)
	385	{
	386	case 0x00: size = arcompact_handle05_00_dasm(DASM_PARAMS); break; // ASL
	387	case 0x01: size = arcompact_handle05_01_dasm(DASM_PARAMS); break; // LSR
	388	case 0x02: size = arcompact_handle05_02_dasm(DASM_PARAMS); break; // ASR
	389	case 0x03: size = arcompact_handle05_03_dasm(DASM_PARAMS); break; // ROR
	390	case 0x04: size = arcompact_handle05_04_dasm(DASM_PARAMS); break; // MUL64
	391	case 0x05: size = arcompact_handle05_05_dasm(DASM_PARAMS); break; // MULU64
	392	case 0x06: size = arcompact_handle05_06_dasm(DASM_PARAMS); break; // ADDS
	393	case 0x07: size = arcompact_handle05_07_dasm(DASM_PARAMS); break; // SUBS
	394	case 0x08: size = arcompact_handle05_08_dasm(DASM_PARAMS); break; // DIVAW
	395	case 0x09: size = arcompact_handle05_09_dasm(DASM_PARAMS); break; // illegal
	396	case 0x0a: size = arcompact_handle05_0a_dasm(DASM_PARAMS); break; // ASLS
	397	case 0x0b: size = arcompact_handle05_0b_dasm(DASM_PARAMS); break; // ASRS
	398	case 0x0c: size = arcompact_handle05_0c_dasm(DASM_PARAMS); break; // illegal
	399	case 0x0d: size = arcompact_handle05_0d_dasm(DASM_PARAMS); break; // illegal
	400	case 0x0e: size = arcompact_handle05_0e_dasm(DASM_PARAMS); break; // illegal
	401	case 0x0f: size = arcompact_handle05_0f_dasm(DASM_PARAMS); break; // illegal
	402	case 0x10: size = arcompact_handle05_10_dasm(DASM_PARAMS); break; // illegal
	403	case 0x11: size = arcompact_handle05_11_dasm(DASM_PARAMS); break; // illegal
	404	case 0x12: size = arcompact_handle05_12_dasm(DASM_PARAMS); break; // illegal
	405	case 0x13: size = arcompact_handle05_13_dasm(DASM_PARAMS); break; // illegal
	406	case 0x14: size = arcompact_handle05_14_dasm(DASM_PARAMS); break; // illegal
	407	case 0x15: size = arcompact_handle05_15_dasm(DASM_PARAMS); break; // illegal
	408	case 0x16: size = arcompact_handle05_16_dasm(DASM_PARAMS); break; // illegal
	409	case 0x17: size = arcompact_handle05_17_dasm(DASM_PARAMS); break; // illegal
	410	case 0x18: size = arcompact_handle05_18_dasm(DASM_PARAMS); break; // illegal
	411	case 0x19: size = arcompact_handle05_19_dasm(DASM_PARAMS); break; // illegal
	412	case 0x1a: size = arcompact_handle05_1a_dasm(DASM_PARAMS); break; // illegal
	413	case 0x1b: size = arcompact_handle05_1b_dasm(DASM_PARAMS); break; // illegal
	414	case 0x1c: size = arcompact_handle05_1c_dasm(DASM_PARAMS); break; // illegal
	415	case 0x1d: size = arcompact_handle05_1d_dasm(DASM_PARAMS); break; // illegal
	416	case 0x1e: size = arcompact_handle05_1e_dasm(DASM_PARAMS); break; // illegal
	417	case 0x1f: size = arcompact_handle05_1f_dasm(DASM_PARAMS); break; // illegal
	418	case 0x20: size = arcompact_handle05_20_dasm(DASM_PARAMS); break; // illegal
	419	case 0x21: size = arcompact_handle05_21_dasm(DASM_PARAMS); break; // illegal
	420	case 0x22: size = arcompact_handle05_22_dasm(DASM_PARAMS); break; // illegal
	421	case 0x23: size = arcompact_handle05_23_dasm(DASM_PARAMS); break; // illegal
	422	case 0x24: size = arcompact_handle05_24_dasm(DASM_PARAMS); break; // illegal
	423	case 0x25: size = arcompact_handle05_25_dasm(DASM_PARAMS); break; // illegal
	424	case 0x26: size = arcompact_handle05_26_dasm(DASM_PARAMS); break; // illegal
	425	case 0x27: size = arcompact_handle05_27_dasm(DASM_PARAMS); break; // illegal
	426	case 0x28: size = arcompact_handle05_28_dasm(DASM_PARAMS); break; // ADDSDW
	427	case 0x29: size = arcompact_handle05_29_dasm(DASM_PARAMS); break; // SUBSDW
	428	case 0x2a: size = arcompact_handle05_2a_dasm(DASM_PARAMS); break; // illegal
	429	case 0x2b: size = arcompact_handle05_2b_dasm(DASM_PARAMS); break; // illegal
	430	case 0x2c: size = arcompact_handle05_2c_dasm(DASM_PARAMS); break; // illegal
	431	case 0x2d: size = arcompact_handle05_2d_dasm(DASM_PARAMS); break; // illegal
	432	case 0x2e: size = arcompact_handle05_2e_dasm(DASM_PARAMS); break; // illegal
	433	case 0x2f: size = arcompact_handle05_2f_dasm(DASM_PARAMS); break; // SOPs
	434	case 0x30: size = arcompact_handle05_30_dasm(DASM_PARAMS); break; // illegal
	435	case 0x31: size = arcompact_handle05_31_dasm(DASM_PARAMS); break; // illegal
	436	case 0x32: size = arcompact_handle05_32_dasm(DASM_PARAMS); break; // illegal
	437	case 0x33: size = arcompact_handle05_33_dasm(DASM_PARAMS); break; // illegal
	438	case 0x34: size = arcompact_handle05_34_dasm(DASM_PARAMS); break; // illegal
	439	case 0x35: size = arcompact_handle05_35_dasm(DASM_PARAMS); break; // illegal
	440	case 0x36: size = arcompact_handle05_36_dasm(DASM_PARAMS); break; // illegal
	441	case 0x37: size = arcompact_handle05_37_dasm(DASM_PARAMS); break; // illegal
	442	case 0x38: size = arcompact_handle05_38_dasm(DASM_PARAMS); break; // illegal
	443	case 0x39: size = arcompact_handle05_39_dasm(DASM_PARAMS); break; // illegal
	444	case 0x3a: size = arcompact_handle05_3a_dasm(DASM_PARAMS); break; // illegal
	445	case 0x3b: size = arcompact_handle05_3b_dasm(DASM_PARAMS); break; // illegal
	446	case 0x3c: size = arcompact_handle05_3c_dasm(DASM_PARAMS); break; // illegal
	447	case 0x3d: size = arcompact_handle05_3d_dasm(DASM_PARAMS); break; // illegal
	448	case 0x3e: size = arcompact_handle05_3e_dasm(DASM_PARAMS); break; // illegal
	449	case 0x3f: size = arcompact_handle05_3f_dasm(DASM_PARAMS); break; // illegal
	450	}
	451
	452	return size;
	453	}
	454
	455	int arcompact_handle0c_dasm(DASM_OPS_16)
	456	{
	457	int size = 2;
	458	UINT8 subinstr = (op & 0x0018) >> 3;
	459	op &= ~0x0018;
	460
	461	switch (subinstr)
	462	{
	463	case 0x00: size = arcompact_handle0c_00_dasm(DASM_PARAMS); break; // LD_S
	464	case 0x01: size = arcompact_handle0c_01_dasm(DASM_PARAMS); break; // LDB_S
	465	case 0x02: size = arcompact_handle0c_02_dasm(DASM_PARAMS); break; // LDW_S
	466	case 0x03: size = arcompact_handle0c_03_dasm(DASM_PARAMS); break; // ADD_S
	467	}
	468	return size;
	469	}
	470
	471	int arcompact_handle0d_dasm(DASM_OPS_16)
	472	{
	473	int size = 2;
	474	UINT8 subinstr = (op & 0x0018) >> 3;
	475	op &= ~0x0018;
	476
	477	switch (subinstr)
	478	{
	479	case 0x00: size = arcompact_handle0d_00_dasm(DASM_PARAMS); break; // ADD_S
	480	case 0x01: size = arcompact_handle0d_01_dasm(DASM_PARAMS); break; // SUB_S
	481	case 0x02: size = arcompact_handle0d_02_dasm(DASM_PARAMS); break; // ASL_S
	482	case 0x03: size = arcompact_handle0d_03_dasm(DASM_PARAMS); break; // ASR_S
	483	}
	484	return size;
	485	}
	486
	487	int arcompact_handle0e_dasm(DASM_OPS_16)
	488	{
	489	int size = 2;
	490	UINT8 subinstr = (op & 0x0018) >> 3;
	491	op &= ~0x0018;
	492
	493	switch (subinstr)
	494	{
	495	case 0x00: size = arcompact_handle0e_00_dasm(DASM_PARAMS); break; // ADD_S
	496	case 0x01: size = arcompact_handle0e_01_dasm(DASM_PARAMS); break; // MOV_S
	497	case 0x02: size = arcompact_handle0e_02_dasm(DASM_PARAMS); break; // CMP_S
	498	case 0x03: size = arcompact_handle0e_03_dasm(DASM_PARAMS); break; // MOV_S
	499	}
	500	return size;
	501	}
	502
	503	int arcompact_handle0f_dasm(DASM_OPS_16)
	504	{
	505	int size = 2;
	506	// General Register Instructions (16-bit)
	507	// 01111 bbb ccc iiiii
	508	UINT8 subinstr = (op & 0x01f) >> 0;
	509	op &= ~0x001f;
	510
	511	switch (subinstr)
	512	{
	513	case 0x00: size = arcompact_handle0f_00_dasm(DASM_PARAMS); break; // SOPs
	514	case 0x01: size = arcompact_handle0f_01_dasm(DASM_PARAMS); break; // 0x01 <illegal>
	515	case 0x02: size = arcompact_handle0f_02_dasm(DASM_PARAMS); break; // SUB_S
	516	case 0x03: size = arcompact_handle0f_03_dasm(DASM_PARAMS); break; // 0x03 <illegal>
	517	case 0x04: size = arcompact_handle0f_04_dasm(DASM_PARAMS); break; // AND_S
	518	case 0x05: size = arcompact_handle0f_05_dasm(DASM_PARAMS); break; // OR_S
	519	case 0x06: size = arcompact_handle0f_06_dasm(DASM_PARAMS); break; // BIC_S
	520	case 0x07: size = arcompact_handle0f_07_dasm(DASM_PARAMS); break; // XOR_S
	521	case 0x08: size = arcompact_handle0f_08_dasm(DASM_PARAMS); break; // 0x08 <illegal>
	522	case 0x09: size = arcompact_handle0f_09_dasm(DASM_PARAMS); break; // 0x09 <illegal>
	523	case 0x0a: size = arcompact_handle0f_0a_dasm(DASM_PARAMS); break; // 0x0a <illegal>
	524	case 0x0b: size = arcompact_handle0f_0b_dasm(DASM_PARAMS); break; // TST_S
	525	case 0x0c: size = arcompact_handle0f_0c_dasm(DASM_PARAMS); break; // MUL64_S
	526	case 0x0d: size = arcompact_handle0f_0d_dasm(DASM_PARAMS); break; // SEXB_S
	527	case 0x0e: size = arcompact_handle0f_0e_dasm(DASM_PARAMS); break; // SEXW_S
	528	case 0x0f: size = arcompact_handle0f_0f_dasm(DASM_PARAMS); break; // EXTB_S
	529	case 0x10: size = arcompact_handle0f_10_dasm(DASM_PARAMS); break; // EXTW_S
	530	case 0x11: size = arcompact_handle0f_11_dasm(DASM_PARAMS); break; // ABS_S
	531	case 0x12: size = arcompact_handle0f_12_dasm(DASM_PARAMS); break; // NOT_S
	532	case 0x13: size = arcompact_handle0f_13_dasm(DASM_PARAMS); break; // NEG_S
	533	case 0x14: size = arcompact_handle0f_14_dasm(DASM_PARAMS); break; // ADD1_S
	534	case 0x15: size = arcompact_handle0f_15_dasm(DASM_PARAMS); break; // ADD2_S
	535	case 0x16: size = arcompact_handle0f_16_dasm(DASM_PARAMS); break; // ADD3_S
	536	case 0x17: size = arcompact_handle0f_17_dasm(DASM_PARAMS); break; // 0x17 <illegal>
	537	case 0x18: size = arcompact_handle0f_18_dasm(DASM_PARAMS); break; // ASL_S (multiple)
	538	case 0x19: size = arcompact_handle0f_19_dasm(DASM_PARAMS); break; // LSR_S (multiple)
	539	case 0x1a: size = arcompact_handle0f_1a_dasm(DASM_PARAMS); break; // ASR_S (multiple)
	540	case 0x1b: size = arcompact_handle0f_1b_dasm(DASM_PARAMS); break; // ASL_S (single)
	541	case 0x1c: size = arcompact_handle0f_1c_dasm(DASM_PARAMS); break; // LSR_S (single)
	542	case 0x1d: size = arcompact_handle0f_1d_dasm(DASM_PARAMS); break; // ASR_S (single)
	543	case 0x1e: size = arcompact_handle0f_1e_dasm(DASM_PARAMS); break; // TRAP (not a5?)
	544	case 0x1f: size = arcompact_handle0f_1f_dasm(DASM_PARAMS); break; // BRK_S ( 0x7fff only? )
	545
	546	}
	547	return size;
	548	}
	549
	550	int arcompact_handle0f_00_dasm(DASM_OPS_16)
	551	{
	552	int size = 2;
	553	UINT8 subinstr = (op & 0x00e0) >> 5;
	554	op &= ~0x00e0;
	555
	556	switch (subinstr)
	557	{
	558	case 0x00: size = arcompact_handle0f_00_00_dasm(DASM_PARAMS); break; // J_S
	559	case 0x01: size = arcompact_handle0f_00_01_dasm(DASM_PARAMS); break; // J_S.D
	560	case 0x02: size = arcompact_handle0f_00_02_dasm(DASM_PARAMS); break; // JL_S
	561	case 0x03: size = arcompact_handle0f_00_03_dasm(DASM_PARAMS); break; // JL_S.D
	562	case 0x04: size = arcompact_handle0f_00_04_dasm(DASM_PARAMS); break; // 0x04 <illegal>
	563	case 0x05: size = arcompact_handle0f_00_05_dasm(DASM_PARAMS); break; // 0x05 <illegal>
	564	case 0x06: size = arcompact_handle0f_00_06_dasm(DASM_PARAMS); break; // SUB_S.NE
	565	case 0x07: size = arcompact_handle0f_00_07_dasm(DASM_PARAMS); break; // ZOPs
	566
	567	}
	568
	569	return size;
	570	}
	571
	572	int arcompact_handle0f_00_07_dasm(DASM_OPS_16)
	573	{
	574	int size = 2;
	575	// General Operations w/o Register
	576	// 01111 iii 111 00000
	577	UINT8 subinstr3 = (op & 0x0700) >> 8;
	578	op &= ~0x0700;
	579
	580	switch (subinstr3)
	581	{
	582	case 0x00: size = arcompact_handle0f_00_07_00_dasm(DASM_PARAMS); break; // NOP_S
	583	case 0x01: size = arcompact_handle0f_00_07_01_dasm(DASM_PARAMS); break; // UNIMP_S
	584	case 0x02: size = arcompact_handle0f_00_07_02_dasm(DASM_PARAMS); break; // 0x02 <illegal>
	585	case 0x03: size = arcompact_handle0f_00_07_03_dasm(DASM_PARAMS); break; // 0x03 <illegal>
	586	case 0x04: size = arcompact_handle0f_00_07_04_dasm(DASM_PARAMS); break; // JEQ_S [BLINK]
	587	case 0x05: size = arcompact_handle0f_00_07_05_dasm(DASM_PARAMS); break; // JNE_S [BLINK]
	588	case 0x06: size = arcompact_handle0f_00_07_06_dasm(DASM_PARAMS); break; // J_S [BLINK]
	589	case 0x07: size = arcompact_handle0f_00_07_07_dasm(DASM_PARAMS); break; // J_S.D [BLINK]
	590
	591	}
	592	return size;
	593	}
	594
	595	int arcompact_handle17_dasm(DASM_OPS_16)
	596	{
	597	int size = 2;
	598	UINT8 subinstr = (op & 0x00e0) >> 5;
	599	op &= ~0x00e0;
	600
	601	switch (subinstr)
	602	{
	603	case 0x00: size = arcompact_handle17_00_dasm(DASM_PARAMS); break; // ASL_S
	604	case 0x01: size = arcompact_handle17_01_dasm(DASM_PARAMS); break; // LSR_S
	605	case 0x02: size = arcompact_handle17_02_dasm(DASM_PARAMS); break; // ASR_S
	606	case 0x03: size = arcompact_handle17_03_dasm(DASM_PARAMS); break; // SUB_S
	607	case 0x04: size = arcompact_handle17_04_dasm(DASM_PARAMS); break; // BSET_S
	608	case 0x05: size = arcompact_handle17_05_dasm(DASM_PARAMS); break; // BCLR_S
	609	case 0x06: size = arcompact_handle17_06_dasm(DASM_PARAMS); break; // BMSK_S
	610	case 0x07: size = arcompact_handle17_07_dasm(DASM_PARAMS); break; // BTST_S
	611	}
	612
	613	return size;
	614	}
	615
	616	int arcompact_handle18_dasm(DASM_OPS_16)
	617	{
	618	int size = 2;
	619	// Stack Pointer Based Instructions (16-bit)
	620	// 11000 bbb iii uuuuu
	621	UINT8 subinstr = (op & 0x00e0) >> 5;
	622	op &= ~0x00e0;
	623
	624	switch (subinstr)
	625	{
	626	case 0x00: size = arcompact_handle18_00_dasm(DASM_PARAMS); break; // LD_S (SP)
	627	case 0x01: size = arcompact_handle18_01_dasm(DASM_PARAMS); break; // LDB_S (SP)
	628	case 0x02: size = arcompact_handle18_02_dasm(DASM_PARAMS); break; // ST_S (SP)
	629	case 0x03: size = arcompact_handle18_03_dasm(DASM_PARAMS); break; // STB_S (SP)
	630	case 0x04: size = arcompact_handle18_04_dasm(DASM_PARAMS); break; // ADD_S (SP)
	631	case 0x05: size = arcompact_handle18_05_dasm(DASM_PARAMS); break; // subtable 18_05
	632	case 0x06: size = arcompact_handle18_06_dasm(DASM_PARAMS); break; // subtable 18_06
	633	case 0x07: size = arcompact_handle18_07_dasm(DASM_PARAMS); break; // subtable 18_07
	634	}
	635
	636	return size;
	637	}
	638
	639	int arcompact_handle18_05_dasm(DASM_OPS_16)
	640	{
	641	int size = 2;
	642	UINT8 subinstr2 = (op & 0x0700) >> 8;
	643	op &= ~0x001f;
	644
	645	switch (subinstr2)
	646	{
	647	case 0x00: size = arcompact_handle18_05_00_dasm(DASM_PARAMS); break; // ADD_S (SP)
	648	case 0x01: size = arcompact_handle18_05_01_dasm(DASM_PARAMS); break; // SUB_S (SP)
	649	case 0x02: size = arcompact_handle18_05_02_dasm(DASM_PARAMS); break; // <illegal 0x18_05_02>
	650	case 0x03: size = arcompact_handle18_05_03_dasm(DASM_PARAMS); break; // <illegal 0x18_05_03>
	651	case 0x04: size = arcompact_handle18_05_04_dasm(DASM_PARAMS); break; // <illegal 0x18_05_04>
	652	case 0x05: size = arcompact_handle18_05_05_dasm(DASM_PARAMS); break; // <illegal 0x18_05_05>
	653	case 0x06: size = arcompact_handle18_05_06_dasm(DASM_PARAMS); break; // <illegal 0x18_05_06>
	654	case 0x07: size = arcompact_handle18_05_07_dasm(DASM_PARAMS); break; // <illegal 0x18_05_07>
	655	}
	656
	657	return size;
	658	}
	659
	660	int arcompact_handle18_06_dasm(DASM_OPS_16)
	661	{
	662	int size = 2;
	663	UINT8 subinstr2 = (op & 0x001f) >> 0;
	664	op &= ~0x001f;
	665
	666	switch (subinstr2)
	667	{
	668	case 0x00: size = arcompact_handle18_06_00_dasm(DASM_PARAMS); break; // <illegal 0x18_06_00>
	669	case 0x01: size = arcompact_handle18_06_01_dasm(DASM_PARAMS); break; // POP_S b
	670	case 0x02: size = arcompact_handle18_06_02_dasm(DASM_PARAMS); break; // <illegal 0x18_06_02>
	671	case 0x03: size = arcompact_handle18_06_03_dasm(DASM_PARAMS); break; // <illegal 0x18_06_03>
	672	case 0x04: size = arcompact_handle18_06_04_dasm(DASM_PARAMS); break; // <illegal 0x18_06_04>
	673	case 0x05: size = arcompact_handle18_06_05_dasm(DASM_PARAMS); break; // <illegal 0x18_06_05>
	674	case 0x06: size = arcompact_handle18_06_06_dasm(DASM_PARAMS); break; // <illegal 0x18_06_06>
	675	case 0x07: size = arcompact_handle18_06_07_dasm(DASM_PARAMS); break; // <illegal 0x18_06_07>
	676	case 0x08: size = arcompact_handle18_06_08_dasm(DASM_PARAMS); break; // <illegal 0x18_06_08>
	677	case 0x09: size = arcompact_handle18_06_09_dasm(DASM_PARAMS); break; // <illegal 0x18_06_09>
	678	case 0x0a: size = arcompact_handle18_06_0a_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0a>
	679	case 0x0b: size = arcompact_handle18_06_0b_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0b>
	680	case 0x0c: size = arcompact_handle18_06_0c_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0c>
	681	case 0x0d: size = arcompact_handle18_06_0d_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0d>
	682	case 0x0e: size = arcompact_handle18_06_0e_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0e>
	683	case 0x0f: size = arcompact_handle18_06_0f_dasm(DASM_PARAMS); break; // <illegal 0x18_06_0f>
	684	case 0x10: size = arcompact_handle18_06_10_dasm(DASM_PARAMS); break; // <illegal 0x18_06_10>
	685	case 0x11: size = arcompact_handle18_06_11_dasm(DASM_PARAMS); break; // POP_S blink
	686	case 0x12: size = arcompact_handle18_06_12_dasm(DASM_PARAMS); break; // <illegal 0x18_06_12>
	687	case 0x13: size = arcompact_handle18_06_13_dasm(DASM_PARAMS); break; // <illegal 0x18_06_13>
	688	case 0x14: size = arcompact_handle18_06_14_dasm(DASM_PARAMS); break; // <illegal 0x18_06_14>
	689	case 0x15: size = arcompact_handle18_06_15_dasm(DASM_PARAMS); break; // <illegal 0x18_06_15>
	690	case 0x16: size = arcompact_handle18_06_16_dasm(DASM_PARAMS); break; // <illegal 0x18_06_16>
	691	case 0x17: size = arcompact_handle18_06_17_dasm(DASM_PARAMS); break; // <illegal 0x18_06_17>
	692	case 0x18: size = arcompact_handle18_06_18_dasm(DASM_PARAMS); break; // <illegal 0x18_06_18>
	693	case 0x19: size = arcompact_handle18_06_19_dasm(DASM_PARAMS); break; // <illegal 0x18_06_19>
	694	case 0x1a: size = arcompact_handle18_06_1a_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1a>
	695	case 0x1b: size = arcompact_handle18_06_1b_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1b>
	696	case 0x1c: size = arcompact_handle18_06_1c_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1c>
	697	case 0x1d: size = arcompact_handle18_06_1d_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1d>
	698	case 0x1e: size = arcompact_handle18_06_1e_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1e>
	699	case 0x1f: size = arcompact_handle18_06_1f_dasm(DASM_PARAMS); break; // <illegal 0x18_06_1f>
	700	}
	701
	702	return size;
	703	}
	704
	705	int arcompact_handle18_07_dasm(DASM_OPS_16)
	706	{
	707	int size = 2;
	708	UINT8 subinstr2 = (op & 0x001f) >> 0;
	709	op &= ~0x001f;
	710
	711	switch (subinstr2)
	712	{
	713	case 0x00: size = arcompact_handle18_07_00_dasm(DASM_PARAMS); break; // <illegal 0x18_07_00>
	714	case 0x01: size = arcompact_handle18_07_01_dasm(DASM_PARAMS); break; // PUSH_S b
	715	case 0x02: size = arcompact_handle18_07_02_dasm(DASM_PARAMS); break; // <illegal 0x18_07_02>
	716	case 0x03: size = arcompact_handle18_07_03_dasm(DASM_PARAMS); break; // <illegal 0x18_07_03>
	717	case 0x04: size = arcompact_handle18_07_04_dasm(DASM_PARAMS); break; // <illegal 0x18_07_04>
	718	case 0x05: size = arcompact_handle18_07_05_dasm(DASM_PARAMS); break; // <illegal 0x18_07_05>
	719	case 0x06: size = arcompact_handle18_07_06_dasm(DASM_PARAMS); break; // <illegal 0x18_07_06>
	720	case 0x07: size = arcompact_handle18_07_07_dasm(DASM_PARAMS); break; // <illegal 0x18_07_07>
	721	case 0x08: size = arcompact_handle18_07_08_dasm(DASM_PARAMS); break; // <illegal 0x18_07_08>
	722	case 0x09: size = arcompact_handle18_07_09_dasm(DASM_PARAMS); break; // <illegal 0x18_07_09>
	723	case 0x0a: size = arcompact_handle18_07_0a_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0a>
	724	case 0x0b: size = arcompact_handle18_07_0b_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0b>
	725	case 0x0c: size = arcompact_handle18_07_0c_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0c>
	726	case 0x0d: size = arcompact_handle18_07_0d_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0d>
	727	case 0x0e: size = arcompact_handle18_07_0e_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0e>
	728	case 0x0f: size = arcompact_handle18_07_0f_dasm(DASM_PARAMS); break; // <illegal 0x18_07_0f>
	729	case 0x10: size = arcompact_handle18_07_10_dasm(DASM_PARAMS); break; // <illegal 0x18_07_10>
	730	case 0x11: size = arcompact_handle18_07_11_dasm(DASM_PARAMS); break; // PUSH_S blink
	731	case 0x12: size = arcompact_handle18_07_12_dasm(DASM_PARAMS); break; // <illegal 0x18_07_12>
	732	case 0x13: size = arcompact_handle18_07_13_dasm(DASM_PARAMS); break; // <illegal 0x18_07_13>
	733	case 0x14: size = arcompact_handle18_07_14_dasm(DASM_PARAMS); break; // <illegal 0x18_07_14>
	734	case 0x15: size = arcompact_handle18_07_15_dasm(DASM_PARAMS); break; // <illegal 0x18_07_15>
	735	case 0x16: size = arcompact_handle18_07_16_dasm(DASM_PARAMS); break; // <illegal 0x18_07_16>
	736	case 0x17: size = arcompact_handle18_07_17_dasm(DASM_PARAMS); break; // <illegal 0x18_07_17>
	737	case 0x18: size = arcompact_handle18_07_18_dasm(DASM_PARAMS); break; // <illegal 0x18_07_18>
	738	case 0x19: size = arcompact_handle18_07_19_dasm(DASM_PARAMS); break; // <illegal 0x18_07_19>
	739	case 0x1a: size = arcompact_handle18_07_1a_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1a>
	740	case 0x1b: size = arcompact_handle18_07_1b_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1b>
	741	case 0x1c: size = arcompact_handle18_07_1c_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1c>
	742	case 0x1d: size = arcompact_handle18_07_1d_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1d>
	743	case 0x1e: size = arcompact_handle18_07_1e_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1e>
	744	case 0x1f: size = arcompact_handle18_07_1f_dasm(DASM_PARAMS); break; // <illegal 0x18_07_1f>
	745	}
	746
	747	return size;
	748	}
	749
	750	int arcompact_handle19_dasm(DASM_OPS_16)
	751	{
	752	int size = 2;
	753	UINT8 subinstr = (op & 0x0600) >> 9;
	754	op &= ~0x0600;
	755
	756	switch (subinstr)
	757	{
	758	case 0x00: size = arcompact_handle19_00_dasm(DASM_PARAMS); break; // LD_S (GP)
	759	case 0x01: size = arcompact_handle19_01_dasm(DASM_PARAMS); break; // LDB_S (GP)
	760	case 0x02: size = arcompact_handle19_02_dasm(DASM_PARAMS); break; // LDW_S (GP)
	761	case 0x03: size = arcompact_handle19_03_dasm(DASM_PARAMS); break; // ADD_S (GP)
	762	}
	763	return size;
	764	}
	765
	766	int arcompact_handle1c_dasm(DASM_OPS_16)
	767	{
	768	int size = 2;
	769	UINT8 subinstr = (op & 0x0080) >> 7;
	770	op &= ~0x0080;
	771
	772	switch (subinstr)
	773	{
	774	case 0x00: size = arcompact_handle1c_00_dasm(DASM_PARAMS); break; // ADD_S
	775	case 0x01: size = arcompact_handle1c_01_dasm(DASM_PARAMS); break; // CMP_S
	776	}
	777	return size;
	778	}
	779
	780	int arcompact_handle1d_dasm(DASM_OPS_16)
	781	{
	782	int size = 2;
	783	UINT8 subinstr = (op & 0x0080) >> 7;
	784	op &= ~0x0080;
	785
	786	switch (subinstr)
	787	{
	788	case 0x00: size = arcompact_handle1d_00_dasm(DASM_PARAMS); break; // BREQ_S
	789	case 0x01: size = arcompact_handle1d_01_dasm(DASM_PARAMS); break; // BRNE_S
	790	}
	791	return size;
	792	}
	793
	794	int arcompact_handle1e_dasm(DASM_OPS_16)
	795	{
	796	int size = 2;
	797	UINT8 subinstr = (op & 0x0600) >> 9;
	798	op &= ~0x0600;
	799
	800	switch (subinstr)
	801	{
	802	case 0x00: size = arcompact_handle1e_00_dasm(DASM_PARAMS); break; // B_S
	803	case 0x01: size = arcompact_handle1e_01_dasm(DASM_PARAMS); break; // BEQ_S
	804	case 0x02: size = arcompact_handle1e_02_dasm(DASM_PARAMS); break; // BNE_S
	805	case 0x03: size = arcompact_handle1e_03_dasm(DASM_PARAMS); break; // Bcc_S
	806	}
	807	return size;
	808	}
	809
	810	int arcompact_handle1e_03_dasm(DASM_OPS_16)
	811	{
	812
	813	int size = 2;
	814	UINT8 subinstr2 = (op & 0x01c0) >> 6;
	815	op &= ~0x01c0;
	816
	817	switch (subinstr2)
	818	{
	819	case 0x00: size = arcompact_handle1e_03_00_dasm(DASM_PARAMS); break; // BGT_S
	820	case 0x01: size = arcompact_handle1e_03_01_dasm(DASM_PARAMS); break; // BGE_S
	821	case 0x02: size = arcompact_handle1e_03_02_dasm(DASM_PARAMS); break; // BLT_S
	822	case 0x03: size = arcompact_handle1e_03_03_dasm(DASM_PARAMS); break; // BLE_S
	823	case 0x04: size = arcompact_handle1e_03_04_dasm(DASM_PARAMS); break; // BHI_S
	824	case 0x05: size = arcompact_handle1e_03_05_dasm(DASM_PARAMS); break; // BHS_S
	825	case 0x06: size = arcompact_handle1e_03_06_dasm(DASM_PARAMS); break; // BLO_S
	826	case 0x07: size = arcompact_handle1e_03_07_dasm(DASM_PARAMS); break; // BLS_S
	827	}
	828	return size;
	829
	830	}

trunk/src/emu/cpu/arcompact/arcompactdasm_dispatch.h

r0	r242414
	1	/*********************************\
	2
	3	ARCompact disassembler
	4
	5	\*********************************/
	6
	7	#define DASM_OPS_16 char *output, offs_t pc, UINT16 op, const UINT8* oprom
	8	#define DASM_OPS_32 char *output, offs_t pc, UINT32 op, const UINT8* oprom
	9	#define DASM_PARAMS output, pc, op, oprom
	10
	11	#define LIMM_REG 62
	12
	13	#define GET_LIMM_32 \
	14	limm = oprom[6] | (oprom[7] << 8); \
	15	limm |= (oprom[4] << 16) | (oprom[5] << 24); \
	16
	17
	18
	19	int arcompact_handle00_dasm(DASM_OPS_32);
	20	int arcompact_handle01_dasm(DASM_OPS_32);
	21	int arcompact_handle01_00_dasm(DASM_OPS_32);
	22	int arcompact_handle01_01_dasm(DASM_OPS_32);
	23	int arcompact_handle01_01_00_dasm(DASM_OPS_32);
	24	int arcompact_handle01_01_01_dasm(DASM_OPS_32);
	25	int arcompact_handle04_dasm(DASM_OPS_32);
	26	int arcompact_handle04_2f_dasm(DASM_OPS_32);
	27	int arcompact_handle04_2f_3f_dasm(DASM_OPS_32);
	28	int arcompact_handle05_dasm(DASM_OPS_32);
	29
	30	int arcompact_handle0c_dasm(DASM_OPS_16);
	31	int arcompact_handle0d_dasm(DASM_OPS_16);
	32	int arcompact_handle0e_dasm(DASM_OPS_16);
	33	int arcompact_handle0f_dasm(DASM_OPS_16);
	34	int arcompact_handle0f_00_dasm(DASM_OPS_16);
	35	int arcompact_handle0f_00_07_dasm(DASM_OPS_16);
	36	int arcompact_handle17_dasm(DASM_OPS_16);
	37	int arcompact_handle18_dasm(DASM_OPS_16);
	38	int arcompact_handle18_05_dasm(DASM_OPS_16);
	39	int arcompact_handle18_06_dasm(DASM_OPS_16);
	40	int arcompact_handle18_07_dasm(DASM_OPS_16);
	41	int arcompact_handle19_dasm(DASM_OPS_16);
	42	int arcompact_handle1c_dasm(DASM_OPS_16);
	43	int arcompact_handle1d_dasm(DASM_OPS_16);
	44	int arcompact_handle1e_dasm(DASM_OPS_16);
	45	int arcompact_handle1e_03_dasm(DASM_OPS_16);

trunk/src/emu/cpu/arcompact/arcompactdasm_ops.c

r0	r242414
	1	/*********************************\
	2
	3	ARCompact disassembler
	4
	5	\*********************************/
	6
	7	#include "emu.h"
	8	#include <stdarg.h>
	9
	10	#include "arcompactdasm_ops.h"
	11
	12	char *output;
	13
	14	static void ATTR_PRINTF(1,2) print(const char *fmt, ...)
	15	{
	16	va_list vl;
	17
	18	va_start(vl, fmt);
	19	vsprintf(output, fmt, vl);
	20	va_end(vl);
	21	}
	22
	23
	24	// condition codes (basic ones are the same as arc
	25	static const char *conditions[0x20] =
	26	{
	27	/* 00 */ "AL", // (aka RA         - Always)
	28	/* 01 */ "EQ", // (aka Z          - Zero
	29	/* 02 */ "NE", // (aka NZ         - Non-Zero)
	30	/* 03 */ "PL", // (aka P          - Positive)
	31	/* 04 */ "MI", // (aka N          - Negative)
	32	/* 05 */ "CS", // (aka C,  LO     - Carry set / Lower than) (unsigned)
	33	/* 06 */ "CC", // (aka CC, NC, HS - Carry Clear / Higher or Same) (unsigned)
	34	/* 07 */ "VS", // (aka V          - Overflow set)
	35	/* 08 */ "VC", // (aka NV         - Overflow clear)
	36	/* 09 */ "GT", // (               - Greater than) (signed)
	37	/* 0a */ "GE", // (               - Greater than or Equal) (signed)
	38	/* 0b */ "LT", // (               - Less than) (signed)
	39	/* 0c */ "LE", // (               - Less than or Equal) (signed)
	40	/* 0d */ "HI", // (               - Higher than) (unsigned)
	41	/* 0e */ "LS", // (               - Lower or Same) (unsigned)
	42	/* 0f */ "PNZ",// (               - Positive non-0 value)
	43	/* 10 */ "0x10 Reserved", // possible CPU implementation specifics
	44	/* 11 */ "0x11 Reserved",
	45	/* 12 */ "0x12 Reserved",
	46	/* 13 */ "0x13 Reserved",
	47	/* 14 */ "0x14 Reserved",
	48	/* 15 */ "0x15 Reserved",
	49	/* 16 */ "0x16 Reserved",
	50	/* 17 */ "0x17 Reserved",
	51	/* 18 */ "0x18 Reserved",
	52	/* 19 */ "0x19 Reserved",
	53	/* 1a */ "0x1a Reserved",
	54	/* 1b */ "0x1b Reserved",
	55	/* 1c */ "0x1c Reserved",
	56	/* 1d */ "0x1d Reserved",
	57	/* 1e */ "0x1e Reserved",
	58	/* 1f */ "0x1f Reserved"
	59	};
	60
	61
	62	//#define EXPLICIT_EXTENSIONS
	63
	64	static const char *datasize[0x4] =
	65	{
	66	#ifdef EXPLICIT_EXTENSIONS
	67	/* 00 */ ".L", // Dword (default) (can use no extension, using .L to be explicit)
	68	#else
	69	/* 00 */ "",// Dword (default)
	70	#endif
	71	/* 01 */ ".B", // Byte
	72	/* 02 */ ".W", // Word
	73	/* 03 */ ".<illegal data size>"
	74	};
	75
	76	static const char *dataextend[0x2] =
	77	{
	78	#ifdef EXPLICIT_EXTENSIONS
	79	/* 00 */ ".ZX", // Zero Extend (can use no extension, using .ZX to be explicit)
	80	else
	81	/* 00 */ "", // Zero Extend
	82	#endif
	83	/* 01 */ ".X" // Sign Extend
	84	};
	85
	86	static const char *addressmode[0x4] =
	87	{
	88	#ifdef EXPLICIT_EXTENSIONS
	89	/* 00 */ ".AN", // No Writeback (can use no extension, using .AN to be explicit)
	90	#else
	91	/* 00 */ "", // No Writeback
	92	#endif
	93	/* 01 */ ".AW", // Writeback pre memory access
	94	/* 02 */ ".AB", // Writeback post memory access
	95	/* 03 */ ".AS"  // scaled
	96	};
	97
	98	static const char *cachebit[0x2] =
	99	{
	100	#ifdef EXPLICIT_EXTENSIONS
	101	/* 00 */ ".EN", // Data Cache Enabled (can use no extension, using .EN to be explicit)
	102	#else
	103	/* 00 */ "", // Data Cache Enabled
	104	#endif
	105	/* 01 */ ".DI" // Direct to Memory (Cache Bypass)
	106	};
	107
	108	static const char *flagbit[0x2] =
	109	{
	110	#ifdef EXPLICIT_EXTENSIONS
	111	/* 00 */ ".NF", // Don't Set Flags (can use no extension, using .NF to be explicit)
	112	#else
	113	/* 00 */ "", // Don't Set Flags
	114	#endif
	115	/* 01 */ ".F" // Set Flags
	116	};
	117
	118	static const char *delaybit[0x2] =
	119	{
	120	/* 00 */ ".ND", // Don't execute opcode in delay slot
	121	/* 01 */ ".D"   // Execute Opcode in delay slot
	122	};
	123
	124
	125	static const char *regnames[0x40] =
	126	{
	127	/* 00 */ "r0",
	128	/* 01 */ "r1",
	129	/* 02 */ "r2",
	130	/* 03 */ "r3",
	131	/* 04 */ "r4",
	132	/* 05 */ "r5",
	133	/* 06 */ "r6",
	134	/* 07 */ "r7",
	135	/* 08 */ "r8",
	136	/* 09 */ "r9",
	137	/* 0a */ "r10",
	138	/* 0b */ "r11",
	139	/* 0c */ "r12",
	140	/* 0d */ "r13",
	141	/* 0e */ "r14",
	142	/* 0f */ "r15",
	143
	144	/* 10 */ "r16",
	145	/* 11 */ "r17",
	146	/* 12 */ "r18",
	147	/* 13 */ "r19",
	148	/* 14 */ "r20",
	149	/* 15 */ "r21",
	150	/* 16 */ "r22",
	151	/* 17 */ "r23",
	152	/* 18 */ "r24",
	153	/* 19 */ "r25",
	154	/* 1a */ "r26(GP)",
	155	/* 1b */ "r27(FP)",
	156	/* 1c */ "r28(SP)",
	157	/* 1d */ "r29(ILINK1)",
	158	/* 1e */ "r30(ILINK2)",
	159	/* 1f */ "r31(BLINK)",
	160
	161	/* 20 */ "r32(ext)",
	162	/* 21 */ "r33(ext)",
	163	/* 22 */ "r34(ext)",
	164	/* 23 */ "r35(ext)",
	165	/* 24 */ "r36(ext)",
	166	/* 25 */ "r37(ext)",
	167	/* 26 */ "r38(ext)",
	168	/* 27 */ "r39(ext)",
	169	/* 28 */ "r40(ext)",
	170	/* 29 */ "r41(ext)",
	171	/* 2a */ "r42(ext)",
	172	/* 2b */ "r43(ext)",
	173	/* 2c */ "r44(ext)",
	174	/* 2d */ "r45(ext)",
	175	/* 2e */ "r46(ext)",
	176	/* 2f */ "r47(ext)",
	177
	178	/* 30 */ "r48(ext)",
	179	/* 31 */ "r49(ext)",
	180	/* 32 */ "r50(ext)",
	181	/* 33 */ "r51(ext)",
	182	/* 34 */ "r52(ext)",
	183	/* 35 */ "r53(ext)",
	184	/* 36 */ "r54(ext)",
	185	/* 37 */ "r55(ext)",
	186	/* 38 */ "r56(ext)",
	187	/* 39 */ "r57(ext)", // MLO  (result registers for optional multply functions)
	188	/* 3a */ "r58(ext)", // MMID
	189	/* 3b */ "r59(ext)", // MHI
	190	/* 3c */ "r60(LP_COUNT)",
	191	/* 3d */ "r61(reserved)",
	192	/* 3e */ "r62(LIMM)", // use Long Immediate Data instead of register
	193	/* 3f */ "r63(PCL)"
	194	};
	195
	196
	197
	198	int arcompact_01_01_00_helper(char *output, offs_t pc, UINT32 op, const UINT8* oprom, const char* optext)
	199	{
	200	int size = 4;
	201
	202	// Branch on Compare / Bit Test - Register-Register
	203	// 00001 bbb sssssss 1 S BBB CCCCCC N 0 iiii
	204	INT32 address = (op & 0x00fe0000) >> 17;
	205	address |= ((op & 0x00008000) >> 15) << 7;
	206	if (address & 0x80) address = -(address & 0x7f);
	207
	208	int c = (op & 0x00000fc0) >> 6;
	209	int b = (op & 0x07000000) >> 24;
	210	b |= ((op & 0x00007000) >> 12) << 3;
	211	int n = (op & 0x00000020) >> 5; op &= ~0x00000020;
	212
	213	op &= ~0x07007fe0;
	214
	215	if ((b != LIMM_REG) && (c != LIMM_REG))
	216	{
	217	print("%s%s (r%d) (r%d) %08x (%08x)", optext, delaybit[n], b, c, pc + (address * 2) + 4, op & ~0xf8fe800f);
	218	}
	219	else
	220	{
	221	UINT32 limm;
	222	GET_LIMM_32;
	223	size = 8;
	224
	225	if ((b == LIMM_REG) && (c != LIMM_REG))
	226	{
	227	print("%s%s (%08x) (r%d) %08x (%08x)", optext, delaybit[n], limm, c, pc + (address * 2) + 4, op & ~0xf8fe800f);
	228	}
	229	else if ((c == LIMM_REG) && (b != LIMM_REG))
	230	{
	231	print("%s%s (r%d) (%08x) %08x (%08x)", optext, delaybit[n], b, limm, pc + (address * 2) + 4, op & ~0xf8fe800f);
	232	}
	233	else
	234	{
	235	// b and c are LIMM? invalid??
	236	print("%s%s (%08x) (%08x) (illegal?) %08x (%08x)", optext, delaybit[n], limm, limm, pc + (address * 2) + 4, op & ~0xf8fe800f);
	237
	238	}
	239	}
	240
	241	return size;
	242	}
	243
	244	#define GET_01_01_01_BRANCH_ADDR \
	245	INT32 address = (op & 0x00fe0000) >> 17; \
	246	address |= ((op & 0x00008000) >> 15) << 7; \
	247	if (address & 0x80) address = -(address & 0x7f); \
	248	op &= ~ 0x00fe800f;
	249
	250
	251	#define GROUP_0e_GET_h \
	252	h =  ((op & 0x0007) << 3); \
	253	h |= ((op & 0x00e0) >> 5); \
	254
	255	// this is as messed up as the rest of the 16-bit alignment in LE mode...
	256
	257	#define GET_LIMM \
	258	limm = oprom[4] | (oprom[5] << 8); \
	259	limm |= (oprom[2] << 16) | (oprom[3] << 24); \
	260
	261
	262	/************************************************************************************************************************************
	263	*                                                                                                                                   *
	264	* individual opcode handlers (disassembly)                                                                                          *
	265	*                                                                                                                                   *
	266	************************************************************************************************************************************/
	267
	268	int arcompact_handle00_00_dasm(DASM_OPS_32)
	269	{
	270	int size = 4;
	271	// Branch Conditionally
	272	// 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ
	273	INT32 address = (op & 0x07fe0000) >> 17;
	274	address |= ((op & 0x0000ffc0) >> 6) << 10;
	275	if (address & 0x800000) address = -(address & 0x7fffff);
	276	int n = (op & 0x00000020) >> 5; op &= ~0x00000020;
	277	UINT8 condition = op & 0x0000001f;
	278
	279	output  += sprintf( output, "B%s(%s) %08x", delaybit[n], conditions[condition], pc + (address * 2));
	280	return size;
	281	}
	282
	283	int arcompact_handle00_01_dasm(DASM_OPS_32)
	284	{
	285	int size = 4;
	286	// Branch Unconditionally Far
	287	// 00000 ssssssssss 1  SSSSSSSSSS N R TTTT
	288	INT32 address = (op & 0x07fe0000) >> 17;
	289	address |= ((op & 0x0000ffc0) >> 6) << 10;
	290	address |= ((op & 0x0000000f) >> 0) << 20;
	291	if (address & 0x800000) address = -(address & 0x7fffff);
	292	int n = (op & 0x00000020) >> 5; op &= ~0x00000020;
	293	int res =  (op & 0x00000010) >> 4; op &= ~0x00000010;
	294
	295	output  += sprintf( output, "B%s %08x", delaybit[n], pc + (address * 2) );
	296	if (res)  output += sprintf(output, "(reserved bit set)");
	297
	298	return size;
	299	}
	300
	301	int arcompact_handle01_00_00dasm(DASM_OPS_32)
	302	{
	303	int size = 4;
	304
	305	// Branch and Link Conditionally
	306	// 00001 sssssssss 00 SSSSSSSSSS N QQQQQ
	307	INT32 address =   (op & 0x07fc0000) >> 17;
	308	address |=        ((op & 0x0000ffc0) >> 6) << 10;
	309	if (address & 0x800000) address = -(address&0x7fffff);
	310	int n = (op & 0x00000020) >> 5; op &= ~0x00000020;
	311
	312	UINT8 condition = op & 0x0000001f;
	313
	314	output  += sprintf( output, "BL%s(%s) %08x", delaybit[n], conditions[condition], pc + (address *2) );
	315	return size;
	316	}
	317
	318	int arcompact_handle01_00_01dasm(DASM_OPS_32)
	319	{
	320	int size = 4;
	321	// Branch and Link Unconditionally Far
	322	// 00001 sssssssss 10  SSSSSSSSSS N R TTTT
	323	INT32 address =   (op & 0x07fc0000) >> 17;
	324	address |=        ((op & 0x0000ffc0) >> 6) << 10;
	325	address |=        ((op & 0x0000000f) >> 0) << 20;
	326	if (address & 0x800000) address = -(address&0x7fffff);
	327	int n = (op & 0x00000020) >> 5; op &= ~0x00000020;
	328	int res =  (op & 0x00000010) >> 4; op &= ~0x00000010;
	329
	330	output  += sprintf( output, "BL%s %08x", delaybit[n], pc + (address *2) );
	331	if (res)  output += sprintf(output, "(reserved bit set)");
	332
	333	return size;
	334	}
	335
	336	int arcompact_handle01_01_00_00_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BREQ b - c"); }
	337	int arcompact_handle01_01_00_01_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRNE b - c"); }
	338	int arcompact_handle01_01_00_02_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRLT b - c"); }
	339	int arcompact_handle01_01_00_03_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRGE b - c"); }
	340	int arcompact_handle01_01_00_04_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRLO b - c"); }
	341	int arcompact_handle01_01_00_05_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BRHS b - c"); }
	342	int arcompact_handle01_01_00_0e_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BBIT0 (b & 1<<c) == 0");  }
	343	int arcompact_handle01_01_00_0f_dasm(DASM_OPS_32)  { return arcompact_01_01_00_helper( output, pc, op, oprom, "BBIT1 (b & 1<<c) != 0");  }
	344
	345
	346	int arcompact_handle01_01_01_00_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BREQ b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
	347	int arcompact_handle01_01_01_01_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRNE b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
	348	int arcompact_handle01_01_01_02_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRLT b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
	349	int arcompact_handle01_01_01_03_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRGE b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
	350	int arcompact_handle01_01_01_04_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRLO b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
	351	int arcompact_handle01_01_01_05_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BRHS b - u6 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
	352
	353
	354	int arcompact_handle01_01_01_0e_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BBIT0 (b & 1<<u6) == 0 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
	355	int arcompact_handle01_01_01_0f_dasm(DASM_OPS_32)  { GET_01_01_01_BRANCH_ADDR;  print("BBIT1 (b & 1<<u6) != 0 (dst %08x) (%08x)", pc + (address * 2) + 4, op); return 4; }
	356
	357
	358	int arcompact_handle02_dasm(DASM_OPS_32)
	359	{
	360	// bitpos
	361	// 1111 1111 1111 1111 0000 0000 0000 0000
	362	// fedc ba98 7654 3210 fedc ba98 7654 3210
	363	// fields
	364	// 0001 0bbb ssss ssss SBBB DaaZ ZXAA AAAA
	365	int size = 4;
	366
	367	int A = (op & 0x0000003f) >> 0;  //op &= ~0x0000003f;
	368	int X = (op & 0x00000040) >> 6;  //op &= ~0x00000040;
	369	int Z = (op & 0x00000180) >> 7;  //op &= ~0x00000180;
	370	int a = (op & 0x00000600) >> 9;  //op &= ~0x00000600;
	371	int D = (op & 0x00000800) >> 11;// op &= ~0x00000800;
	372	int B = (op & 0x00007000) >> 12;// op &= ~0x00007000;
	373	int S = (op & 0x00008000) >> 15;// op &= ~0x00008000;
	374	int s = (op & 0x00ff0000) >> 16;// op &= ~0x00ff0000;
	375	int b = (op & 0x07000000) >> 24;// op &= ~0x07000000;
	376
	377	int breg = b | (B << 3);
	378	int sdat = s | (S << 8); // todo - signed
	379
	380	UINT32 limm = 0;
	381	if (breg == LIMM_REG)
	382	{
	383	GET_LIMM_32;
	384	size = 8;
	385	}
	386
	387	output  += sprintf( output, "LD");
	388	output  += sprintf( output, "%s", datasize[Z]);
	389	output  += sprintf( output, "%s", dataextend[X]);
	390	output  += sprintf( output, "%s", addressmode[a]);
	391	output  += sprintf( output, "%s", cachebit[D]);
	392	output  += sprintf( output, " ");
	393	output  += sprintf( output, "%s, ", regnames[A]);
	394	output  += sprintf( output, "[");
	395	if (breg == LIMM_REG) output  += sprintf( output, "(%08x), ", limm);
	396	else output  += sprintf( output, "%s, ", regnames[breg]);
	397	output  += sprintf( output, "%d", sdat);
	398	output  += sprintf( output, "]");
	399
	400	return size;
	401	}
	402
	403	int arcompact_handle03_dasm(DASM_OPS_32)
	404	{
	405	int size = 4;
	406	// bitpos
	407	// 1111 1111 1111 1111 0000 0000 0000 0000
	408	// fedc ba98 7654 3210 fedc ba98 7654 3210
	409	// fields
	410	// 0001 1bbb ssss ssss SBBB CCCC CCDa aZZR
	411	int B = (op & 0x00007000) >> 12;// op &= ~0x00007000;
	412	int S = (op & 0x00008000) >> 15;// op &= ~0x00008000;
	413	int s = (op & 0x00ff0000) >> 16;// op &= ~0x00ff0000;
	414	int b = (op & 0x07000000) >> 24;// op &= ~0x07000000;
	415
	416	int breg = b | (B << 3);
	417	int sdat = s | (S << 8); // todo - signed
	418
	419	int R = (op & 0x00000001) >> 0; op &= ~0x00000001;
	420	int Z = (op & 0x00000006) >> 1; op &= ~0x00000006;
	421	int a = (op & 0x00000018) >> 3; op &= ~0x00000018;
	422	int D = (op & 0x00000020) >> 5; op &= ~0x00000020;
	423	int C = (op & 0x00000fc0) >> 6; op &= ~0x00000fc0;
	424
	425	UINT32 limm = 0;
	426	if (breg == LIMM_REG)
	427	{
	428	GET_LIMM_32;
	429	size = 8;
	430	}
	431
	432
	433	output  += sprintf( output, "ST");
	434	output  += sprintf( output, "%s", datasize[Z]);
	435	output  += sprintf( output, "%s", addressmode[a]);
	436	output  += sprintf( output, "%s", cachebit[D]);
	437	output  += sprintf( output, " ");
	438
	439	output  += sprintf( output, "%s, ", regnames[C]);
	440	if (breg == LIMM_REG) output  += sprintf( output, "(%08x), ", limm);
	441	else output  += sprintf( output, "%s, ", regnames[breg]);
	442	output  += sprintf( output, "%d", sdat);
	443
	444	if (R) output  += sprintf( output, "(reserved bit set)");
	445
	446
	447	return size;
	448	}
	449
	450
	451	int arcompact_handle04_helper_dasm(char *output, offs_t pc, UINT32 op, const UINT8* oprom, const char* optext, int ignore_dst, int b_reserved)
	452	{
	453	//           PP
	454	// 0010 0bbb 00ii iiii FBBB CCCC CCAA AAAA
	455	int size = 4;
	456
	457	int p = (op & 0x00c00000) >> 22; op &= ~0x00c00000;
	458	int b = (op & 0x07000000) >> 24; op &= ~0x07000000;
	459	int B = (op & 0x00007000) >> 12; op &= ~0x00007000;
	460	int breg = b | (B << 3);
	461	int F = (op & 0x00008000) >> 15;op &= ~0x00008000;
	462
	463	output  += sprintf( output, "%s", optext);
	464	output  += sprintf( output, "%s", flagbit[F]);
	465	//   output  += sprintf( output, " p(%d)", p);
	466
	467
	468	if (!b_reserved)
	469	{
	470	output += sprintf(output, " %s, ", regnames[breg]);
	471	}
	472	else
	473	{
	474	if (breg) output += sprintf(output, "reserved(%s), ", regnames[breg]);
	475	}
	476
	477
	478	if (p == 0)
	479	{
	480	// 0010 0bbb 00ii iiii FBBB CCCC CCAA AAAA
	481
	482	int C = (op & 0x00000fc0) >> 6; op &= ~0x00000fc0;
	483	int A = (op & 0x0000003f) >> 0; op &= ~0x0000003f;
	484
	485	if (C == LIMM_REG)
	486	{
	487	UINT32 limm;
	488	GET_LIMM_32;
	489	size = 8;
	490	output  += sprintf( output, "(%08x) ", limm );
	491	if (!ignore_dst) output  += sprintf( output, "DST(%s)", regnames[A]);
	492	else
	493	{
	494	if (A) output += sprintf(output, "unused(%s)", regnames[A]);
	495	}
	496	}
	497	else
	498	{
	499	output  += sprintf( output, "C(%s) ", regnames[C]);
	500	if (!ignore_dst) output  += sprintf( output, "DST(%s)", regnames[A]);
	501	else
	502	{
	503	if (A) output += sprintf(output, "unused(%s)", regnames[A]);
	504	}
	505
	506	}
	507	}
	508	else if (p == 1)
	509	{
	510	// 0010 0bbb 00ii iiii FBBB UUUU UUAA AAAA
	511	int U = (op & 0x00000fc0) >> 6; op &= ~0x00000fc0;
	512	int A = (op & 0x0000003f) >> 0; op &= ~0x0000003f;
	513
	514	output  += sprintf( output, "U(%02x) ", U );
	515	if (!ignore_dst) output  += sprintf( output, "DST(%s)", regnames[A]);
	516	else
	517	{
	518	if (A) output += sprintf(output, "unused(%s)", regnames[A]);
	519	}
	520	}
	521	else if (p == 2)
	522	{
	523	int S = (op & 0x00000fff) >> 0; op &= ~0x00000fff;
	524	output  += sprintf( output, "S(%02x)", S);
	525
	526	}
	527	else if (p == 3)
	528	{
	529	int M = (op & 0x00000020) >> 5; op &= ~0x00000020;
	530	int Q = (op & 0x0000001f) >> 0; op &= ~0x0000001f;
	531
	532	output  += sprintf( output, " M(%d)", M);
	533	output  += sprintf( output, " Cond<%s> ", conditions[Q]);
	534
	535	if (M == 0)
	536	{
	537	int C = (op & 0x00000fc0) >> 6; op &= ~0x00000fc0;
	538	output  += sprintf( output, "C(%s)", regnames[C]);
	539
	540	}
	541	else if (M == 1)
	542	{
	543	int U = (op & 0x00000fc0) >> 6; op &= ~0x00000fc0;
	544	output  += sprintf( output, "U(%02x)", U);
	545
	546	}
	547
	548	}
	549
	550	return size;
	551	}
	552
	553	int arcompact_handle04_00_dasm(DASM_OPS_32)
	554	{
	555	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "ADD", 0,0);
	556	}
	557
	558	int arcompact_handle04_01_dasm(DASM_OPS_32)
	559	{
	560	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "ADC", 0,0);
	561	}
	562
	563	int arcompact_handle04_02_dasm(DASM_OPS_32)
	564	{
	565	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "SUB", 0,0);
	566	}
	567
	568	int arcompact_handle04_03_dasm(DASM_OPS_32)
	569	{
	570	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "SBC", 0,0);
	571	}
	572
	573	int arcompact_handle04_04_dasm(DASM_OPS_32)
	574	{
	575	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "AND", 0,0);
	576	}
	577
	578	int arcompact_handle04_05_dasm(DASM_OPS_32)
	579	{
	580	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "OR", 0,0);
	581	}
	582
	583	int arcompact_handle04_06_dasm(DASM_OPS_32)
	584	{
	585	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "BIC", 0,0);
	586	}
	587
	588	int arcompact_handle04_07_dasm(DASM_OPS_32)
	589	{
	590	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "XOR", 0,0);
	591	}
	592
	593	int arcompact_handle04_08_dasm(DASM_OPS_32)
	594	{
	595	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "MAX", 0,0);
	596	}
	597
	598	int arcompact_handle04_09_dasm(DASM_OPS_32)
	599	{
	600	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "MIN", 0,0);
	601	}
	602
	603
	604	int arcompact_handle04_0a_dasm(DASM_OPS_32)
	605	{
	606	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "MOV", 1,0);
	607	}
	608
	609	int arcompact_handle04_0b_dasm(DASM_OPS_32)
	610	{
	611	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "TST", 1,0);
	612	}
	613
	614	int arcompact_handle04_0c_dasm(DASM_OPS_32)
	615	{
	616	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "CMP", 1,0);
	617	}
	618
	619	int arcompact_handle04_0d_dasm(DASM_OPS_32)
	620	{
	621	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "RCMP", 1,0);
	622	}
	623
	624	int arcompact_handle04_0e_dasm(DASM_OPS_32)
	625	{
	626	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "RSUB", 0,0);
	627	}
	628
	629	int arcompact_handle04_0f_dasm(DASM_OPS_32)
	630	{
	631	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "BSET", 0,0);
	632	}
	633
	634	int arcompact_handle04_10_dasm(DASM_OPS_32)
	635	{
	636	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "BCLR", 0,0);
	637	}
	638
	639	int arcompact_handle04_11_dasm(DASM_OPS_32)
	640	{
	641	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "BTST", 0,0);
	642	}
	643
	644	int arcompact_handle04_12_dasm(DASM_OPS_32)
	645	{
	646	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "BXOR", 0,0);
	647	}
	648
	649	int arcompact_handle04_13_dasm(DASM_OPS_32)
	650	{
	651	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "BMSK", 0,0);
	652	}
	653
	654	int arcompact_handle04_14_dasm(DASM_OPS_32)
	655	{
	656	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "ADD1", 0,0);
	657	}
	658
	659	int arcompact_handle04_15_dasm(DASM_OPS_32)
	660	{
	661	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "ADD2", 0,0);
	662	}
	663
	664	int arcompact_handle04_16_dasm(DASM_OPS_32)
	665	{
	666	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "ADD3", 0,0);
	667	}
	668
	669	int arcompact_handle04_17_dasm(DASM_OPS_32)
	670	{
	671	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "SUB1", 0,0);
	672	}
	673
	674	int arcompact_handle04_18_dasm(DASM_OPS_32)
	675	{
	676	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "SUB2", 0,0);
	677	}
	678
	679	int arcompact_handle04_19_dasm(DASM_OPS_32)
	680	{
	681	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "SUB3", 0,0);
	682	}
	683
	684	int arcompact_handle04_1a_dasm(DASM_OPS_32)
	685	{
	686	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "MPY", 0,0);
	687	} // *
	688
	689	int arcompact_handle04_1b_dasm(DASM_OPS_32)
	690	{
	691	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "MPYH", 0,0);
	692	} // *
	693
	694	int arcompact_handle04_1c_dasm(DASM_OPS_32)
	695	{
	696	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "MPYHU", 0,0);
	697	} // *
	698
	699	int arcompact_handle04_1d_dasm(DASM_OPS_32)
	700	{
	701	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "MPYU", 0,0);
	702	} // *
	703
	704
	705
	706	int arcompact_handle04_20_dasm(DASM_OPS_32)
	707	{
	708	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "J", 1,1);
	709	}
	710
	711
	712
	713	int arcompact_handle04_21_dasm(DASM_OPS_32)
	714	{
	715	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "J.D", 1,1);
	716	}
	717
	718	int arcompact_handle04_22_dasm(DASM_OPS_32)
	719	{
	720	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "JL", 1,1);
	721	}
	722
	723	int arcompact_handle04_23_dasm(DASM_OPS_32)
	724	{
	725	return arcompact_handle04_helper_dasm(output, pc, op, oprom, "JL.D", 1,1);
	726	}
	727
	728
	729
	730
	731	int arcompact_handle04_28_dasm(DASM_OPS_32)  { print("LPcc (%08x)", op); return 4;}
	732	int arcompact_handle04_29_dasm(DASM_OPS_32)  { print("FLAG (%08x)", op); return 4;}
	733	int arcompact_handle04_2a_dasm(DASM_OPS_32)  { print("LR (%08x)", op); return 4;}
	734	int arcompact_handle04_2b_dasm(DASM_OPS_32)  { print("SR (%08x)", op); return 4;}
	735
	736
	737	int arcompact_handle04_2f_helper_dasm(char *output, offs_t pc, UINT32 op, const UINT8* oprom, const char* optext)
	738	{
	739	//
	740	// 0010 0bbb pp10 1111 FBBB CCCC CCII IIII
	741	int size = 4;
	742
	743	int p = (op & 0x00c00000) >> 22; op &= ~0x00c00000;
	744	int b = (op & 0x07000000) >> 24; op &= ~0x07000000;
	745	int B = (op & 0x00007000) >> 12; op &= ~0x00007000;
	746	int breg = b | (B << 3);
	747	int F = (op & 0x00008000) >> 15;op &= ~0x00008000;
	748
	749	output  += sprintf( output, "%s", optext);
	750	output  += sprintf( output, "%s", flagbit[F]);
	751	//   output  += sprintf( output, " p(%d)", p);
	752
	753
	754	output += sprintf(output, " %s, ", regnames[breg]);
	755
	756
	757	if (p == 0)
	758	{
	759	int C = (op & 0x00000fc0) >> 6; op &= ~0x00000fc0;
	760
	761	if (C == LIMM_REG)
	762	{
	763	UINT32 limm;
	764	GET_LIMM_32;
	765	size = 8;
	766	output  += sprintf( output, "(%08x) ", limm );
	767
	768	}
	769	else
	770	{
	771	output  += sprintf( output, "C(%s) ", regnames[C]);
	772	}
	773	}
	774	else if (p == 1)
	775	{
	776	output  += sprintf( output, "<04_2f illegal p=01>");
	777	}
	778	else if (p == 2)
	779	{
	780	output  += sprintf( output, "<04_2f illegal p=10>");
	781	}
	782	else if (p == 3)
	783	{
	784	output  += sprintf( output, "<04_2f illegal p=11>");
	785	}
	786
	787	return size;
	788	}
	789
	790
	791	int arcompact_handle04_2f_00_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "ASL"); } // ASL
	792	int arcompact_handle04_2f_01_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "ASR"); } // ASR
	793	int arcompact_handle04_2f_02_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "LSR"); } // LSR
	794	int arcompact_handle04_2f_03_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "ROR"); } // ROR
	795	int arcompact_handle04_2f_04_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "RCC"); } // RCC
	796	int arcompact_handle04_2f_05_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "SEXB"); } // SEXB
	797	int arcompact_handle04_2f_06_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "SEXW"); } // SEXW
	798	int arcompact_handle04_2f_07_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "EXTB"); } // EXTB
	799	int arcompact_handle04_2f_08_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "EXTW"); } // EXTW
	800	int arcompact_handle04_2f_09_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "ABS"); } // ABS
	801	int arcompact_handle04_2f_0a_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "NOT"); } // NOT
	802	int arcompact_handle04_2f_0b_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "RCL"); } // RLC
	803	int arcompact_handle04_2f_0c_dasm(DASM_OPS_32)  { return arcompact_handle04_2f_helper_dasm(output, pc, op, oprom, "EX"); } // EX
	804
	805
	806	int arcompact_handle04_2f_3f_01_dasm(DASM_OPS_32)  { print("SLEEP (%08x)", op); return 4;}
	807	int arcompact_handle04_2f_3f_02_dasm(DASM_OPS_32)  { print("SWI / TRAP0 (%08x)", op); return 4;}
	808	int arcompact_handle04_2f_3f_03_dasm(DASM_OPS_32)  { print("SYNC (%08x)", op); return 4;}
	809	int arcompact_handle04_2f_3f_04_dasm(DASM_OPS_32)  { print("RTIE (%08x)", op); return 4;}
	810	int arcompact_handle04_2f_3f_05_dasm(DASM_OPS_32)  { print("BRK (%08x)", op); return 4;}
	811
	812
	813
	814
	815
	816	// format on these is..
	817
	818	// 0010 0bbb aa11 0ZZX DBBB CCCC CCAA AAAA
	819	// note, bits  11 0ZZX are part of the sub-opcode # already - this is a special encoding
	820	int arcompact_handle04_3x_helper_dasm(char *output, offs_t pc, UINT32 op, const UINT8* oprom, int dsize, int extend)
	821	{
	822	int size = 4;
	823	output += sprintf(output, "LD");
	824	output += sprintf(output, "%s", datasize[dsize]);
	825	output += sprintf(output, "%s", dataextend[extend]);
	826
	827	int mode = (op & 0x00c00000) >> 22; op &= ~0x00c00000;
	828	int b = (op & 0x07000000) >> 24; op &= ~0x07000000;
	829	int B = (op & 0x00007000) >> 12; op &= ~0x00007000;
	830	int breg = b | (B << 3);
	831	int D = (op & 0x00008000) >> 15;op &= ~0x00008000;
	832	int C = (op & 0x00000fc0) >> 6; op &= ~0x00000fc0;
	833	int A = (op & 0x0000003f) >> 0; op &= ~0x0000003f;
	834
	835	output += sprintf(output, "%s", addressmode[mode]);
	836	output += sprintf(output, "%s", cachebit[D]);
	837
	838	output  += sprintf( output, "DST(%s)", regnames[A]);
	839	output  += sprintf( output, "SRC1(%s)", regnames[breg]);
	840	output  += sprintf( output, "SRC2(%s)", regnames[C]);
	841
	842
	843
	844
	845	return size;
	846
	847
	848
	849	}
	850
	851	int arcompact_handle04_30_dasm(DASM_OPS_32)  { return arcompact_handle04_3x_helper_dasm(output,pc,op,oprom,0,0); }
	852	// ZZ value of 0x0 with X of 1 is illegal
	853	int arcompact_handle04_31_dasm(DASM_OPS_32)  { return arcompact_handle04_3x_helper_dasm(output,pc,op,oprom,0,1); }
	854	int arcompact_handle04_32_dasm(DASM_OPS_32)  { return arcompact_handle04_3x_helper_dasm(output,pc,op,oprom,1,0); }
	855	int arcompact_handle04_33_dasm(DASM_OPS_32)  { return arcompact_handle04_3x_helper_dasm(output,pc,op,oprom,1,1); }
	856	int arcompact_handle04_34_dasm(DASM_OPS_32)  { return arcompact_handle04_3x_helper_dasm(output,pc,op,oprom,2,0); }
	857	int arcompact_handle04_35_dasm(DASM_OPS_32)  { return arcompact_handle04_3x_helper_dasm(output,pc,op,oprom,2,1); }
	858	// ZZ value of 0x3 is illegal
	859	int arcompact_handle04_36_dasm(DASM_OPS_32)  { return arcompact_handle04_3x_helper_dasm(output,pc,op,oprom,3,0); }
	860	int arcompact_handle04_37_dasm(DASM_OPS_32)  { return arcompact_handle04_3x_helper_dasm(output,pc,op,oprom,3,1); }
	861
	862
	863
	864
	865
	866
	867	int arcompact_handle05_00_dasm(DASM_OPS_32)  { print("ASL a <- b asl c (%08x)", op); return 4;}
	868	int arcompact_handle05_01_dasm(DASM_OPS_32)  { print("LSR a <- b lsr c (%08x)", op); return 4;}
	869	int arcompact_handle05_02_dasm(DASM_OPS_32)  { print("ASR a <- b asr c (%08x)", op); return 4;}
	870	int arcompact_handle05_03_dasm(DASM_OPS_32)  { print("ROR a <- b ror c (%08x)", op); return 4;}
	871	int arcompact_handle05_04_dasm(DASM_OPS_32)  { print("MUL64 mulres <- b * c (%08x)", op); return 4;}
	872	int arcompact_handle05_05_dasm(DASM_OPS_32)  { print("MULU64 mulres <- b * c (%08x)", op); return 4;}
	873	int arcompact_handle05_06_dasm(DASM_OPS_32)  { print("ADDS a <- sat32 (b + c) (%08x)", op); return 4;}
	874	int arcompact_handle05_07_dasm(DASM_OPS_32)  { print("SUBS a <- sat32 (b + c) (%08x)", op); return 4;}
	875	int arcompact_handle05_08_dasm(DASM_OPS_32)  { print("DIVAW (%08x)", op); return 4;}
	876
	877
	878
	879	int arcompact_handle05_0a_dasm(DASM_OPS_32)  { print("ASLS a <- sat32 (b << c) (%08x)", op); return 4;}
	880	int arcompact_handle05_0b_dasm(DASM_OPS_32)  { print("ASRS a ,- sat32 (b >> c) (%08x)", op); return 4;}
	881
	882	int arcompact_handle05_28_dasm(DASM_OPS_32)  { print("ADDSDW (%08x)", op); return 4;}
	883	int arcompact_handle05_29_dasm(DASM_OPS_32)  { print("SUBSDW (%08x)", op); return 4;}
	884
	885
	886	int arcompact_handle05_2f_dasm(DASM_OPS_32)  { print("SOP (another table) (%08x)", op); return 4;}
	887
	888
	889
	890
	891	int arcompact_handle06_dasm(DASM_OPS_32)
	892	{
	893	print("op a,b,c (06 ARC ext) (%08x)", op );
	894	return 4;
	895	}
	896
	897	int arcompact_handle07_dasm(DASM_OPS_32)
	898	{
	899	print("op a,b,c (07 User ext) (%08x)", op );
	900	return 4;
	901	}
	902
	903	int arcompact_handle08_dasm(DASM_OPS_32)
	904	{
	905	print("op a,b,c (08 User ext) (%08x)", op );
	906	return 4;
	907	}
	908
	909	int arcompact_handle09_dasm(DASM_OPS_32)
	910	{
	911	print("op a,b,c (09 Market ext) (%08x)", op );
	912	return 4;
	913	}
	914
	915	int arcompact_handle0a_dasm(DASM_OPS_32)
	916	{
	917	print("op a,b,c (0a Market ext) (%08x)",  op );
	918	return 4;
	919	}
	920
	921	int arcompact_handle0b_dasm(DASM_OPS_32)
	922	{
	923	print("op a,b,c (0b Market ext) (%08x)",  op );
	924	return 4;
	925	}
	926
	927
	928
	929
	930
	931
	932	int arcompact_handle0c_00_dasm(DASM_OPS_16)
	933	{
	934	int size = 2;
	935	print("LD_S a <- m[b + c].long (%04x)", op);
	936	return size;
	937	}
	938
	939	int arcompact_handle0c_01_dasm(DASM_OPS_16)
	940	{
	941	int size = 2;
	942	print("LDB_S a <- m[b + c].byte (%04x)", op);
	943	return size;
	944	}
	945
	946	int arcompact_handle0c_02_dasm(DASM_OPS_16)
	947	{
	948	int size = 2;
	949	print("LDW_S a <- m[b + c].word (%04x)", op);
	950	return size;
	951	}
	952
	953	int arcompact_handle0c_03_dasm(DASM_OPS_16)
	954	{
	955	int size = 2;
	956	print("ADD_S a <- b + c (%04x)", op);
	957	return size;
	958	}
	959
	960
	961
	962	int arcompact_handle0d_00_dasm(DASM_OPS_16)
	963	{
	964	int size = 2;
	965	print("ADD_S c <- b + u3 (%04x)", op);
	966	return size;
	967	}
	968
	969	int arcompact_handle0d_01_dasm(DASM_OPS_16)
	970	{
	971	int size = 2;
	972	print("SUB_S c <- b - u3 (%04x)", op);
	973	return size;
	974	}
	975
	976	int arcompact_handle0d_02_dasm(DASM_OPS_16)
	977	{
	978	int size = 2;
	979	print("ASL_S c <- b asl u3 (%04x)", op);
	980	return size;
	981	}
	982
	983	int arcompact_handle0d_03_dasm(DASM_OPS_16)
	984	{
	985	int size = 2;
	986	print("ASL_S c <- b asr u3 (%04x)", op);
	987	return size;
	988	}
	989
	990
	991
	992
	993
	994
	995	int arcompact_handle0e_00_dasm(DASM_OPS_16)
	996	{
	997	int h;
	998	int size = 2;
	999
	1000	GROUP_0e_GET_h;
	1001
	1002	if (h == LIMM_REG)
	1003	{
	1004	UINT32 limm;
	1005	GET_LIMM;
	1006	size = 6;
	1007	print("ADD_S b <- b + (%08x) (%04x)", limm, op);
	1008	}
	1009	else
	1010	{
	1011
	1012	print("ADD_S b <- b + (r%d) (%04x)", h, op);
	1013	}
	1014
	1015	return size;
	1016	}
	1017
	1018	int arcompact_handle0e_01_dasm(DASM_OPS_16)
	1019	{
	1020	int h;
	1021	int size = 2;
	1022	GROUP_0e_GET_h;
	1023
	1024	if (h == LIMM_REG)
	1025	{
	1026	UINT32 limm;
	1027	GET_LIMM;
	1028	size = 6;
	1029	print("MOV_S b <- (%08x)  (%04x)", limm, op);
	1030	}
	1031	else
	1032	{
	1033	print("MOV_S b <- (r%d)  (%04x)", h, op);
	1034	}
	1035	return size;
	1036	}
	1037
	1038	int arcompact_handle0e_02_dasm(DASM_OPS_16)
	1039	{
	1040	int h;
	1041	int size = 2;
	1042	GROUP_0e_GET_h;
	1043
	1044	if (h == LIMM_REG)
	1045	{
	1046	UINT32 limm;
	1047	GET_LIMM;
	1048	size = 6;
	1049	print("CMP_S b - (%08x) (%04x)", limm, op);
	1050	}
	1051	else
	1052	{
	1053	print("CMP_S b - (r%d) (%04x)", h, op);
	1054	}
	1055	return size;
	1056	}
	1057
	1058	int arcompact_handle0e_03_dasm(DASM_OPS_16)
	1059	{
	1060	int h;
	1061	int size = 2;
	1062	GROUP_0e_GET_h;
	1063
	1064	if (h == LIMM_REG)
	1065	{
	1066	UINT32 limm;
	1067	GET_LIMM;
	1068	size = 6;
	1069	print("MOV_S (%08x) <- b (%04x)", limm, op);
	1070	}
	1071	else
	1072	{
	1073	print("MOV_S (r%d) <- b (%04x)", h, op);
	1074	}
	1075
	1076	return size;
	1077	}
	1078
	1079
	1080
	1081
	1082
	1083	int arcompact_handle0f_00_00_dasm(DASM_OPS_16)  { print("J_S pc <- b (%08x)", op); return 2;}
	1084	int arcompact_handle0f_00_01_dasm(DASM_OPS_16)  { print("J_S.D pc <- b (%08x)", op); return 2;}
	1085	int arcompact_handle0f_00_02_dasm(DASM_OPS_16)  { print("JL_S blink <- pc; pc <- b (%08x)", op); return 2;}
	1086	int arcompact_handle0f_00_03_dasm(DASM_OPS_16)  { print("L_S.D blink <- pc; pc <- b( %08x)", op); return 2;}
	1087	int arcompact_handle0f_00_06_dasm(DASM_OPS_16)  { print("SUB_S.NE if (f.Z==0) b <- b - b  (%08x)", op); return 2;}
	1088
	1089
	1090
	1091
	1092
	1093	int arcompact_handle0f_00_07_00_dasm(DASM_OPS_16)  { print("NOP_S (%08x)", op); return 2;}
	1094	int arcompact_handle0f_00_07_01_dasm(DASM_OPS_16)  { print("UNIMP_S (%08x)", op); return 2;} // Unimplemented Instruction (how does this differ from illegal ops?)
	1095
	1096
	1097
	1098	int arcompact_handle0f_00_07_04_dasm(DASM_OPS_16)  { print("JEQ_S [blink] (%08x)", op); return 2;}
	1099	int arcompact_handle0f_00_07_05_dasm(DASM_OPS_16)  { print("JNE_S [blink]  (%08x)", op); return 2;}
	1100	int arcompact_handle0f_00_07_06_dasm(DASM_OPS_16)  { print("J_S [blink]  (%08x)", op); return 2;}
	1101	int arcompact_handle0f_00_07_07_dasm(DASM_OPS_16)  { print("J_S.D [blink] (%08x)", op); return 2;}
	1102
	1103
	1104	int arcompact_handle0f_02_dasm(DASM_OPS_16)  { print("SUB_S b <- b - c (%08x)", op); return 2;}
	1105
	1106
	1107	int arcompact_handle0f_04_dasm(DASM_OPS_16)  { print("AND_S b <- b and c (%08x)", op); return 2;}
	1108	int arcompact_handle0f_05_dasm(DASM_OPS_16)  { print("OR_S b <- b or c (%08x)", op); return 2;}
	1109	int arcompact_handle0f_06_dasm(DASM_OPS_16)  { print("BIC_S b <- b & !c (%08x)", op); return 2;}
	1110	int arcompact_handle0f_07_dasm(DASM_OPS_16)  { print("XOR_S b <- b ^ c (%08x)", op); return 2;}
	1111
	1112
	1113	int arcompact_handle0f_0b_dasm(DASM_OPS_16)  { print("TST_S b & c (%08x)", op); return 2;}
	1114	int arcompact_handle0f_0c_dasm(DASM_OPS_16)  { print("MUL64_S mulres <- b * c  (%08x)", op); return 2;}
	1115	int arcompact_handle0f_0d_dasm(DASM_OPS_16)  { print("SEXB_S b <- sexb(c) (%08x)", op); return 2;}
	1116	int arcompact_handle0f_0e_dasm(DASM_OPS_16)  { print("SEXW_S b <- sexw(c) (%08x)", op); return 2;}
	1117	int arcompact_handle0f_0f_dasm(DASM_OPS_16)  { print("EXTB_S b <- extb(c) (%08x)", op); return 2;}
	1118	int arcompact_handle0f_10_dasm(DASM_OPS_16)  { print("EXTW_S b <- extw(c) (%08x)", op); return 2;}
	1119	int arcompact_handle0f_11_dasm(DASM_OPS_16)  { print("ABS_S b <- abs(c)  (%08x)", op); return 2;}
	1120	int arcompact_handle0f_12_dasm(DASM_OPS_16)  { print("NOT_S b <- !(c) (%08x)", op); return 2;}
	1121	int arcompact_handle0f_13_dasm(DASM_OPS_16)  { print("NEG_S b <- neg(c)  (%08x)", op); return 2;}
	1122	int arcompact_handle0f_14_dasm(DASM_OPS_16)  { print("ADD1_S b <- b + (c << 1) (%08x)", op); return 2;}
	1123	int arcompact_handle0f_15_dasm(DASM_OPS_16)  { print("ADD2_S b <- b + (c << 2) (%08x)", op); return 2;}
	1124	int arcompact_handle0f_16_dasm(DASM_OPS_16)  { print("ADD3_S b <- b + (c << 3)  (%08x)", op); return 2;}
	1125
	1126
	1127	int arcompact_handle0f_18_dasm(DASM_OPS_16)  { print("ASL_S b <- b asl c (%08x)", op); return 2;}
	1128	int arcompact_handle0f_19_dasm(DASM_OPS_16)  { print("LSR_S b <- b lsr c (%08x)", op); return 2;}
	1129	int arcompact_handle0f_1a_dasm(DASM_OPS_16)  { print("ASR_S b <- b asr c (%08x)", op); return 2;}
	1130	int arcompact_handle0f_1b_dasm(DASM_OPS_16)  { print("ASL_S b <- c + c (%08x)", op); return 2;}
	1131	int arcompact_handle0f_1c_dasm(DASM_OPS_16)  { print("ASR_S b <- c asr 1 (%08x)", op); return 2;}
	1132	int arcompact_handle0f_1d_dasm(DASM_OPS_16)  { print("LSR_S b <- c lsr 1(%08x)", op); return 2;}
	1133	int arcompact_handle0f_1e_dasm(DASM_OPS_16)  { print("TRAP_S (%08x)", op); return 2;}
	1134	int arcompact_handle0f_1f_dasm(DASM_OPS_16)  { print("BRK_S (%08x)", op); return 2;}
	1135
	1136
	1137	int arcompact_handle10_dasm(DASM_OPS_16)
	1138	{
	1139	print("LD_S (%04x)",  op);
	1140	return 2;
	1141	}
	1142
	1143	int arcompact_handle11_dasm(DASM_OPS_16)
	1144	{
	1145	print("LDB_S (%04x)", op);
	1146	return 2;
	1147	}
	1148
	1149	int arcompact_handle12_dasm(DASM_OPS_16)
	1150	{
	1151	print("LDW_S (%04x)", op);
	1152	return 2;
	1153	}
	1154
	1155	int arcompact_handle13_dasm(DASM_OPS_16)
	1156	{
	1157	print("LSW_S.X (%04x)", op);
	1158	return 2;
	1159	}
	1160
	1161	int arcompact_handle14_dasm(DASM_OPS_16)
	1162	{
	1163	print("ST_S (%04x)", op);
	1164	return 2;
	1165	}
	1166
	1167	int arcompact_handle15_dasm(DASM_OPS_16)
	1168	{
	1169	print("STB_S (%04x)", op);
	1170	return 2;
	1171	}
	1172
	1173	int arcompact_handle16_dasm(DASM_OPS_16)
	1174	{
	1175	print("STW_S (%04x)",  op);
	1176	return 2;
	1177	}
	1178
	1179
	1180	int arcompact_handle17_00_dasm(DASM_OPS_16)
	1181	{
	1182	int size = 2;
	1183	print("ASL_S b <- b asl u5 (%04x)",  op);
	1184	return size;
	1185	}
	1186
	1187	int arcompact_handle17_01_dasm(DASM_OPS_16)
	1188	{
	1189	int size = 2;
	1190	print("LSR_S b <- b lsr u5 (%04x)",  op);
	1191	return size;
	1192	}
	1193
	1194	int arcompact_handle17_02_dasm(DASM_OPS_16)
	1195	{
	1196	int size = 2;
	1197	print("ASR_S b <- b asr u5 (%04x)",  op);
	1198	return size;
	1199	}
	1200
	1201	int arcompact_handle17_03_dasm(DASM_OPS_16)
	1202	{
	1203	int size = 2;
	1204	print("SUB_S b <- b - u5 (%04x)",  op);
	1205	return size;
	1206	}
	1207
	1208	int arcompact_handle17_04_dasm(DASM_OPS_16)
	1209	{
	1210	int size = 2;
	1211	print("BSET_S b <- b | (1 << u5) (%04x)",  op);
	1212	return size;
	1213	}
	1214
	1215	int arcompact_handle17_05_dasm(DASM_OPS_16)
	1216	{
	1217	int size = 2;
	1218	print("BCLR_S b <- b & !(1 << u5) (%04x)",  op);
	1219	return size;
	1220	}
	1221
	1222	int arcompact_handle17_06_dasm(DASM_OPS_16)
	1223	{
	1224	int size = 2;
	1225	print("BMSK_S (%04x)",  op);
	1226	return size;
	1227	}
	1228
	1229	int arcompact_handle17_07_dasm(DASM_OPS_16)
	1230	{
	1231	int size = 2;
	1232	print("BTST_S (%04x)",  op);
	1233	return size;
	1234	}
	1235
	1236
	1237	// op bits remaining for 0x18_xx subgroups 0x071f
	1238
	1239	int arcompact_handle18_00_dasm(DASM_OPS_16)
	1240	{
	1241	print("LD_S (SP) (%04x)",  op);
	1242	return 2;
	1243	}
	1244
	1245	int arcompact_handle18_01_dasm(DASM_OPS_16)
	1246	{
	1247	print("LDB_S (SP) (%04x)",  op);
	1248	return 2;
	1249	}
	1250
	1251	int arcompact_handle18_02_dasm(DASM_OPS_16)
	1252	{
	1253	print("ST_S (SP) (%04x)",  op);
	1254	return 2;
	1255	}
	1256
	1257	int arcompact_handle18_03_dasm(DASM_OPS_16)
	1258	{
	1259	print("STB_S (SP) (%04x)",  op);
	1260	return 2;
	1261	}
	1262
	1263	int arcompact_handle18_04_dasm(DASM_OPS_16)
	1264	{
	1265	print("ADD_S (SP) (%04x)",  op);
	1266	return 2;
	1267	}
	1268
	1269	// op bits remaining for 0x18_05_xx subgroups 0x001f
	1270	int arcompact_handle18_05_00_dasm(DASM_OPS_16)
	1271	{
	1272	int u = op & 0x001f;
	1273	op &= ~0x001f; // all bits now used
	1274
	1275	print("ADD_S %02x (SP)", u);
	1276	return 2;
	1277
	1278	}
	1279
	1280	int arcompact_handle18_05_01_dasm(DASM_OPS_16)
	1281	{
	1282	int u = op & 0x001f;
	1283	op &= ~0x001f; // all bits now used
	1284
	1285	print("SUB_S %02x (SP)", u);
	1286	return 2;
	1287	}
	1288
	1289	// op bits remaining for 0x18_06_xx subgroups 0x0700
	1290	int arcompact_handle18_06_01_dasm(DASM_OPS_16)
	1291	{
	1292	int b = (op & 0x0700) >> 8;
	1293	op &= ~0x0700; // all bits now used
	1294
	1295	print("POP_S [%02x]", b);
	1296
	1297	return 2;
	1298	}
	1299
	1300	int arcompact_handle18_06_11_dasm(DASM_OPS_16)
	1301	{
	1302	int res = (op & 0x0700) >> 8;
	1303	op &= ~0x0700; // all bits now used
	1304
	1305	if (res)
	1306	print("POP_S [BLINK] (Reserved Bits set %04x)", op);
	1307	else
	1308	print("POP_S [BLINK]");
	1309
	1310	return 2;
	1311	}
	1312
	1313	// op bits remaining for 0x18_07_xx subgroups 0x0700
	1314	int arcompact_handle18_07_01_dasm(DASM_OPS_16)
	1315	{
	1316	int b = (op & 0x0700) >> 8;
	1317	op &= ~0x0700; // all bits now used
	1318
	1319	print("PUSH_S [%02x]", b);
	1320
	1321	return 2;
	1322	}
	1323
	1324
	1325	int arcompact_handle18_07_11_dasm(DASM_OPS_16)
	1326	{
	1327	int res = (op & 0x0700) >> 8;
	1328	op &= ~0x0700; // all bits now used
	1329
	1330	if (res)
	1331	print("PUSH_S [BLINK] (Reserved Bits set %04x)", op);
	1332	else
	1333	print("PUSH_S [BLINK]");
	1334
	1335	return 2;
	1336	}
	1337
	1338	int arcompact_handle19_00_dasm(DASM_OPS_16)  { print("LD_S r0 <- m[GP + s11].long (%04x)",  op); return 2;}
	1339	int arcompact_handle19_01_dasm(DASM_OPS_16)  { print("LDB_S r0 <- m[GP + s9].byte (%04x)",  op); return 2;}
	1340	int arcompact_handle19_02_dasm(DASM_OPS_16)  { print("LDW_S r0 <- m[GP + s10].word (%04x)",  op); return 2;}
	1341	int arcompact_handle19_03_dasm(DASM_OPS_16)  { print("ADD_S r0 <- GP + s11 (%04x)",  op); return 2;}
	1342
	1343	int arcompact_handle1a_dasm(DASM_OPS_16)
	1344	{
	1345	print("PCL Instr (%04x)", op);
	1346	return 2;
	1347	}
	1348
	1349	int arcompact_handle1b_dasm(DASM_OPS_16)
	1350	{
	1351	print("MOV_S (%04x)", op);
	1352	return 2;
	1353	}
	1354
	1355	int arcompact_handle1c_00_dasm(DASM_OPS_16)  { print("ADD_S b <- b + u7 (%04x)",  op); return 2;}
	1356	int arcompact_handle1c_01_dasm(DASM_OPS_16)  { print("CMP_S b - u7 (%04x)",  op); return 2;}
	1357
	1358
	1359	int arcompact_handle1d_00_dasm(DASM_OPS_16)  { print("BREQ_S (%04x)",  op); return 2;}
	1360	int arcompact_handle1d_01_dasm(DASM_OPS_16)  { print("BRNE_S (%04x)",  op); return 2;}
	1361
	1362
	1363	int arcompact_handle1e_00_dasm(DASM_OPS_16)  { print("B_S (%04x)",  op); return 2;}
	1364	int arcompact_handle1e_01_dasm(DASM_OPS_16)  { print("BEQ_S (%04x)",  op); return 2;}
	1365	int arcompact_handle1e_02_dasm(DASM_OPS_16)  { print("BNE_S (%04x)",  op); return 2;}
	1366
	1367	int arcompact_handle1e_03_00_dasm(DASM_OPS_16)  { print("BGT_S (%04x)",  op); return 2;}
	1368	int arcompact_handle1e_03_01_dasm(DASM_OPS_16)  { print("BGE_S (%04x)",  op); return 2;}
	1369	int arcompact_handle1e_03_02_dasm(DASM_OPS_16)  { print("BLT_S (%04x)",  op); return 2;}
	1370	int arcompact_handle1e_03_03_dasm(DASM_OPS_16)  { print("BLE_S (%04x)",  op); return 2;}
	1371	int arcompact_handle1e_03_04_dasm(DASM_OPS_16)  { print("BHI_S (%04x)",  op); return 2;}
	1372	int arcompact_handle1e_03_05_dasm(DASM_OPS_16)  { print("BHS_S (%04x)",  op); return 2;}
	1373	int arcompact_handle1e_03_06_dasm(DASM_OPS_16)  { print("BLO_S (%04x)",  op); return 2;}
	1374	int arcompact_handle1e_03_07_dasm(DASM_OPS_16)  { print("BLS_S (%04x)",  op); return 2;}
	1375
	1376	int arcompact_handle1f_dasm(DASM_OPS_16)
	1377	{
	1378	print("BL_S (%04x)", op);
	1379	return 2;
	1380	}
	1381
	1382	/************************************************************************************************************************************
	1383	*                                                                                                                                   *
	1384	* illegal opcode handlers (disassembly)                                                                                             *
	1385	*                                                                                                                                   *
	1386	************************************************************************************************************************************/
	1387
	1388	int arcompact_handle01_01_00_06_dasm(DASM_OPS_32)  { print("<illegal 01_01_00_06> (%08x)", op); return 4; }
	1389	int arcompact_handle01_01_00_07_dasm(DASM_OPS_32)  { print("<illegal 01_01_00_07> (%08x)", op); return 4; }
	1390	int arcompact_handle01_01_00_08_dasm(DASM_OPS_32)  { print("<illegal 01_01_00_08> (%08x)", op); return 4; }
	1391	int arcompact_handle01_01_00_09_dasm(DASM_OPS_32)  { print("<illegal 01_01_00_09> (%08x)", op); return 4; }
	1392	int arcompact_handle01_01_00_0a_dasm(DASM_OPS_32)  { print("<illegal 01_01_00_0a> (%08x)", op); return 4; }
	1393	int arcompact_handle01_01_00_0b_dasm(DASM_OPS_32)  { print("<illegal 01_01_00_0b> (%08x)", op); return 4; }
	1394	int arcompact_handle01_01_00_0c_dasm(DASM_OPS_32)  { print("<illegal 01_01_00_0c> (%08x)", op); return 4; }
	1395	int arcompact_handle01_01_00_0d_dasm(DASM_OPS_32)  { print("<illegal 01_01_00_0d> (%08x)", op); return 4; }
	1396
	1397	int arcompact_handle01_01_01_06_dasm(DASM_OPS_32)  { print("<illegal 01_01_01_06> (%08x)", op); return 4; }
	1398	int arcompact_handle01_01_01_07_dasm(DASM_OPS_32)  { print("<illegal 01_01_01_07> (%08x)", op); return 4; }
	1399	int arcompact_handle01_01_01_08_dasm(DASM_OPS_32)  { print("<illegal 01_01_01_08> (%08x)", op); return 4; }
	1400	int arcompact_handle01_01_01_09_dasm(DASM_OPS_32)  { print("<illegal 01_01_01_09> (%08x)", op); return 4; }
	1401	int arcompact_handle01_01_01_0a_dasm(DASM_OPS_32)  { print("<illegal 01_01_01_0a> (%08x)", op); return 4; }
	1402	int arcompact_handle01_01_01_0b_dasm(DASM_OPS_32)  { print("<illegal 01_01_01_0b> (%08x)", op); return 4; }
	1403	int arcompact_handle01_01_01_0c_dasm(DASM_OPS_32)  { print("<illegal 01_01_01_0c> (%08x)", op); return 4; }
	1404	int arcompact_handle01_01_01_0d_dasm(DASM_OPS_32)  { print("<illegal 01_01_01_0d> (%08x)", op); return 4; }
	1405
	1406
	1407	int arcompact_handle04_1e_dasm(DASM_OPS_32)  { print("<illegal 0x04_1e> (%08x)", op); return 4;}
	1408	int arcompact_handle04_1f_dasm(DASM_OPS_32)  { print("<illegal 0x04_1f> (%08x)", op); return 4;}
	1409
	1410	int arcompact_handle04_24_dasm(DASM_OPS_32)  { print("<illegal 0x04_24> (%08x)", op); return 4;}
	1411	int arcompact_handle04_25_dasm(DASM_OPS_32)  { print("<illegal 0x04_25> (%08x)", op); return 4;}
	1412	int arcompact_handle04_26_dasm(DASM_OPS_32)  { print("<illegal 0x04_26> (%08x)", op); return 4;}
	1413	int arcompact_handle04_27_dasm(DASM_OPS_32)  { print("<illegal 0x04_27> (%08x)", op); return 4;}
	1414
	1415	int arcompact_handle04_2c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2c> (%08x)", op); return 4;}
	1416	int arcompact_handle04_2d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2d> (%08x)", op); return 4;}
	1417	int arcompact_handle04_2e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2e> (%08x)", op); return 4;}
	1418
	1419	int arcompact_handle04_2f_0d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_0d> (%08x)", op); return 4;}
	1420	int arcompact_handle04_2f_0e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_0e> (%08x)", op); return 4;}
	1421	int arcompact_handle04_2f_0f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_0f> (%08x)", op); return 4;}
	1422	int arcompact_handle04_2f_10_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_10> (%08x)", op); return 4;}
	1423	int arcompact_handle04_2f_11_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_11> (%08x)", op); return 4;}
	1424	int arcompact_handle04_2f_12_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_12> (%08x)", op); return 4;}
	1425	int arcompact_handle04_2f_13_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_13> (%08x)", op); return 4;}
	1426	int arcompact_handle04_2f_14_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_14> (%08x)", op); return 4;}
	1427	int arcompact_handle04_2f_15_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_15> (%08x)", op); return 4;}
	1428	int arcompact_handle04_2f_16_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_16> (%08x)", op); return 4;}
	1429	int arcompact_handle04_2f_17_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_17> (%08x)", op); return 4;}
	1430	int arcompact_handle04_2f_18_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_18> (%08x)", op); return 4;}
	1431	int arcompact_handle04_2f_19_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_19> (%08x)", op); return 4;}
	1432	int arcompact_handle04_2f_1a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1a> (%08x)", op); return 4;}
	1433	int arcompact_handle04_2f_1b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1b> (%08x)", op); return 4;}
	1434	int arcompact_handle04_2f_1c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1c> (%08x)", op); return 4;}
	1435	int arcompact_handle04_2f_1d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1d> (%08x)", op); return 4;}
	1436	int arcompact_handle04_2f_1e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1e> (%08x)", op); return 4;}
	1437	int arcompact_handle04_2f_1f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_1f> (%08x)", op); return 4;}
	1438	int arcompact_handle04_2f_20_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_20> (%08x)", op); return 4;}
	1439	int arcompact_handle04_2f_21_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_21> (%08x)", op); return 4;}
	1440	int arcompact_handle04_2f_22_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_22> (%08x)", op); return 4;}
	1441	int arcompact_handle04_2f_23_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_23> (%08x)", op); return 4;}
	1442	int arcompact_handle04_2f_24_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_24> (%08x)", op); return 4;}
	1443	int arcompact_handle04_2f_25_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_25> (%08x)", op); return 4;}
	1444	int arcompact_handle04_2f_26_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_26> (%08x)", op); return 4;}
	1445	int arcompact_handle04_2f_27_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_27> (%08x)", op); return 4;}
	1446	int arcompact_handle04_2f_28_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_28> (%08x)", op); return 4;}
	1447	int arcompact_handle04_2f_29_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_29> (%08x)", op); return 4;}
	1448	int arcompact_handle04_2f_2a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2a> (%08x)", op); return 4;}
	1449	int arcompact_handle04_2f_2b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2b> (%08x)", op); return 4;}
	1450	int arcompact_handle04_2f_2c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2c> (%08x)", op); return 4;}
	1451	int arcompact_handle04_2f_2d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2d> (%08x)", op); return 4;}
	1452	int arcompact_handle04_2f_2e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2e> (%08x)", op); return 4;}
	1453	int arcompact_handle04_2f_2f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_2f> (%08x)", op); return 4;}
	1454	int arcompact_handle04_2f_30_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_30> (%08x)", op); return 4;}
	1455	int arcompact_handle04_2f_31_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_31> (%08x)", op); return 4;}
	1456	int arcompact_handle04_2f_32_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_32> (%08x)", op); return 4;}
	1457	int arcompact_handle04_2f_33_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_33> (%08x)", op); return 4;}
	1458	int arcompact_handle04_2f_34_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_34> (%08x)", op); return 4;}
	1459	int arcompact_handle04_2f_35_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_35> (%08x)", op); return 4;}
	1460	int arcompact_handle04_2f_36_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_36> (%08x)", op); return 4;}
	1461	int arcompact_handle04_2f_37_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_37> (%08x)", op); return 4;}
	1462	int arcompact_handle04_2f_38_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_38> (%08x)", op); return 4;}
	1463	int arcompact_handle04_2f_39_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_39> (%08x)", op); return 4;}
	1464	int arcompact_handle04_2f_3a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3a> (%08x)", op); return 4;}
	1465	int arcompact_handle04_2f_3b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3b> (%08x)", op); return 4;}
	1466	int arcompact_handle04_2f_3c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3c> (%08x)", op); return 4;}
	1467	int arcompact_handle04_2f_3d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3d> (%08x)", op); return 4;}
	1468	int arcompact_handle04_2f_3e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3e> (%08x)", op); return 4;}
	1469
	1470	int arcompact_handle04_2f_3f_00_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_00> (%08x)", op); return 4;}
	1471	int arcompact_handle04_2f_3f_06_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_06> (%08x)", op); return 4;}
	1472	int arcompact_handle04_2f_3f_07_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_07> (%08x)", op); return 4;}
	1473	int arcompact_handle04_2f_3f_08_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_08> (%08x)", op); return 4;}
	1474	int arcompact_handle04_2f_3f_09_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_09> (%08x)", op); return 4;}
	1475	int arcompact_handle04_2f_3f_0a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0a> (%08x)", op); return 4;}
	1476	int arcompact_handle04_2f_3f_0b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0b> (%08x)", op); return 4;}
	1477	int arcompact_handle04_2f_3f_0c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0c> (%08x)", op); return 4;}
	1478	int arcompact_handle04_2f_3f_0d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0d> (%08x)", op); return 4;}
	1479	int arcompact_handle04_2f_3f_0e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0e> (%08x)", op); return 4;}
	1480	int arcompact_handle04_2f_3f_0f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_0f> (%08x)", op); return 4;}
	1481	int arcompact_handle04_2f_3f_10_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_10> (%08x)", op); return 4;}
	1482	int arcompact_handle04_2f_3f_11_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_11> (%08x)", op); return 4;}
	1483	int arcompact_handle04_2f_3f_12_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_12> (%08x)", op); return 4;}
	1484	int arcompact_handle04_2f_3f_13_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_13> (%08x)", op); return 4;}
	1485	int arcompact_handle04_2f_3f_14_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_14> (%08x)", op); return 4;}
	1486	int arcompact_handle04_2f_3f_15_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_15> (%08x)", op); return 4;}
	1487	int arcompact_handle04_2f_3f_16_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_16> (%08x)", op); return 4;}
	1488	int arcompact_handle04_2f_3f_17_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_17> (%08x)", op); return 4;}
	1489	int arcompact_handle04_2f_3f_18_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_18> (%08x)", op); return 4;}
	1490	int arcompact_handle04_2f_3f_19_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_19> (%08x)", op); return 4;}
	1491	int arcompact_handle04_2f_3f_1a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1a> (%08x)", op); return 4;}
	1492	int arcompact_handle04_2f_3f_1b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1b> (%08x)", op); return 4;}
	1493	int arcompact_handle04_2f_3f_1c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1c> (%08x)", op); return 4;}
	1494	int arcompact_handle04_2f_3f_1d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1d> (%08x)", op); return 4;}
	1495	int arcompact_handle04_2f_3f_1e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1e> (%08x)", op); return 4;}
	1496	int arcompact_handle04_2f_3f_1f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_1f> (%08x)", op); return 4;}
	1497	int arcompact_handle04_2f_3f_20_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_20> (%08x)", op); return 4;}
	1498	int arcompact_handle04_2f_3f_21_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_21> (%08x)", op); return 4;}
	1499	int arcompact_handle04_2f_3f_22_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_22> (%08x)", op); return 4;}
	1500	int arcompact_handle04_2f_3f_23_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_23> (%08x)", op); return 4;}
	1501	int arcompact_handle04_2f_3f_24_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_24> (%08x)", op); return 4;}
	1502	int arcompact_handle04_2f_3f_25_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_25> (%08x)", op); return 4;}
	1503	int arcompact_handle04_2f_3f_26_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_26> (%08x)", op); return 4;}
	1504	int arcompact_handle04_2f_3f_27_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_27> (%08x)", op); return 4;}
	1505	int arcompact_handle04_2f_3f_28_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_28> (%08x)", op); return 4;}
	1506	int arcompact_handle04_2f_3f_29_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_29> (%08x)", op); return 4;}
	1507	int arcompact_handle04_2f_3f_2a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2a> (%08x)", op); return 4;}
	1508	int arcompact_handle04_2f_3f_2b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2b> (%08x)", op); return 4;}
	1509	int arcompact_handle04_2f_3f_2c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2c> (%08x)", op); return 4;}
	1510	int arcompact_handle04_2f_3f_2d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2d> (%08x)", op); return 4;}
	1511	int arcompact_handle04_2f_3f_2e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2e> (%08x)", op); return 4;}
	1512	int arcompact_handle04_2f_3f_2f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_2f> (%08x)", op); return 4;}
	1513	int arcompact_handle04_2f_3f_30_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_30> (%08x)", op); return 4;}
	1514	int arcompact_handle04_2f_3f_31_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_31> (%08x)", op); return 4;}
	1515	int arcompact_handle04_2f_3f_32_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_32> (%08x)", op); return 4;}
	1516	int arcompact_handle04_2f_3f_33_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_33> (%08x)", op); return 4;}
	1517	int arcompact_handle04_2f_3f_34_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_34> (%08x)", op); return 4;}
	1518	int arcompact_handle04_2f_3f_35_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_35> (%08x)", op); return 4;}
	1519	int arcompact_handle04_2f_3f_36_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_36> (%08x)", op); return 4;}
	1520	int arcompact_handle04_2f_3f_37_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_37> (%08x)", op); return 4;}
	1521	int arcompact_handle04_2f_3f_38_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_38> (%08x)", op); return 4;}
	1522	int arcompact_handle04_2f_3f_39_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_39> (%08x)", op); return 4;}
	1523	int arcompact_handle04_2f_3f_3a_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3a> (%08x)", op); return 4;}
	1524	int arcompact_handle04_2f_3f_3b_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3b> (%08x)", op); return 4;}
	1525	int arcompact_handle04_2f_3f_3c_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3c> (%08x)", op); return 4;}
	1526	int arcompact_handle04_2f_3f_3d_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3d> (%08x)", op); return 4;}
	1527	int arcompact_handle04_2f_3f_3e_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3e> (%08x)", op); return 4;}
	1528	int arcompact_handle04_2f_3f_3f_dasm(DASM_OPS_32)  { print("<illegal 0x04_2f_3f_3f> (%08x)", op); return 4;}
	1529
	1530
	1531
	1532
	1533	int arcompact_handle04_38_dasm(DASM_OPS_32)  { print("<illegal 0x04_38> (%08x)", op); return 4;}
	1534	int arcompact_handle04_39_dasm(DASM_OPS_32)  { print("<illegal 0x04_39> (%08x)", op); return 4;}
	1535	int arcompact_handle04_3a_dasm(DASM_OPS_32)  { print("<illegal 0x04_3a> (%08x)", op); return 4;}
	1536	int arcompact_handle04_3b_dasm(DASM_OPS_32)  { print("<illegal 0x04_3b> (%08x)", op); return 4;}
	1537	int arcompact_handle04_3c_dasm(DASM_OPS_32)  { print("<illegal 0x04_3c> (%08x)", op); return 4;}
	1538	int arcompact_handle04_3d_dasm(DASM_OPS_32)  { print("<illegal 0x04_3d> (%08x)", op); return 4;}
	1539	int arcompact_handle04_3e_dasm(DASM_OPS_32)  { print("<illegal 0x04_3e> (%08x)", op); return 4;}
	1540	int arcompact_handle04_3f_dasm(DASM_OPS_32)  { print("<illegal 0x04_3f> (%08x)", op); return 4;}
	1541
	1542
	1543	int arcompact_handle05_09_dasm(DASM_OPS_32)  { print("<illegal 0x05_09> (%08x)", op); return 4;}
	1544	int arcompact_handle05_0c_dasm(DASM_OPS_32)  { print("<illegal 0x05_0c> (%08x)", op); return 4;}
	1545	int arcompact_handle05_0d_dasm(DASM_OPS_32)  { print("<illegal 0x05_0d> (%08x)", op); return 4;}
	1546	int arcompact_handle05_0e_dasm(DASM_OPS_32)  { print("<illegal 0x05_0e> (%08x)", op); return 4;}
	1547	int arcompact_handle05_0f_dasm(DASM_OPS_32)  { print("<illegal 0x05_0f> (%08x)", op); return 4;}
	1548	int arcompact_handle05_10_dasm(DASM_OPS_32)  { print("<illegal 0x05_10> (%08x)", op); return 4;}
	1549	int arcompact_handle05_11_dasm(DASM_OPS_32)  { print("<illegal 0x05_11> (%08x)", op); return 4;}
	1550	int arcompact_handle05_12_dasm(DASM_OPS_32)  { print("<illegal 0x05_12> (%08x)", op); return 4;}
	1551	int arcompact_handle05_13_dasm(DASM_OPS_32)  { print("<illegal 0x05_13> (%08x)", op); return 4;}
	1552	int arcompact_handle05_14_dasm(DASM_OPS_32)  { print("<illegal 0x05_14> (%08x)", op); return 4;}
	1553	int arcompact_handle05_15_dasm(DASM_OPS_32)  { print("<illegal 0x05_15> (%08x)", op); return 4;}
	1554	int arcompact_handle05_16_dasm(DASM_OPS_32)  { print("<illegal 0x05_16> (%08x)", op); return 4;}
	1555	int arcompact_handle05_17_dasm(DASM_OPS_32)  { print("<illegal 0x05_17> (%08x)", op); return 4;}
	1556	int arcompact_handle05_18_dasm(DASM_OPS_32)  { print("<illegal 0x05_18> (%08x)", op); return 4;}
	1557	int arcompact_handle05_19_dasm(DASM_OPS_32)  { print("<illegal 0x05_19> (%08x)", op); return 4;}
	1558	int arcompact_handle05_1a_dasm(DASM_OPS_32)  { print("<illegal 0x05_1a> (%08x)", op); return 4;}
	1559	int arcompact_handle05_1b_dasm(DASM_OPS_32)  { print("<illegal 0x05_1b> (%08x)", op); return 4;}
	1560	int arcompact_handle05_1c_dasm(DASM_OPS_32)  { print("<illegal 0x05_1c> (%08x)", op); return 4;}
	1561	int arcompact_handle05_1d_dasm(DASM_OPS_32)  { print("<illegal 0x05_1d> (%08x)", op); return 4;}
	1562	int arcompact_handle05_1e_dasm(DASM_OPS_32)  { print("<illegal 0x05_1e> (%08x)", op); return 4;}
	1563	int arcompact_handle05_1f_dasm(DASM_OPS_32)  { print("<illegal 0x05_1f> (%08x)", op); return 4;}
	1564	int arcompact_handle05_20_dasm(DASM_OPS_32)  { print("<illegal 0x05_20> (%08x)", op); return 4;}
	1565	int arcompact_handle05_21_dasm(DASM_OPS_32)  { print("<illegal 0x05_21> (%08x)", op); return 4;}
	1566	int arcompact_handle05_22_dasm(DASM_OPS_32)  { print("<illegal 0x05_22> (%08x)", op); return 4;}
	1567	int arcompact_handle05_23_dasm(DASM_OPS_32)  { print("<illegal 0x05_23> (%08x)", op); return 4;}
	1568	int arcompact_handle05_24_dasm(DASM_OPS_32)  { print("<illegal 0x05_24> (%08x)", op); return 4;}
	1569	int arcompact_handle05_25_dasm(DASM_OPS_32)  { print("<illegal 0x05_25> (%08x)", op); return 4;}
	1570	int arcompact_handle05_26_dasm(DASM_OPS_32)  { print("<illegal 0x05_26> (%08x)", op); return 4;}
	1571	int arcompact_handle05_27_dasm(DASM_OPS_32)  { print("<illegal 0x05_27> (%08x)", op); return 4;}
	1572
	1573	int arcompact_handle05_2a_dasm(DASM_OPS_32)  { print("<illegal 0x05_2a> (%08x)", op); return 4;}
	1574	int arcompact_handle05_2b_dasm(DASM_OPS_32)  { print("<illegal 0x05_2b> (%08x)", op); return 4;}
	1575	int arcompact_handle05_2c_dasm(DASM_OPS_32)  { print("<illegal 0x05_2c> (%08x)", op); return 4;}
	1576	int arcompact_handle05_2d_dasm(DASM_OPS_32)  { print("<illegal 0x05_2d> (%08x)", op); return 4;}
	1577	int arcompact_handle05_2e_dasm(DASM_OPS_32)  { print("<illegal 0x05_2e> (%08x)", op); return 4;}
	1578
	1579	int arcompact_handle05_30_dasm(DASM_OPS_32)  { print("<illegal 0x05_30> (%08x)", op); return 4;}
	1580	int arcompact_handle05_31_dasm(DASM_OPS_32)  { print("<illegal 0x05_31> (%08x)", op); return 4;}
	1581	int arcompact_handle05_32_dasm(DASM_OPS_32)  { print("<illegal 0x05_32> (%08x)", op); return 4;}
	1582	int arcompact_handle05_33_dasm(DASM_OPS_32)  { print("<illegal 0x05_33> (%08x)", op); return 4;}
	1583	int arcompact_handle05_34_dasm(DASM_OPS_32)  { print("<illegal 0x05_34> (%08x)", op); return 4;}
	1584	int arcompact_handle05_35_dasm(DASM_OPS_32)  { print("<illegal 0x05_35> (%08x)", op); return 4;}
	1585	int arcompact_handle05_36_dasm(DASM_OPS_32)  { print("<illegal 0x05_36> (%08x)", op); return 4;}
	1586	int arcompact_handle05_37_dasm(DASM_OPS_32)  { print("<illegal 0x05_37> (%08x)", op); return 4;}
	1587	int arcompact_handle05_38_dasm(DASM_OPS_32)  { print("<illegal 0x05_38> (%08x)", op); return 4;}
	1588	int arcompact_handle05_39_dasm(DASM_OPS_32)  { print("<illegal 0x05_39> (%08x)", op); return 4;}
	1589	int arcompact_handle05_3a_dasm(DASM_OPS_32)  { print("<illegal 0x05_3a> (%08x)", op); return 4;}
	1590	int arcompact_handle05_3b_dasm(DASM_OPS_32)  { print("<illegal 0x05_3b> (%08x)", op); return 4;}
	1591	int arcompact_handle05_3c_dasm(DASM_OPS_32)  { print("<illegal 0x05_3c> (%08x)", op); return 4;}
	1592	int arcompact_handle05_3d_dasm(DASM_OPS_32)  { print("<illegal 0x05_3d> (%08x)", op); return 4;}
	1593	int arcompact_handle05_3e_dasm(DASM_OPS_32)  { print("<illegal 0x05_3e> (%08x)", op); return 4;}
	1594	int arcompact_handle05_3f_dasm(DASM_OPS_32)  { print("<illegal 0x05_3f> (%08x)", op); return 4;}
	1595
	1596	int arcompact_handle0f_00_04_dasm(DASM_OPS_16)  { print("<illegal 0x0f_00_00> (%08x)", op); return 2;}
	1597	int arcompact_handle0f_00_05_dasm(DASM_OPS_16)  { print("<illegal 0x0f_00_00> (%08x)", op); return 2;}
	1598	int arcompact_handle0f_00_07_02_dasm(DASM_OPS_16)  { print("<illegal 0x0f_00_07_02> (%08x)", op); return 2;}
	1599	int arcompact_handle0f_00_07_03_dasm(DASM_OPS_16)  { print("<illegal 0x0f_00_07_03> (%08x)", op); return 2;}
	1600	int arcompact_handle0f_01_dasm(DASM_OPS_16)  { print("<illegal 0x0f_01> (%08x)", op); return 2;}
	1601	int arcompact_handle0f_03_dasm(DASM_OPS_16)  { print("<illegal 0x0f_03> (%08x)", op); return 2;}
	1602	int arcompact_handle0f_08_dasm(DASM_OPS_16)  { print("<illegal 0x0f_08> (%08x)", op); return 2;}
	1603	int arcompact_handle0f_09_dasm(DASM_OPS_16)  { print("<illegal 0x0f_09> (%08x)", op); return 2;}
	1604	int arcompact_handle0f_0a_dasm(DASM_OPS_16)  { print("<illegal 0x0f_0a> (%08x)", op); return 2;}
	1605	int arcompact_handle0f_17_dasm(DASM_OPS_16)  { print("<illegal 0x0f_17> (%08x)", op); return 2;}
	1606
	1607	int arcompact_handle18_05_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_02> (%04x)", op); return 2;}
	1608	int arcompact_handle18_05_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_03> (%04x)", op); return 2;}
	1609	int arcompact_handle18_05_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_04> (%04x)", op); return 2;}
	1610	int arcompact_handle18_05_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_05> (%04x)", op); return 2;}
	1611	int arcompact_handle18_05_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_06> (%04x)", op); return 2;}
	1612	int arcompact_handle18_05_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_07> (%04x)", op); return 2;}
	1613	int arcompact_handle18_06_00_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_00> (%04x)",  op); return 2;}
	1614	int arcompact_handle18_06_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_02> (%04x)", op); return 2;}
	1615	int arcompact_handle18_06_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_03> (%04x)", op); return 2;}
	1616	int arcompact_handle18_06_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_04> (%04x)", op); return 2;}
	1617	int arcompact_handle18_06_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_05> (%04x)", op); return 2;}
	1618	int arcompact_handle18_06_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_06> (%04x)", op); return 2;}
	1619	int arcompact_handle18_06_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_07> (%04x)", op); return 2;}
	1620	int arcompact_handle18_06_08_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_08> (%04x)", op); return 2;}
	1621	int arcompact_handle18_06_09_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_09> (%04x)", op); return 2;}
	1622	int arcompact_handle18_06_0a_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0a> (%04x)", op); return 2;}
	1623	int arcompact_handle18_06_0b_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0b> (%04x)", op); return 2;}
	1624	int arcompact_handle18_06_0c_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0c> (%04x)", op); return 2;}
	1625	int arcompact_handle18_06_0d_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0d> (%04x)", op); return 2;}
	1626	int arcompact_handle18_06_0e_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0e> (%04x)", op); return 2;}
	1627	int arcompact_handle18_06_0f_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0f> (%04x)", op); return 2;}
	1628	int arcompact_handle18_06_10_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_10> (%04x)", op); return 2;}
	1629	int arcompact_handle18_06_12_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_12> (%04x)",  op); return 2;}
	1630	int arcompact_handle18_06_13_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_13> (%04x)",  op); return 2;}
	1631	int arcompact_handle18_06_14_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_14> (%04x)",  op); return 2;}
	1632	int arcompact_handle18_06_15_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_15> (%04x)",  op); return 2;}
	1633	int arcompact_handle18_06_16_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_16> (%04x)",  op); return 2;}
	1634	int arcompact_handle18_06_17_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_17> (%04x)",  op); return 2;}
	1635	int arcompact_handle18_06_18_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_18> (%04x)",  op); return 2;}
	1636	int arcompact_handle18_06_19_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_19> (%04x)",  op); return 2;}
	1637	int arcompact_handle18_06_1a_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1a> (%04x)",  op); return 2;}
	1638	int arcompact_handle18_06_1b_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1b> (%04x)",  op); return 2;}
	1639	int arcompact_handle18_06_1c_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1c> (%04x)",  op); return 2;}
	1640	int arcompact_handle18_06_1d_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1d> (%04x)",  op); return 2;}
	1641	int arcompact_handle18_06_1e_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1e> (%04x)",  op); return 2;}
	1642	int arcompact_handle18_06_1f_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1f> (%04x)",  op); return 2;}
	1643	int arcompact_handle18_07_00_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_00> (%04x)",  op); return 2;}
	1644	int arcompact_handle18_07_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_02> (%04x)", op); return 2;}
	1645	int arcompact_handle18_07_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_03> (%04x)", op); return 2;}
	1646	int arcompact_handle18_07_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_04> (%04x)", op); return 2;}
	1647	int arcompact_handle18_07_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_05> (%04x)", op); return 2;}
	1648	int arcompact_handle18_07_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_06> (%04x)", op); return 2;}
	1649	int arcompact_handle18_07_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_07> (%04x)", op); return 2;}
	1650	int arcompact_handle18_07_08_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_08> (%04x)", op); return 2;}
	1651	int arcompact_handle18_07_09_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_09> (%04x)", op); return 2;}
	1652	int arcompact_handle18_07_0a_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0a> (%04x)", op); return 2;}
	1653	int arcompact_handle18_07_0b_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0b> (%04x)", op); return 2;}
	1654	int arcompact_handle18_07_0c_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0c> (%04x)", op); return 2;}
	1655	int arcompact_handle18_07_0d_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0d> (%04x)", op); return 2;}
	1656	int arcompact_handle18_07_0e_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0e> (%04x)", op); return 2;}
	1657	int arcompact_handle18_07_0f_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0f> (%04x)", op); return 2;}
	1658	int arcompact_handle18_07_10_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_10> (%04x)", op); return 2;}
	1659	int arcompact_handle18_07_12_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_12> (%04x)",  op); return 2;}
	1660	int arcompact_handle18_07_13_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_13> (%04x)",  op); return 2;}
	1661	int arcompact_handle18_07_14_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_14> (%04x)",  op); return 2;}
	1662	int arcompact_handle18_07_15_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_15> (%04x)",  op); return 2;}
	1663	int arcompact_handle18_07_16_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_16> (%04x)",  op); return 2;}
	1664	int arcompact_handle18_07_17_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_17> (%04x)",  op); return 2;}
	1665	int arcompact_handle18_07_18_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_18> (%04x)",  op); return 2;}
	1666	int arcompact_handle18_07_19_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_19> (%04x)",  op); return 2;}
	1667	int arcompact_handle18_07_1a_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1a> (%04x)",  op); return 2;}
	1668	int arcompact_handle18_07_1b_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1b> (%04x)",  op); return 2;}
	1669	int arcompact_handle18_07_1c_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1c> (%04x)",  op); return 2;}
	1670	int arcompact_handle18_07_1d_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1d> (%04x)",  op); return 2;}
	1671	int arcompact_handle18_07_1e_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1e> (%04x)",  op); return 2;}
	1672	int arcompact_handle18_07_1f_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1f> (%04x)",  op); return 2;}
	1673

trunk/src/emu/cpu/arcompact/arcompactdasm_ops.h

r0	r242414
	1
	2	/************************************************************************************************************************************
	3	*                                                                                                                                   *
	4	* individual opcode handlers (disassembly)                                                                                          *
	5	*                                                                                                                                   *
	6	************************************************************************************************************************************/
	7
	8	#define DASM_OPS_16 char *output, offs_t pc, UINT16 op, const UINT8* oprom
	9	#define DASM_OPS_32 char *output, offs_t pc, UINT32 op, const UINT8* oprom
	10	#define DASM_PARAMS output, pc, op, oprom
	11
	12	#define LIMM_REG 62
	13
	14	#define GET_LIMM_32 \
	15	limm = oprom[6] | (oprom[7] << 8); \
	16	limm |= (oprom[4] << 16) | (oprom[5] << 24); \
	17
	18
	19	int arcompact_handle00_00_dasm(DASM_OPS_32);
	20	int arcompact_handle00_01_dasm(DASM_OPS_32);
	21	int arcompact_handle01_00_00dasm(DASM_OPS_32);
	22	int arcompact_handle01_00_01dasm(DASM_OPS_32);
	23	int arcompact_handle01_01_00_00_dasm(DASM_OPS_32);
	24	int arcompact_handle01_01_00_01_dasm(DASM_OPS_32);
	25	int arcompact_handle01_01_00_02_dasm(DASM_OPS_32);
	26	int arcompact_handle01_01_00_03_dasm(DASM_OPS_32);
	27	int arcompact_handle01_01_00_04_dasm(DASM_OPS_32);
	28	int arcompact_handle01_01_00_05_dasm(DASM_OPS_32);
	29	int arcompact_handle01_01_00_0e_dasm(DASM_OPS_32);
	30	int arcompact_handle01_01_00_0f_dasm(DASM_OPS_32);
	31	int arcompact_handle01_01_01_00_dasm(DASM_OPS_32);
	32	int arcompact_handle01_01_01_01_dasm(DASM_OPS_32);
	33	int arcompact_handle01_01_01_02_dasm(DASM_OPS_32);
	34	int arcompact_handle01_01_01_03_dasm(DASM_OPS_32);
	35	int arcompact_handle01_01_01_04_dasm(DASM_OPS_32);
	36	int arcompact_handle01_01_01_05_dasm(DASM_OPS_32);
	37	int arcompact_handle01_01_01_0e_dasm(DASM_OPS_32);
	38	int arcompact_handle01_01_01_0f_dasm(DASM_OPS_32);
	39	int arcompact_handle02_dasm(DASM_OPS_32);
	40	int arcompact_handle03_dasm(DASM_OPS_32);
	41	int arcompact_handle04_00_dasm(DASM_OPS_32);
	42	int arcompact_handle04_01_dasm(DASM_OPS_32);
	43	int arcompact_handle04_02_dasm(DASM_OPS_32);
	44	int arcompact_handle04_03_dasm(DASM_OPS_32);
	45	int arcompact_handle04_04_dasm(DASM_OPS_32);
	46	int arcompact_handle04_05_dasm(DASM_OPS_32);
	47	int arcompact_handle04_06_dasm(DASM_OPS_32);
	48	int arcompact_handle04_07_dasm(DASM_OPS_32);
	49	int arcompact_handle04_08_dasm(DASM_OPS_32);
	50	int arcompact_handle04_09_dasm(DASM_OPS_32);
	51	int arcompact_handle04_0a_dasm(DASM_OPS_32);
	52	int arcompact_handle04_0b_dasm(DASM_OPS_32);
	53	int arcompact_handle04_0c_dasm(DASM_OPS_32);
	54	int arcompact_handle04_0d_dasm(DASM_OPS_32);
	55	int arcompact_handle04_0e_dasm(DASM_OPS_32);
	56	int arcompact_handle04_0f_dasm(DASM_OPS_32);
	57	int arcompact_handle04_10_dasm(DASM_OPS_32);
	58	int arcompact_handle04_11_dasm(DASM_OPS_32);
	59	int arcompact_handle04_12_dasm(DASM_OPS_32);
	60	int arcompact_handle04_13_dasm(DASM_OPS_32);
	61	int arcompact_handle04_14_dasm(DASM_OPS_32);
	62	int arcompact_handle04_15_dasm(DASM_OPS_32);
	63	int arcompact_handle04_16_dasm(DASM_OPS_32);
	64	int arcompact_handle04_17_dasm(DASM_OPS_32);
	65	int arcompact_handle04_18_dasm(DASM_OPS_32);
	66	int arcompact_handle04_19_dasm(DASM_OPS_32);
	67	int arcompact_handle04_1a_dasm(DASM_OPS_32);
	68	int arcompact_handle04_1b_dasm(DASM_OPS_32);
	69	int arcompact_handle04_1c_dasm(DASM_OPS_32);
	70	int arcompact_handle04_1d_dasm(DASM_OPS_32);
	71	int arcompact_handle04_20_dasm(DASM_OPS_32);
	72	int arcompact_handle04_21_dasm(DASM_OPS_32);
	73	int arcompact_handle04_22_dasm(DASM_OPS_32);
	74	int arcompact_handle04_23_dasm(DASM_OPS_32);
	75	int arcompact_handle04_28_dasm(DASM_OPS_32);
	76	int arcompact_handle04_29_dasm(DASM_OPS_32);
	77	int arcompact_handle04_2a_dasm(DASM_OPS_32);
	78	int arcompact_handle04_2b_dasm(DASM_OPS_32);
	79	int arcompact_handle04_2f_00_dasm(DASM_OPS_32);
	80	int arcompact_handle04_2f_01_dasm(DASM_OPS_32);
	81	int arcompact_handle04_2f_02_dasm(DASM_OPS_32);
	82	int arcompact_handle04_2f_03_dasm(DASM_OPS_32);
	83	int arcompact_handle04_2f_04_dasm(DASM_OPS_32);
	84	int arcompact_handle04_2f_05_dasm(DASM_OPS_32);
	85	int arcompact_handle04_2f_06_dasm(DASM_OPS_32);
	86	int arcompact_handle04_2f_07_dasm(DASM_OPS_32);
	87	int arcompact_handle04_2f_08_dasm(DASM_OPS_32);
	88	int arcompact_handle04_2f_09_dasm(DASM_OPS_32);
	89	int arcompact_handle04_2f_0a_dasm(DASM_OPS_32);
	90	int arcompact_handle04_2f_0b_dasm(DASM_OPS_32);
	91	int arcompact_handle04_2f_0c_dasm(DASM_OPS_32);
	92	int arcompact_handle04_2f_3f_01_dasm(DASM_OPS_32);
	93	int arcompact_handle04_2f_3f_02_dasm(DASM_OPS_32);
	94	int arcompact_handle04_2f_3f_03_dasm(DASM_OPS_32);
	95	int arcompact_handle04_2f_3f_04_dasm(DASM_OPS_32);
	96	int arcompact_handle04_2f_3f_05_dasm(DASM_OPS_32);
	97	int arcompact_handle04_30_dasm(DASM_OPS_32);
	98	int arcompact_handle04_31_dasm(DASM_OPS_32);
	99	int arcompact_handle04_32_dasm(DASM_OPS_32);
	100	int arcompact_handle04_33_dasm(DASM_OPS_32);
	101	int arcompact_handle04_34_dasm(DASM_OPS_32);
	102	int arcompact_handle04_35_dasm(DASM_OPS_32);
	103	int arcompact_handle04_36_dasm(DASM_OPS_32);
	104	int arcompact_handle04_37_dasm(DASM_OPS_32);
	105	int arcompact_handle05_00_dasm(DASM_OPS_32);
	106	int arcompact_handle05_01_dasm(DASM_OPS_32);
	107	int arcompact_handle05_02_dasm(DASM_OPS_32);
	108	int arcompact_handle05_03_dasm(DASM_OPS_32);
	109	int arcompact_handle05_04_dasm(DASM_OPS_32);
	110	int arcompact_handle05_05_dasm(DASM_OPS_32);
	111	int arcompact_handle05_06_dasm(DASM_OPS_32);
	112	int arcompact_handle05_07_dasm(DASM_OPS_32);
	113	int arcompact_handle05_08_dasm(DASM_OPS_32);
	114	int arcompact_handle05_0a_dasm(DASM_OPS_32);
	115	int arcompact_handle05_0b_dasm(DASM_OPS_32);
	116	int arcompact_handle05_28_dasm(DASM_OPS_32);
	117	int arcompact_handle05_29_dasm(DASM_OPS_32);
	118	int arcompact_handle05_2f_dasm(DASM_OPS_32);
	119	int arcompact_handle06_dasm(DASM_OPS_32);
	120	int arcompact_handle07_dasm(DASM_OPS_32);
	121	int arcompact_handle08_dasm(DASM_OPS_32);
	122	int arcompact_handle09_dasm(DASM_OPS_32);
	123	int arcompact_handle0a_dasm(DASM_OPS_32);
	124	int arcompact_handle0b_dasm(DASM_OPS_32);
	125
	126	int arcompact_handle0c_00_dasm(DASM_OPS_16);
	127	int arcompact_handle0c_01_dasm(DASM_OPS_16);
	128	int arcompact_handle0c_02_dasm(DASM_OPS_16);
	129	int arcompact_handle0c_03_dasm(DASM_OPS_16);
	130	int arcompact_handle0d_00_dasm(DASM_OPS_16);
	131	int arcompact_handle0d_01_dasm(DASM_OPS_16);
	132	int arcompact_handle0d_02_dasm(DASM_OPS_16);
	133	int arcompact_handle0d_03_dasm(DASM_OPS_16);
	134	int arcompact_handle0e_00_dasm(DASM_OPS_16);
	135	int arcompact_handle0e_01_dasm(DASM_OPS_16);
	136	int arcompact_handle0e_02_dasm(DASM_OPS_16);
	137	int arcompact_handle0e_03_dasm(DASM_OPS_16);
	138	int arcompact_handle0f_00_00_dasm(DASM_OPS_16);
	139	int arcompact_handle0f_00_01_dasm(DASM_OPS_16);
	140	int arcompact_handle0f_00_02_dasm(DASM_OPS_16);
	141	int arcompact_handle0f_00_03_dasm(DASM_OPS_16);
	142	int arcompact_handle0f_00_06_dasm(DASM_OPS_16);
	143	int arcompact_handle0f_00_07_00_dasm(DASM_OPS_16);
	144	int arcompact_handle0f_00_07_01_dasm(DASM_OPS_16);
	145	int arcompact_handle0f_00_07_04_dasm(DASM_OPS_16);
	146	int arcompact_handle0f_00_07_05_dasm(DASM_OPS_16);
	147	int arcompact_handle0f_00_07_06_dasm(DASM_OPS_16);
	148	int arcompact_handle0f_00_07_07_dasm(DASM_OPS_16);
	149	int arcompact_handle0f_02_dasm(DASM_OPS_16);
	150	int arcompact_handle0f_04_dasm(DASM_OPS_16);
	151	int arcompact_handle0f_05_dasm(DASM_OPS_16);
	152	int arcompact_handle0f_06_dasm(DASM_OPS_16);
	153	int arcompact_handle0f_07_dasm(DASM_OPS_16);
	154	int arcompact_handle0f_0b_dasm(DASM_OPS_16);
	155	int arcompact_handle0f_0c_dasm(DASM_OPS_16);
	156	int arcompact_handle0f_0d_dasm(DASM_OPS_16);
	157	int arcompact_handle0f_0e_dasm(DASM_OPS_16);
	158	int arcompact_handle0f_0f_dasm(DASM_OPS_16);
	159	int arcompact_handle0f_10_dasm(DASM_OPS_16);
	160	int arcompact_handle0f_11_dasm(DASM_OPS_16);
	161	int arcompact_handle0f_12_dasm(DASM_OPS_16);
	162	int arcompact_handle0f_13_dasm(DASM_OPS_16);
	163	int arcompact_handle0f_14_dasm(DASM_OPS_16);
	164	int arcompact_handle0f_15_dasm(DASM_OPS_16);
	165	int arcompact_handle0f_16_dasm(DASM_OPS_16);
	166	int arcompact_handle0f_18_dasm(DASM_OPS_16);
	167	int arcompact_handle0f_19_dasm(DASM_OPS_16);
	168	int arcompact_handle0f_1a_dasm(DASM_OPS_16);
	169	int arcompact_handle0f_1b_dasm(DASM_OPS_16);
	170	int arcompact_handle0f_1c_dasm(DASM_OPS_16);
	171	int arcompact_handle0f_1d_dasm(DASM_OPS_16);
	172	int arcompact_handle0f_1e_dasm(DASM_OPS_16);
	173	int arcompact_handle0f_1f_dasm(DASM_OPS_16);
	174	int arcompact_handle10_dasm(DASM_OPS_16);
	175	int arcompact_handle11_dasm(DASM_OPS_16);
	176	int arcompact_handle12_dasm(DASM_OPS_16);
	177	int arcompact_handle13_dasm(DASM_OPS_16);
	178	int arcompact_handle14_dasm(DASM_OPS_16);
	179	int arcompact_handle15_dasm(DASM_OPS_16);
	180	int arcompact_handle16_dasm(DASM_OPS_16);
	181	int arcompact_handle17_00_dasm(DASM_OPS_16);
	182	int arcompact_handle17_01_dasm(DASM_OPS_16);
	183	int arcompact_handle17_02_dasm(DASM_OPS_16);
	184	int arcompact_handle17_03_dasm(DASM_OPS_16);
	185	int arcompact_handle17_04_dasm(DASM_OPS_16);
	186	int arcompact_handle17_05_dasm(DASM_OPS_16);
	187	int arcompact_handle17_06_dasm(DASM_OPS_16);
	188	int arcompact_handle17_07_dasm(DASM_OPS_16);
	189	int arcompact_handle18_00_dasm(DASM_OPS_16);
	190	int arcompact_handle18_01_dasm(DASM_OPS_16);
	191	int arcompact_handle18_02_dasm(DASM_OPS_16);
	192	int arcompact_handle18_03_dasm(DASM_OPS_16);
	193	int arcompact_handle18_04_dasm(DASM_OPS_16);
	194	int arcompact_handle18_05_00_dasm(DASM_OPS_16);
	195	int arcompact_handle18_05_01_dasm(DASM_OPS_16);
	196	int arcompact_handle18_06_01_dasm(DASM_OPS_16);
	197	int arcompact_handle18_06_11_dasm(DASM_OPS_16);
	198	int arcompact_handle18_07_01_dasm(DASM_OPS_16);
	199	int arcompact_handle18_07_11_dasm(DASM_OPS_16);
	200	int arcompact_handle19_00_dasm(DASM_OPS_16);
	201	int arcompact_handle19_01_dasm(DASM_OPS_16);
	202	int arcompact_handle19_02_dasm(DASM_OPS_16);
	203	int arcompact_handle19_03_dasm(DASM_OPS_16);
	204	int arcompact_handle1a_dasm(DASM_OPS_16);
	205	int arcompact_handle1b_dasm(DASM_OPS_16);
	206	int arcompact_handle1c_00_dasm(DASM_OPS_16);
	207	int arcompact_handle1c_01_dasm(DASM_OPS_16);
	208	int arcompact_handle1d_00_dasm(DASM_OPS_16);
	209	int arcompact_handle1d_01_dasm(DASM_OPS_16);
	210	int arcompact_handle1e_00_dasm(DASM_OPS_16);
	211	int arcompact_handle1e_01_dasm(DASM_OPS_16);
	212	int arcompact_handle1e_02_dasm(DASM_OPS_16);
	213	int arcompact_handle1e_03_00_dasm(DASM_OPS_16);
	214	int arcompact_handle1e_03_01_dasm(DASM_OPS_16);
	215	int arcompact_handle1e_03_02_dasm(DASM_OPS_16);
	216	int arcompact_handle1e_03_03_dasm(DASM_OPS_16);
	217	int arcompact_handle1e_03_04_dasm(DASM_OPS_16);
	218	int arcompact_handle1e_03_05_dasm(DASM_OPS_16);
	219	int arcompact_handle1e_03_06_dasm(DASM_OPS_16);
	220	int arcompact_handle1e_03_07_dasm(DASM_OPS_16);
	221	int arcompact_handle1f_dasm(DASM_OPS_16);
	222
	223	/************************************************************************************************************************************
	224	*                                                                                                                                   *
	225	* illegal opcode handlers (disassembly)                                                                                             *
	226	*                                                                                                                                   *
	227	************************************************************************************************************************************/
	228
	229	int arcompact_handle01_01_00_06_dasm(DASM_OPS_32); //("<illegal 01_01_00_06> (%08x)", op); return 4; }
	230	int arcompact_handle01_01_00_07_dasm(DASM_OPS_32); //("<illegal 01_01_00_07> (%08x)", op); return 4; }
	231	int arcompact_handle01_01_00_08_dasm(DASM_OPS_32); //("<illegal 01_01_00_08> (%08x)", op); return 4; }
	232	int arcompact_handle01_01_00_09_dasm(DASM_OPS_32); //("<illegal 01_01_00_09> (%08x)", op); return 4; }
	233	int arcompact_handle01_01_00_0a_dasm(DASM_OPS_32); //("<illegal 01_01_00_0a> (%08x)", op); return 4; }
	234	int arcompact_handle01_01_00_0b_dasm(DASM_OPS_32); //("<illegal 01_01_00_0b> (%08x)", op); return 4; }
	235	int arcompact_handle01_01_00_0c_dasm(DASM_OPS_32); //("<illegal 01_01_00_0c> (%08x)", op); return 4; }
	236	int arcompact_handle01_01_00_0d_dasm(DASM_OPS_32); //("<illegal 01_01_00_0d> (%08x)", op); return 4; }
	237
	238	int arcompact_handle01_01_01_06_dasm(DASM_OPS_32); //("<illegal 01_01_01_06> (%08x)", op); return 4; }
	239	int arcompact_handle01_01_01_07_dasm(DASM_OPS_32); //("<illegal 01_01_01_07> (%08x)", op); return 4; }
	240	int arcompact_handle01_01_01_08_dasm(DASM_OPS_32); //("<illegal 01_01_01_08> (%08x)", op); return 4; }
	241	int arcompact_handle01_01_01_09_dasm(DASM_OPS_32); //("<illegal 01_01_01_09> (%08x)", op); return 4; }
	242	int arcompact_handle01_01_01_0a_dasm(DASM_OPS_32); //("<illegal 01_01_01_0a> (%08x)", op); return 4; }
	243	int arcompact_handle01_01_01_0b_dasm(DASM_OPS_32); //("<illegal 01_01_01_0b> (%08x)", op); return 4; }
	244	int arcompact_handle01_01_01_0c_dasm(DASM_OPS_32); //("<illegal 01_01_01_0c> (%08x)", op); return 4; }
	245	int arcompact_handle01_01_01_0d_dasm(DASM_OPS_32); //("<illegal 01_01_01_0d> (%08x)", op); return 4; }
	246
	247
	248	int arcompact_handle04_1e_dasm(DASM_OPS_32); //("<illegal 0x04_1e> (%08x)", op); return 4;}
	249	int arcompact_handle04_1f_dasm(DASM_OPS_32); //("<illegal 0x04_1f> (%08x)", op); return 4;}
	250
	251	int arcompact_handle04_24_dasm(DASM_OPS_32); //("<illegal 0x04_24> (%08x)", op); return 4;}
	252	int arcompact_handle04_25_dasm(DASM_OPS_32); //("<illegal 0x04_25> (%08x)", op); return 4;}
	253	int arcompact_handle04_26_dasm(DASM_OPS_32); //("<illegal 0x04_26> (%08x)", op); return 4;}
	254	int arcompact_handle04_27_dasm(DASM_OPS_32); //("<illegal 0x04_27> (%08x)", op); return 4;}
	255
	256	int arcompact_handle04_2c_dasm(DASM_OPS_32); //("<illegal 0x04_2c> (%08x)", op); return 4;}
	257	int arcompact_handle04_2d_dasm(DASM_OPS_32); //("<illegal 0x04_2d> (%08x)", op); return 4;}
	258	int arcompact_handle04_2e_dasm(DASM_OPS_32); //("<illegal 0x04_2e> (%08x)", op); return 4;}
	259
	260	int arcompact_handle04_2f_0d_dasm(DASM_OPS_32); //("<illegal 0x04_2f_0d> (%08x)", op); return 4;}
	261	int arcompact_handle04_2f_0e_dasm(DASM_OPS_32); //("<illegal 0x04_2f_0e> (%08x)", op); return 4;}
	262	int arcompact_handle04_2f_0f_dasm(DASM_OPS_32); //("<illegal 0x04_2f_0f> (%08x)", op); return 4;}
	263	int arcompact_handle04_2f_10_dasm(DASM_OPS_32); //("<illegal 0x04_2f_10> (%08x)", op); return 4;}
	264	int arcompact_handle04_2f_11_dasm(DASM_OPS_32); //("<illegal 0x04_2f_11> (%08x)", op); return 4;}
	265	int arcompact_handle04_2f_12_dasm(DASM_OPS_32); //("<illegal 0x04_2f_12> (%08x)", op); return 4;}
	266	int arcompact_handle04_2f_13_dasm(DASM_OPS_32); //("<illegal 0x04_2f_13> (%08x)", op); return 4;}
	267	int arcompact_handle04_2f_14_dasm(DASM_OPS_32); //("<illegal 0x04_2f_14> (%08x)", op); return 4;}
	268	int arcompact_handle04_2f_15_dasm(DASM_OPS_32); //("<illegal 0x04_2f_15> (%08x)", op); return 4;}
	269	int arcompact_handle04_2f_16_dasm(DASM_OPS_32); //("<illegal 0x04_2f_16> (%08x)", op); return 4;}
	270	int arcompact_handle04_2f_17_dasm(DASM_OPS_32); //("<illegal 0x04_2f_17> (%08x)", op); return 4;}
	271	int arcompact_handle04_2f_18_dasm(DASM_OPS_32); //("<illegal 0x04_2f_18> (%08x)", op); return 4;}
	272	int arcompact_handle04_2f_19_dasm(DASM_OPS_32); //("<illegal 0x04_2f_19> (%08x)", op); return 4;}
	273	int arcompact_handle04_2f_1a_dasm(DASM_OPS_32); //("<illegal 0x04_2f_1a> (%08x)", op); return 4;}
	274	int arcompact_handle04_2f_1b_dasm(DASM_OPS_32); //("<illegal 0x04_2f_1b> (%08x)", op); return 4;}
	275	int arcompact_handle04_2f_1c_dasm(DASM_OPS_32); //("<illegal 0x04_2f_1c> (%08x)", op); return 4;}
	276	int arcompact_handle04_2f_1d_dasm(DASM_OPS_32); //("<illegal 0x04_2f_1d> (%08x)", op); return 4;}
	277	int arcompact_handle04_2f_1e_dasm(DASM_OPS_32); //("<illegal 0x04_2f_1e> (%08x)", op); return 4;}
	278	int arcompact_handle04_2f_1f_dasm(DASM_OPS_32); //("<illegal 0x04_2f_1f> (%08x)", op); return 4;}
	279	int arcompact_handle04_2f_20_dasm(DASM_OPS_32); //("<illegal 0x04_2f_20> (%08x)", op); return 4;}
	280	int arcompact_handle04_2f_21_dasm(DASM_OPS_32); //("<illegal 0x04_2f_21> (%08x)", op); return 4;}
	281	int arcompact_handle04_2f_22_dasm(DASM_OPS_32); //("<illegal 0x04_2f_22> (%08x)", op); return 4;}
	282	int arcompact_handle04_2f_23_dasm(DASM_OPS_32); //("<illegal 0x04_2f_23> (%08x)", op); return 4;}
	283	int arcompact_handle04_2f_24_dasm(DASM_OPS_32); //("<illegal 0x04_2f_24> (%08x)", op); return 4;}
	284	int arcompact_handle04_2f_25_dasm(DASM_OPS_32); //("<illegal 0x04_2f_25> (%08x)", op); return 4;}
	285	int arcompact_handle04_2f_26_dasm(DASM_OPS_32); //("<illegal 0x04_2f_26> (%08x)", op); return 4;}
	286	int arcompact_handle04_2f_27_dasm(DASM_OPS_32); //("<illegal 0x04_2f_27> (%08x)", op); return 4;}
	287	int arcompact_handle04_2f_28_dasm(DASM_OPS_32); //("<illegal 0x04_2f_28> (%08x)", op); return 4;}
	288	int arcompact_handle04_2f_29_dasm(DASM_OPS_32); //("<illegal 0x04_2f_29> (%08x)", op); return 4;}
	289	int arcompact_handle04_2f_2a_dasm(DASM_OPS_32); //("<illegal 0x04_2f_2a> (%08x)", op); return 4;}
	290	int arcompact_handle04_2f_2b_dasm(DASM_OPS_32); //("<illegal 0x04_2f_2b> (%08x)", op); return 4;}
	291	int arcompact_handle04_2f_2c_dasm(DASM_OPS_32); //("<illegal 0x04_2f_2c> (%08x)", op); return 4;}
	292	int arcompact_handle04_2f_2d_dasm(DASM_OPS_32); //("<illegal 0x04_2f_2d> (%08x)", op); return 4;}
	293	int arcompact_handle04_2f_2e_dasm(DASM_OPS_32); //("<illegal 0x04_2f_2e> (%08x)", op); return 4;}
	294	int arcompact_handle04_2f_2f_dasm(DASM_OPS_32); //("<illegal 0x04_2f_2f> (%08x)", op); return 4;}
	295	int arcompact_handle04_2f_30_dasm(DASM_OPS_32); //("<illegal 0x04_2f_30> (%08x)", op); return 4;}
	296	int arcompact_handle04_2f_31_dasm(DASM_OPS_32); //("<illegal 0x04_2f_31> (%08x)", op); return 4;}
	297	int arcompact_handle04_2f_32_dasm(DASM_OPS_32); //("<illegal 0x04_2f_32> (%08x)", op); return 4;}
	298	int arcompact_handle04_2f_33_dasm(DASM_OPS_32); //("<illegal 0x04_2f_33> (%08x)", op); return 4;}
	299	int arcompact_handle04_2f_34_dasm(DASM_OPS_32); //("<illegal 0x04_2f_34> (%08x)", op); return 4;}
	300	int arcompact_handle04_2f_35_dasm(DASM_OPS_32); //("<illegal 0x04_2f_35> (%08x)", op); return 4;}
	301	int arcompact_handle04_2f_36_dasm(DASM_OPS_32); //("<illegal 0x04_2f_36> (%08x)", op); return 4;}
	302	int arcompact_handle04_2f_37_dasm(DASM_OPS_32); //("<illegal 0x04_2f_37> (%08x)", op); return 4;}
	303	int arcompact_handle04_2f_38_dasm(DASM_OPS_32); //("<illegal 0x04_2f_38> (%08x)", op); return 4;}
	304	int arcompact_handle04_2f_39_dasm(DASM_OPS_32); //("<illegal 0x04_2f_39> (%08x)", op); return 4;}
	305	int arcompact_handle04_2f_3a_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3a> (%08x)", op); return 4;}
	306	int arcompact_handle04_2f_3b_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3b> (%08x)", op); return 4;}
	307	int arcompact_handle04_2f_3c_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3c> (%08x)", op); return 4;}
	308	int arcompact_handle04_2f_3d_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3d> (%08x)", op); return 4;}
	309	int arcompact_handle04_2f_3e_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3e> (%08x)", op); return 4;}
	310
	311	int arcompact_handle04_2f_3f_00_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_00> (%08x)", op); return 4;}
	312	int arcompact_handle04_2f_3f_06_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_06> (%08x)", op); return 4;}
	313	int arcompact_handle04_2f_3f_07_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_07> (%08x)", op); return 4;}
	314	int arcompact_handle04_2f_3f_08_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_08> (%08x)", op); return 4;}
	315	int arcompact_handle04_2f_3f_09_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_09> (%08x)", op); return 4;}
	316	int arcompact_handle04_2f_3f_0a_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_0a> (%08x)", op); return 4;}
	317	int arcompact_handle04_2f_3f_0b_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_0b> (%08x)", op); return 4;}
	318	int arcompact_handle04_2f_3f_0c_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_0c> (%08x)", op); return 4;}
	319	int arcompact_handle04_2f_3f_0d_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_0d> (%08x)", op); return 4;}
	320	int arcompact_handle04_2f_3f_0e_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_0e> (%08x)", op); return 4;}
	321	int arcompact_handle04_2f_3f_0f_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_0f> (%08x)", op); return 4;}
	322	int arcompact_handle04_2f_3f_10_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_10> (%08x)", op); return 4;}
	323	int arcompact_handle04_2f_3f_11_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_11> (%08x)", op); return 4;}
	324	int arcompact_handle04_2f_3f_12_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_12> (%08x)", op); return 4;}
	325	int arcompact_handle04_2f_3f_13_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_13> (%08x)", op); return 4;}
	326	int arcompact_handle04_2f_3f_14_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_14> (%08x)", op); return 4;}
	327	int arcompact_handle04_2f_3f_15_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_15> (%08x)", op); return 4;}
	328	int arcompact_handle04_2f_3f_16_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_16> (%08x)", op); return 4;}
	329	int arcompact_handle04_2f_3f_17_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_17> (%08x)", op); return 4;}
	330	int arcompact_handle04_2f_3f_18_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_18> (%08x)", op); return 4;}
	331	int arcompact_handle04_2f_3f_19_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_19> (%08x)", op); return 4;}
	332	int arcompact_handle04_2f_3f_1a_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_1a> (%08x)", op); return 4;}
	333	int arcompact_handle04_2f_3f_1b_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_1b> (%08x)", op); return 4;}
	334	int arcompact_handle04_2f_3f_1c_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_1c> (%08x)", op); return 4;}
	335	int arcompact_handle04_2f_3f_1d_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_1d> (%08x)", op); return 4;}
	336	int arcompact_handle04_2f_3f_1e_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_1e> (%08x)", op); return 4;}
	337	int arcompact_handle04_2f_3f_1f_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_1f> (%08x)", op); return 4;}
	338	int arcompact_handle04_2f_3f_20_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_20> (%08x)", op); return 4;}
	339	int arcompact_handle04_2f_3f_21_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_21> (%08x)", op); return 4;}
	340	int arcompact_handle04_2f_3f_22_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_22> (%08x)", op); return 4;}
	341	int arcompact_handle04_2f_3f_23_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_23> (%08x)", op); return 4;}
	342	int arcompact_handle04_2f_3f_24_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_24> (%08x)", op); return 4;}
	343	int arcompact_handle04_2f_3f_25_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_25> (%08x)", op); return 4;}
	344	int arcompact_handle04_2f_3f_26_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_26> (%08x)", op); return 4;}
	345	int arcompact_handle04_2f_3f_27_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_27> (%08x)", op); return 4;}
	346	int arcompact_handle04_2f_3f_28_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_28> (%08x)", op); return 4;}
	347	int arcompact_handle04_2f_3f_29_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_29> (%08x)", op); return 4;}
	348	int arcompact_handle04_2f_3f_2a_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_2a> (%08x)", op); return 4;}
	349	int arcompact_handle04_2f_3f_2b_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_2b> (%08x)", op); return 4;}
	350	int arcompact_handle04_2f_3f_2c_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_2c> (%08x)", op); return 4;}
	351	int arcompact_handle04_2f_3f_2d_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_2d> (%08x)", op); return 4;}
	352	int arcompact_handle04_2f_3f_2e_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_2e> (%08x)", op); return 4;}
	353	int arcompact_handle04_2f_3f_2f_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_2f> (%08x)", op); return 4;}
	354	int arcompact_handle04_2f_3f_30_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_30> (%08x)", op); return 4;}
	355	int arcompact_handle04_2f_3f_31_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_31> (%08x)", op); return 4;}
	356	int arcompact_handle04_2f_3f_32_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_32> (%08x)", op); return 4;}
	357	int arcompact_handle04_2f_3f_33_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_33> (%08x)", op); return 4;}
	358	int arcompact_handle04_2f_3f_34_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_34> (%08x)", op); return 4;}
	359	int arcompact_handle04_2f_3f_35_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_35> (%08x)", op); return 4;}
	360	int arcompact_handle04_2f_3f_36_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_36> (%08x)", op); return 4;}
	361	int arcompact_handle04_2f_3f_37_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_37> (%08x)", op); return 4;}
	362	int arcompact_handle04_2f_3f_38_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_38> (%08x)", op); return 4;}
	363	int arcompact_handle04_2f_3f_39_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_39> (%08x)", op); return 4;}
	364	int arcompact_handle04_2f_3f_3a_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_3a> (%08x)", op); return 4;}
	365	int arcompact_handle04_2f_3f_3b_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_3b> (%08x)", op); return 4;}
	366	int arcompact_handle04_2f_3f_3c_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_3c> (%08x)", op); return 4;}
	367	int arcompact_handle04_2f_3f_3d_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_3d> (%08x)", op); return 4;}
	368	int arcompact_handle04_2f_3f_3e_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_3e> (%08x)", op); return 4;}
	369	int arcompact_handle04_2f_3f_3f_dasm(DASM_OPS_32); //("<illegal 0x04_2f_3f_3f> (%08x)", op); return 4;}
	370
	371	int arcompact_handle04_38_dasm(DASM_OPS_32); //("<illegal 0x04_38> (%08x)", op); return 4;}
	372	int arcompact_handle04_39_dasm(DASM_OPS_32); //("<illegal 0x04_39> (%08x)", op); return 4;}
	373	int arcompact_handle04_3a_dasm(DASM_OPS_32); //("<illegal 0x04_3a> (%08x)", op); return 4;}
	374	int arcompact_handle04_3b_dasm(DASM_OPS_32); //("<illegal 0x04_3b> (%08x)", op); return 4;}
	375	int arcompact_handle04_3c_dasm(DASM_OPS_32); //("<illegal 0x04_3c> (%08x)", op); return 4;}
	376	int arcompact_handle04_3d_dasm(DASM_OPS_32); //("<illegal 0x04_3d> (%08x)", op); return 4;}
	377	int arcompact_handle04_3e_dasm(DASM_OPS_32); //("<illegal 0x04_3e> (%08x)", op); return 4;}
	378	int arcompact_handle04_3f_dasm(DASM_OPS_32); //("<illegal 0x04_3f> (%08x)", op); return 4;}
	379
	380	int arcompact_handle05_09_dasm(DASM_OPS_32); //("<illegal 0x05_09> (%08x)", op); return 4;}
	381	int arcompact_handle05_0c_dasm(DASM_OPS_32); //("<illegal 0x05_0c> (%08x)", op); return 4;}
	382	int arcompact_handle05_0d_dasm(DASM_OPS_32); //("<illegal 0x05_0d> (%08x)", op); return 4;}
	383	int arcompact_handle05_0e_dasm(DASM_OPS_32); //("<illegal 0x05_0e> (%08x)", op); return 4;}
	384	int arcompact_handle05_0f_dasm(DASM_OPS_32); //("<illegal 0x05_0f> (%08x)", op); return 4;}
	385	int arcompact_handle05_10_dasm(DASM_OPS_32); //("<illegal 0x05_10> (%08x)", op); return 4;}
	386	int arcompact_handle05_11_dasm(DASM_OPS_32); //("<illegal 0x05_11> (%08x)", op); return 4;}
	387	int arcompact_handle05_12_dasm(DASM_OPS_32); //("<illegal 0x05_12> (%08x)", op); return 4;}
	388	int arcompact_handle05_13_dasm(DASM_OPS_32); //("<illegal 0x05_13> (%08x)", op); return 4;}
	389	int arcompact_handle05_14_dasm(DASM_OPS_32); //("<illegal 0x05_14> (%08x)", op); return 4;}
	390	int arcompact_handle05_15_dasm(DASM_OPS_32); //("<illegal 0x05_15> (%08x)", op); return 4;}
	391	int arcompact_handle05_16_dasm(DASM_OPS_32); //("<illegal 0x05_16> (%08x)", op); return 4;}
	392	int arcompact_handle05_17_dasm(DASM_OPS_32); //("<illegal 0x05_17> (%08x)", op); return 4;}
	393	int arcompact_handle05_18_dasm(DASM_OPS_32); //("<illegal 0x05_18> (%08x)", op); return 4;}
	394	int arcompact_handle05_19_dasm(DASM_OPS_32); //("<illegal 0x05_19> (%08x)", op); return 4;}
	395	int arcompact_handle05_1a_dasm(DASM_OPS_32); //("<illegal 0x05_1a> (%08x)", op); return 4;}
	396	int arcompact_handle05_1b_dasm(DASM_OPS_32); //("<illegal 0x05_1b> (%08x)", op); return 4;}
	397	int arcompact_handle05_1c_dasm(DASM_OPS_32); //("<illegal 0x05_1c> (%08x)", op); return 4;}
	398	int arcompact_handle05_1d_dasm(DASM_OPS_32); //("<illegal 0x05_1d> (%08x)", op); return 4;}
	399	int arcompact_handle05_1e_dasm(DASM_OPS_32); //("<illegal 0x05_1e> (%08x)", op); return 4;}
	400	int arcompact_handle05_1f_dasm(DASM_OPS_32); //("<illegal 0x05_1f> (%08x)", op); return 4;}
	401	int arcompact_handle05_20_dasm(DASM_OPS_32); //("<illegal 0x05_20> (%08x)", op); return 4;}
	402	int arcompact_handle05_21_dasm(DASM_OPS_32); //("<illegal 0x05_21> (%08x)", op); return 4;}
	403	int arcompact_handle05_22_dasm(DASM_OPS_32); //("<illegal 0x05_22> (%08x)", op); return 4;}
	404	int arcompact_handle05_23_dasm(DASM_OPS_32); //("<illegal 0x05_23> (%08x)", op); return 4;}
	405	int arcompact_handle05_24_dasm(DASM_OPS_32); //("<illegal 0x05_24> (%08x)", op); return 4;}
	406	int arcompact_handle05_25_dasm(DASM_OPS_32); //("<illegal 0x05_25> (%08x)", op); return 4;}
	407	int arcompact_handle05_26_dasm(DASM_OPS_32); //("<illegal 0x05_26> (%08x)", op); return 4;}
	408	int arcompact_handle05_27_dasm(DASM_OPS_32); //("<illegal 0x05_27> (%08x)", op); return 4;}
	409
	410	int arcompact_handle05_2a_dasm(DASM_OPS_32); //("<illegal 0x05_2a> (%08x)", op); return 4;}
	411	int arcompact_handle05_2b_dasm(DASM_OPS_32); //("<illegal 0x05_2b> (%08x)", op); return 4;}
	412	int arcompact_handle05_2c_dasm(DASM_OPS_32); //("<illegal 0x05_2c> (%08x)", op); return 4;}
	413	int arcompact_handle05_2d_dasm(DASM_OPS_32); //("<illegal 0x05_2d> (%08x)", op); return 4;}
	414	int arcompact_handle05_2e_dasm(DASM_OPS_32); //("<illegal 0x05_2e> (%08x)", op); return 4;}
	415
	416	int arcompact_handle05_30_dasm(DASM_OPS_32); //("<illegal 0x05_30> (%08x)", op); return 4;}
	417	int arcompact_handle05_31_dasm(DASM_OPS_32); //("<illegal 0x05_31> (%08x)", op); return 4;}
	418	int arcompact_handle05_32_dasm(DASM_OPS_32); //("<illegal 0x05_32> (%08x)", op); return 4;}
	419	int arcompact_handle05_33_dasm(DASM_OPS_32); //("<illegal 0x05_33> (%08x)", op); return 4;}
	420	int arcompact_handle05_34_dasm(DASM_OPS_32); //("<illegal 0x05_34> (%08x)", op); return 4;}
	421	int arcompact_handle05_35_dasm(DASM_OPS_32); //("<illegal 0x05_35> (%08x)", op); return 4;}
	422	int arcompact_handle05_36_dasm(DASM_OPS_32); //("<illegal 0x05_36> (%08x)", op); return 4;}
	423	int arcompact_handle05_37_dasm(DASM_OPS_32); //("<illegal 0x05_37> (%08x)", op); return 4;}
	424	int arcompact_handle05_38_dasm(DASM_OPS_32); //("<illegal 0x05_38> (%08x)", op); return 4;}
	425	int arcompact_handle05_39_dasm(DASM_OPS_32); //("<illegal 0x05_39> (%08x)", op); return 4;}
	426	int arcompact_handle05_3a_dasm(DASM_OPS_32); //("<illegal 0x05_3a> (%08x)", op); return 4;}
	427	int arcompact_handle05_3b_dasm(DASM_OPS_32); //("<illegal 0x05_3b> (%08x)", op); return 4;}
	428	int arcompact_handle05_3c_dasm(DASM_OPS_32); //("<illegal 0x05_3c> (%08x)", op); return 4;}
	429	int arcompact_handle05_3d_dasm(DASM_OPS_32); //("<illegal 0x05_3d> (%08x)", op); return 4;}
	430	int arcompact_handle05_3e_dasm(DASM_OPS_32); //("<illegal 0x05_3e> (%08x)", op); return 4;}
	431	int arcompact_handle05_3f_dasm(DASM_OPS_32); //("<illegal 0x05_3f> (%08x)", op); return 4;}
	432
	433	int arcompact_handle0f_00_04_dasm(DASM_OPS_16); //("<illegal 0x0f_00_00> (%08x)", op); return 2;}
	434	int arcompact_handle0f_00_05_dasm(DASM_OPS_16); //("<illegal 0x0f_00_00> (%08x)", op); return 2;}
	435	int arcompact_handle0f_00_07_02_dasm(DASM_OPS_16); //("<illegal 0x0f_00_07_02> (%08x)", op); return 2;}
	436	int arcompact_handle0f_00_07_03_dasm(DASM_OPS_16); //("<illegal 0x0f_00_07_03> (%08x)", op); return 2;}
	437	int arcompact_handle0f_01_dasm(DASM_OPS_16); //("<illegal 0x0f_01> (%08x)", op); return 2;}
	438	int arcompact_handle0f_03_dasm(DASM_OPS_16); //("<illegal 0x0f_03> (%08x)", op); return 2;}
	439	int arcompact_handle0f_08_dasm(DASM_OPS_16); //("<illegal 0x0f_08> (%08x)", op); return 2;}
	440	int arcompact_handle0f_09_dasm(DASM_OPS_16); //("<illegal 0x0f_09> (%08x)", op); return 2;}
	441	int arcompact_handle0f_0a_dasm(DASM_OPS_16); //("<illegal 0x0f_0a> (%08x)", op); return 2;}
	442	int arcompact_handle0f_17_dasm(DASM_OPS_16); //("<illegal 0x0f_17> (%08x)", op); return 2;}
	443
	444	int arcompact_handle18_05_02_dasm(DASM_OPS_16); //("<illegal 0x18_05_02> (%04x)", op); return 2;}
	445	int arcompact_handle18_05_03_dasm(DASM_OPS_16); //("<illegal 0x18_05_03> (%04x)", op); return 2;}
	446	int arcompact_handle18_05_04_dasm(DASM_OPS_16); //("<illegal 0x18_05_04> (%04x)", op); return 2;}
	447	int arcompact_handle18_05_05_dasm(DASM_OPS_16); //("<illegal 0x18_05_05> (%04x)", op); return 2;}
	448	int arcompact_handle18_05_06_dasm(DASM_OPS_16); //("<illegal 0x18_05_06> (%04x)", op); return 2;}
	449	int arcompact_handle18_05_07_dasm(DASM_OPS_16); //("<illegal 0x18_05_07> (%04x)", op); return 2;}
	450	int arcompact_handle18_06_00_dasm(DASM_OPS_16); //("<illegal 0x18_06_00> (%04x)",  op); return 2;}
	451	int arcompact_handle18_06_02_dasm(DASM_OPS_16); //("<illegal 0x18_06_02> (%04x)", op); return 2;}
	452	int arcompact_handle18_06_03_dasm(DASM_OPS_16); //("<illegal 0x18_06_03> (%04x)", op); return 2;}
	453	int arcompact_handle18_06_04_dasm(DASM_OPS_16); //("<illegal 0x18_06_04> (%04x)", op); return 2;}
	454	int arcompact_handle18_06_05_dasm(DASM_OPS_16); //("<illegal 0x18_06_05> (%04x)", op); return 2;}
	455	int arcompact_handle18_06_06_dasm(DASM_OPS_16); //("<illegal 0x18_06_06> (%04x)", op); return 2;}
	456	int arcompact_handle18_06_07_dasm(DASM_OPS_16); //("<illegal 0x18_06_07> (%04x)", op); return 2;}
	457	int arcompact_handle18_06_08_dasm(DASM_OPS_16); //("<illegal 0x18_06_08> (%04x)", op); return 2;}
	458	int arcompact_handle18_06_09_dasm(DASM_OPS_16); //("<illegal 0x18_06_09> (%04x)", op); return 2;}
	459	int arcompact_handle18_06_0a_dasm(DASM_OPS_16); //("<illegal 0x18_06_0a> (%04x)", op); return 2;}
	460	int arcompact_handle18_06_0b_dasm(DASM_OPS_16); //("<illegal 0x18_06_0b> (%04x)", op); return 2;}
	461	int arcompact_handle18_06_0c_dasm(DASM_OPS_16); //("<illegal 0x18_06_0c> (%04x)", op); return 2;}
	462	int arcompact_handle18_06_0d_dasm(DASM_OPS_16); //("<illegal 0x18_06_0d> (%04x)", op); return 2;}
	463	int arcompact_handle18_06_0e_dasm(DASM_OPS_16); //("<illegal 0x18_06_0e> (%04x)", op); return 2;}
	464	int arcompact_handle18_06_0f_dasm(DASM_OPS_16); //("<illegal 0x18_06_0f> (%04x)", op); return 2;}
	465	int arcompact_handle18_06_10_dasm(DASM_OPS_16); //("<illegal 0x18_06_10> (%04x)", op); return 2;}
	466	int arcompact_handle18_06_12_dasm(DASM_OPS_16); //("<illegal 0x18_06_12> (%04x)",  op); return 2;}
	467	int arcompact_handle18_06_13_dasm(DASM_OPS_16); //("<illegal 0x18_06_13> (%04x)",  op); return 2;}
	468	int arcompact_handle18_06_14_dasm(DASM_OPS_16); //("<illegal 0x18_06_14> (%04x)",  op); return 2;}
	469	int arcompact_handle18_06_15_dasm(DASM_OPS_16); //("<illegal 0x18_06_15> (%04x)",  op); return 2;}
	470	int arcompact_handle18_06_16_dasm(DASM_OPS_16); //("<illegal 0x18_06_16> (%04x)",  op); return 2;}
	471	int arcompact_handle18_06_17_dasm(DASM_OPS_16); //("<illegal 0x18_06_17> (%04x)",  op); return 2;}
	472	int arcompact_handle18_06_18_dasm(DASM_OPS_16); //("<illegal 0x18_06_18> (%04x)",  op); return 2;}
	473	int arcompact_handle18_06_19_dasm(DASM_OPS_16); //("<illegal 0x18_06_19> (%04x)",  op); return 2;}
	474	int arcompact_handle18_06_1a_dasm(DASM_OPS_16); //("<illegal 0x18_06_1a> (%04x)",  op); return 2;}
	475	int arcompact_handle18_06_1b_dasm(DASM_OPS_16); //("<illegal 0x18_06_1b> (%04x)",  op); return 2;}
	476	int arcompact_handle18_06_1c_dasm(DASM_OPS_16); //("<illegal 0x18_06_1c> (%04x)",  op); return 2;}
	477	int arcompact_handle18_06_1d_dasm(DASM_OPS_16); //("<illegal 0x18_06_1d> (%04x)",  op); return 2;}
	478	int arcompact_handle18_06_1e_dasm(DASM_OPS_16); //("<illegal 0x18_06_1e> (%04x)",  op); return 2;}
	479	int arcompact_handle18_06_1f_dasm(DASM_OPS_16); //("<illegal 0x18_06_1f> (%04x)",  op); return 2;}
	480	int arcompact_handle18_07_00_dasm(DASM_OPS_16); //("<illegal 0x18_07_00> (%04x)",  op); return 2;}
	481	int arcompact_handle18_07_02_dasm(DASM_OPS_16); //("<illegal 0x18_07_02> (%04x)", op); return 2;}
	482	int arcompact_handle18_07_03_dasm(DASM_OPS_16); //("<illegal 0x18_07_03> (%04x)", op); return 2;}
	483	int arcompact_handle18_07_04_dasm(DASM_OPS_16); //("<illegal 0x18_07_04> (%04x)", op); return 2;}
	484	int arcompact_handle18_07_05_dasm(DASM_OPS_16); //("<illegal 0x18_07_05> (%04x)", op); return 2;}
	485	int arcompact_handle18_07_06_dasm(DASM_OPS_16); //("<illegal 0x18_07_06> (%04x)", op); return 2;}
	486	int arcompact_handle18_07_07_dasm(DASM_OPS_16); //("<illegal 0x18_07_07> (%04x)", op); return 2;}
	487	int arcompact_handle18_07_08_dasm(DASM_OPS_16); //("<illegal 0x18_07_08> (%04x)", op); return 2;}
	488	int arcompact_handle18_07_09_dasm(DASM_OPS_16); //("<illegal 0x18_07_09> (%04x)", op); return 2;}
	489	int arcompact_handle18_07_0a_dasm(DASM_OPS_16); //("<illegal 0x18_07_0a> (%04x)", op); return 2;}
	490	int arcompact_handle18_07_0b_dasm(DASM_OPS_16); //("<illegal 0x18_07_0b> (%04x)", op); return 2;}
	491	int arcompact_handle18_07_0c_dasm(DASM_OPS_16); //("<illegal 0x18_07_0c> (%04x)", op); return 2;}
	492	int arcompact_handle18_07_0d_dasm(DASM_OPS_16); //("<illegal 0x18_07_0d> (%04x)", op); return 2;}
	493	int arcompact_handle18_07_0e_dasm(DASM_OPS_16); //("<illegal 0x18_07_0e> (%04x)", op); return 2;}
	494	int arcompact_handle18_07_0f_dasm(DASM_OPS_16); //("<illegal 0x18_07_0f> (%04x)", op); return 2;}
	495	int arcompact_handle18_07_10_dasm(DASM_OPS_16); //("<illegal 0x18_07_10> (%04x)", op); return 2;}
	496	int arcompact_handle18_07_12_dasm(DASM_OPS_16); //("<illegal 0x18_07_12> (%04x)",  op); return 2;}
	497	int arcompact_handle18_07_13_dasm(DASM_OPS_16); //("<illegal 0x18_07_13> (%04x)",  op); return 2;}
	498	int arcompact_handle18_07_14_dasm(DASM_OPS_16); //("<illegal 0x18_07_14> (%04x)",  op); return 2;}
	499	int arcompact_handle18_07_15_dasm(DASM_OPS_16); //("<illegal 0x18_07_15> (%04x)",  op); return 2;}
	500	int arcompact_handle18_07_16_dasm(DASM_OPS_16); //("<illegal 0x18_07_16> (%04x)",  op); return 2;}
	501	int arcompact_handle18_07_17_dasm(DASM_OPS_16); //("<illegal 0x18_07_17> (%04x)",  op); return 2;}
	502	int arcompact_handle18_07_18_dasm(DASM_OPS_16); //("<illegal 0x18_07_18> (%04x)",  op); return 2;}
	503	int arcompact_handle18_07_19_dasm(DASM_OPS_16); //("<illegal 0x18_07_19> (%04x)",  op); return 2;}
	504	int arcompact_handle18_07_1a_dasm(DASM_OPS_16); //("<illegal 0x18_07_1a> (%04x)",  op); return 2;}
	505	int arcompact_handle18_07_1b_dasm(DASM_OPS_16); //("<illegal 0x18_07_1b> (%04x)",  op); return 2;}
	506	int arcompact_handle18_07_1c_dasm(DASM_OPS_16); //("<illegal 0x18_07_1c> (%04x)",  op); return 2;}
	507	int arcompact_handle18_07_1d_dasm(DASM_OPS_16); //("<illegal 0x18_07_1d> (%04x)",  op); return 2;}
	508	int arcompact_handle18_07_1e_dasm(DASM_OPS_16); //("<illegal 0x18_07_1e> (%04x)",  op); return 2;}
	509	int arcompact_handle18_07_1f_dasm(DASM_OPS_16); //("<illegal 0x18_07_1f> (%04x)",  op); return 2;}
	510

trunk/src/emu/cpu/cpu.mak

r242413	r242414
101	101	ifneq ($(filter ARCOMPACT,$(CPUS)),)
102	102	OBJDIRS += $(CPUOBJ)/arcompact
103	103	CPUOBJS += $(CPUOBJ)/arcompact/arcompact.o
104		DASMOBJS += $(CPUOBJ)/arcompact/arcompactdasm.o
	104	DASMOBJS += $(CPUOBJ)/arcompact/arcompactdasm.o $(CPUOBJ)/arcompact/arcompactdasm_dispatch.o $(CPUOBJ)/arcompact/arcompactdasm_ops.o
105	105	endif
106	106
107	107	$(CPUOBJ)/arcompact/arcompact.o:  $(CPUSRC)/arcompact/arcompact.c \

trunk/src/emu/cpu/e132xs/e132xs.c

r242413	r242414
583	583	UINT32 hyperstone_device::compute_tr()
584	584	{
585	585	UINT64 cycles_since_base = total_cycles() - m_tr_base_cycles;
586		UINT64 clocks_since_base = cycles_since_base >> m_clock_scale;
	586	UINT64 clocks_since_base = cycles_since_base >> m_clck_scale;
587	587	return m_tr_base_value + (clocks_since_base / m_tr_clocks_per_tick);
588	588	}
589	589
r242413	r242414
591	591	{
592	592	UINT32 prevtr = compute_tr();
593	593	TPR &= ~0x80000000;
594		m_clock_scale = (TPR >> 26) & m_clock_scale_mask;
595		m_clock_cycles_1 = 1 << m_clock_scale;
596		m_clock_cycles_2 = 2 << m_clock_scale;
597		m_clock_cycles_4 = 4 << m_clock_scale;
598		m_clock_cycles_6 = 6 << m_clock_scale;
	594	m_clck_scale = (TPR >> 26) & m_clock_scale_mask;
	595	m_clock_cycles_1 = 1 << m_clck_scale;
	596	m_clock_cycles_2 = 2 << m_clck_scale;
	597	m_clock_cycles_4 = 4 << m_clck_scale;
	598	m_clock_cycles_6 = 6 << m_clck_scale;
599	599	m_tr_clocks_per_tick = ((TPR >> 16) & 0xff) + 2;
600	600	m_tr_base_value = prevtr;
601	601	m_tr_base_cycles = total_cycles();
r242413	r242414
604	604	void hyperstone_device::adjust_timer_interrupt()
605	605	{
606	606	UINT64 cycles_since_base = total_cycles() - m_tr_base_cycles;
607		UINT64 clocks_since_base = cycles_since_base >> m_clock_scale;
608		UINT64 cycles_until_next_clock = cycles_since_base - (clocks_since_base << m_clock_scale);
	607	UINT64 clocks_since_base = cycles_since_base >> m_clck_scale;
	608	UINT64 cycles_until_next_clock = cycles_since_base - (clocks_since_base << m_clck_scale);
609	609
610	610	if (cycles_until_next_clock == 0)
611		cycles_until_next_clock = (UINT64)(1 << m_clock_scale);
	611	cycles_until_next_clock = (UINT64)(1 << m_clck_scale);
612	612
613	613	/* special case: if we have a change pending, set a timer to fire then */
614	614	if (TPR & 0x80000000)
615	615	{
616	616	UINT64 clocks_until_int = m_tr_clocks_per_tick - (clocks_since_base % m_tr_clocks_per_tick);
617		UINT64 cycles_until_int = (clocks_until_int << m_clock_scale) + cycles_until_next_clock;
	617	UINT64 cycles_until_int = (clocks_until_int << m_clck_scale) + cycles_until_next_clock;
618	618	m_timer->adjust(cycles_to_attotime(cycles_until_int + 1), 1);
619	619	}
620	620
r242413	r242414
631	631	else
632	632	{
633	633	UINT64 clocks_until_int = mulu_32x32(delta, m_tr_clocks_per_tick);
634		UINT64 cycles_until_int = (clocks_until_int << m_clock_scale) + cycles_until_next_clock;
	634	UINT64 cycles_until_int = (clocks_until_int << m_clck_scale) + cycles_until_next_clock;
635	635	m_timer->adjust(cycles_to_attotime(cycles_until_int));
636	636	}
637	637	}
r242413	r242414
1536	1536	m_op = 0;
1537	1537	m_trap_entry = 0;
1538	1538	m_clock_scale_mask = 0;
1539		m_clock_scale = 0;
	1539	m_clck_scale = 0;
1540	1540	m_clock_cycles_1 = 0;
1541	1541	m_clock_cycles_2 = 0;
1542	1542	m_clock_cycles_4 = 0;
r242413	r242414
1685	1685	save_item(NAME(m_intblock));
1686	1686	save_item(NAME(m_delay.delay_cmd));
1687	1687	save_item(NAME(m_tr_clocks_per_tick));
	1688	save_item(NAME(m_tr_base_value));
	1689	save_item(NAME(m_tr_base_cycles));
	1690	save_item(NAME(m_timer_int_pending));
	1691	save_item(NAME(m_clck_scale));
	1692	save_item(NAME(m_clock_scale_mask));
	1693	save_item(NAME(m_clock_cycles_1));
	1694	save_item(NAME(m_clock_cycles_2));
	1695	save_item(NAME(m_clock_cycles_4));
	1696	save_item(NAME(m_clock_cycles_6));
1688	1697
1689	1698	// set our instruction counter
1690	1699	m_icountptr = &m_icount;
r242413	r242414
2052	2061	}
2053	2062	}
2054	2063
2055		m_icount -= 36 << m_clock_scale;
	2064	m_icount -= 36 << m_clck_scale;
2056	2065	}
2057	2066
2058	2067	void hyperstone_device::hyperstone_divs(struct hyperstone_device::regs_decode *decode)
r242413	r242414
2101	2110	}
2102	2111	}
2103	2112
2104		m_icount -= 36 << m_clock_scale;
	2113	m_icount -= 36 << m_clck_scale;
2105	2114	}
2106	2115
2107	2116	void hyperstone_device::hyperstone_xm(struct hyperstone_device::regs_decode *decode)
r242413	r242414
4109	4118	}
4110	4119
4111	4120	if((SREG >= 0xffff8000 && SREG <= 0x7fff) && (DREG >= 0xffff8000 && DREG <= 0x7fff))
4112		m_icount -= 3 << m_clock_scale;
	4121	m_icount -= 3 << m_clck_scale;
4113	4122	else
4114		m_icount -= 5 << m_clock_scale;
	4123	m_icount -= 5 << m_clck_scale;
4115	4124	}
4116	4125
4117	4126	void hyperstone_device::hyperstone_fadd(struct hyperstone_device::regs_decode *decode)

trunk/src/emu/cpu/e132xs/e132xs.h

r242413	r242414
267	267	UINT32  m_trap_entry;   // entry point to get trap address
268	268
269	269	UINT8   m_clock_scale_mask;
270		UINT8   m_clock_scale;
	270	UINT8   m_clck_scale;
271	271	UINT8   m_clock_cycles_1;
272	272	UINT8   m_clock_cycles_2;
273	273	UINT8   m_clock_cycles_4;

trunk/src/emu/cpu/h8/h8_intc.c

r242413	r242414
22	22	void h8_intc_device::device_start()
23	23	{
24	24	memset(pending_irqs, 0, sizeof(pending_irqs));
	25	save_item(NAME(pending_irqs));
	26	save_item(NAME(irq_type));
	27	save_item(NAME(nmi_input));
	28	save_item(NAME(irq_input));
	29	save_item(NAME(ier));
	30	save_item(NAME(isr));
	31	save_item(NAME(iscr));
	32	save_item(NAME(icr_filter));
	33	save_item(NAME(ipr_filter));
25	34	}
26	35
27	36	void h8_intc_device::device_reset()
r242413	r242414
195	204	void h8h_intc_device::device_start()
196	205	{
197	206	h8_intc_device::device_start();
	207	save_item(NAME(icr));
198	208	}
199	209
200	210	void h8h_intc_device::device_reset()

trunk/src/emu/cpu/h8/h8_timer16.c

r242413	r242414
162	162	{
163	163	intc = owner()->siblingdevice<h8_intc_device>(intc_tag);
164	164	channel_active = false;
	165
	166	save_item(NAME(tgr_clearing));
	167	save_item(NAME(tcr));
	168	save_item(NAME(tier));
	169	save_item(NAME(ier));
	170	save_item(NAME(isr));
	171	save_item(NAME(clock_type));
	172	save_item(NAME(clock_divider));
	173	save_item(NAME(tcnt));
	174	save_item(NAME(tgr));
	175	save_item(NAME(last_clock_update));
	176	save_item(NAME(event_time));
	177	save_item(NAME(phase));
	178	save_item(NAME(counter_cycle));
	179	save_item(NAME(counter_incrementing));
	180	save_item(NAME(channel_active));
165	181	}
166	182
167	183	void h8_timer16_channel_device::device_reset()
r242413	r242414
330	346	sprintf(tm, "%d", i);
331	347	timer_channel[i] = subdevice<h8_timer16_channel_device>(tm);
332	348	}
	349
	350	save_item(NAME(tstr));
333	351	}
334	352
335	353	void h8_timer16_device::device_reset()

trunk/src/emu/cpu/m68000/m68kdasm.c

r242413	r242414
1718	1718	sprintf(g_dasm_str, "extb.l  D%d; (2+)", g_cpu_ir&7);
1719	1719	}
1720	1720
	1721	static void d68881_ftrap(void)
	1722	{
	1723	UINT16 w2, w3;
	1724	UINT32 l2;
	1725
	1726	LIMIT_CPU_TYPES(M68020_PLUS);
	1727	w2 = read_imm_16();
	1728
	1729	switch (g_cpu_ir & 0x7)
	1730	{
	1731	case 2:   // word operand
	1732	w3 = read_imm_16();
	1733	sprintf(g_dasm_str, "ftrap%s.w   $%04x", g_cpcc[w2 & 0x3f], w3);
	1734	break;
	1735
	1736	case 3:   // long word operand
	1737	l2 = read_imm_32();
	1738	sprintf(g_dasm_str, "ftrap%s.l   $%08x", g_cpcc[w2 & 0x3f], l2);
	1739	break;
	1740
	1741	case 4: // no operand
	1742	sprintf(g_dasm_str, "ftrap%s", g_cpcc[w2 & 0x3f]);
	1743	break;
	1744	}
	1745	}
	1746
1721	1747	static void d68040_fpu(void)
1722	1748	{
1723	1749	char float_data_format[8][3] =
r242413	r242414
3456	3482	{d68020_bfins        , 0xffc0, 0xefc0, 0xa78},
3457	3483	{d68020_bfset        , 0xffc0, 0xeec0, 0xa78},
3458	3484	{d68020_bftst        , 0xffc0, 0xe8c0, 0xa7b},
	3485	{d68881_ftrap        , 0xfff8, 0xf278, 0x000},
3459	3486	{d68010_bkpt         , 0xfff8, 0x4848, 0x000},
3460	3487	{d68000_bra_8        , 0xff00, 0x6000, 0x000},
3461	3488	{d68000_bra_16       , 0xffff, 0x6000, 0x000},

trunk/src/emu/cpu/pps4/pps4.c

r242413	r242414
1187	1187	* inverted are placed on the data lines for acceptance by
1188	1188	* the I/O. At the same time, input data received by the I/O
1189	1189	* device is transferred to the accumulator inverted.
	1190	*
	1191	* FIXME: Is BL on the I/D:8-5 lines during the I/O cycle?
1190	1192	*/
1191	1193	void pps4_device::iIOL()
1192	1194	{
1193		UINT8 ac = ~m_A & 15;
	1195	UINT8 ac = ((m_B & 15) << 4) | (~m_A & 15);
1194	1196	m_I2 = ARG();
1195	1197	m_io->write_byte(m_I2, ac);
1196	1198	LOG(("%s: port:%02x <- %x\n", __FUNCTION__, m_I2, ac));

trunk/src/emu/cpu/sh2/sh2comn.c

r242413	r242414
699	699	case 0x00:
700	700	break;
701	701	case 0x01:
702		return m_m[1] | 0; // bit31 is TDRE: Trasmit Data Register Empty. Forcing it to be '1' breaks Saturn.
	702	return m_m[1] | 0; // bit31 is TDRE: Trasmit Data Register Empty. Forcing it to be '1' breaks Saturn ...
	703	//      return m_m[1] | (0x84 << 24); // ... but this is actually needed to make EGWord on SS to boot?
703	704
704	705	case 0x04: // TIER, FTCSR, FRC
705	706	if ( mem_mask == 0x00ff0000 )

trunk/src/emu/cpu/tms0980/tms0980.c

r242413	r242414
92	92	#define M_SSE               0x00080000 /* Special Status Enable */
93	93	#define M_SSS               0x00100000 /* Special Status Sample */
94	94
95		#define M_RSTR              0x00200000 /* -> line #36, F_RSTR (TMC02x0 custom) */
96		#define M_UNK1              0x00400000 /* -> line #37, F_???? (TMC0270 custom) */
	95	#define M_RSTR              0x00200000 /* -> line #36, F_RSTR (TMS02x0 custom) */
	96	#define M_UNK1              0x00400000 /* -> line #37, F_???? (TMS0270 custom) */
97	97
98	98	/* Standard/fixed instructions - these are documented more in their specific handlers below */
99	99	#define F_BR                0x00000001
r242413	r242414
154	154	// - 32-term microinstructions PLA between the RAM and ROM, supporting 15 microinstructions
155	155	// - 16-term output PLA and segment PLA above the RAM (rotate opla 90 degrees)
156	156	const device_type TMS0970 = &device_creator<tms0970_cpu_device>; // 28-pin DIP, 11 R pins
	157	// TMS0950 is same?
157	158
158		// TMC0270 on the other hand, is a TMS0980 with earrings and a new hat. The new changes look like a quick afterthought, almost hacky
	159	// TMS0270 on the other hand, is a TMS0980 with earrings and a new hat. The new changes look like a quick afterthought, almost hacky
159	160	// - RAM, ROM, and main instructions PLA is exactly the same as TMS0980
160	161	// - 64-term microinstructions PLA between the RAM and ROM, supporting 20 microinstructions plus optional separate lines for custom opcode handling
161	162	// - 48-term output PLA above the RAM (rotate opla 90 degrees)
162		const device_type TMC0270 = &device_creator<tmc0270_cpu_device>; // 40-pin DIP, 16 O pins, 8 R pins (the other R pins are internally hooked up to support more I/O)
163		// TMC0260 is same? except opla is 32 instead of 48 terms
	163	const device_type TMS0270 = &device_creator<tms0270_cpu_device>; // 40-pin DIP, 16 O pins, 8+ R pins (some R pins are internally hooked up to support more I/O)
	164	// TMS0260 is same? except opla is 32 instead of 48 terms
164	165
165	166
166	167	static ADDRESS_MAP_START(program_11bit_9, AS_PROGRAM, 16, tms1xxx_cpu_device)
r242413	r242414
249	250	}
250	251
251	252
252		tmc0270_cpu_device::tmc0270_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
253		: tms0980_cpu_device(mconfig, TMC0270, "TMC0270", tag, owner, clock, 16, 8, 4, 7, 9, 4, 12, ADDRESS_MAP_NAME(program_11bit_9), 8, ADDRESS_MAP_NAME(data_64x9_as4), "tmc0270", __FILE__)
	253	tms0270_cpu_device::tms0270_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	254	: tms0980_cpu_device(mconfig, TMS0270, "TMS0270", tag, owner, clock, 16, 16, 4, 7, 9, 4, 12, ADDRESS_MAP_NAME(program_11bit_9), 8, ADDRESS_MAP_NAME(data_64x9_as4), "tms0270", __FILE__)
254	255	{
255	256	}
256	257
r242413	r242414
309	310	}
310	311
311	312
312		static MACHINE_CONFIG_FRAGMENT(tmc0270)
	313	static MACHINE_CONFIG_FRAGMENT(tms0270)
313	314
314	315	// main opcodes PLA, microinstructions PLA, output PLA
315	316	MCFG_PLA_ADD("ipla", 9, 22, 24)
r242413	r242414
320	321	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
321	322	MACHINE_CONFIG_END
322	323
323		machine_config_constructor tmc0270_cpu_device::device_mconfig_additions() const
	324	machine_config_constructor tms0270_cpu_device::device_mconfig_additions() const
324	325	{
325		return MACHINE_CONFIG_NAME(tmc0270);
	326	return MACHINE_CONFIG_NAME(tms0270);
326	327	}
327	328
328	329
r242413	r242414
396	397	m_cs = 0;
397	398	m_r = 0;
398	399	m_o = 0;
399		m_o_latch = 0;
400		m_o_latch_low = 0;
401	400	m_cki_bus = 0;
402	401	m_c4 = 0;
403	402	m_p = 0;
r242413	r242414
422	421	m_micro = 0;
423	422	m_subcycle = 0;
424	423
425		m_a_prev = m_a;
426		m_r_prev = m_r;
427		m_o_latch_prev = m_o_latch;
428
429	424	// register for savestates
430	425	save_item(NAME(m_pc));
431	426	save_item(NAME(m_sr));
r242413	r242414
439	434	save_item(NAME(m_cs));
440	435	save_item(NAME(m_r));
441	436	save_item(NAME(m_o));
442		save_item(NAME(m_o_latch));
443		save_item(NAME(m_o_latch_low));
444	437	save_item(NAME(m_cki_bus));
445	438	save_item(NAME(m_c4));
446	439	save_item(NAME(m_p));
r242413	r242414
465	458	save_item(NAME(m_micro));
466	459	save_item(NAME(m_subcycle));
467	460
468		save_item(NAME(m_a_prev));
469		save_item(NAME(m_r_prev));
470		save_item(NAME(m_o_latch_prev));
471
472	461	// register state for debugger
473	462	state_add(TMS0980_PC,     "PC",     m_pc    ).formatstr("%02X");
474	463	state_add(TMS0980_SR,     "SR",     m_sr    ).formatstr("%01X");
r242413	r242414
485	474	m_icountptr = &m_icount;
486	475	}
487	476
	477	void tms0270_cpu_device::device_start()
	478	{
	479	// common init
	480	tms1xxx_cpu_device::device_start();
488	481
	482	// zerofill
	483	m_a_prev = 0;
	484	m_r_prev = 0;
489	485
	486	m_o_latch_low = 0;
	487	m_o_latch = 0;
	488	m_o_latch_prev = 0;
	489
	490	// register for savestates
	491	save_item(NAME(m_a_prev));
	492	save_item(NAME(m_r_prev));
	493
	494	save_item(NAME(m_o_latch_low));
	495	save_item(NAME(m_o_latch));
	496	save_item(NAME(m_o_latch_prev));
	497	}
	498
	499
	500
490	501	//-------------------------------------------------
491	502	//  device_reset - device-specific reset
492	503	//-------------------------------------------------
r242413	r242414
513	524	// clear outputs
514	525	m_r = 0;
515	526	m_write_r(0, m_r & m_r_mask, 0xffff);
516		m_o_latch_low = 0;
517		m_o_latch = 0;
518	527	write_o_output(0);
519	528	m_write_r(0, m_r & m_r_mask, 0xffff);
520	529	m_power_off(0);
r242413	r242414
625	634	UINT32 mask = m_mpla->read(sel);
626	635	mask ^= 0x43fc3; // invert active-negative
627	636
628		// M_RSTR is specific to TMC02x0, it redirects to F_RSTR
629		// M_UNK1 is specific to TMC0270, unknown yet
	637	// M_RSTR is specific to TMS02x0, it redirects to F_RSTR
	638	// M_UNK1 is specific to TMS0270, unknown yet
630	639	//                      _______  ______                                _____  _____  _____  _____  ______  _____  ______  _____                            _____
631	640	const UINT32 md[22] = { M_NDMTP, M_DMTP, M_AUTY, M_AUTA, M_CKM, M_SSE, M_CKP, M_YTP, M_MTP, M_ATN, M_NATN, M_MTN, M_15TN, M_CKN, M_NE, M_C8, M_SSS, M_CME, M_CIN, M_STO, M_RSTR, M_UNK1 };
632	641
r242413	r242414
673	682	m_micro_direct[op] = decode_micro(op);
674	683	}
675	684
	685	void tms0270_cpu_device::device_reset()
	686	{
	687	// common reset
	688	tms0980_cpu_device::device_reset();
676	689
	690	m_a_prev = m_a;
	691	m_r_prev = m_r;
677	692
	693	m_o_latch_low = 0;
	694	m_o_latch = 0;
	695	m_o_latch_prev = 0;
	696	}
	697
	698
	699
678	700	//-------------------------------------------------
679	701	//  program counter/opcode decode
680	702	//-------------------------------------------------
r242413	r242414
724	746	next_pc();
725	747	}
726	748
727		void tmc0270_cpu_device::read_opcode()
	749	void tms0270_cpu_device::read_opcode()
728	750	{
729	751	tms0980_cpu_device::read_opcode();
730	752
731	753	// RSTR is on the mpla
732	754	if (m_micro & M_RSTR)
733	755	m_fixed |= F_RSTR;
734
735		// TODO: M_UNK1
736	756	}
737	757
738	758
r242413	r242414
741	761	//  i/o handling
742	762	//-------------------------------------------------
743	763
744		void tms1xxx_cpu_device::write_o_output(UINT8 data)
	764	void tms1xxx_cpu_device::write_o_output(UINT8 index)
745	765	{
746	766	// a hardcoded table is supported if the output pla is unknown
747		m_o = (c_output_pla == NULL) ? m_opla->read(data) : c_output_pla[data];
	767	m_o = (c_output_pla == NULL) ? m_opla->read(index) : c_output_pla[index];
748	768	m_write_o(0, m_o & m_o_mask, 0xffff);
749	769	}
750	770
751		void tms0970_cpu_device::write_o_output(UINT8 data)
	771	void tms0970_cpu_device::write_o_output(UINT8 index)
752	772	{
753		m_o = m_spla->read(data);
	773	m_o = m_spla->read(index);
754	774	m_write_o(0, m_o & m_o_mask, 0xffff);
755	775	}
756	776
757	777
758		void tmc0270_cpu_device::dynamic_output()
	778	void tms0270_cpu_device::dynamic_output()
759	779	{
760	780	// TODO..
761	781
r242413	r242414
773	793	return (k & 0xf) | k3;
774	794	}
775	795
776		UINT8 tmc0270_cpu_device::read_k_input()
	796	UINT8 tms0270_cpu_device::read_k_input()
777	797	{
778	798	// TODO..
779	799
r242413	r242414
994	1014	}
995	1015
996	1016
997		// TMC0270-specific
998		void tmc0270_cpu_device::op_tdo()
	1017	// TMS0270-specific
	1018	void tms0270_cpu_device::op_tdo()
999	1019	{
1000	1020	// TDO: transfer data out
1001	1021	if (m_status)
r242413	r242414
1003	1023	else
1004	1024	m_o_latch = m_o_latch_low | (m_a << 4 & 0x30);
1005	1025
1006		// handled further in dynamic_output
	1026	// write to output is done in dynamic_output
1007	1027	}
1008	1028
	1029	void tms0270_cpu_device::op_setr()
	1030	{
	1031	// same as default, but handle write to output in dynamic_output
	1032	m_r = m_r | (1 << m_y);
	1033	}
1009	1034
	1035	void tms0270_cpu_device::op_rstr()
	1036	{
	1037	// same as default, but handle write to output in dynamic_output
	1038	m_r = m_r & ~(1 << m_y);
	1039	}
1010	1040
	1041
	1042
1011	1043	//-------------------------------------------------
1012	1044	//  execute_run
1013	1045	//-------------------------------------------------
r242413	r242414
1070	1102	}
1071	1103
1072	1104	// execute: k input valid, read ram, clear alu inputs
	1105	dynamic_output();
1073	1106	set_cki_bus();
1074		dynamic_output();
1075	1107	m_ram_in = m_data->read_byte(m_ram_address) & 0xf;
1076	1108	m_dam_in = m_data->read_byte(m_ram_address | (0x10 << (m_x_bits-1))) & 0xf;
1077	1109	m_ram_out = -1;

trunk/src/emu/cpu/tms0980/tms0980.h

r242413	r242414
5	5	TMS0980/TMS1000-family MCU cores
6	6
7	7	*/
	8
8	9	#ifndef _TMS0980_H_
9	10	#define _TMS0980_H_
10	11
r242413	r242414
12	13	#include "machine/pla.h"
13	14
14	15
15		#define MCFG_TMS1XXX_OUTPUT_PLA(_pla) \
16		tms1xxx_cpu_device::set_output_pla(*device, _pla);
17
	16	// K input pins
18	17	#define MCFG_TMS1XXX_READ_K_CB(_devcb) \
19	18	tms1xxx_cpu_device::set_read_k_callback(*device, DEVCB_##_devcb);
20	19
	20	// O/Segment output pins
21	21	#define MCFG_TMS1XXX_WRITE_O_CB(_devcb) \
22	22	tms1xxx_cpu_device::set_write_o_callback(*device, DEVCB_##_devcb);
23	23
	24	// R output pins (also called D on some chips)
24	25	#define MCFG_TMS1XXX_WRITE_R_CB(_devcb) \
25	26	tms1xxx_cpu_device::set_write_r_callback(*device, DEVCB_##_devcb);
26	27
	28	// OFF opcode on TMS0980 and up
27	29	#define MCFG_TMS1XXX_POWER_OFF_CB(_devcb) \
28	30	tms1xxx_cpu_device::set_power_off_callback(*device, DEVCB_##_devcb);
29	31
	32	// Use this if the output PLA is unknown:
	33	// If the microinstructions (or other) PLA is unknown, try using one from another romset.
	34	#define MCFG_TMS1XXX_OUTPUT_PLA(_pla) \
	35	tms1xxx_cpu_device::set_output_pla(*device, _pla);
30	36
	37
	38
31	39	class tms1xxx_cpu_device : public cpu_device
32	40	{
33	41	public:
r242413	r242414
61	69	template<class _Object> static devcb_base &set_write_r_callback(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_write_r.set_callback(object); }
62	70	template<class _Object> static devcb_base &set_power_off_callback(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_power_off.set_callback(object); }
63	71	static void set_output_pla(device_t &device, const UINT16 *output_pla) { downcast<tms1xxx_cpu_device &>(device).c_output_pla = output_pla; }
64
	72
65	73	protected:
66	74	// device-level overrides
67	75	virtual void device_start();
r242413	r242414
69	77
70	78	// device_execute_interface overrides
71	79	virtual UINT32 execute_min_cycles() const { return 1; }
72		virtual UINT32 execute_max_cycles() const { return 1; }
	80	virtual UINT32 execute_max_cycles() const { return 6; }
73	81	virtual UINT32 execute_input_lines() const { return 1; }
74	82	virtual void execute_run();
75	83
r242413	r242414
84	92
85	93	void next_pc();
86	94
87		virtual void write_o_output(UINT8 data);
	95	virtual void write_o_output(UINT8 index);
88	96	virtual UINT8 read_k_input();
89	97	virtual void set_cki_bus();
90	98	virtual void dynamic_output() { ; } // not used by default
r242413	r242414
122	130	UINT8   m_pa;        // 4-bit page address register
123	131	UINT8   m_pb;        // 4-bit page buffer register
124	132	UINT8   m_a;         // 4-bit accumulator
125		UINT8   m_a_prev;
126	133	UINT8   m_x;         // 2,3,or 4-bit RAM X register
127	134	UINT8   m_y;         // 4-bit RAM Y register
128	135	UINT8   m_ca;        // chapter address bit
129	136	UINT8   m_cb;        // chapter buffer bit
130	137	UINT8   m_cs;        // chapter subroutine bit
131	138	UINT16  m_r;
132		UINT16  m_r_prev;
133	139	UINT16  m_o;
134		UINT8   m_o_latch;   // TMC0270 hold latch
135		UINT8   m_o_latch_low;
136		UINT8   m_o_latch_prev;
137	140	UINT8   m_cki_bus;
138	141	UINT8   m_c4;
139	142	UINT8   m_p;         // 4-bit adder p(lus)-input
r242413	r242414
252	255	virtual void device_reset();
253	256	virtual machine_config_constructor device_mconfig_additions() const;
254	257
255		virtual void write_o_output(UINT8 data);
	258	virtual void write_o_output(UINT8 index);
256	259
257	260	virtual void op_setr();
258	261	virtual void op_tdo();
r242413	r242414
284	287	};
285	288
286	289
287		class tmc0270_cpu_device : public tms0980_cpu_device
	290	class tms0270_cpu_device : public tms0980_cpu_device
288	291	{
289	292	public:
290		tmc0270_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	293	tms0270_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
291	294
292	295	protected:
293	296	// overrides
	297	virtual void device_start();
	298	virtual void device_reset();
	299
294	300	virtual machine_config_constructor device_mconfig_additions() const;
295	301
296		virtual void write_o_output(UINT8 data) { tms1xxx_cpu_device::write_o_output(data); }
	302	virtual void write_o_output(UINT8 index) { tms1xxx_cpu_device::write_o_output(index); }
297	303	virtual UINT8 read_k_input();
298	304	virtual void dynamic_output();
299	305	virtual void read_opcode();
300	306
301		virtual void op_setr() { tms1xxx_cpu_device::op_setr(); }
302		virtual void op_rstr() { tms1xxx_cpu_device::op_rstr(); }
	307	virtual void op_setr();
	308	virtual void op_rstr();
303	309	virtual void op_tdo();
	310
	311	private:
	312	UINT8   m_a_prev;
	313	UINT16  m_r_prev;
	314
	315	UINT8   m_o_latch_low;
	316	UINT8   m_o_latch;
	317	UINT8   m_o_latch_prev;
304	318	};
305	319
306	320
r242413	r242414
312	326	extern const device_type TMS1300;
313	327	extern const device_type TMS0970;
314	328	extern const device_type TMS0980;
315		extern const device_type TMC0270;
	329	extern const device_type TMS0270;
316	330
317	331
318	332	#endif /* _TMS0980_H_ */

trunk/src/emu/drivers/xtal.h

r242413	r242414
47	47	------------------    ------------  ------------------------------------------------------------ */
48	48	XTAL_32_768kHz      = 32768,        /* 32.768kHz, used to drive RTC chips */
49	49	XTAL_1MHz           = 1000000,      /* Used to drive OKI M6295 chips */
	50	XTAL_1_2944MHz      = 1294400,      /* BBN BitGraph PSG */
50	51	XTAL_1_75MHz        = 1750000,      /* RCA CDP1861 */
51	52	XTAL_1_8432MHz      = 1843200,      /* Bondwell 12/14 */
52	53	XTAL_1_9968MHz      = 1996800,      /* NEC PC-98xx */
r242413	r242414
80	81	XTAL_6MHz           = 6000000,      /* American Poker II */
81	82	XTAL_6_144MHz       = 6144000,      /* Used on Alpha Denshi early 80's games sound board and Casio FP-200 main CPU */
82	83	XTAL_6_5MHz         = 6500000,      /* Jupiter Ace */
	84	XTAL_6_9MHz         = 6900000,      /* BBN BitGraph CPU */
83	85	XTAL_7MHz           = 7000000,      /* Jaleco Mega System PCBs */
84	86	XTAL_7_15909MHz     = 7159090,      /* Blood Bros (2x NTSC subcarrier) */
85	87	XTAL_7_3728MHz      = 7372800,
r242413	r242414
92	94	XTAL_8_7MHz         = 8700000,      /* Tandberg TDV 2324 */
93	95	XTAL_8_867236MHz    = 8867236,      /* RCA CDP1869 PAL color clock (~2x PAL subcarrier) */
94	96	XTAL_8_867238MHz    = 8867238,      /* ETI-660 (~2x PAL subcarrier) */
	97	XTAL_8_945MHz       = 8945000,      /* Hit Me */
95	98	XTAL_9_216MHz       = 9216000,      /* Conitec PROF-180X */
96		XTAL_8_945MHz       = 8945000,      /* Hit Me */
97	99	XTAL_9_828MHz       = 9828000,      /* Universal PCBs */
98	100	XTAL_9_8304MHz      = 9830400,      /* Epson PX-8 */
99	101	XTAL_9_987MHz       = 9987000,      /* Crazy Balloon */
r242413	r242414
187	189	XTAL_30_4761MHz     = 30476100,     /* Taito JC */
188	190	XTAL_30_8MHz        = 30800000,     /* 15IE-00-013 */
189	191	XTAL_32MHz          = 32000000,
190		XTAL_32_22MHz       = 32220000,     /* Typically used on 90's Data East PCBs */
	192	XTAL_32_22MHz       = 32220000,     /* Typically used on 90's Data East PCBs (close to 9x NTSC subcarrier which is 32.215905Mhz*/
191	193	XTAL_32_5304MHz     = 32530400,     /* Seta 2 */
192	194	XTAL_33MHz          = 33000000,     /* Sega Model 3 video board */
193	195	XTAL_33_333MHz      = 33333000,     /* Sega Model 3 CPU board, Vegas */
r242413	r242414
207	209	XTAL_48_66MHz       = 48660000,     /* Zaxxon */
208	210	XTAL_49_152MHz      = 49152000,     /* Used on some Namco PCBs, Baraduke h/w, System 21, Super System 22  */
209	211	XTAL_50MHz          = 50000000,     /* Williams/Midway T/W/V-unit system */
210		XTAL_50_113MHz      = 50113000,     /* Namco NA-1 */
	212	XTAL_50_113MHz      = 50113000,     /* Namco NA-1 (14x NTSC subcarrier)*/
211	213	XTAL_52MHz          = 52000000,     /* Cojag */
212	214	XTAL_52_832MHz      = 52832000,     /* Wang PC TIG video controller */
213	215	XTAL_53_693175MHz   = 53693175,     /* PSX-based h/w, Sony ZN1-2-based (15x NTSC subcarrier) */
r242413	r242414
231	233	XTAL_400kHz         = 400000,       /* OKI MSM5205 on Great Swordman h/w */
232	234	XTAL_455kHz         = 455000,       /* OKI MSM5205 on Gladiator h/w */
233	235	XTAL_512kHz         = 512000,       /* Toshiba TC8830F */
234		XTAL_640kHz         = 640000,       /* NEC UPD7759, Texas Instruments Speech Chips */
	236	XTAL_640kHz         = 640000,       /* NEC UPD7759, Texas Instruments Speech Chips @ 8khz */
235	237	XTAL_1_056MHz       = 1056000       /* OKI M6295 on Trio The Punch h/w */
236	238	};
237	239

trunk/src/emu/imagedev/floppy.c

r242413	r242414
295	295	ready_counter = 0;
296	296
297	297	setup_characteristics();
	298
	299	save_item(NAME(cyl));
	300	save_item(NAME(subcyl));
298	301	}
299	302
300	303	void floppy_image_device::device_reset()

trunk/src/emu/luaengine.c

r242413	r242414
197	197	}
198	198
199	199	//-------------------------------------------------
	200	//  emu_app_name - return application name
	201	//-------------------------------------------------
	202
	203	int lua_engine::l_emu_app_name(lua_State *L)
	204	{
	205	lua_pushstring(L, emulator_info::get_appname_lower());
	206	return 1;
	207	}
	208
	209	//-------------------------------------------------
	210	//  emu_app_version - return application version
	211	//-------------------------------------------------
	212
	213	int lua_engine::l_emu_app_version(lua_State *L)
	214	{
	215	lua_pushstring(L, bare_build_version);
	216	return 1;
	217	}
	218
	219
	220	//-------------------------------------------------
200	221	//  emu_gamename - returns game full name
201	222	//-------------------------------------------------
202	223
r242413	r242414
521	542	{
522	543	luabridge::getGlobalNamespace (m_lua_state)
523	544	.beginNamespace ("emu")
	545	.addCFunction ("app_name",    l_emu_app_name )
	546	.addCFunction ("app_version", l_emu_app_version )
524	547	.addCFunction ("gamename",    l_emu_gamename )
525	548	.addCFunction ("romname",     l_emu_romname )
526	549	.addCFunction ("keypost",     l_emu_keypost )
r242413	r242414
549	572	.addData ("manufacturer", &game_driver::manufacturer)
550	573	.endClass ()
551	574	.endNamespace ();
	575
552	576	luabridge::push (m_lua_state, machine_manager::instance());
553	577	lua_setglobal(m_lua_state, "manager");
554	578	}

trunk/src/emu/luaengine.h

r242413	r242414
76	76
77	77	static int l_ioport_write(lua_State *L);
78	78	static int l_emu_after(lua_State *L);
	79	static int l_emu_app_name(lua_State *L);
	80	static int l_emu_app_version(lua_State *L);
79	81	static int l_emu_wait(lua_State *L);
80	82	static int l_emu_time(lua_State *L);
81	83	static int l_emu_gamename(lua_State *L);

trunk/src/emu/machine/i6300esb.c

r242413	r242414
40	40	AM_RANGE(0x88, 0x8b) AM_READWRITE8 (d31_err_sts_r,          d31_err_sts_w,          0x00ff0000)
41	41	AM_RANGE(0x90, 0x93) AM_READWRITE16(pci_dma_cfg_r,          pci_dma_cfg_w,          0x0000ffff)
42	42	AM_RANGE(0xa0, 0xa3) AM_READWRITE16(gen_pmcon_1_r,          gen_pmcon_1_w,          0x0000ffff)
43		AM_RANGE(0xa0, 0xa3) AM_READWRITE16(gen_pmcon_2_r,          gen_pmcon_2_w,          0xffff0000)
	43	AM_RANGE(0xa0, 0xa3) AM_READWRITE8 (gen_pmcon_2_r,          gen_pmcon_2_w,          0x00ff0000)
44	44	AM_RANGE(0xa4, 0xa7) AM_READWRITE8 (gen_pmcon_3_r,          gen_pmcon_3_w,          0x000000ff)
45	45	AM_RANGE(0xac, 0xaf) AM_READWRITE  (rst_cnt2_r,             rst_cnt2_w)
46	46	AM_RANGE(0xb0, 0xb3) AM_READWRITE8 (apm_cnt_r,              apm_cnt_w,              0x00ff0000)
r242413	r242414
121	121	memset(mon_trp_rng, 0, sizeof(mon_trp_rng));
122	122	mon_trp_msk = 0;
123	123	nmi_sc = 0;
	124	gen_sta = 0x00;
124	125	}
125	126
126	127	void i6300esb_lpc_device::reset_all_mappings()
r242413	r242414
293	294	logerror("%s: gen_pmcon_1 = %04x\n", tag(), gen_pmcon_1);
294	295	}
295	296
296		READ16_MEMBER (i6300esb_lpc_device::gen_pmcon_2_r)
	297	READ8_MEMBER (i6300esb_lpc_device::gen_pmcon_2_r)
297	298	{
298	299	return gen_pmcon_2;
299	300	}
300	301
301		WRITE16_MEMBER(i6300esb_lpc_device::gen_pmcon_2_w)
	302	WRITE8_MEMBER (i6300esb_lpc_device::gen_pmcon_2_w)
302	303	{
303		COMBINE_DATA(&gen_pmcon_2);
304		logerror("%s: gen_pmcon_2 = %04x\n", tag(), gen_pmcon_2);
	304	gen_pmcon_2 = data;
	305	logerror("%s: gen_pmcon_2 = %02x\n", tag(), gen_pmcon_2);
305	306	}
306	307
307	308	READ8_MEMBER  (i6300esb_lpc_device::gen_pmcon_3_r)

trunk/src/emu/machine/i6300esb.h

r242413	r242414
37	37	DECLARE_ADDRESS_MAP(internal_io_map, 32);
38	38
39	39	UINT32 pmbase, gpio_base, fwh_sel1, gen_cntl, etr1, rst_cnt2, gpi_rout;
40		UINT16 bios_cntl, pci_dma_cfg, gen1_dec, lpc_en, gen2_dec, fwh_sel2, func_dis, gen_pmcon_1, gen_pmcon_2;
	40	UINT16 bios_cntl, pci_dma_cfg, gen1_dec, lpc_en, gen2_dec, fwh_sel2, func_dis, gen_pmcon_1;
41	41	UINT16 mon_trp_rng[4], mon_trp_msk;
42	42	UINT8 pirq_rout[8];
43	43	UINT8 acpi_cntl, tco_cntl, gpio_cntl, serirq_cntl, d31_err_cfg, d31_err_sts, gen_sta, back_cntl, rtc_conf;
44	44	UINT8 lpc_if_com_range, lpc_if_fdd_lpt_range, lpc_if_sound_range, fwh_dec_en1, fwh_dec_en2, siu_config_port;
45		UINT8 gen_pmcon_3, apm_cnt, apm_sts, mon_fwd_en, nmi_sc;
	45	UINT8 gen_pmcon_2, gen_pmcon_3, apm_cnt, apm_sts, mon_fwd_en, nmi_sc;
46	46	int siu_config_state;
47	47
48	48	DECLARE_WRITE8_MEMBER (nop_w);
r242413	r242414
74	74	DECLARE_WRITE16_MEMBER(pci_dma_cfg_w);
75	75	DECLARE_READ16_MEMBER (gen_pmcon_1_r);          // a0
76	76	DECLARE_WRITE16_MEMBER(gen_pmcon_1_w);
77		DECLARE_READ16_MEMBER (gen_pmcon_2_r);          // a2
78		DECLARE_WRITE16_MEMBER(gen_pmcon_2_w);
	77	DECLARE_READ8_MEMBER (gen_pmcon_2_r);           // a2
	78	DECLARE_WRITE8_MEMBER(gen_pmcon_2_w);
79	79	DECLARE_READ8_MEMBER  (gen_pmcon_3_r);          // a4
80	80	DECLARE_WRITE8_MEMBER (gen_pmcon_3_w);
81	81	DECLARE_READ32_MEMBER (rst_cnt2_r);             // ac

trunk/src/emu/machine/i82875p.c

r242413	r242414
1	1	#include "i82875p.h"
2	2
3		const device_type I82875P_HOST = &device_creator<i82875p_host_device>;
4		const device_type I82875P_AGP  = &device_creator<i82875p_agp_device>;
	3	const device_type I82875P_HOST     = &device_creator<i82875p_host_device>;
	4	const device_type I82875P_AGP      = &device_creator<i82875p_agp_device>;
	5	const device_type I82875P_OVERFLOW = &device_creator<i82875p_overflow_device>;
5	6
6	7	DEVICE_ADDRESS_MAP_START(agp_translation_map, 32, i82875p_host_device)
7	8	ADDRESS_MAP_END
r242413	r242414
237	238	return toud;
238	239	}
239	240
	241	#include "debugger.h"
	242
240	243	WRITE16_MEMBER(i82875p_host_device::toud_w)
241	244	{
242	245	COMBINE_DATA(&toud);
243		logerror("%s: toud = %08x\n", tag(), 512*toud);
	246	toud &= ~7;
	247	logerror("%s: toud = %08x\n", tag(), toud << 16);
244	248	remap_cb();
	249	debugger_break(machine());
245	250	}
246	251
247	252	READ16_MEMBER( i82875p_host_device::mchcfg_r)
r242413	r242414
309	314	return 0x00;
310	315	}
311	316
	317	void i82875p_host_device::reset_all_mappings()
	318	{
	319	pci_host_device::reset_all_mappings();
	320
	321	toud = 0x0400;
	322	smram = 0x02;
	323	esmramc = 0x38;
	324	memset(pam, 0, sizeof(pam));
	325	}
	326
312	327	void i82875p_host_device::device_reset()
313	328	{
314	329	pci_host_device::device_reset();
315	330
316	331	agpm = 0x00;
317	332	fpllcont = 0x00;
318		memset(pam, 0, sizeof(pam));
319		smram = 0x02;
320		esmramc = 0x38;
321	333	agpctrl = 0x00000000;
322	334	apsize = 0x00;
323	335	attbase = 0x00000000;
324	336	amtt = 0x10;
325	337	lptt = 0x10;
326		toud = 0x0400;
327	338	mchcfg = 0x0000;
328	339	errcmd = 0x0000;
329	340	smicmd = 0x0000;
r242413	r242414
337	348	io_space->install_device(0, 0xffff, *static_cast<pci_host_device *>(this), &pci_host_device::io_configuration_access_map);
338	349
339	350	UINT32 top = toud << 16;
	351	if(esmramc & 1) {
	352	switch((esmramc >> 1) & 3) {
	353	case 2: top += 512*1024; break;
	354	case 3: top += 1024*1024; break;
	355	}
	356	}
	357
340	358	if(top > ram_size)
341	359	top = ram_size;
342	360
r242413	r242414
406	424
407	425	if((esmramc & 0x40) && (smram & 0x08))
408	426	memory_space->install_ram      (0xfeda0000, 0xfedbffff, &ram[0x000a0000/4]);
409
410	427	}
411	428
412	429
413
414
415	430	i82875p_agp_device::i82875p_agp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
416	431	: agp_bridge_device(mconfig, I82875P_AGP, "i82875p AGP bridge", tag, owner, clock, "i82875p_agp", __FILE__)
417	432	{
r242413	r242414
426	441	{
427	442	agp_bridge_device::device_reset();
428	443	}
	444
	445	DEVICE_ADDRESS_MAP_START(overflow_map, 32, i82875p_overflow_device)
	446	AM_RANGE(0x000, 0x007) AM_READWRITE8(dram_row_boundary_r,    dram_row_boundary_w,  0xffffffff)
	447	AM_RANGE(0x010, 0x013) AM_READWRITE8(dram_row_attribute_r,   dram_row_attribute_w, 0xffffffff)
	448	AM_RANGE(0x060, 0x064) AM_READWRITE (dram_timing_r,          dram_timing_w)
	449	AM_RANGE(0x068, 0x06b) AM_READWRITE (dram_controller_mode_r, dram_controller_mode_w)
	450	ADDRESS_MAP_END
	451
	452
	453	i82875p_overflow_device::i82875p_overflow_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	454	: pci_device(mconfig, I82875P_OVERFLOW, "i82875p configuration overflow", tag, owner, clock, "i82875p_overflow", __FILE__)
	455	{
	456	}
	457
	458	void i82875p_overflow_device::device_start()
	459	{
	460	pci_device::device_start();
	461
	462	add_map(4*1024, M_MEM, FUNC(i82875p_overflow_device::overflow_map));
	463	}
	464
	465	void i82875p_overflow_device::device_reset()
	466	{
	467	pci_device::device_reset();
	468	memset(dram_row_boundary, 1, sizeof(dram_row_boundary));
	469	memset(dram_row_attribute, 0, sizeof(dram_row_attribute));
	470	dram_timing = 0;
	471	dram_controller_mode = 0x00010001;
	472	}
	473
	474	READ8_MEMBER  (i82875p_overflow_device::dram_row_boundary_r)
	475	{
	476	return dram_row_boundary[offset];
	477	}
	478
	479	WRITE8_MEMBER (i82875p_overflow_device::dram_row_boundary_w)
	480	{
	481	dram_row_boundary[offset] = data;
	482	logerror("%s: dram_row_boundary_w %d, %02x\n", tag(), offset, data);
	483	}
	484
	485	READ8_MEMBER  (i82875p_overflow_device::dram_row_attribute_r)
	486	{
	487	return dram_row_attribute[offset];
	488	}
	489
	490	WRITE8_MEMBER (i82875p_overflow_device::dram_row_attribute_w)
	491	{
	492	dram_row_attribute[offset] = data;
	493	logerror("%s: dram_row_attribute_w %d, %02x\n", tag(), offset, data);
	494	}
	495
	496	READ32_MEMBER (i82875p_overflow_device::dram_timing_r)
	497	{
	498	return dram_timing;
	499	}
	500
	501	WRITE32_MEMBER(i82875p_overflow_device::dram_timing_w)
	502	{
	503	COMBINE_DATA(&dram_timing);
	504	logerror("%s: dram_timing_w %08x\n", tag(), dram_timing);
	505	}
	506
	507	READ32_MEMBER (i82875p_overflow_device::dram_controller_mode_r)
	508	{
	509	return dram_controller_mode;
	510	}
	511
	512	WRITE32_MEMBER(i82875p_overflow_device::dram_controller_mode_w)
	513	{
	514	COMBINE_DATA(&dram_controller_mode);
	515	logerror("%s: dram_controller_mode_w %08x\n", tag(), dram_controller_mode);
	516	}

trunk/src/emu/machine/i82875p.h

r242413	r242414
5	5
6	6	#include "pci.h"
7	7
8		#define MCFG_I82875P_HOST_ADD(_tag, _subdevice_id, _cpu_tag, _ram_size)         \
	8	#define MCFG_I82875P_HOST_ADD(_tag, _subdevice_id, _cpu_tag, _ram_size)    \
9	9	MCFG_PCI_HOST_ADD(_tag, I82875P_HOST, 0x80862578, 0x02, _subdevice_id) \
10		downcast<i82875p_host_device *>(device)->set_cpu_tag(_cpu_tag); \
	10	downcast<i82875p_host_device *>(device)->set_cpu_tag(_cpu_tag);        \
11	11	downcast<i82875p_host_device *>(device)->set_ram_size(_ram_size);
12	12
13	13	#define MCFG_I82875P_AGP_ADD(_tag) \
14	14	MCFG_AGP_BRIDGE_ADD(_tag, I82875P_AGP, 0x80862579, 0x02)
15	15
	16	#define MCFG_I82875P_OVERFLOW_ADD(_tag, _subdevice_id)    \
	17	MCFG_PCI_DEVICE_ADD(_tag, I82875P_OVERFLOW, 0x8086257e, 0x02, 0x088000, _subdevice_id)
	18
16	19	class i82875p_host_device : public pci_host_device {
17	20	public:
18	21	i82875p_host_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
r242413	r242414
20	23	void set_cpu_tag(const char *tag);
21	24	void set_ram_size(int ram_size);
22	25
	26	virtual void reset_all_mappings();
	27
23	28	virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
24	29	UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
25	30
r242413	r242414
98	103	virtual void device_reset();
99	104	};
100	105
	106	class i82875p_overflow_device : public pci_device {
	107	public:
	108	i82875p_overflow_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	109
	110
	111	DECLARE_READ8_MEMBER  (dram_row_boundary_r);
	112	DECLARE_WRITE8_MEMBER (dram_row_boundary_w);
	113	DECLARE_READ8_MEMBER  (dram_row_attribute_r);
	114	DECLARE_WRITE8_MEMBER (dram_row_attribute_w);
	115	DECLARE_READ32_MEMBER (dram_timing_r);
	116	DECLARE_WRITE32_MEMBER(dram_timing_w);
	117	DECLARE_READ32_MEMBER (dram_controller_mode_r);
	118	DECLARE_WRITE32_MEMBER(dram_controller_mode_w);
	119
	120	protected:
	121
	122	virtual void device_start();
	123	virtual void device_reset();
	124
	125	private:
	126	DECLARE_ADDRESS_MAP(overflow_map, 32);
	127
	128	UINT8 dram_row_boundary[8], dram_row_attribute[4];
	129	UINT32 dram_timing, dram_controller_mode;
	130	};
	131
101	132	extern const device_type I82875P_HOST;
102	133	extern const device_type I82875P_AGP;
	134	extern const device_type I82875P_OVERFLOW;
103	135
104	136
105	137	#endif

trunk/src/emu/machine/machine.mak

r242413	r242414
1304	1304
1305	1305	#-------------------------------------------------
1306	1306	#
	1307	#@src/emu/machine/r10696.h,MACHINES += R10696
	1308	#-------------------------------------------------
	1309
	1310	ifneq ($(filter R10696,$(MACHINES)),)
	1311	MACHINEOBJS+= $(MACHINEOBJ)/r10696.o
	1312	endif
	1313
	1314	#-------------------------------------------------
	1315	#
1307	1316	#@src/emu/machine/r10788.h,MACHINES += R10788
1308	1317	#-------------------------------------------------
1309	1318
r242413	r242414
1313	1322
1314	1323	#-------------------------------------------------
1315	1324	#
	1325	#@src/emu/machine/ra17xx.h,MACHINES += RA17XX
	1326	#-------------------------------------------------
	1327
	1328	ifneq ($(filter RA17XX,$(MACHINES)),)
	1329	MACHINEOBJS+= $(MACHINEOBJ)/ra17xx.o
	1330	endif
	1331
	1332	#-------------------------------------------------
	1333	#
1316	1334	#@src/emu/machine/rf5c296.h,MACHINES += RF5C296
1317	1335	#-------------------------------------------------
1318	1336

trunk/src/emu/machine/pci.c

r242413	r242414
63	63	revision = 0x00;
64	64	pclass = 0xffffff;
65	65	subsystem_id = 0xffffffff;
	66	is_multifunction_device = false;
66	67	}
67	68
68	69	void pci_device::set_ids(UINT32 _main_id, UINT8 _revision, UINT32 _pclass, UINT32 _subsystem_id)
r242413	r242414
194	195	return 0x00;
195	196	}
196	197
	198	void pci_device::set_multifunction_device(bool enable)
	199	{
	200	is_multifunction_device = enable;
	201	}
	202
197	203	READ8_MEMBER(pci_device::header_type_r)
198	204	{
199		return 0x00;
	205	return is_multifunction_device ? 0x80 : 0x00;
200	206	}
201	207
202	208	READ8_MEMBER(pci_device::bist_r)
r242413	r242414
237	243	return 0x00;
238	244	}
239	245
240		void pci_device::scan_sub_devices(pci_device **devices, dynamic_array<pci_device *> &all, dynamic_array<pci_device *> &bridges, device_t *root)
241		{
242		}
243
244	246	void pci_device::set_remap_cb(mapper_cb _remap_cb)
245	247	{
246	248	remap_cb = _remap_cb;
r242413	r242414
425	427
426	428	for(int i=0; i<32*8; i++)
427	429	if(sub_devices[i]) {
	430	if((i & 7) && sub_devices[i & ~7])
	431	sub_devices[i & ~7]->set_multifunction_device(true);
	432
428	433	all_devices.append(sub_devices[i]);
429	434	if(sub_devices[i] != this) {
430	435	sub_devices[i]->remap_config_cb = cf_cb;
r242413	r242414
449	454
450	455	void pci_bridge_device::reset_all_mappings()
451	456	{
	457	pci_device::reset_all_mappings();
	458
452	459	for(int i=0; i != all_devices.count(); i++)
453	460	if(all_devices[i] != this)
454	461	all_devices[i]->reset_all_mappings();
	462
	463	prefetch_baseu = 0;
	464	prefetch_limitu = 0;
	465	memory_base = 0;
	466	memory_limit = 0;
	467	prefetch_base = 0;
	468	prefetch_limit = 0;
	469	iobaseu = 0;
	470	iolimitu = 0;
	471	iobase = 0;
	472	iolimit = 0;
455	473	}
456	474
457	475	void pci_bridge_device::map_device(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
r242413	r242414
588	606
589	607	READ8_MEMBER  (pci_bridge_device::iobase_r)
590	608	{
591		logerror("%s: iobase_r\n", tag());
592		return 0xff;
	609	return iobase;
593	610	}
594	611
595	612	WRITE8_MEMBER (pci_bridge_device::iobase_w)
596	613	{
	614	iobase = data;
597	615	logerror("%s: iobase_w %02x\n", tag(), data);
598	616	}
599	617
600	618	READ8_MEMBER  (pci_bridge_device::iolimit_r)
601	619	{
602		logerror("%s: iolimit_r\n", tag());
603		return 0xff;
	620	return iolimit;
604	621	}
605	622
606	623	WRITE8_MEMBER (pci_bridge_device::iolimit_w)
607	624	{
	625	iolimit = data;
608	626	logerror("%s: iolimit_w %02x\n", tag(), data);
609	627	}
610	628
r242413	r242414
621	639
622	640	READ16_MEMBER (pci_bridge_device::memory_base_r)
623	641	{
624		logerror("%s: memory_base_r\n", tag());
625		return 0xffff;
	642	return memory_base;
626	643	}
627	644
628	645	WRITE16_MEMBER(pci_bridge_device::memory_base_w)
629	646	{
630		logerror("%s: memory_base_w %04x\n", tag(), data);
	647	COMBINE_DATA(&memory_base);
	648	logerror("%s: memory_base_w %04x\n", tag(), memory_base);
631	649	}
632	650
633	651	READ16_MEMBER (pci_bridge_device::memory_limit_r)
634	652	{
635		logerror("%s: memory_limit_r\n", tag());
636		return 0xffff;
	653	return memory_limit;
637	654	}
638	655
639	656	WRITE16_MEMBER(pci_bridge_device::memory_limit_w)
640	657	{
641		logerror("%s: memory_limit_w %04x\n", tag(), data);
	658	COMBINE_DATA(&memory_limit);
	659	logerror("%s: memory_limit_w %04x\n", tag(), memory_limit);
642	660	}
643	661
644	662	READ16_MEMBER (pci_bridge_device::prefetch_base_r)
645	663	{
646		logerror("%s: prefetch_base_r\n", tag());
647		return 0xffff;
	664	return prefetch_base;
648	665	}
649	666
650	667	WRITE16_MEMBER(pci_bridge_device::prefetch_base_w)
651	668	{
652		logerror("%s: prefetch_base_w %04x\n", tag(), data);
	669	COMBINE_DATA(&prefetch_base);
	670	logerror("%s: prefetch_base_w %04x\n", tag(), prefetch_base);
653	671	}
654	672
655	673	READ16_MEMBER (pci_bridge_device::prefetch_limit_r)
656	674	{
657		logerror("%s: prefetch_limit_r\n", tag());
658		return 0xffff;
	675	return prefetch_limit;
659	676	}
660	677
661	678	WRITE16_MEMBER(pci_bridge_device::prefetch_limit_w)
662	679	{
663		logerror("%s: prefetch_limit_w %04x\n", tag(), data);
	680	COMBINE_DATA(&prefetch_limit);
	681	logerror("%s: prefetch_limit_w %04x\n", tag(), prefetch_limit);
664	682	}
665	683
666	684	READ32_MEMBER (pci_bridge_device::prefetch_baseu_r)
667	685	{
668		logerror("%s: prefetch_baseu_r\n", tag());
669		return 0xffffffff;
	686	return prefetch_baseu;
670	687	}
671	688
672	689	WRITE32_MEMBER(pci_bridge_device::prefetch_baseu_w)
673	690	{
674		logerror("%s: prefetch_baseu_w %08x\n", tag(), data);
	691	COMBINE_DATA(&prefetch_baseu);
	692	logerror("%s: prefetch_baseu_w %08x\n", tag(), prefetch_baseu);
675	693	}
676	694
677	695	READ32_MEMBER (pci_bridge_device::prefetch_limitu_r)
678	696	{
679		logerror("%s: prefetch_limitu_r\n", tag());
680		return 0xffffffff;
	697	return prefetch_limitu;
681	698	}
682	699
683	700	WRITE32_MEMBER(pci_bridge_device::prefetch_limitu_w)
684	701	{
685		logerror("%s: prefetch_limitu_w %08x\n", tag(), data);
	702	COMBINE_DATA(&prefetch_limitu);
	703	logerror("%s: prefetch_limitu_w %08x\n", tag(), prefetch_limitu);
686	704	}
687	705
688	706	READ16_MEMBER (pci_bridge_device::iobaseu_r)
689	707	{
690		logerror("%s: iobaseu_r\n", tag());
691		return 0xffff;
	708	return iobaseu;
692	709	}
693	710
694	711	WRITE16_MEMBER(pci_bridge_device::iobaseu_w)
695	712	{
696		logerror("%s: iobaseu_w %04x\n", tag(), data);
	713	COMBINE_DATA(&iobaseu);
	714	logerror("%s: iobaseu_w %04x\n", tag(), iobaseu);
697	715	}
698	716
699	717	READ16_MEMBER (pci_bridge_device::iolimitu_r)
700	718	{
701		logerror("%s: iolimitu_r\n", tag());
702		return 0xffff;
	719	return iolimitu;
703	720	}
704	721
705	722	WRITE16_MEMBER(pci_bridge_device::iolimitu_w)
706	723	{
707		logerror("%s: iolimitu_w %04x\n", tag(), data);
	724	COMBINE_DATA(&iolimitu);
	725	logerror("%s: iolimitu_w %04x\n", tag(), iolimitu);
708	726	}
709	727
710	728	READ8_MEMBER  (pci_bridge_device::interrupt_line_r)
r242413	r242414
731	749
732	750	READ16_MEMBER (pci_bridge_device::bridge_control_r)
733	751	{
734		logerror("%s: bridge_control_r\n", tag());
735	752	return bridge_control;
736	753	}
737	754
r242413	r242414
784	801	memory_window_start = memory_window_end = memory_offset = 0;
785	802	io_window_start = io_window_end = io_offset = 0;
786	803
787		for(int i=0; i != all_devices.count(); i++)
788		if(all_devices[i] != this)
789		all_devices[i]->reset_all_mappings();
	804	reset_all_mappings();
790	805	}
791	806
792	807	void pci_host_device::device_reset()

trunk/src/emu/machine/pci.h

r242413	r242414
31	31	pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
32	32
33	33	void set_ids(UINT32 main_id, UINT8 revision, UINT32 pclass, UINT32 subsystem_id);
	34	void set_multifunction_device(bool enable);
34	35
35	36	virtual void set_remap_cb(mapper_cb _remap_cb);
36	37	virtual void reset_all_mappings();
r242413	r242414
109	110	const UINT8 *expansion_rom;
110	111	UINT32 expansion_rom_size;
111	112	UINT32 expansion_rom_base;
	113	bool is_multifunction_device;
112	114
113	115	virtual void device_start();
114	116	virtual void device_reset();
115	117
116		static void scan_sub_devices(pci_device **devices, dynamic_array<pci_device *> &all, dynamic_array<pci_device *> &bridges, device_t *root);
117
118	118	void skip_map_regs(int count);
119	119	void add_map(UINT64 size, int flags, address_map_delegate &map);
120	120	template <typename T> void add_map(UINT64 size, int flags, void (T::*map)(address_map &map, device_t &device), const char *name) {
r242413	r242414
193	193	dynamic_array<pci_device *> all_devices;
194	194	dynamic_array<pci_bridge_device *> all_bridges;
195	195
196		UINT8 primary_bus, secondary_bus, subordinate_bus;
197		UINT16 bridge_control;
	196	UINT32 prefetch_baseu, prefetch_limitu;
	197	UINT16 bridge_control, memory_base, memory_limit, prefetch_base, prefetch_limit, iobaseu, iolimitu;
	198	UINT8 primary_bus, secondary_bus, subordinate_bus, iobase, iolimit;
198	199
199	200	virtual void device_start();
200	201	virtual void device_reset();

trunk/src/emu/machine/r10696.c

r0	r242414
	1	/**********************************************************************
	2
	3	Rockwell 10696 General Purpose Input/Output (I/O)
	4
	5	Copyright Nicola Salmoria and the MAME Team.
	6	Visit http://mamedev.org for licensing and usage restrictions.
	7
	8
	9	REGISTER DESCRIPTION
	10
	11	HEX    Address   Select     Names
	12	-------------------------------------------------------
	13	A      x x x x   1 0 1 0    Read Group A
	14	9      x x x x   1 0 0 1    Read Group B
	15	3      x x x x   0 0 1 1    Read Group C
	16	0      x x x x   0 0 0 0    Read Groups A | B | C
	17	1      x x x x   0 0 0 1    Read Groups B | C
	18	2      x x x x   0 0 1 0    Read Groups A | C
	19	8      x x x x   1 0 0 0    Read Groups A | B
	20
	21	E      x x x x   1 1 1 0    Set Group A
	22	D      x x x x   1 1 0 1    Set Group B
	23	7      x x x x   0 1 1 1    Set Group C
	24	4      x x x x   0 1 0 0    Set Groups A, B and C
	25	5      x x x x   0 1 0 1    Set Groups B and C
	26	6      x x x x   0 1 1 0    Set Groups A and C
	27	C      x x x x   1 1 0 0    Set Groups A and B
	28
	29	Notes:
	30	Any of the I/O chips may be used to read or set any group
	31	(A, B, C) or combination of groups.
	32	**********************************************************************/
	33
	34	#include "emu.h"
	35	#include "machine/r10696.h"
	36
	37	#define   VERBOSE   1
	38	#if VERBOSE
	39	#define LOG(x) logerror x
	40	#else
	41	#define LOG(x)
	42	#endif
	43
	44	/*************************************
	45	*
	46	*  Device interface
	47	*
	48	*************************************/
	49
	50	const device_type R10696 = &device_creator<r10696_device>;
	51
	52	r10696_device::r10696_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	53	: device_t(mconfig, R10696, "Rockwell 10696", tag, owner, clock, "r10696", __FILE__),
	54	m_io_a(0), m_io_b(0), m_io_c(0),
	55	m_iord(*this), m_iowr(*this)
	56	{
	57	}
	58
	59	/**
	60	* @brief r10696_device::device_start device-specific startup
	61	*/
	62	void r10696_device::device_start()
	63	{
	64	m_iord.resolve();
	65	m_iowr.resolve();
	66
	67	save_item(NAME(m_io_a));
	68	save_item(NAME(m_io_b));
	69	save_item(NAME(m_io_c));
	70	}
	71
	72	/**
	73	* @brief r10696_device::device_reset device-specific reset
	74	*/
	75	void r10696_device::device_reset()
	76	{
	77	m_io_a = 0;
	78	m_io_b = 0;
	79	m_io_c = 0;
	80	}
	81
	82	/*************************************
	83	*
	84	*  Command access handlers
	85	*
	86	*************************************/
	87
	88	WRITE8_MEMBER( r10696_device::io_w )
	89	{
	90	assert(offset < 16);
	91	const UINT8 io_a = m_io_a;
	92	const UINT8 io_b = m_io_b;
	93	const UINT8 io_c = m_io_c;
	94	switch (offset)
	95	{
	96	case 0x0A: // Read Group A
	97	case 0x09: // Read Group B
	98	case 0x03: // Read Group C
	99	case 0x00: // Read Groups A | B | C
	100	case 0x01: // Read Groups B | C
	101	case 0x02: // Read Groups A | C
	102	case 0x08: // Read Groups A | B
	103	break;
	104
	105	case 0x0E: // Set Group A
	106	m_io_a = data & 0x0f;
	107	break;
	108	case 0x0D: // Set Group B
	109	m_io_b = data & 0x0f;
	110	break;
	111	case 0x07: // Set Group C
	112	m_io_c = data & 0x0f;
	113	break;
	114	case 0x04: // Set Groups A, B and C
	115	m_io_a = m_io_b = m_io_c = data & 0x0f;
	116	break;
	117	case 0x05: // Set Groups B and C
	118	m_io_b = m_io_c = data & 0x0f;
	119	break;
	120	case 0x06: // Set Groups A and C
	121	m_io_a = m_io_c = data & 0x0f;
	122	break;
	123	case 0x0C: // Set Groups A and B
	124	m_io_a = m_io_b = data & 0x0f;
	125	break;
	126	}
	127	if (io_a != m_io_a)
	128	m_iowr(0, m_io_a, 0x0f);
	129	if (io_b != m_io_b)
	130	m_iowr(1, m_io_b, 0x0f);
	131	if (io_c != m_io_c)
	132	m_iowr(2, m_io_c, 0x0f);
	133	}
	134
	135
	136	READ8_MEMBER( r10696_device::io_r )
	137	{
	138	assert(offset < 16);
	139	UINT8 io_a, io_b, io_c;
	140	UINT8 data = 0xf;
	141	switch (offset)
	142	{
	143	case 0x0A: // Read Group A
	144	io_a = m_iord(0);
	145	data = io_a & 0x0f;
	146	break;
	147	case 0x09: // Read Group B
	148	io_b = m_iord(1);
	149	data = io_b & 0x0f;
	150	break;
	151	case 0x03: // Read Group C
	152	io_c = m_iord(2);
	153	data = io_c & 0x0f;
	154	break;
	155	case 0x00: // Read Groups A | B | C
	156	io_a = m_iord(0);
	157	io_b = m_iord(1);
	158	io_c = m_iord(2);
	159	data = (io_a | io_b | io_a) & 0x0f;
	160	break;
	161	case 0x01: // Read Groups B | C
	162	io_b = m_iord(1);
	163	io_c = m_iord(2);
	164	data = (io_b | io_c) & 0x0f;
	165	break;
	166	case 0x02: // Read Groups A | C
	167	io_a = m_iord(0);
	168	io_c = m_iord(2);
	169	data = (io_a | io_c) & 0x0f;
	170	break;
	171	case 0x08: // Read Groups A | B
	172	io_a = m_iord(0);
	173	io_b = m_iord(1);
	174	data = (io_a | io_b) & 0x0f;
	175	break;
	176
	177	case 0x0E: // Set Group A
	178	case 0x0D: // Set Group B
	179	case 0x07: // Set Group C
	180	case 0x04: // Set Groups A, B and C
	181	case 0x05: // Set Groups B and C
	182	case 0x06: // Set Groups A and C
	183	case 0x0C: // Set Groups A and B
	184	break;
	185	}
	186	return data;
	187	}

trunk/src/emu/machine/r10696.h

r0	r242414
	1	/**********************************************************************
	2
	3	Rockwell 10696 General Purpose Input/Output (I/O)
	4
	5	Juergen Buchmueller <pullmoll@t-online.de>
	6
	7	The device decodes reads/write to a 16 byte I/O range defined
	8	by four wired inputs SC1, SC2, SC3 and SC4.
	9	It provides 12 inputs and 12 outputs in groups of three
	10	time 4 bits each.
	11
	12	**********************************************************************/
	13
	14	#ifndef __R10696_H__
	15	#define __R10696_H__
	16
	17	#include "device.h"
	18
	19	/*************************************
	20	*
	21	*  Device configuration macros
	22	*
	23	*************************************/
	24
	25	/* Set the read and write group (4-bit; nibble) delegates */
	26	#define MCFG_R10696_IO(_devcb_rd,_devcb_wr) \
	27	r10696_device::set_iord(*device, DEVCB_##_devcb_rd); \
	28	r10696_device::set_iowr(*device, DEVCB_##_devcb_wr);
	29
	30	class r10696_device : public device_t
	31	{
	32	public:
	33	r10696_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	34	~r10696_device() {}
	35
	36	DECLARE_READ8_MEMBER ( io_r );
	37	DECLARE_WRITE8_MEMBER( io_w );
	38
	39	template<class _Object> static devcb_base &set_iord(device_t &device, _Object object) { return downcast<r10696_device &>(device).m_iord.set_callback(object); }
	40	template<class _Object> static devcb_base &set_iowr(device_t &device, _Object object) { return downcast<r10696_device &>(device).m_iowr.set_callback(object); }
	41	protected:
	42	// device-level overrides
	43	virtual void device_start();
	44	virtual void device_reset();
	45
	46	private:
	47	UINT8         m_io_a;   //!< input/output flip-flops group A
	48	UINT8         m_io_b;   //!< input/output flip-flops group B
	49	UINT8         m_io_c;   //!< input/output flip-flops group C
	50	devcb_read8   m_iord;   //!< input line (read, offset = group, data = 4 bits)
	51	devcb_write8  m_iowr;   //!< output line (write, offset = group, data = 4 bits)
	52	};
	53
	54	extern const device_type R10696;
	55
	56	#endif /* __R10696_H__ */

trunk/src/emu/machine/ra17xx.c

r0	r242414
	1	/**********************************************************************
	2
	3	Rockwell A17XX ROM, RAM and I/O chip
	4
	5	Copyright Nicola Salmoria and the MAME Team.
	6	Visit http://mamedev.org for licensing and usage restrictions.
	7
	8	A ROM of 2048 x 8 bits is addressed whenever the RRSEL line
	9	(ROM/RAM select) is 0. A RAM of 128 x 4 bit is addressed when
	10	RRSEL is 1. The 16 I/O ports are addressed when the WI/O line
	11	is 1, i.e. whenever the CPU executes an IOL instruction.
	12	There are two basic I/O instructions:
	13	SES = Select Enable Status and SOS = Select Output Status
	14	The lower 4 bits of the I/O address select one of 16 I/O lines.
	15
	16	There are at most two A17XX per system, one for the lower
	17	ROM and RAM portion and one for the higher.
	18
	19	I/O section instructions
	20
	21	Menmonic  I/O bus            Accu      Description
	22	------------------------------------------------------------------
	23	SES       0 S S 0 X X X 0    1 X X X   Enable all outputs
	24	Acuu:3 <- I/O(BL)
	25	------------------------------------------------------------------
	26	SES       0 S S 0 X X X 0    0 X X X   Disable all outputs
	27	Acuu:3 <- I/O(BL)
	28	------------------------------------------------------------------
	29	SOS       0 S S 0 X X X 1    1 X X X   I/O(BL) <- 1
	30	Acuu:3 <- I/O(BL)
	31	------------------------------------------------------------------
	32	SOS       0 S S 0 X X X 1    0 X X X   I/O(BL) <- 0
	33	Acuu:3 <- I/O(BL)
	34
	35	This device emulation takes care of the I/O commands, not the
	36	ROM and RAM, because these are emulated using the generic MAME
	37	memory system.
	38	**********************************************************************/
	39
	40	#include "emu.h"
	41	#include "machine/ra17xx.h"
	42
	43	#define   VERBOSE   1
	44	#if VERBOSE
	45	#define LOG(x) logerror x
	46	#else
	47	#define LOG(x)
	48	#endif
	49
	50	/*************************************
	51	*
	52	*  Device interface
	53	*
	54	*************************************/
	55
	56	const device_type RA17XX = &device_creator<ra17xx_device>;
	57
	58	ra17xx_device::ra17xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	59	: device_t(mconfig, RA17XX, "Rockwell A17XX", tag, owner, clock, "ra17xx", __FILE__),
	60	m_line(),
	61	m_enable(false),
	62	m_iord(*this),
	63	m_iowr(*this)
	64	{
	65	}
	66
	67	/**
	68	* @brief ra17xx_device::device_start device-specific startup
	69	*/
	70	void ra17xx_device::device_start()
	71	{
	72	m_iord.resolve();
	73	m_iowr.resolve();
	74
	75	save_item(NAME(m_line));
	76	}
	77
	78	/**
	79	* @brief ra17xx_device::device_reset device-specific reset
	80	*/
	81	void ra17xx_device::device_reset()
	82	{
	83	memset(m_line, 0, sizeof(m_line));
	84	}
	85
	86
	87	/*************************************
	88	*
	89	*  Constants
	90	*
	91	*************************************/
	92
	93	/*************************************
	94	*
	95	*  Command access handlers
	96	*
	97	*************************************/
	98
	99	WRITE8_MEMBER( ra17xx_device::io_w )
	100	{
	101	assert(offset < 16);
	102	m_bl = (data >> 4) & 15;    // BL on the data bus most significant bits
	103	if (offset & 1) {
	104	// SOS command
	105	if (data & (1 << 3)) {
	106	m_line[m_bl] = 1;   // enable output
	107	if (m_enable)
	108	m_iowr(m_bl, 1);
	109	} else {
	110	m_line[m_bl] = 0;   // disable output
	111	if (m_enable)
	112	m_iowr(m_bl, 0);
	113	}
	114	} else {
	115	// SES command
	116	if (data & (1 << 3)) {
	117	// enable all outputs
	118	m_enable = true;
	119	for (int i = 0; i < 16; i++)
	120	m_iowr(i, m_line[i], 1);
	121	} else {
	122	// disable all outputs
	123	m_enable = false;
	124	}
	125	}
	126	}
	127
	128
	129	READ8_MEMBER( ra17xx_device::io_r )
	130	{
	131	assert(offset < 16);
	132	return (m_iord(m_bl) & 1) ? 0x0f : 0x07;
	133	}

trunk/src/emu/machine/ra17xx.h

r0	r242414
	1	/**********************************************************************
	2
	3	Rockwell RA17xx (e.g. A1752, A1753) ROM, RAM and I/O chip
	4
	5	Juergen Buchmueller <pullmoll@t-online.de>
	6
	7	The device integrates a 2048 x 8 ROM, a 128 x 4 RAM and
	8	and 16 I/O ports at one of the port ranges 00 ... 0f,
	9	20 ... 2f, 40 ... 4f or 60 ... 6f.
	10
	11	**********************************************************************/
	12
	13	#ifndef __RA17XX_H__
	14	#define __RA17XX_H__
	15
	16	#include "device.h"
	17
	18	/*************************************
	19	*
	20	*  Device configuration macros
	21	*
	22	*************************************/
	23
	24	/* Set the read line handler */
	25	#define MCFG_RA17XX_READ(_devcb) \
	26	ra17xx_device::set_iord(*device, DEVCB_##_devcb); \
	27
	28	/* Set the write line handler */
	29	#define MCFG_RA17XX_WRITE(_devcb) \
	30	ra17xx_device::set_iowr(*device, DEVCB_##_devcb); \
	31
	32	class ra17xx_device : public device_t
	33	{
	34	public:
	35	ra17xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	36	~ra17xx_device() {}
	37
	38	DECLARE_READ8_MEMBER ( io_r );
	39	DECLARE_WRITE8_MEMBER( io_w );
	40
	41	template<class _Object> static devcb_base &set_iord(device_t &device, _Object object) { return downcast<ra17xx_device &>(device).m_iord.set_callback(object); }
	42	template<class _Object> static devcb_base &set_iowr(device_t &device, _Object object) { return downcast<ra17xx_device &>(device).m_iowr.set_callback(object); }
	43	protected:
	44	// device-level overrides
	45	virtual void device_start();
	46	virtual void device_reset();
	47
	48	private:
	49	UINT8           m_line[16];   //!< input/output flip-flops for 16 I/O lines
	50	UINT8           m_bl;         //!< value of BL during the most recent output
	51	bool            m_enable;     //!< true if outputs are enabled
	52	devcb_read8     m_iord;       //!< input line (read, offset = line, data = 0/1)
	53	devcb_write8    m_iowr;       //!< output line (write, offset = line, data = 0/1)
	54	};
	55
	56	extern const device_type RA17XX;
	57
	58	#endif /* __RA17XX_H__ */

trunk/src/emu/machine/smpc.c

r242413	r242414
171	171	if (m_cart_reg[gameno] && m_cart_reg[gameno]->base())
172	172	memcpy(memregion("abus")->base(), m_cart_reg[gameno]->base(), 0x3000000);
173	173	else
174		memset(memregion("abus")->base(), 0x00, 0x3000000);
	174	memset(memregion("abus")->base(), 0x00, 0x3000000); // TODO: 1-filled?
175	175
176	176	m_prev_bankswitch = gameno;
177	177	}
r242413	r242414
393	393	void saturn_state::smpc_keyboard(UINT8 pad_num, UINT8 offset)
394	394	{
395	395	UINT16 game_key;
396
	396
397	397	game_key = 0xffff;
398	398
399	399	game_key ^= ((ioport("KEYS_1")->read() & 0x80) << 8); // right
r242413	r242414
415	415	m_smpc.OREG[2+pad_num*offset] = game_key>>8; // game buttons, TODO
416	416	m_smpc.OREG[3+pad_num*offset] = game_key & 0xff;
417	417	/*
	418	Keyboard Status hook-up
	419	TODO: how shift key actually works? EGWord uses it in order to switch between hiragana and katakana modes.
418	420	x--- ---- 0
419	421	-x-- ---- caps lock
420	422	--x- ---- num lock
r242413	r242414
425	427	---- ---x Break key
426	428	*/
427	429	m_smpc.OREG[4+pad_num*offset] = m_keyb.status | 6;
428		m_smpc.OREG[5+pad_num*offset] = m_keyb.data;
	430	if(m_keyb.prev_data != m_keyb.data)
	431	{
	432	m_smpc.OREG[5+pad_num*offset] = m_keyb.data;
	433	m_keyb.repeat_count = 0;
	434	m_keyb.prev_data = m_keyb.data;
	435	}
	436	else
	437	{
	438	/* Very crude repeat support */
	439	m_keyb.repeat_count ++;
	440	m_keyb.repeat_count = m_keyb.repeat_count > 32 ? 32 : m_keyb.repeat_count;
	441	m_smpc.OREG[5+pad_num*offset] = (m_keyb.repeat_count == 32) ? m_keyb.data : 0;
	442	}
429	443	}
430	444
431	445	void saturn_state::smpc_mouse(UINT8 pad_num, UINT8 offset, UINT8 id)

trunk/src/emu/mame.h

r242413	r242414
120	120	//**************************************************************************
121	121
122	122	extern const char build_version[];
	123	extern const char bare_build_version[];
123	124
124	125
125
126	126	/***************************************************************************
127	127	FUNCTION PROTOTYPES
128	128	***************************************************************************/

trunk/src/emu/video/upd7220.c

r242413	r242414
148	148
149	149
150	150	// default address map
151		static ADDRESS_MAP_START( upd7220_vram, AS_0, 8, upd7220_device )
	151	static ADDRESS_MAP_START( upd7220_vram, AS_0, 16, upd7220_device )
152	152	AM_RANGE(0x00000, 0x3ffff) AM_RAM
153	153	ADDRESS_MAP_END
154	154
r242413	r242414
206	206	space().write_byte(address, data);
207	207	}
208	208
	209	inline UINT16 upd7220_device::readword(offs_t address)
	210	{
	211	return space().read_word(address);
	212	}
	213
	214
	215	inline void upd7220_device::writeword(offs_t address, UINT16 data)
	216	{
	217	space().write_word(address, data);
	218	}
	219
209	220	//-------------------------------------------------
210	221	//  fifo_clear -
211	222	//-------------------------------------------------
r242413	r242414
495	506
496	507	result = 0;
497	508
498		if(((m_mode & UPD7220_MODE_DISPLAY_MASK) == UPD7220_MODE_DISPLAY_GRAPHICS) || m_figs.m_gd)
499		result = BITSWAP8(m_pr[1],0,1,2,3,4,5,6,7) | (BITSWAP8(m_pr[2],0,1,2,3,4,5,6,7) << 8);
500		else
501		result = m_pr[1] | (m_pr[2] << 8);
	509	result = m_pr[1] | (m_pr[2] << 8);
502	510
503	511	switch(type)
504	512	{
r242413	r242414
526	534	switch(mod & 3)
527	535	{
528	536	case 0x00: //replace
529		if(type == 0 || type == 2)
	537	if(type == 0)
	538	writeword(m_ead*2+0, result);
	539	if(type == 2)
530	540	writebyte(m_ead*2+0, result & 0xff);
531		if(type == 0 || type == 3)
	541	if(type == 3)
532	542	writebyte(m_ead*2+1, result >> 8);
533	543	break;
534	544	case 0x01: //complement
535		if(type == 0 || type == 2)
	545	if(type == 0)
	546	writeword(m_ead*2+0, readword(m_ead*2+0) ^ result);
	547	if(type == 2)
536	548	writebyte(m_ead*2+0, readbyte(m_ead*2+0) ^ (result & 0xff));
537		if(type == 0 || type == 3)
	549	if(type == 3)
538	550	writebyte(m_ead*2+1, readbyte(m_ead*2+1) ^ (result >> 8));
539	551	break;
540	552	case 0x02: //reset to zero
541		if(type == 0 || type == 2)
	553	if(type == 0)
	554	writeword(m_ead*2+0, readword(m_ead*2+0) & ~result);
	555	if(type == 2)
542	556	writebyte(m_ead*2+0, readbyte(m_ead*2+0) & ~(result & 0xff));
543		if(type == 0 || type == 3)
	557	if(type == 3)
544	558	writebyte(m_ead*2+1, readbyte(m_ead*2+1) & ~(result >> 8));
545	559	break;
546	560	case 0x03: //set to one
547		if(type == 0 || type == 2)
	561	if(type == 0)
	562	writeword(m_ead*2+0, readword(m_ead*2+0) | result);
	563	if(type == 2)
548	564	writebyte(m_ead*2+0, readbyte(m_ead*2+0) | (result & 0xff));
549		if(type == 0 || type == 3)
	565	if(type == 3)
550	566	writebyte(m_ead*2+1, readbyte(m_ead*2+1) | (result >> 8));
551	567	break;
552	568	}
r242413	r242414
631	647	m_disp(0),
632	648	m_gchr(0),
633	649	m_bitmap_mod(0),
634		m_space_config("videoram", ENDIANNESS_LITTLE, 8, 18, 0, NULL, *ADDRESS_MAP_NAME(upd7220_vram))
	650	m_space_config("videoram", ENDIANNESS_LITTLE, 16, 18, 0, NULL, *ADDRESS_MAP_NAME(upd7220_vram))
635	651	{
636	652	for (int i = 0; i < 16; i++)
637	653	{
r242413	r242414
773	789	void upd7220_device::draw_pixel(int x, int y, int xi, UINT16 tile_data)
774	790	{
775	791	UINT32 addr = ((y * (m_pitch << (m_figs.m_gd ? 0 : 1))) + (x >> 3)) & 0x3ffff;
776		UINT8 data = readbyte(addr);
777		UINT8 new_pixel = (xi & 8 ? tile_data >> 8 : tile_data & 0xff) & (0x80 >> (xi & 7));
778		new_pixel = new_pixel ? (0xff & (0x80 >> (x & 7))) : 0;
	792	UINT16 data = readword(addr);
	793	UINT16 new_pixel = (tile_data & (1 << (xi & 0xf))) ? (1 << (x & 0xf)) : 0;
779	794
780	795	switch(m_bitmap_mod)
781	796	{
782	797	case 0: //replace
783		writebyte(addr, (data & ~(0x80 >> (x & 7))) | new_pixel);
	798	writeword(addr, (data & ~(1 << (x & 0xf))) | new_pixel);
784	799	break;
785	800	case 1: //complement
786		writebyte(addr, data ^ new_pixel);
	801	writeword(addr, data ^ new_pixel);
787	802	break;
788	803	case 2: //reset
789		writebyte(addr, data & ~new_pixel);
	804	writeword(addr, data & ~new_pixel);
790	805	break;
791	806	case 3: //set
792		writebyte(addr, data | new_pixel);
	807	writeword(addr, data | new_pixel);
793	808	break;
794	809	}
795	810	}
r242413	r242414
986	1001
987	1002	for(int pi = 0; pi < psize; pi++)
988	1003	{
989		tile_data = BITSWAP8(m_ra[((psize-1-pi) & 7) | 8],0,1,2,3,4,5,6,7);
990		tile_data = (tile_data << 8) | (tile_data & 0xff);
	1004	tile_data = (m_ra[((psize-1-pi) & 7) | 8] << 8) | m_ra[((psize-1-pi) & 7) | 8];
991	1005	for(int pz = 0; pz <= m_gchr; pz++)
992	1006	{
993	1007	for(int ii = 0, curpixel = 0; ii < isize; ii++)
r242413	r242414
1572	1586
1573	1587	for (sx = 0; sx < pitch; sx++)
1574	1588	{
1575		if((sx << 3) < m_aw * 16 && y < al)
1576		m_display_cb(bitmap, y, sx << 3, addr);
	1589	if((sx << 4) < m_aw * 16 && y < al)
	1590	m_display_cb(bitmap, y, sx << 4, addr);
1577	1591
1578		addr+= wd + 1;
	1592	addr+= (wd + 1) * 2;
1579	1593	}
1580	1594	}
1581	1595

trunk/src/emu/video/upd7220.h

r242413	r242414
126	126
127	127	inline UINT8 readbyte(offs_t address);
128	128	inline void writebyte(offs_t address, UINT8 data);
	129	inline UINT16 readword(offs_t address);
	130	inline void writeword(offs_t address, UINT16 data);
129	131	inline void fifo_clear();
130	132	inline int fifo_param_count();
131	133	inline void fifo_set_direction(int dir);

trunk/src/lib/formats/d64_dsk.h

r242413	r242414
63	63	virtual int get_sectors_per_track(const format &f, int track);
64	64	virtual int get_disk_id_offset(const format &f);
65	65	void get_disk_id(const format &f, io_generic *io, UINT8 &id1, UINT8 &id2);
66		floppy_image_format_t::desc_e* get_sector_desc(const format &f, int &current_size, int sector_count, UINT8 id1, UINT8 id2, int gap_2);
	66	virtual floppy_image_format_t::desc_e* get_sector_desc(const format &f, int &current_size, int sector_count, UINT8 id1, UINT8 id2, int gap_2);
67	67	void build_sector_description(const format &f, UINT8 *sectdata, offs_t sect_offs, offs_t error_offs, desc_s *sectors, int sector_count) const;
68	68
69	69	static const format file_formats[];

trunk/src/lib/formats/d80_dsk.c

r242413	r242414
43	43
44	44	const UINT32 d80_format::d80_cell_size[] =
45	45	{
46		2667, // 12MHz/16/2
47		2500, // 12MHz/15/2
48		2333, // 12MHz/14/2
49		2167  // 12MHz/13/2
	46	2667, // 12MHz/2/16
	47	2500, // 12MHz/2/15
	48	2333, // 12MHz/2/14
	49	2167  // 12MHz/2/13
50	50	};
51	51
52	52	const int d80_format::d80_sectors_per_track[] =

trunk/src/lib/formats/dcp_dsk.c

r0	r242414
	1	// license:BSD-3-Clause
	2	// copyright-holders:etabeta
	3	/*********************************************************************
	4
	5	formats/dcp_dsk.h
	6
	7	PC98 DCP & DCU disk images
	8
	9	0xA2 header, followed by track data
	10	header[0] - disk format
	11	header[1-0xA1] - track map (1=track used, 0=track unused/unformatted)
	12	header[0xA2] - all tracks used?
	13	(there seems to be a diff in its usage between DCP and DCU)
	14
	15	TODO:
	16	- add support for track map. images available for tests were all
	17	of type 0x01, with all 154 tracks present. combined with pete_j
	18	reporting some images have faulty track map, we need some more
	19	test cases to properly handle these disks!
	20
	21	*********************************************************************/
	22
	23	#include "emu.h"
	24	#include "dcp_dsk.h"
	25
	26	dcp_format::dcp_format()
	27	{
	28	}
	29
	30	const char *dcp_format::name() const
	31	{
	32	return "dcx";
	33	}
	34
	35	const char *dcp_format::description() const
	36	{
	37	return "DCP/DCU disk image";
	38	}
	39
	40	const char *dcp_format::extensions() const
	41	{
	42	return "dcp,dcu";
	43	}
	44
	45	int dcp_format::identify(io_generic *io, UINT32 form_factor)
	46	{
	47	UINT64 size = io_generic_size(io);
	48	UINT8 h[0xa2];
	49	int heads, tracks, spt, bps, count_tracks = 0;
	50	bool is_hdb = false;
	51
	52	io_generic_read(io, h, 0, 0xa2);
	53
	54	// First byte is the disk format (see below in load() for details)
	55	switch (h[0])
	56	{
	57	case 0x01:
	58	default:
	59	heads = 2; tracks = 77;
	60	spt = 8; bps = 1024;
	61	break;
	62	case 0x02:
	63	heads = 2; tracks = 80;
	64	spt = 15; bps = 512;
	65	break;
	66	case 0x03:
	67	heads = 2; tracks = 80;
	68	spt = 18; bps = 512;
	69	break;
	70	case 0x04:
	71	heads = 2; tracks = 80;
	72	spt = 8; bps = 512;
	73	break;
	74	case 0x05:
	75	heads = 2; tracks = 80;
	76	spt = 9; bps = 512;
	77	break;
	78	case 0x08:
	79	heads = 2; tracks = 80;
	80	spt = 9; bps = 1024;
	81	break;
	82	case 0x11:
	83	is_hdb = true;
	84	heads = 2; tracks = 77;
	85	spt = 26; bps = 256;
	86	break;
	87	case 0x19:
	88	heads = 2; tracks = 80;
	89	spt = 16; bps = 256;
	90	break;
	91	case 0x21:
	92	heads = 2; tracks = 80;
	93	spt = 26; bps = 256;
	94	break;
	95	}
	96
	97	// bytes 0x01 to 0xa1 are track map (0x01 if track is used, 0x00 if track is unformatted/unused)
	98	for (int i = 1; i < 0xa1; i++)
	99	if (h[i])
	100	count_tracks++;
	101
	102	// in theory track map should be enough (former check), but some images have it wrong!
	103	// hence, if this check fails, we also allow for images with all tracks and wrong track map
	104	if (size - 0xa2 == (heads * count_tracks * spt * bps) || size - 0xa2 == (heads * tracks * spt * bps))
	105	return 100;
	106
	107	// for disk type 0x11 the head 0 track 0 has 26 sectors of half width, so we need to compensate calculation
	108	if (is_hdb && (size - 0xa2 + (0x80 * 26) == (heads * count_tracks * spt * bps) || size - 0xa2 + (0x80 * 26) == (heads * tracks * spt * bps)))
	109	return 100;
	110
	111	return 0;
	112	}
	113
	114	bool dcp_format::load(io_generic *io, UINT32 form_factor, floppy_image *image)
	115	{
	116	UINT8 h[0xa2];
	117	int heads, tracks, spt, bps;
	118	bool is_hdb = false;
	119
	120	io_generic_read(io, h, 0, 0xa2);
	121
	122	// First byte is the disk format:
	123	switch (h[0])
	124	{
	125	case 0x01:
	126	default:
	127	//01h: 2HD-8 sector (1.25MB) (BKDSK .HDM) (aka 2HS)
	128	//2 sides, 77 tracks, 8 sectors/track, 1024 bytes/sector = 1261568 bytes (360rpm)
	129	heads = 2;
	130	tracks = 77;
	131	spt = 8;
	132	bps = 1024;
	133	break;
	134	case 0x02:
	135	//02H: 2HD-15 sector (1.21MB) (BKDSK .HD5) (aka 2HC)
	136	//2 sides, 80 tracks, 15 sectors/track, 512 bytes/sector = 1228800 bytes (360rpm)
	137	heads = 2;
	138	tracks = 80;
	139	spt = 15;
	140	bps = 512;
	141	break;
	142	case 0x03:
	143	//03H: 2HQ-18 sector (1.44MB) (BKDSK .HD4) (aka 2HDE)
	144	//2 sides, 80 tracks, 18 sectors/track, 512 bytes/sector = 1474560 bytes (300rpm)
	145	heads = 2;
	146	tracks = 80;
	147	spt = 18;
	148	bps = 512;
	149	break;
	150	case 0x04:
	151	//04H: 2DD-8 sector (640KB) (BKDSK .DD6)
	152	//2 sides, 80 tracks, 8 sectors/track, 512 bytes/sector = 655360 bytes (300rpm)
	153	heads = 2;
	154	tracks = 80;
	155	spt = 8;
	156	bps = 512;
	157	break;
	158	case 0x05:
	159	//05h: 2DD-9 sector ( 720KB) (BKDSK .DD9)
	160	//2 sides, 80 tracks, 9 sectors/track, 512 bytes/sector = 737280 bytes (300rpm)
	161	heads = 2;
	162	tracks = 80;
	163	spt = 9;
	164	bps = 512;
	165	break;
	166	case 0x08:
	167	//08h: 2HD-9 sector (1.44MB)
	168	//2 sides, 80 tracks, 9 sectors/track, 1024 bytes/sector = 1474560 bytes (300rpm)(??)
	169	heads = 2;
	170	tracks = 80;
	171	spt = 9;
	172	bps = 1024;
	173	break;
	174	case 0x11:
	175	//11h: BASIC-2HD (BKDSK .HDB)
	176	//Head 0 Track 0 - FM encoding - 26 sectors of 128 bytes = 1 track
	177	//Head 1 Track 0 - MFM encoding - 26 sectors of 256 bytes = 1 track
	178	//Head 0 Track 1 to Head 1 Track 77 - 26 sectors of 256 bytes = 152 tracks
	179	//2 sides, 77 tracks, 26 sectors/track, 256 bytes/sector (except for head 0 track 0) = 1021696 bytes (360rpm)
	180	is_hdb = true;
	181	heads = 2;
	182	tracks = 77;
	183	spt = 26;
	184	bps = 256;
	185	break;
	186	case 0x19:
	187	//19h: BASIC 2DD (BKDSK .DDB)
	188	//2 sides, 80 tracks, 16 sectors/track, 256 bytes/sector = 655360 bytes (300rpm)
	189	heads = 2;
	190	tracks = 80;
	191	spt = 16;
	192	bps = 256;
	193	break;
	194	case 0x21:
	195	//21H: 2HD-26 sector
	196	//2 sides, 80 tracks, 26 sectors/track, 256 bytes/sector = 1064960 bytes (??rpm)(??)
	197	heads = 2;
	198	tracks = 80;
	199	spt = 26;
	200	bps = 256;
	201	break;
	202	}
	203
	204	int cell_count = form_factor == floppy_image::FF_35 ? 200000 : 166666;
	205
	206	int ssize;
	207	for (ssize = 0; (128 << ssize) < bps; ssize++);
	208
	209	desc_pc_sector sects[256];
	210	UINT8 sect_data[65536];
	211
	212	if (!is_hdb)
	213	{
	214	for (int track = 0; track < tracks; track++)
	215	for (int head = 0; head < heads; head++)
	216	{
	217	io_generic_read(io, sect_data, 0xa2 + bps * spt * (track * heads + head), bps * spt);
	218
	219	for (int i = 0; i < spt; i++)
	220	{
	221	sects[i].track       = track;
	222	sects[i].head        = head;
	223	sects[i].sector      = i + 1;
	224	sects[i].size        = ssize;
	225	sects[i].actual_size = bps;
	226	sects[i].deleted     = false;
	227	sects[i].bad_crc     = false;
	228	sects[i].data        = sect_data + i * bps;
	229	}
	230
	231	build_pc_track_mfm(track, head, image, cell_count, spt, sects, calc_default_pc_gap3_size(form_factor, bps));
	232	}
	233	}
	234	else   // FIXME: the code below is untested, because no image was found... there might be some silly mistake in the disk geometry!
	235	{
	236	// Read Head 0 Track 0 is FM with 26 sectors of 128bytes instead of 256
	237	io_generic_read(io, sect_data, 0xa2, 128 * spt);
	238
	239	for (int i = 0; i < spt; i++)
	240	{
	241	sects[i].track       = 0;
	242	sects[i].head        = 0;
	243	sects[i].sector      = i + 1;
	244	sects[i].size        = 0;
	245	sects[i].actual_size = 128;
	246	sects[i].deleted     = false;
	247	sects[i].bad_crc     = false;
	248	sects[i].data        = sect_data + i * 128;
	249	}
	250
	251	build_pc_track_fm(0, 0, image, cell_count, spt, sects, calc_default_pc_gap3_size(form_factor, 128));
	252
	253	// Read Head 1 Track 0 is MFM with 26 sectors of 256bytes
	254	io_generic_read(io, sect_data, 0xa2 + 128 * spt, bps * spt);
	255
	256	for (int i = 0; i < spt; i++)
	257	{
	258	sects[i].track       = 0;
	259	sects[i].head        = 1;
	260	sects[i].sector      = i + 1;
	261	sects[i].size        = ssize;
	262	sects[i].actual_size = bps;
	263	sects[i].deleted     = false;
	264	sects[i].bad_crc     = false;
	265	sects[i].data        = sect_data + i * bps;
	266	}
	267
	268	build_pc_track_mfm(0, 1, image, cell_count, spt, sects, calc_default_pc_gap3_size(form_factor, bps));
	269
	270	// Read other tracks as usual
	271	UINT32 data_offs = 0xa2 + (26 * 0x80) + (26 * 0x100);
	272	for (int track = 1; track < tracks; track++)
	273	for (int head = 0; head < heads; head++)
	274	{
	275	io_generic_read(io, sect_data, data_offs + bps * spt * ((track - 1) * heads + head), bps * spt);
	276
	277	for (int i = 0; i < spt; i++)
	278	{
	279	sects[i].track       = track;
	280	sects[i].head        = head;
	281	sects[i].sector      = i + 1;
	282	sects[i].size        = ssize;
	283	sects[i].actual_size = bps;
	284	sects[i].deleted     = false;
	285	sects[i].bad_crc     = false;
	286	sects[i].data        = sect_data + i * bps;
	287	}
	288
	289	build_pc_track_mfm(track, head, image, cell_count, spt, sects, calc_default_pc_gap3_size(form_factor, bps));
	290	}
	291	}
	292
	293	return true;
	294	}
	295
	296	bool dcp_format::supports_save() const
	297	{
	298	return false;
	299	}
	300
	301	const floppy_format_type FLOPPY_DCP_FORMAT = &floppy_image_format_creator<dcp_format>;

trunk/src/lib/formats/dcp_dsk.h

r0	r242414
	1	/*********************************************************************
	2
	3	formats/dcp_dsk.h
	4
	5	PC98 DCP & DCU disk images
	6
	7	*********************************************************************/
	8
	9	#ifndef DCP_DSK_H
	10	#define DCP_DSK_H
	11
	12	#include "flopimg.h"
	13
	14
	15	class dcp_format : public floppy_image_format_t
	16	{
	17	public:
	18	dcp_format();
	19
	20	virtual int identify(io_generic *io, UINT32 form_factor);
	21	virtual bool load(io_generic *io, UINT32 form_factor, floppy_image *image);
	22
	23	virtual const char *name() const;
	24	virtual const char *description() const;
	25	virtual const char *extensions() const;
	26	virtual bool supports_save() const;
	27	};
	28
	29	extern const floppy_format_type FLOPPY_DCP_FORMAT;
	30
	31	#endif /* PC98DCP_DSK_H */

trunk/src/lib/formats/dip_dsk.c

r0	r242414
	1	// license:BSD-3-Clause
	2	// copyright-holders:etabeta
	3	/*********************************************************************
	4
	5	formats/dip_dsk.h
	6
	7	PC98 DIP disk images
	8
	9	0x100 header, followed by track data
	10
	11	TODO:
	12	- Investigate header structure
	13	- can this format be used to support different disc types?
	14
	15	*********************************************************************/
	16
	17	#include "emu.h"
	18	#include "dip_dsk.h"
	19
	20	dip_format::dip_format()
	21	{
	22	}
	23
	24	const char *dip_format::name() const
	25	{
	26	return "dip";
	27	}
	28
	29	const char *dip_format::description() const
	30	{
	31	return "DIP disk image";
	32	}
	33
	34	const char *dip_format::extensions() const
	35	{
	36	return "dip";
	37	}
	38
	39	int dip_format::identify(io_generic *io, UINT32 form_factor)
	40	{
	41	UINT64 size = io_generic_size(io);
	42
	43	if (size == 0x134000 + 0x100)
	44	return 100;
	45
	46	return 0;
	47	}
	48
	49	bool dip_format::load(io_generic *io, UINT32 form_factor, floppy_image *image)
	50	{
	51	int heads, tracks, spt, bps;
	52
	53	//For the moment we only support this disk structure...
	54	//2 sides, 77 tracks, 8 sectors/track, 1024 bytes/sector = 1261568 bytes (360rpm)
	55	heads = 2;
	56	tracks = 77;
	57	spt = 8;
	58	bps = 1024;
	59
	60	int cell_count = form_factor == floppy_image::FF_35 ? 200000 : 166666;
	61
	62	int ssize;
	63	for (ssize = 0; (128 << ssize) < bps; ssize++);
	64
	65	desc_pc_sector sects[256];
	66	UINT8 sect_data[65536];
	67
	68	for (int track = 0; track < tracks; track++)
	69	for (int head = 0; head < heads; head++)
	70	{
	71	io_generic_read(io, sect_data, 0x100 + bps * spt * (track * heads + head), bps * spt);
	72
	73	for (int i = 0; i < spt; i++)
	74	{
	75	sects[i].track       = track;
	76	sects[i].head        = head;
	77	sects[i].sector      = i + 1;
	78	sects[i].size        = ssize;
	79	sects[i].actual_size = bps;
	80	sects[i].deleted     = false;
	81	sects[i].bad_crc     = false;
	82	sects[i].data        = sect_data + i * bps;
	83	}
	84
	85	build_pc_track_mfm(track, head, image, cell_count, spt, sects, calc_default_pc_gap3_size(form_factor, bps));
	86	}
	87
	88	return true;
	89	}
	90
	91	bool dip_format::supports_save() const
	92	{
	93	return false;
	94	}
	95
	96	const floppy_format_type FLOPPY_DIP_FORMAT = &floppy_image_format_creator<dip_format>;

trunk/src/lib/formats/dip_dsk.h

r0	r242414
	1	/*********************************************************************
	2
	3	formats/dip_dsk.h
	4
	5	PC98DIP disk images
	6
	7	*********************************************************************/
	8
	9	#ifndef DIP_DSK_H
	10	#define DIP_DSK_H
	11
	12	#include "flopimg.h"
	13
	14
	15	class dip_format : public floppy_image_format_t
	16	{
	17	public:
	18	dip_format();
	19
	20	virtual int identify(io_generic *io, UINT32 form_factor);
	21	virtual bool load(io_generic *io, UINT32 form_factor, floppy_image *image);
	22
	23	virtual const char *name() const;
	24	virtual const char *description() const;
	25	virtual const char *extensions() const;
	26	virtual bool supports_save() const;
	27	};
	28
	29	extern const floppy_format_type FLOPPY_DIP_FORMAT;
	30
	31	#endif /* DIP_DSK_H */

trunk/src/lib/formats/fdd_dsk.c

r0	r242414
	1	// license:BSD-3-Clause
	2	// copyright-holders:etabeta
	3	/*********************************************************************
	4
	5	formats/fdd_dsk.h
	6
	7	PC98 FDD disk images
	8
	9	0xC3FC header, followed by track data
	10	Sector map starts at offset 0xDC, with 12bytes for each sector
	11
	12	Each entry of the sector map has the following structure
	13	- 0x0 = track number (if 0xff the sector/track is unformatted/unused)
	14	- 0x1 = head number
	15	- 0x2 = sector number
	16	- 0x3 = sector size (128 << this byte)
	17	- 0x4 = fill byte. if it's not 0xff, then this sector in the original
	18	disk consisted of this single value repeated for the whole
	19	sector size, and the sector is skipped in the .fdd file.
	20	if it's 0xff, then this sector is wholly contained in the .fdd
	21	file
	22	- 0x5 = ??
	23	- 0x6 = ??
	24	- 0x7 = ??
	25	- 0x8-0x0b = absolute offset of the data for this sector, or 0xfffffff
	26	if the sector was skipped in the .fdd (and it has to be
	27	filled with the value at 0x4)
	28
	29	TODO:
	30	- Investigate remaining sector map bytes (maybe related to protections?)
	31
	32	*********************************************************************/
	33
	34	#include "emu.h"
	35	#include "fdd_dsk.h"
	36
	37	fdd_format::fdd_format()
	38	{
	39	}
	40
	41	const char *fdd_format::name() const
	42	{
	43	return "fdd";
	44	}
	45
	46	const char *fdd_format::description() const
	47	{
	48	return "FDD disk image";
	49	}
	50
	51	const char *fdd_format::extensions() const
	52	{
	53	return "fdd";
	54	}
	55
	56	int fdd_format::identify(io_generic *io, UINT32 form_factor)
	57	{
	58	UINT8 h[7];
	59	io_generic_read(io, h, 0, 7);
	60
	61	if (strncmp((const char *)h, "VFD1.0", 6) == 0)
	62	return 100;
	63
	64	return 0;
	65	}
	66
	67	bool fdd_format::load(io_generic *io, UINT32 form_factor, floppy_image *image)
	68	{
	69	UINT8 hsec[0x0c];
	70
	71	// sector map
	72	UINT8 num_secs[160];
	73	UINT8 tracks[160 * 26];
	74	UINT8 heads[160 * 26];
	75	UINT8 secs[160 * 26];
	76	UINT8 fill_vals[160 * 26];
	77	UINT32 sec_offs[160 * 26];
	78	UINT8 sec_sizes[160 * 26];
	79
	80	int pos = 0xdc;
	81
	82	for (int track = 0; track < 160; track++)
	83	{
	84	int curr_num_sec = 0, curr_track_size = 0;
	85	for (int sect = 0; sect < 26; sect++)
	86	{
	87	// read sector map for this sector
	88	io_generic_read(io, hsec, pos, 0x0c);
	89	pos += 0x0c;
	90
	91	if (hsec[0] == 0xff)   // unformatted/unused sector
	92	continue;
	93
	94	tracks[(track * 26) + sect] = hsec[0];
	95	heads[(track * 26) + sect] = hsec[1];
	96	secs[(track * 26) + sect] = hsec[2];
	97	sec_sizes[(track * 26) + sect] = hsec[3];
	98	fill_vals[(track * 26) + sect] = hsec[4];
	99	sec_offs[(track * 26) + sect] = LITTLE_ENDIANIZE_INT32(*(UINT32 *)(hsec + 0x08));
	100
	101	curr_track_size += (128 << hsec[3]);
	102	curr_num_sec++;
	103	}
	104	num_secs[track] = curr_num_sec;
	105	}
	106
	107	int cell_count = form_factor == floppy_image::FF_35 ? 200000 : 166666;
	108	desc_pc_sector sects[256];
	109	UINT8 sect_data[65536];
	110	int cur_sec_map = 0, sector_size;
	111
	112	for (int track = 0; track < 160; track++)
	113	{
	114	int cur_pos = 0;
	115	for (int i = 0; i < num_secs[track]; i++)
	116	{
	117	cur_sec_map = track * 26 + i;
	118	sector_size = 128 << sec_sizes[cur_sec_map];
	119
	120	if (sec_offs[cur_sec_map] == 0xffffffff)
	121	memset(sect_data + cur_pos, fill_vals[cur_sec_map], sector_size);
	122	else
	123	io_generic_read(io, sect_data + cur_pos, sec_offs[cur_sec_map], sector_size);
	124
	125	sects[i].track       = tracks[cur_sec_map];
	126	sects[i].head        = heads[cur_sec_map];
	127	sects[i].sector      = secs[cur_sec_map];
	128	sects[i].size        = sec_sizes[cur_sec_map];
	129	sects[i].actual_size = sector_size;
	130	sects[i].deleted     = false;
	131	sects[i].bad_crc     = false;
	132	sects[i].data        = sect_data + cur_pos;
	133	cur_pos += sector_size;
	134	}
	135
	136	build_pc_track_mfm(track / 2, track % 2, image, cell_count, num_secs[track], sects, calc_default_pc_gap3_size(form_factor, (128 << sec_sizes[track * 26])));
	137	}
	138
	139	return true;
	140	}
	141
	142	bool fdd_format::supports_save() const
	143	{
	144	return false;
	145	}
	146
	147	const floppy_format_type FLOPPY_FDD_FORMAT = &floppy_image_format_creator<fdd_format>;

trunk/src/lib/formats/fdd_dsk.h

r0	r242414
	1	/*********************************************************************
	2
	3	formats/fdd_dsk.h
	4
	5	PC98 FDD disk images
	6
	7	*********************************************************************/
	8
	9	#ifndef FDD_DSK_H
	10	#define FDD_DSK_H
	11
	12	#include "flopimg.h"
	13
	14
	15	class fdd_format : public floppy_image_format_t
	16	{
	17	public:
	18	fdd_format();
	19
	20	virtual int identify(io_generic *io, UINT32 form_factor);
	21	virtual bool load(io_generic *io, UINT32 form_factor, floppy_image *image);
	22
	23	virtual const char *name() const;
	24	virtual const char *description() const;
	25	virtual const char *extensions() const;
	26	virtual bool supports_save() const;
	27	};
	28
	29	extern const floppy_format_type FLOPPY_FDD_FORMAT;
	30
	31	#endif /* FDD_DSK_H */

trunk/src/lib/formats/nfd_dsk.c

r0	r242414
	1	// license:BSD-3-Clause
	2	// copyright-holders:etabeta
	3	/*********************************************************************
	4
	5	formats/nfd_dsk.h
	6
	7	PC98 NFD disk images (info from: http://www.geocities.jp/t98next/dev.html )
	8
	9	Revision 0
	10	==========
	11
	12	header structure (variable length > 0x120, header length = DWORD at 0x110)
	13	0x000-0x00F = T98FDDIMAGE.R* followed by 2 0x00 bytes, * = format revision (0 or 1 so far)
	14	0x010-0x10F = space for image info / comments
	15	0x110-0x113 = header length (DWORD)
	16	0x114       = write protect (any value > 0 means not writeable)
	17	0x115       = number of heads
	18	0x116-0x11F = reserved
	19	0x120-EOHeader = sector map (0x10 for each sector of the disk!)
	20	last 0x10 are fixed to 0x00, probably it marks the end of sector map?
	21
	22	sector map structure
	23	0x0     = track number
	24	0x1     = head
	25	0x2     = sector number
	26	0x3     = sector size (in 128byte chunks)
	27	0x4     = MFM/FM (1 = MFM, 0 = FM)?
	28	0x5     = DDAM/DAM (1 = DDAM, 0 = DAM)
	29	0x6-0x9 = READ DATA (FDDBIOS) Results (Status, St0, St1, St2) ??
	30	0xA     = PDA (disk type)
	31	0xB-0xF = reserved and equal to 0x00 (possibly available for future format extensions?)
	32
	33
	34	Revision 1
	35	==========
	36
	37	header structure (variable length > 0x120, header length = DWORD at 0x110)
	38	0x000-0x11F = same as Rev. 0 format
	39	0x120-0x3AF = 164 DWORDs containing, for each track, the absolute position of the sector maps
	40	for sectors of the track. for unformatted/unused tracks 0 is used
	41	0x3B0-0x3B3 = absolute position of addintional info in the header, if any
	42	0x3B4-0x3BF = reserved
	43	0x120-EOHeader = sector map + special data for each track:
	44	first 0x10 of each track = #sectors (WORD), #extra data (WORD), reserved 0xc bytes zeroed
	45	then 0x10 for each sector of this track and 0x10 for each extra data chunk
	46
	47	sector map structure
	48	0x0     = track number
	49	0x1     = head
	50	0x2     = sector number
	51	0x3     = sector size (in 128byte chunks)
	52	0x4     = MFM/FM (1 = MFM, 0 = FM)?
	53	0x5     = DDAM/DAM (1 = DDAM, 0 = DAM)
	54	0x6-0x9 = READ DATA (FDDBIOS) Results (Status, St0, St1, St2) ??
	55	0xA     = RETRY DATA (1 = Yes, 0 = No)
	56	0xB     = PDA (disk type)
	57	0xC-0xF = reserved and equal to 0x00 (possibly available for future format extensions?)
	58
	59	extra data map structure
	60	0x0     = command
	61	0x1     = track number
	62	0x2     = head
	63	0x3     = sector number
	64	0x4     = sector size (in 128byte chunks)
	65	0x5-0x8 = READ DATA (FDDBIOS) Results (Status, St0, St1, St2) ??
	66	0x9     = Number of times to RETRY loading data
	67	0xA-0xD = length of RETRY DATA
	68	0xE     = PDA (disk type)
	69	0xF     = reserved and equal to 0x00 (possibly available for future format extensions?)
	70
	71	TODO:
	72	- add support for write protect header bit? apparently, some disks try to write and
	73	fail to boot if they succeed which is the reason this bit was added
	74	- add support for DDAM in Rev. 0 (need an image which set it in some sector)
	75	- investigate the READ DATA bytes of sector headers
	76	- investigate RETRY DATA chunks
	77
	78	*********************************************************************/
	79
	80	#include "emu.h"
	81	#include "nfd_dsk.h"
	82
	83	nfd_format::nfd_format()
	84	{
	85	}
	86
	87	const char *nfd_format::name() const
	88	{
	89	return "nfd";
	90	}
	91
	92	const char *nfd_format::description() const
	93	{
	94	return "NFD disk image";
	95	}
	96
	97	const char *nfd_format::extensions() const
	98	{
	99	return "nfd";
	100	}
	101
	102	int nfd_format::identify(io_generic *io, UINT32 form_factor)
	103	{
	104	UINT8 h[16];
	105	io_generic_read(io, h, 0, 16);
	106
	107	if (strncmp((const char *)h, "T98FDDIMAGE.R0", 14) == 0 || strncmp((const char *)h, "T98FDDIMAGE.R1", 14) == 0)
	108	return 100;
	109
	110	return 0;
	111	}
	112
	113	bool nfd_format::load(io_generic *io, UINT32 form_factor, floppy_image *image)
	114	{
	115	UINT64 size = io_generic_size(io);
	116	UINT8 h[0x120], hsec[0x10];
	117	io_generic_read(io, h, 0, 0x120);
	118	int format_version = !strncmp((const char *)h, "T98FDDIMAGE.R0", 14) ? 0 : 1;
	119
	120	// sector map (the 164th entry is only used by rev.1 format, loops with track < 163 are correct for rev.0)
	121	UINT8 disk_type = 0;
	122	UINT8 num_secs[164];
	123	UINT8 num_specials[164];
	124	UINT32 track_sizes[164];
	125	UINT8 tracks[164 * 26];
	126	UINT8 heads[164 * 26];
	127	UINT8 secs[164 * 26];
	128	UINT8 mfm[164 * 26];
	129	UINT8 sec_sizes[164 * 26];
	130
	131	UINT32 hsize = LITTLE_ENDIANIZE_INT32(*(UINT32 *)(h+0x110));
	132
	133	int pos = 0x120;
	134
	135	// set up sector map
	136	if (format_version == 1)
	137	{
	138	for (int track = 0; track < 164; track++)
	139	{
	140	int curr_track_size = 0;
	141	// read sector map absolute location
	142	io_generic_read(io, hsec, pos, 4);
	143	pos += 4;
	144	UINT32 secmap_addr = LITTLE_ENDIANIZE_INT32(*(UINT32 *)(hsec));
	145
	146	if (secmap_addr)
	147	{
	148	// read actual sector map for the sectors of this track
	149	// for rev.1 format the first 0x10 are a track summary:
	150	// first WORD is # of sectors, second WORD is # of special data sectors
	151	io_generic_read(io, hsec, secmap_addr, 0x10);
	152	secmap_addr += 0x10;
	153	num_secs[track] = LITTLE_ENDIANIZE_INT16(*(UINT16 *)(hsec));
	154	num_specials[track] = LITTLE_ENDIANIZE_INT16(*(UINT16 *)(hsec + 0x2));
	155
	156	for (int sect = 0; sect < num_secs[track]; sect++)
	157	{
	158	io_generic_read(io, hsec, secmap_addr, 0x10);
	159
	160	if (track == 0 && sect == 0)
	161	disk_type = hsec[0xb];   // can this change across the disk? I don't think so...
	162	secmap_addr += 0x10;
	163
	164	tracks[(track * 26) + sect] = hsec[0];
	165	heads[(track * 26) + sect] = hsec[1];
	166	secs[(track * 26) + sect] = hsec[2];
	167	sec_sizes[(track * 26) + sect] = hsec[3];
	168	mfm[(track * 26) + sect] = hsec[4];
	169
	170	curr_track_size += (128 << hsec[3]);
	171	}
	172
	173	if (num_specials[track] > 0)
	174	{
	175	for (int sect = 0; sect < num_specials[track]; sect++)
	176	{
	177	io_generic_read(io, hsec, secmap_addr, 0x10);
	178	secmap_addr += 0x10;
	179	curr_track_size += (hsec[9] + 1) * LITTLE_ENDIANIZE_INT32(*(UINT32 *)(hsec + 0x0a));
	180	}
	181	}
	182	}
	183	else
	184	{
	185	num_secs[track] = 0;
	186	num_specials[track] = 0;
	187	}
	188	track_sizes[track] = curr_track_size;
	189	}
	190	}
	191	else
	192	{
	193	for (int track = 0; track < 163 && pos < hsize; track++)
	194	{
	195	int curr_num_sec = 0, curr_track_size = 0;
	196	for (int sect = 0; sect < 26; sect++)
	197	{
	198	// read sector map for this sector
	199	// for rev.0 format each sector uses 0x10 bytes
	200	io_generic_read(io, hsec, pos, 0x10);
	201
	202	if (track == 0 && sect == 0)
	203	disk_type = hsec[0xa];   // can this change across the disk? I don't think so...
	204	pos += 0x10;
	205
	206	if (hsec[0] == 0xff)   // unformatted/unused sector
	207	continue;
	208
	209	tracks[(track * 26) + sect] = hsec[0];
	210	heads[(track * 26) + sect] = hsec[1];
	211	secs[(track * 26) + sect] = hsec[2];
	212	sec_sizes[(track * 26) + sect] = hsec[3];
	213	mfm[(track * 26) + sect] = hsec[4];
	214
	215	curr_track_size += (128 << hsec[3]);
	216	curr_num_sec++;
	217	}
	218
	219	num_secs[track] = curr_num_sec;
	220	track_sizes[track] = curr_track_size;
	221	}
	222	}
	223
	224	// shouln't this be set-up depending on disk_type? gaplus does not like having less than 166666 cells
	225	int cell_count = form_factor == floppy_image::FF_35 ? 200000 : 166666;
	226
	227	switch (disk_type)
	228	{
	229	case 0x10:   // 640K disk, 2DD
	230	image->set_variant(floppy_image::DSDD);
	231	break;
	232	//case 0x30:   // 1.44M disk, ?? (no images found)
	233	//   break;
	234	case 0x90:   // 1.2M disk, 2HD
	235	default:
	236	image->set_variant(floppy_image::DSHD);
	237	break;
	238	}
	239
	240	desc_pc_sector sects[256];
	241	UINT8 sect_data[65536];
	242	int cur_sec_map = 0, sector_size;
	243	pos = hsize;
	244
	245	for (int track = 0; track < 163 && pos < size; track++)
	246	{
	247	io_generic_read(io, sect_data, pos, track_sizes[track]);
	248
	249	for (int i = 0; i < num_secs[track]; i++)
	250	{
	251	cur_sec_map = track * 26 + i;
	252	sector_size = 128 << sec_sizes[cur_sec_map];
	253	sects[i].track       = tracks[cur_sec_map];
	254	sects[i].head        = heads[cur_sec_map];
	255	sects[i].sector      = secs[cur_sec_map];
	256	sects[i].size        = sec_sizes[cur_sec_map];
	257	sects[i].actual_size = sector_size;
	258	sects[i].deleted     = false;
	259	sects[i].bad_crc     = false;
	260	sects[i].data        = sect_data + i * sector_size;
	261	}
	262	pos += track_sizes[track];
	263
	264	// notice that the operation below might fail if sectors of the same track have variable sec_sizes,
	265	// because the gap3 calculation would account correctly only for the first sector...
	266	// examined images had constant sec_sizes in the each track, so probably this is not an issue
	267	if (mfm[track * 26])
	268	build_pc_track_mfm(track / 2, track % 2, image, cell_count, num_secs[track], sects, calc_default_pc_gap3_size(form_factor, (128 << sec_sizes[track * 26])));
	269	else
	270	build_pc_track_fm(track / 2, track % 2, image, cell_count, num_secs[track], sects, calc_default_pc_gap3_size(form_factor, (128 << sec_sizes[track * 26])));
	271	}
	272
	273	return true;
	274	}
	275
	276	bool nfd_format::supports_save() const
	277	{
	278	return false;
	279	}
	280
	281	const floppy_format_type FLOPPY_NFD_FORMAT = &floppy_image_format_creator<nfd_format>;

trunk/src/lib/formats/nfd_dsk.h

r0	r242414
	1	/*********************************************************************
	2
	3	formats/nfd_dsk.h
	4
	5	PC98 NFD disk images
	6
	7	*********************************************************************/
	8
	9	#ifndef NFD_DSK_H
	10	#define NFD_DSK_H
	11
	12	#include "flopimg.h"
	13
	14
	15	class nfd_format : public floppy_image_format_t
	16	{
	17	public:
	18	nfd_format();
	19
	20	virtual int identify(io_generic *io, UINT32 form_factor);
	21	virtual bool load(io_generic *io, UINT32 form_factor, floppy_image *image);
	22
	23	virtual const char *name() const;
	24	virtual const char *description() const;
	25	virtual const char *extensions() const;
	26	virtual bool supports_save() const;
	27	};
	28
	29	extern const floppy_format_type FLOPPY_NFD_FORMAT;
	30
	31	#endif /* NFD_DSK_H */

trunk/src/lib/formats/pc98_dsk.c

r242413	r242414
75	75	},
76	76	{   /* 2880K 3 1/2 inch extended density - gaps unverified */
77	77	floppy_image::FF_35,  floppy_image::DSED, floppy_image::MFM,
78		500, 36, 80, 2, 512, {}, 1, {}, 80, 50, 41, 80
	78	500, 36, 80, 2, 512, {}, 1, {}, 80, 50, 41, 80
79	79	},
80	80	{
81	81	floppy_image::FF_525,  floppy_image::DSHD, floppy_image::MFM,

trunk/src/lib/lib.mak

r242413	r242414
138	138	$(LIBOBJ)/formats/d81_dsk.o     \
139	139	$(LIBOBJ)/formats/d82_dsk.o     \
140	140	$(LIBOBJ)/formats/d88_dsk.o     \
	141	$(LIBOBJ)/formats/dcp_dsk.o     \
141	142	$(LIBOBJ)/formats/dfi_dsk.o     \
142	143	$(LIBOBJ)/formats/dim_dsk.o     \
	144	$(LIBOBJ)/formats/dip_dsk.o     \
143	145	$(LIBOBJ)/formats/dmk_dsk.o     \
144	146	$(LIBOBJ)/formats/dmv_dsk.o     \
145	147	$(LIBOBJ)/formats/dsk_dsk.o     \
r242413	r242414
148	150	$(LIBOBJ)/formats/esq16_dsk.o   \
149	151	$(LIBOBJ)/formats/fc100_cas.o   \
150	152	$(LIBOBJ)/formats/fdi_dsk.o     \
	153	$(LIBOBJ)/formats/fdd_dsk.o     \
151	154	$(LIBOBJ)/formats/flex_dsk.o    \
152	155	$(LIBOBJ)/formats/fm7_cas.o     \
153	156	$(LIBOBJ)/formats/fmsx_cas.o    \
r242413	r242414
175	178	$(LIBOBJ)/formats/nanos_dsk.o   \
176	179	$(LIBOBJ)/formats/naslite_dsk.o \
177	180	$(LIBOBJ)/formats/nes_dsk.o     \
	181	$(LIBOBJ)/formats/nfd_dsk.o     \
178	182	$(LIBOBJ)/formats/orao_cas.o    \
179	183	$(LIBOBJ)/formats/oric_dsk.o    \
180	184	$(LIBOBJ)/formats/oric_tap.o    \

trunk/src/mame/drivers/5clown.c

r242413	r242414
456	456	public:
457	457	_5clown_state(const machine_config &mconfig, device_type type, const char *tag)
458	458	: driver_device(mconfig, type, tag),
459		m_videoram(*this, "videoram"),
460		m_colorram(*this, "colorram"),
461	459	m_maincpu(*this, "maincpu"),
462	460	m_audiocpu(*this, "audiocpu"),
463	461	m_ay8910(*this, "ay8910"),
464	462	m_gfxdecode(*this, "gfxdecode"),
465		m_palette(*this, "palette")
	463	m_palette(*this, "palette"),
	464	m_videoram(*this, "videoram"),
	465	m_colorram(*this, "colorram")
466	466	{
467	467	}
468	468
	469	required_device<cpu_device> m_maincpu;
	470	required_device<cpu_device> m_audiocpu;
	471	required_device<ay8910_device> m_ay8910;
	472	required_device<gfxdecode_device> m_gfxdecode;
	473	required_device<palette_device> m_palette;
	474
	475	required_shared_ptr<UINT8> m_videoram;
	476	required_shared_ptr<UINT8> m_colorram;
	477
469	478	UINT8 m_main_latch_d800;
470	479	UINT8 m_snd_latch_0800;
471	480	UINT8 m_snd_latch_0a02;
472	481	UINT8 m_ay8910_addr;
473		required_shared_ptr<UINT8> m_videoram;
474		required_shared_ptr<UINT8> m_colorram;
475	482	tilemap_t *m_bg_tilemap;
476	483	int m_mux_data;
	484
477	485	DECLARE_WRITE8_MEMBER(fclown_videoram_w);
478	486	DECLARE_WRITE8_MEMBER(fclown_colorram_w);
479	487	DECLARE_WRITE8_MEMBER(cpu_c048_w);
r242413	r242414
490	498	DECLARE_WRITE8_MEMBER(fclown_ay8910_w);
491	499	DECLARE_DRIVER_INIT(fclown);
492	500	TILE_GET_INFO_MEMBER(get_fclown_tile_info);
	501	virtual void machine_start();
493	502	virtual void video_start();
494	503	DECLARE_PALETTE_INIT(_5clown);
495	504	UINT32 screen_update_fclown(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
496		required_device<cpu_device> m_maincpu;
497		required_device<cpu_device> m_audiocpu;
498		required_device<ay8910_device> m_ay8910;
499		required_device<gfxdecode_device> m_gfxdecode;
500		required_device<palette_device> m_palette;
501	505	};
502	506
	507	void _5clown_state::machine_start()
	508	{
	509	m_main_latch_d800 = m_snd_latch_0800 = m_snd_latch_0a02 = m_ay8910_addr = m_mux_data = 0;
	510
	511	save_item(NAME(m_main_latch_d800));
	512	save_item(NAME(m_snd_latch_0800));
	513	save_item(NAME(m_snd_latch_0a02));
	514	save_item(NAME(m_ay8910_addr));
	515	save_item(NAME(m_mux_data));
	516	}
503	517
504
505
506	518	/*************************
507	519	*     Video Hardware     *
508	520	*************************/
r242413	r242414
1210	1222	*************************/
1211	1223
1212	1224	/*    YEAR  NAME      PARENT  MACHINE INPUT   INIT    ROT    COMPANY  FULLNAME                      FLAGS... */
1213		GAME( 1993, 5clown,   0,      fclown, fclown, _5clown_state, fclown, ROT0, "IGS",   "Five Clown (English, set 1)", GAME_IMPERFECT_SOUND )
1214		GAME( 1993, 5clowna,  5clown, fclown, fclown, _5clown_state, fclown, ROT0, "IGS",   "Five Clown (English, set 2)", GAME_IMPERFECT_SOUND )
1215		GAME( 1993, 5clownsp, 5clown, fclown, fclown, _5clown_state, fclown, ROT0, "IGS",   "Five Clown (Spanish hack)",   GAME_IMPERFECT_SOUND )
	1225	GAME( 1993, 5clown,   0,      fclown, fclown, _5clown_state, fclown, ROT0, "IGS",   "Five Clown (English, set 1)", GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
	1226	GAME( 1993, 5clowna,  5clown, fclown, fclown, _5clown_state, fclown, ROT0, "IGS",   "Five Clown (English, set 2)", GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
	1227	GAME( 1993, 5clownsp, 5clown, fclown, fclown, _5clown_state, fclown, ROT0, "IGS",   "Five Clown (Spanish hack)",   GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )

trunk/src/mame/drivers/bwidow.c

r242413	r242414
334	334	m_lastdata = data;
335	335	}
336	336
	337	WRITE8_MEMBER(bwidow_state::spacduel_coin_counter_w)
	338	{
	339	if (data == m_lastdata) return;
	340	set_led_status(machine(), 0, !BIT(data,5)); // start lamp
	341	set_led_status(machine(), 1, !BIT(data,4)); // select lamp
	342	coin_lockout_w(machine(), 0, !BIT(data,3));
	343	coin_lockout_w(machine(), 1, !BIT(data,3));
	344	coin_lockout_w(machine(), 2, !BIT(data,3));
	345	coin_counter_w(machine(), 0, BIT(data,0));
	346	coin_counter_w(machine(), 1, BIT(data,1));
	347	coin_counter_w(machine(), 2, BIT(data,2));
	348	m_lastdata = data;
	349	}
	350
337	351	/*************************************
338	352	*
339	353	*  Interrupt ack
r242413	r242414
379	393	AM_RANGE(0x0900, 0x0907) AM_READ(spacduel_IN3_r)    /* IN1 */
380	394	AM_RANGE(0x0905, 0x0906) AM_WRITENOP /* ignore? */
381	395	AM_RANGE(0x0a00, 0x0a00) AM_DEVREAD("earom", atari_vg_earom_device, read)
382		//  AM_RANGE(0x0c00, 0x0c00) AM_WRITE(coin_counter_w) /* coin out */
	396	AM_RANGE(0x0c00, 0x0c00) AM_WRITE(spacduel_coin_counter_w) /* coin out */
383	397	AM_RANGE(0x0c80, 0x0c80) AM_DEVWRITE("avg", avg_device, go_w)
384	398	AM_RANGE(0x0d00, 0x0d00) AM_WRITENOP /* watchdog clear */
385	399	AM_RANGE(0x0d80, 0x0d80) AM_DEVWRITE("avg", avg_device, reset_w)
386	400	AM_RANGE(0x0e00, 0x0e00) AM_WRITE(irq_ack_w) /* interrupt acknowledge */
387	401	AM_RANGE(0x0e80, 0x0e80) AM_DEVWRITE("earom", atari_vg_earom_device, ctrl_w)
388	402	AM_RANGE(0x0f00, 0x0f3f) AM_DEVWRITE("earom", atari_vg_earom_device, write)
389		AM_RANGE(0x1000, 0x100f) AM_DEVREADWRITE("pokey1", pokey_device, read, write)
390		AM_RANGE(0x1400, 0x140f) AM_DEVREADWRITE("pokey2", pokey_device, read, write)
	403	AM_RANGE(0x1000, 0x10ff) AM_DEVREADWRITE("pokey1", pokey_device, read, write)
	404	AM_RANGE(0x1400, 0x14ff) AM_DEVREADWRITE("pokey2", pokey_device, read, write)
391	405	AM_RANGE(0x2000, 0x27ff) AM_RAM AM_SHARE("vectorram") AM_REGION("maincpu", 0x2000)
392	406	AM_RANGE(0x2800, 0x3fff) AM_ROM
393	407	AM_RANGE(0x4000, 0xffff) AM_ROM
r242413	r242414
936	950	ROM_LOAD( "136002-125.n4",  0x0000, 0x0100, CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
937	951	ROM_END
938	952
	953	ROM_START( spacduel1 )
	954	ROM_REGION( 0x10000, "maincpu", 0 )
	955	/* Vector ROM */
	956	ROM_LOAD( "136006-106.r7",  0x2800, 0x0800, CRC(691122fe) SHA1(f53be76a49dba319050ca7767de3441521910e83) )
	957	ROM_LOAD( "136006-107.np7", 0x3000, 0x1000, CRC(d8dd0461) SHA1(58060b20b2511d30d2ec06479d21840bdd0b53c6) )
	958	/* Program ROM */
	959	ROM_LOAD( "136006-101.r1",  0x4000, 0x1000, CRC(cd239e6c) SHA1(b6143d979dd35a46bcb783bb0ac02d4dca30f0c2) )
	960	ROM_LOAD( "136006-102.np1", 0x5000, 0x1000, CRC(4c451e8a) SHA1(c05c52bb08acccb60950a15f05c960c3bc163d3e) )
	961	ROM_LOAD( "136006-103.m1",  0x6000, 0x1000, CRC(ee72da63) SHA1(d36d62cdf7fe76ee9cdbfc2e76ac5d90f22986ba) )
	962	ROM_LOAD( "136006-104.kl1", 0x7000, 0x1000, CRC(e41b38a3) SHA1(9e8773e78d65d74db824cfd7108e7038f26757db) )
	963	ROM_LOAD( "136006-105.j1",  0x8000, 0x1000, CRC(5652710f) SHA1(b15891d22a47ac3448d2ced40c04d0ab80606c7d) )
	964	ROM_RELOAD(                 0x9000, 0x1000 )
	965	ROM_RELOAD(                 0xa000, 0x1000 )
	966	ROM_RELOAD(                 0xb000, 0x1000 )
	967	ROM_RELOAD(                 0xc000, 0x1000 )
	968	ROM_RELOAD(                 0xd000, 0x1000 )
	969	ROM_RELOAD(                 0xe000, 0x1000 )
	970	ROM_RELOAD(                 0xf000, 0x1000 )   /* for reset/interrupt vectors */
939	971
	972	/* AVG PROM */
	973	ROM_REGION( 0x100, "user1", 0 )
	974	ROM_LOAD( "136002-125.n4",  0x0000, 0x0100, CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
	975	ROM_END
940	976
	977	ROM_START( spacduel0 )
	978	ROM_REGION( 0x10000, "maincpu", 0 )
	979	/* Vector ROM */
	980	ROM_LOAD( "136006-006.r7",  0x2800, 0x0800, CRC(691122fe) SHA1(f53be76a49dba319050ca7767de3441521910e83) )
	981	ROM_LOAD( "136006-007.np7", 0x3000, 0x1000, CRC(d8dd0461) SHA1(58060b20b2511d30d2ec06479d21840bdd0b53c6) )
	982	/* Program ROM */
	983	ROM_LOAD( "136006-001.r1",  0x4000, 0x1000, CRC(8f993ac8) SHA1(38b6d1ee3f19bb77b8aca24fbbae38684f194796) )
	984	ROM_LOAD( "136006-002.np1", 0x5000, 0x1000, CRC(32cca051) SHA1(a01982e4362ba3dcdafd02d5403f8a190042e314) )
	985	ROM_LOAD( "136006-003.m1",  0x6000, 0x1000, CRC(36624d57) SHA1(e66cbd747c2a298f402b91c2cf042a0697ff8296) )
	986	ROM_LOAD( "136006-004.kl1", 0x7000, 0x1000, CRC(b322bf0b) SHA1(d67bf4e1e9b5b14b0455f37f9be11167aa3575c2) )
	987	ROM_LOAD( "136006-005.j1",  0x8000, 0x1000, CRC(0edb1242) SHA1(5ec62e48d15c5baf0fb583e014cae2ec4bd5f5e4) )
	988	ROM_RELOAD(                 0x9000, 0x1000 )
	989	ROM_RELOAD(                 0xa000, 0x1000 )
	990	ROM_RELOAD(                 0xb000, 0x1000 )
	991	ROM_RELOAD(                 0xc000, 0x1000 )
	992	ROM_RELOAD(                 0xd000, 0x1000 )
	993	ROM_RELOAD(                 0xe000, 0x1000 )
	994	ROM_RELOAD(                 0xf000, 0x1000 )   /* for reset/interrupt vectors */
	995
	996	/* AVG PROM */
	997	ROM_REGION( 0x100, "user1", 0 )
	998	ROM_LOAD( "136002-125.n4",  0x0000, 0x0100, CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
	999	ROM_END
	1000
	1001
941	1002	/*************************************
942	1003	*
943	1004	*  Game drivers
944	1005	*
945	1006	*************************************/
946	1007
947		GAME( 1980, spacduel, 0,        spacduel, spacduel, driver_device, 0, ROT0, "Atari", "Space Duel", GAME_SUPPORTS_SAVE )
	1008	GAME( 1980, spacduel, 0,        spacduel, spacduel, driver_device, 0, ROT0, "Atari", "Space Duel (version 2)", GAME_SUPPORTS_SAVE )
	1009	GAME( 1980, spacduel1,spacduel, spacduel, spacduel, driver_device, 0, ROT0, "Atari", "Space Duel (version 1)", GAME_SUPPORTS_SAVE )
	1010	GAME( 1980, spacduel0,spacduel, spacduel, spacduel, driver_device, 0, ROT0, "Atari", "Space Duel (prototype)", GAME_SUPPORTS_SAVE )
948	1011	GAME( 1982, bwidow,   0,        bwidow,   bwidow, driver_device,   0, ROT0, "Atari", "Black Widow", GAME_SUPPORTS_SAVE )
949	1012	GAME( 1982, gravitar, 0,        gravitar, gravitar, driver_device, 0, ROT0, "Atari", "Gravitar (version 3)", GAME_SUPPORTS_SAVE )
950	1013	GAME( 1982, gravitar2,gravitar, gravitar, gravitar, driver_device, 0, ROT0, "Atari", "Gravitar (version 2)", GAME_SUPPORTS_SAVE )

trunk/src/mame/drivers/f-32.c

r242413	r242414
22	22	public:
23	23	mosaicf2_state(const machine_config &mconfig, device_type type, const char *tag)
24	24	: driver_device(mconfig, type, tag),
25		m_maincpu(*this, "maincpu") ,
	25	m_maincpu(*this, "maincpu") ,
26	26	m_videoram(*this, "videoram"){ }
27	27
	28	/* devices */
	29	required_device<e132xn_device>  m_maincpu;
	30
28	31	/* memory pointers */
29		required_device<e132xn_device>  m_maincpu;
30	32	required_shared_ptr<UINT32> m_videoram;
	33
31	34	DECLARE_READ32_MEMBER(f32_input_port_1_r);
32	35	UINT32 screen_update_mosaicf2(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
33	36	};

trunk/src/mame/drivers/gts1.c

r242413	r242414
67	67
68	68
69	69	#include "machine/genpin.h"
	70	#include "machine/ra17xx.h"
	71	#include "machine/r10696.h"
70	72	#include "machine/r10788.h"
71	73	#include "cpu/pps4/pps4.h"
72	74	#include "gts1.lh"
r242413	r242414
89	91
90	92	DECLARE_DRIVER_INIT(gts1);
91	93
	94	DECLARE_READ8_MEMBER (gts1_solenoid_r);
	95	DECLARE_WRITE8_MEMBER(gts1_solenoid_w);
	96	DECLARE_READ8_MEMBER (gts1_switches_r);
	97	DECLARE_WRITE8_MEMBER(gts1_switches_w);
92	98	DECLARE_WRITE8_MEMBER(gts1_display_w);
	99	DECLARE_READ8_MEMBER (gts1_lamp_apm_r);
	100	DECLARE_WRITE8_MEMBER(gts1_lamp_apm_w);
	101	DECLARE_READ8_MEMBER (gts1_nvram_r);
	102	DECLARE_WRITE8_MEMBER(gts1_nvram_w);
93	103	DECLARE_READ8_MEMBER (gts1_io_r);
94	104	DECLARE_WRITE8_MEMBER(gts1_io_w);
95	105	DECLARE_READ8_MEMBER (gts1_pa_r);
r242413	r242414
98	108	private:
99	109	virtual void machine_reset();
100	110	required_device<cpu_device> m_maincpu;
101		UINT8 m_io[256];
102		UINT8 m_counter;
103		UINT8 m_6351_addr;
	111	UINT8 m_io[256];            //!< dummy I/O values of undefined ranges (will be removed)
	112	UINT8 m_nvram_addr;         //!< NVRAM address
	113	bool m_nvram_e2;            //!< NVRWAM enable (E2 line)
	114	bool m_nvram_wr;            //!< NVRWAM write (W/R line)
	115	UINT16 m_6351_addr;
	116	UINT16 m_z30_out;
104	117	};
105	118
106	119	static ADDRESS_MAP_START( gts1_map, AS_PROGRAM, 8, gts1_state )
r242413	r242414
112	125	ADDRESS_MAP_END
113	126
114	127	static ADDRESS_MAP_START( gts1_io, AS_IO, 8, gts1_state )
115		AM_RANGE(0x00d0, 0x00df) AM_DEVREADWRITE ( "r10788", r10788_device, io_r, io_w )
116		AM_RANGE(0x0000, 0x00ff) AM_READ ( gts1_io_r )   AM_WRITE( gts1_io_w ) // connects to all the other chips
117
118		AM_RANGE(0x0100, 0x0100) AM_READ ( gts1_pa_r ) AM_WRITE( gts1_pa_w )
119		AM_RANGE(0x0101, 0x0101) AM_WRITE(gts1_pb_w)
	128	AM_RANGE(0x0020, 0x002f) AM_DEVREADWRITE ( "ra17xx_u4", ra17xx_device, io_r, io_w ) // (U4) solenoid
	129	AM_RANGE(0x0030, 0x003f) AM_DEVREADWRITE ( "r10696_u3", r10696_device, io_r, io_w ) // (U3) solenoid + dips
	130	AM_RANGE(0x0040, 0x004f) AM_DEVREADWRITE ( "ra17xx_u5", ra17xx_device, io_r, io_w ) // (U5) switch matrix
	131	AM_RANGE(0x0060, 0x006f) AM_DEVREADWRITE ( "r10696_u2", r10696_device, io_r, io_w ) // (U2) NVRAM io chip
	132	AM_RANGE(0x00d0, 0x00df) AM_DEVREADWRITE ( "r10788_u6", r10788_device, io_r, io_w ) // (U6) display chip
	133	AM_RANGE(0x0000, 0x00ff) AM_READ ( gts1_io_r ) AM_WRITE( gts1_io_w )             // catch undecoded I/O accesss
	134	AM_RANGE(0x0100, 0x0100) AM_READ ( gts1_pa_r ) AM_WRITE( gts1_pa_w )             // CPU I/O port A (input/output)
	135	AM_RANGE(0x0101, 0x0101) AM_WRITE( gts1_pb_w )                                   // CPU I/O port B (output only)
120	136	ADDRESS_MAP_END
121	137
122	138	static INPUT_PORTS_START( gts1 )
r242413	r242414
201	217
202	218	void gts1_state::machine_reset()
203	219	{
	220	m_nvram_addr = 0;
	221	m_nvram_e2 = false;
	222	m_nvram_wr = false;
204	223	m_6351_addr = 0;
	224	m_z30_out = 0;
205	225	}
206	226
207	227	DRIVER_INIT_MEMBER(gts1_state,gts1)
208	228	{
209	229	}
210	230
	231	READ8_MEMBER (gts1_state::gts1_solenoid_r)
	232	{
	233	UINT8 data = 0;
	234	LOG(("%s: solenoid[%02x] -> %x\n", __FUNCTION__, offset, data));
	235	return data;
	236	}
	237
	238	WRITE8_MEMBER(gts1_state::gts1_solenoid_w)
	239	{
	240	switch (offset) {
	241	case  0:
	242	LOG(("%s: outhole <- %x\n", __FUNCTION__, data));
	243	break;
	244	case  1:
	245	LOG(("%s: knocker <- %x\n", __FUNCTION__, data));
	246	break;
	247	case  2:
	248	LOG(("%s: tens chime <- %x\n", __FUNCTION__, data));
	249	break;
	250	case  3:
	251	LOG(("%s: hundreds chime <- %x\n", __FUNCTION__, data));
	252	break;
	253	case  4:
	254	LOG(("%s: thousands chime <- %x\n", __FUNCTION__, data));
	255	break;
	256	case  5:
	257	LOG(("%s: no. 6 <- %x\n", __FUNCTION__, data));
	258	break;
	259	case  6:
	260	LOG(("%s: no. 7 <- %x\n", __FUNCTION__, data));
	261	break;
	262	case  7:
	263	LOG(("%s: no. 8 <- %x\n", __FUNCTION__, data));
	264	break;
	265	case  8:
	266	case  9:
	267	case 10:
	268	case 11:
	269	LOG(("%s: not used [%x] <- %x\n", __FUNCTION__, offset, data));
	270	break;
	271	case 12:    // spare
	272	LOG(("%s: spare [%x] <- %x\n", __FUNCTION__, offset, data));
	273	break;
	274	case 13:    // RAM control E2
	275	LOG(("%s: RAM control E2 <- %x\n", __FUNCTION__, data));
	276	m_nvram_e2 = (data & 1) ? true : false;
	277	break;
	278	case 14:    // RAM control W/R
	279	LOG(("%s: RAM control W/R <- %x\n", __FUNCTION__, data));
	280	break;
	281	m_nvram_wr = (data & 1) ? true : false;
	282	case 15:    // spare
	283	LOG(("%s: spare [%x] <- %x\n", __FUNCTION__, offset, data));
	284	break;
	285	}
	286	}
	287
	288	READ8_MEMBER (gts1_state::gts1_switches_r)
	289	{
	290	UINT8 data = 0;
	291	LOG(("%s: switches[%02x] -> %x\n", __FUNCTION__, offset, data));
	292	return data;
	293	}
	294
	295	WRITE8_MEMBER(gts1_state::gts1_switches_w)
	296	{
	297	LOG(("%s: switches[%02x] <- %x\n", __FUNCTION__, offset, data));
	298	}
	299
211	300	/**
212	301	* @brief write a 8seg display value
213	302	* @param offset digit number 0 .. 19
r242413	r242414
275	364	#undef _h
276	365	}
277	366
	367	/**
	368	* @brief read input groups A, B, C of NVRAM io chip (U2)
	369	* @param offset 0 ... 2 = group
	370	* @return 4-bit value read from the group
	371	*/
	372	READ8_MEMBER (gts1_state::gts1_nvram_r)
	373	{
	374	UINT8 data = 0x0f;
	375	switch (offset)
	376	{
	377	case 0: // group A
	378	// FIXME: Schematics says TO Z5
	379	if (!m_nvram_wr && m_nvram_e2) {
	380	// FIXME: read generic NVRAM data
	381	}
	382	break;
	383	case 1: // group B
	384	case 2: // group C
	385	// Schematics says: SPARES
	386	break;
	387	}
	388	return data;
	389	}
	390
	391	/**
	392	* @brief write output groups A, B, C of NVRAM io chip (U2)
	393	* @param offset 0 ... 2 = group
	394	* @param data 4 bit value to write
	395	*/
	396	WRITE8_MEMBER(gts1_state::gts1_nvram_w)
	397	{
	398	switch (offset)
	399	{
	400	case 0: // group A - address lines 3:0
	401	m_nvram_addr = (m_nvram_addr & ~15) | (data & 15);
	402	break;
	403	case 1: // group B - address lines 7:4
	404	m_nvram_addr = (m_nvram_addr & ~(15 << 4)) | ((data & 15) << 4);
	405	break;
	406	case 2: // group C - data bits 3:0 of NVRAM
	407	if (m_nvram_wr && m_nvram_e2) {
	408	LOG(("%s: nvram[%02x] <- %x\n", __FUNCTION__, m_nvram_addr, data & 15));
	409	// FIXME: write generic NVRAM data
	410	}
	411	break;
	412	}
	413	}
	414
	415	/**
	416	* @brief read input groups A, B, C of lamp + apm I/O chip (U3)
	417	* @param offset 0 ... 2 = group
	418	* @return 4-bit value read from the group
	419	*/
	420	READ8_MEMBER (gts1_state::gts1_lamp_apm_r)
	421	{
	422	UINT8 data = 0x0f;
	423	switch (offset) {
	424	case 0: // group A switches S01-S04, S09-S12, S17-S20
	425	if (m_z30_out & 1) {
	426	UINT8 dsw0 = ioport("DSW0")->read();
	427	if (0 == BIT(dsw0,0)) // S01
	428	data &= ~(1 << 3);
	429	if (0 == BIT(dsw0,1)) // S02
	430	data &= ~(1 << 2);
	431	if (0 == BIT(dsw0,2)) // S03
	432	data &= ~(1 << 1);
	433	if (0 == BIT(dsw0,3)) // S04
	434	data &= ~(1 << 0);
	435	}
	436	if (m_z30_out & 2) {
	437	UINT8 dsw1 = ioport("DSW1")->read();
	438	if (0 == BIT(dsw1,0)) // S09
	439	data &= ~(1 << 0);
	440	if (0 == BIT(dsw1,1)) // S10
	441	data &= ~(1 << 1);
	442	if (0 == BIT(dsw1,2)) // S11
	443	data &= ~(1 << 2);
	444	if (0 == BIT(dsw1,3)) // S12
	445	data &= ~(1 << 3);
	446	}
	447	if (m_z30_out & 4) {
	448	UINT8 dsw2 = ioport("DSW2")->read();
	449	if (0 == BIT(dsw2,0)) // S17
	450	data &= ~(1 << 0);
	451	if (0 == BIT(dsw2,1)) // S18
	452	data &= ~(1 << 1);
	453	if (0 == BIT(dsw2,2)) // S19
	454	data &= ~(1 << 2);
	455	if (0 == BIT(dsw2,3)) // S20
	456	data &= ~(1 << 3);
	457	}
	458	break;
	459	case 1: // group B switches S05-S08, S09-S12, S17-S20
	460	if (m_z30_out & 1) {
	461	UINT8 dsw0 = ioport("DSW0")->read();
	462	if (0 == BIT(dsw0,4)) // S05
	463	data &= ~(1 << 3);
	464	if (0 == BIT(dsw0,5)) // S06
	465	data &= ~(1 << 2);
	466	if (0 == BIT(dsw0,6)) // S07
	467	data &= ~(1 << 1);
	468	if (0 == BIT(dsw0,7)) // S08
	469	data &= ~(1 << 0);
	470	}
	471	if (m_z30_out & 2) {
	472	UINT8 dsw1 = ioport("DSW1")->read();
	473	if (0 == BIT(dsw1,4)) // S13
	474	data &= ~(1 << 0);
	475	if (0 == BIT(dsw1,5)) // S14
	476	data &= ~(1 << 1);
	477	if (0 == BIT(dsw1,6)) // S15
	478	data &= ~(1 << 2);
	479	if (0 == BIT(dsw1,7)) // S16
	480	data &= ~(1 << 3);
	481	}
	482	if (m_z30_out & 4) {
	483	UINT8 dsw2 = ioport("DSW2")->read();
	484	if (0 == BIT(dsw2,4)) // S21
	485	data &= ~(1 << 0);
	486	if (0 == BIT(dsw2,5)) // S22
	487	data &= ~(1 << 1);
	488	if (0 == BIT(dsw2,6)) // S23
	489	data &= ~(1 << 2);
	490	if (0 == BIT(dsw2,7)) // S24
	491	data &= ~(1 << 3);
	492	}
	493	break;
	494	case 2: // TODO: connect
	495	// IN-9 (unused?)
	496	// IN-10 (reset sw25)
	497	// IN-11 (outhole sw)
	498	// IN-12 (slam sw)
	499	break;
	500	}
	501	return data;
	502	}
	503
	504	/**
	505	* @brief write output groups A, B, C of lamp + apm I/O chip (U3)
	506	* @param offset 0 ... 2 = group
	507	* @param data 4 bit value to write
	508	*/
	509	WRITE8_MEMBER(gts1_state::gts1_lamp_apm_w)
	510	{
	511	switch (offset) {
	512	case 0: // LD1-LD4 on jumper J5
	513	break;
	514	case 1: // Z30 1-of-16 decoder
	515	m_z30_out = 1 << (data & 15);
	516	break;
	517	case 2: // O9: PGOL PROM A8, O10: PGOL PROM A9
	518	m_6351_addr = (m_6351_addr & ~(3 << 8)) | ((data & 3) << 8);
	519	// O11 and O12 are unused(?)
	520	break;
	521	}
	522	}
	523
278	524	READ8_MEMBER (gts1_state::gts1_io_r)
279	525	{
280	526	UINT8 data = m_io[offset] & 0x0f;
r242413	r242414
321	567
322	568	//MCFG_NVRAM_ADD_0FILL("nvram")
323	569
324		/* General Purpose Display and Keyboard */
325		MCFG_DEVICE_ADD( "r10788", R10788, XTAL_3_579545MHz / 18 )  // divided in the circuit
	570	/* A1753CE 2048 x 8 ROM (000-7ff), 128 x 4 RAM (00-7f) and 16 I/O lines (20 ... 2f) */
	571	MCFG_DEVICE_ADD( "ra17xx_u5", RA17XX, 0 )
	572	MCFG_RA17XX_READ ( READ8 (gts1_state,gts1_switches_r) )
	573	MCFG_RA17XX_WRITE( WRITE8(gts1_state,gts1_switches_w) )
	574
	575	/* A1752CF 2048 x 8 ROM (800-fff), 128 x 4 RAM (80-ff) and 16 I/O lines (40 ... 4f) */
	576	MCFG_DEVICE_ADD( "ra17xx_u4", RA17XX, 0 )
	577	MCFG_RA17XX_READ ( READ8 (gts1_state,gts1_solenoid_r) )
	578	MCFG_RA17XX_WRITE( WRITE8(gts1_state,gts1_solenoid_w) )
	579
	580	/* 10696 General Purpose Input/Output */
	581	MCFG_DEVICE_ADD( "r10696_u2", R10696, 0 )
	582	MCFG_R10696_IO( READ8 (gts1_state,gts1_nvram_r),
	583	WRITE8(gts1_state,gts1_nvram_w) )
	584
	585	/* 10696 General Purpose Input/Output */
	586	MCFG_DEVICE_ADD( "r10696_u3", R10696, 0 )
	587	MCFG_R10696_IO( READ8 (gts1_state,gts1_lamp_apm_r),
	588	WRITE8(gts1_state,gts1_lamp_apm_w) )
	589
	590	/* 10788 General Purpose Display and Keyboard */
	591	MCFG_DEVICE_ADD( "r10788_u6", R10788, XTAL_3_579545MHz / 18 )  // divided in the circuit
326	592	MCFG_R10788_UPDATE( WRITE8(gts1_state,gts1_display_w) )
327	593
328	594	/* Video */

trunk/src/mame/drivers/hikaru.c

r242413	r242414
11	11	and this system is said to be one of the most expensive arcade boards developed by Sega.
12	12	The games on this system include....
13	13	Air Trix                     (C) Sega, 2001
14		!Brave Fire Fighters         (C) Sega, 1999
	14	Brave Fire Fighters          (C) Sega, 1999
15	15	*Cyber Troopers Virtual On 4 (C) Sega, 2001
16		Nascar Racing               (C) Sega, 2000
17		Planet Harriers             (C) Sega, 2001
18		!Star Wars Racer Arcade      (C) Sega, 2000
	16	Nascar Racing                (C) Sega, 2000
	17	Planet Harriers              (C) Sega, 2001
	18	Star Wars Racer Arcade       (C) Sega, 2000
19	19
20	20	! - denotes secured but not fully dumped yet
21	21	* - denotes not dumped yet.
r242413	r242414
519	519
520	520	#define HIKARU_BIOS \
521	521	ROM_SYSTEM_BIOS( 0, "bios0", "epr23400a" ) \
522		ROM_LOAD16_WORD_SWAP_BIOS( 0, "epr23400a.ic94",   0x000000, 0x200000, CRC(2aa906a7) SHA1(098c9909b123ed6c338ac874f2ee90e3b2da4c02) ) \
	522	ROM_LOAD16_WORD_SWAP_BIOS( 0, "epr-23400a.ic94",  0x000000, 0x200000, CRC(2aa906a7) SHA1(098c9909b123ed6c338ac874f2ee90e3b2da4c02) ) \
523	523	ROM_SYSTEM_BIOS( 1, "bios1", "epr23400" ) \
524	524	ROM_LOAD16_WORD_SWAP_BIOS( 1, "epr-23400.ic94",   0x000000, 0x200000, CRC(3d557104) SHA1(d39879f5a1acbd54ad8ee4fbd412f870c9ff4aa5) ) \
525	525	ROM_SYSTEM_BIOS( 2, "bios2", "epr21904" ) \
r242413	r242414
542	542	HIKARU_BIOS
543	543
544	544	ROM_REGION( 0x800000, "user1", 0)
545		ROM_LOAD32_WORD("epr23601a.ic29", 0x0000000, 0x0400000, CRC(cd3ccc05) SHA1(49de32d3588511f37486aff900773453739d706d) )
546		ROM_LOAD32_WORD("epr23602a.ic30", 0x0000002, 0x0400000, CRC(24f1bca9) SHA1(719dc4e003c1d13fcbb39604c156c89042c47dfd) )
	545	ROM_LOAD32_WORD( "epr-23601a.ic29", 0x0000000, 0x0400000, CRC(cd3ccc05) SHA1(49de32d3588511f37486aff900773453739d706d) )
	546	ROM_LOAD32_WORD( "epr-23602a.ic30", 0x0000002, 0x0400000, CRC(24f1bca9) SHA1(719dc4e003c1d13fcbb39604c156c89042c47dfd) )
547	547	/* ic31 unpopulated */
548	548	/* ic32 unpopulated */
549	549	/* ic33 unpopulated */
r242413	r242414
553	553
554	554	/* ROM board using 128M TSOP48 MASKROMs */
555	555	ROM_REGION( 0x10000000, "user2", 0)
556		ROM_LOAD("mpr-23573.ic37" , 0x0000000, 0x1000000, CRC(e22a0734) SHA1(fc06d5972d285d09473874aaeb1efed2d19c8f36) )
557		ROM_LOAD("mpr-23577.ic38" , 0x1000000, 0x1000000, CRC(d007680d) SHA1(a795057c40b1851adb0e19e5dfb39e16206215bf) )
558		ROM_LOAD("mpr-23574.ic41" , 0x2000000, 0x1000000, CRC(a77034a5) SHA1(e6e8e2f747e7a972144436103741acfd7030fe84) )
559		ROM_LOAD("mpr-23578.ic42" , 0x3000000, 0x1000000, CRC(db612dd6) SHA1(e6813a1e16099094d67347027e058be582750ad7) )
560		ROM_LOAD("mpr-23575.ic45" , 0x4000000, 0x1000000, CRC(fe660f06) SHA1(73916f67d852df719fd65b1ed0f8b977c0c33390) )
561		ROM_LOAD("mpr-23579.ic46" , 0x5000000, 0x1000000, CRC(55e656d2) SHA1(5d0b26807cf915ab0ae5cc3a7c9dd6bec43da7b2) )
562		ROM_LOAD("mpr-23576.ic49" , 0x6000000, 0x1000000, CRC(c01e0329) SHA1(df1a3c83f338925d69912af56f675197e14e1793) )
563		ROM_LOAD("mpr-23580.ic50" , 0x7000000, 0x1000000, CRC(d260f39c) SHA1(e5cdf399defaaa7dbcee62f7ab64b898c28d8f7d) )
	556	ROM_LOAD32_WORD( "mpr-23573.ic37" , 0x0000000, 0x1000000, CRC(e22a0734) SHA1(fc06d5972d285d09473874aaeb1efed2d19c8f36) )
	557	ROM_LOAD32_WORD( "mpr-23577.ic38" , 0x0000002, 0x1000000, CRC(d007680d) SHA1(a795057c40b1851adb0e19e5dfb39e16206215bf) )
	558	ROM_LOAD32_WORD( "mpr-23574.ic41" , 0x2000000, 0x1000000, CRC(a77034a5) SHA1(e6e8e2f747e7a972144436103741acfd7030fe84) )
	559	ROM_LOAD32_WORD( "mpr-23578.ic42" , 0x2000002, 0x1000000, CRC(db612dd6) SHA1(e6813a1e16099094d67347027e058be582750ad7) )
	560	ROM_LOAD32_WORD( "mpr-23575.ic45" , 0x4000000, 0x1000000, CRC(fe660f06) SHA1(73916f67d852df719fd65b1ed0f8b977c0c33390) )
	561	ROM_LOAD32_WORD( "mpr-23579.ic46" , 0x4000002, 0x1000000, CRC(55e656d2) SHA1(5d0b26807cf915ab0ae5cc3a7c9dd6bec43da7b2) )
	562	ROM_LOAD32_WORD( "mpr-23576.ic49" , 0x6000000, 0x1000000, CRC(c01e0329) SHA1(df1a3c83f338925d69912af56f675197e14e1793) )
	563	ROM_LOAD32_WORD( "mpr-23580.ic50" , 0x6000002, 0x1000000, CRC(d260f39c) SHA1(e5cdf399defaaa7dbcee62f7ab64b898c28d8f7d) )
564	564	/* ic53 unpopulated */
565	565	/* ic54 unpopulated */
566	566	/* ic57 unpopulated */
r242413	r242414
569	569	/* ic62 unpopulated */
570	570	/* ic65 unpopulated */
571	571	/* ic66 unpopulated */
	572
	573	// 315-5881 security IC key
	574	ROM_REGION( 4, "rom_key", 0 )
	575	ROM_LOAD( "airtrix-key.bin", 0, 4, CRC(bebdc179) SHA1(327ea299934ef78f3c88329fc624dc3771877453) )
572	576	ROM_END
573	577
574	578
r242413	r242414
577	581	HIKARU_BIOS
578	582
579	583	ROM_REGION( 0x2000000, "user1", 0)
580		ROM_LOAD32_WORD("epr23565a.ic29", 0x0000000, 0x0400000, CRC(ca9af8a7) SHA1(e7d6badc03ec5833ee89e49dd389ee19b45da29c) )
581		ROM_LOAD32_WORD("epr23566a.ic30", 0x0000002, 0x0400000, CRC(aad0057c) SHA1(c18c0f1797432c74dc21bcd806cb5760916e4936) )
582		ROM_LOAD32_WORD("epr23567.ic31",  0x0800000, 0x0400000, CRC(f0e3dcdc) SHA1(422978a13e39f439da54e43a65dcad1a5b1f2f27) )
583		ROM_LOAD32_WORD("epr23568.ic32",  0x0800002, 0x0400000, CRC(6eee734c) SHA1(0941761b1690ad4eeac0bf682459992c6f38a930) )
584		ROM_LOAD32_WORD("epr23569.ic33",  0x1000000, 0x0400000, CRC(867c7064) SHA1(5cf0d88a1c739ba69b33f1ba3a0e5544331f63f3) )
585		ROM_LOAD32_WORD("epr23570.ic34",  0x1000002, 0x0400000, CRC(556ff58b) SHA1(7eb527aee823d037d1045d850427efa42d5da787) )
586		ROM_LOAD32_WORD("epr23571.ic35",  0x1800000, 0x0400000, CRC(5a75fa92) SHA1(b5e0c8c995ecc954b74d5eb36f3ae2a732a5986b) )
587		ROM_LOAD32_WORD("epr23572.ic36",  0x1800002, 0x0400000, CRC(46054067) SHA1(449800bdc2c40c76aed9bc5e7e8831d8f03ef286) )
	584	ROM_LOAD32_WORD("epr-23565a.ic29", 0x0000000, 0x0400000, CRC(ca9af8a7) SHA1(e7d6badc03ec5833ee89e49dd389ee19b45da29c) )
	585	ROM_LOAD32_WORD("epr-23566a.ic30", 0x0000002, 0x0400000, CRC(aad0057c) SHA1(c18c0f1797432c74dc21bcd806cb5760916e4936) )
	586	ROM_LOAD32_WORD("epr-23567.ic31",  0x0800000, 0x0400000, CRC(f0e3dcdc) SHA1(422978a13e39f439da54e43a65dcad1a5b1f2f27) )
	587	ROM_LOAD32_WORD("epr-23568.ic32",  0x0800002, 0x0400000, CRC(6eee734c) SHA1(0941761b1690ad4eeac0bf682459992c6f38a930) )
	588	ROM_LOAD32_WORD("epr-23569.ic33",  0x1000000, 0x0400000, CRC(867c7064) SHA1(5cf0d88a1c739ba69b33f1ba3a0e5544331f63f3) )
	589	ROM_LOAD32_WORD("epr-23570.ic34",  0x1000002, 0x0400000, CRC(556ff58b) SHA1(7eb527aee823d037d1045d850427efa42d5da787) )
	590	ROM_LOAD32_WORD("epr-23571.ic35",  0x1800000, 0x0400000, CRC(5a75fa92) SHA1(b5e0c8c995ecc954b74d5eb36f3ae2a732a5986b) )
	591	ROM_LOAD32_WORD("epr-23572.ic36",  0x1800002, 0x0400000, CRC(46054067) SHA1(449800bdc2c40c76aed9bc5e7e8831d8f03ef286) )
588	592
589	593	/* ROM board using 128M TSOP48 MASKROMs */
590	594	ROM_REGION( 0x10000000, "user2", 0)
591		ROM_LOAD( "mpr-23549.ic37", 0x0000000, 0x1000000, CRC(ed764200) SHA1(ad840a40347345f72a443f284b1bb0ae2b37f7ac) )
592		ROM_LOAD( "mpr-23553.ic38", 0x1000000, 0x1000000, CRC(5e70ae78) SHA1(2ae6bdb5aa1434bb60b2b9bca7af12d6476cd35f) )
593		ROM_LOAD( "mpr-23550.ic41", 0x2000000, 0x1000000, CRC(841b4d3b) SHA1(d442078b6b4926e6e32b911d88a4408d20a8f0df) )
594		ROM_LOAD( "mpr-23554.ic42", 0x3000000, 0x1000000, CRC(5cce99de) SHA1(c39330e4bcfb4cec8b0b59ab184fad5093188765) )
595		ROM_LOAD( "mpr-23551.ic45", 0x4000000, 0x1000000, CRC(71f61d04) SHA1(6f24f82ddc5aaf9bbb41b8baddbcb855f1d37a16) )
596		ROM_LOAD( "mpr-23555.ic46", 0x5000000, 0x1000000, CRC(582e5453) SHA1(cf9fb8b52a169446b98630d67cdce745de917edc) )
597		ROM_LOAD( "mpr-23552.ic49", 0x6000000, 0x1000000, CRC(32487181) SHA1(a885747428c280f77dd861bf802d953da133ef59) )
598		ROM_LOAD( "mpr-23556.ic50", 0x7000000, 0x1000000, CRC(45002955) SHA1(85a27c86692ca79fc4e51a64af63a5e970b86cfa) )
599		ROM_LOAD( "mpr-23557.ic53", 0x8000000, 0x1000000, CRC(c20dff1b) SHA1(d90d3d85f4fddf39c109502c8f9e9f25a7fc43d1) )
600		ROM_LOAD( "mpr-23561.ic54", 0x9000000, 0x1000000, CRC(01237844) SHA1(7a8c6bfdea1d4db5e9f6850fdf1a03d703df3958) )
601		ROM_LOAD( "mpr-23558.ic57", 0xa000000, 0x1000000, CRC(e93cc8d7) SHA1(05fc23b8382daaca7ccd1ca80e7c5e93cbf2b6b1) )
602		ROM_LOAD( "mpr-23562.ic58", 0xb000000, 0x1000000, CRC(85e0816c) SHA1(28106404d1eef4c85dd425d3535a53c5d71e47a0) )
603		ROM_LOAD( "mpr-23559.ic61", 0xc000000, 0x1000000, CRC(1a7f2ba0) SHA1(e2a20138f21297f5313f5368ef9992da8fa23937) )
604		ROM_LOAD( "mpr-23563.ic62", 0xd000000, 0x1000000, CRC(e3dc328b) SHA1(d04ccc4025442c98b96f84c1b300671f3687ec6c) )
605		ROM_LOAD( "mpr-23560.ic65", 0xe000000, 0x1000000, CRC(24bb7072) SHA1(dad5135c89d292e4a1f96bd0ad28be6a17154be0) )
606		ROM_LOAD( "mpr-23564.ic66", 0xf000000, 0x1000000, CRC(255724b6) SHA1(1b382fad165831de3f2e39352c031146759dfc69) )
	595	ROM_LOAD32_WORD( "mpr-23549.ic37", 0x0000000, 0x1000000, CRC(ed764200) SHA1(ad840a40347345f72a443f284b1bb0ae2b37f7ac) )
	596	ROM_LOAD32_WORD( "mpr-23553.ic38", 0x0000002, 0x1000000, CRC(5e70ae78) SHA1(2ae6bdb5aa1434bb60b2b9bca7af12d6476cd35f) )
	597	ROM_LOAD32_WORD( "mpr-23550.ic41", 0x2000000, 0x1000000, CRC(841b4d3b) SHA1(d442078b6b4926e6e32b911d88a4408d20a8f0df) )
	598	ROM_LOAD32_WORD( "mpr-23554.ic42", 0x2000002, 0x1000000, CRC(5cce99de) SHA1(c39330e4bcfb4cec8b0b59ab184fad5093188765) )
	599	ROM_LOAD32_WORD( "mpr-23551.ic45", 0x4000000, 0x1000000, CRC(71f61d04) SHA1(6f24f82ddc5aaf9bbb41b8baddbcb855f1d37a16) )
	600	ROM_LOAD32_WORD( "mpr-23555.ic46", 0x4000002, 0x1000000, CRC(582e5453) SHA1(cf9fb8b52a169446b98630d67cdce745de917edc) )
	601	ROM_LOAD32_WORD( "mpr-23552.ic49", 0x6000000, 0x1000000, CRC(32487181) SHA1(a885747428c280f77dd861bf802d953da133ef59) )
	602	ROM_LOAD32_WORD( "mpr-23556.ic50", 0x6000002, 0x1000000, CRC(45002955) SHA1(85a27c86692ca79fc4e51a64af63a5e970b86cfa) )
	603	ROM_LOAD32_WORD( "mpr-23557.ic53", 0x8000000, 0x1000000, CRC(c20dff1b) SHA1(d90d3d85f4fddf39c109502c8f9e9f25a7fc43d1) )
	604	ROM_LOAD32_WORD( "mpr-23561.ic54", 0x8000002, 0x1000000, CRC(01237844) SHA1(7a8c6bfdea1d4db5e9f6850fdf1a03d703df3958) )
	605	ROM_LOAD32_WORD( "mpr-23558.ic57", 0xa000000, 0x1000000, CRC(e93cc8d7) SHA1(05fc23b8382daaca7ccd1ca80e7c5e93cbf2b6b1) )
	606	ROM_LOAD32_WORD( "mpr-23562.ic58", 0xa000002, 0x1000000, CRC(85e0816c) SHA1(28106404d1eef4c85dd425d3535a53c5d71e47a0) )
	607	ROM_LOAD32_WORD( "mpr-23559.ic61", 0xc000000, 0x1000000, CRC(1a7f2ba0) SHA1(e2a20138f21297f5313f5368ef9992da8fa23937) )
	608	ROM_LOAD32_WORD( "mpr-23563.ic62", 0xc000002, 0x1000000, CRC(e3dc328b) SHA1(d04ccc4025442c98b96f84c1b300671f3687ec6c) )
	609	ROM_LOAD32_WORD( "mpr-23560.ic65", 0xe000000, 0x1000000, CRC(24bb7072) SHA1(dad5135c89d292e4a1f96bd0ad28be6a17154be0) )
	610	ROM_LOAD32_WORD( "mpr-23564.ic66", 0xe000002, 0x1000000, CRC(255724b6) SHA1(1b382fad165831de3f2e39352c031146759dfc69) )
	611
	612	// 315-5881 security IC key
	613	ROM_REGION( 4, "rom_key", 0 )
	614	ROM_LOAD( "pharrier-key.bin", 0, 4, CRC(1697d591) SHA1(8ad4c93f63e2e379795e820d3edbdd990f8ca7e1) )
607	615	ROM_END
608	616
609	617	ROM_START( podrace )
r242413	r242414
622	630
623	631	/* ROM board using 64M SOP44 MASKROM */
624	632	ROM_REGION( 0x10000000, "user2", 0)
625		ROM_LOAD("mpr-23086.ic37" , 0x0000000, 0x0800000, CRC(ef6f20f1) SHA1(11fb66bf71223b4c6650d3adaea21e8709b8d67b))
626		ROM_LOAD("mpr-23087.ic38" , 0x0800000, 0x0800000, CRC(54389822) SHA1(6357f0aa77ef0a5a08a751e085fa026d26ba47d1))
627		ROM_LOAD("mpr-23088.ic39" , 0x1000000, 0x0800000, CRC(9f1a382e) SHA1(b846c3a091d04e49cc1e731237c9326ccac39a64))
628		ROM_LOAD("mpr-23089.ic40" , 0x1800000, 0x0800000, CRC(6aae64fc) SHA1(392b6fba25d20bb41fd72be3a3a9ce95b2374065))
629		ROM_LOAD("mpr-23090.ic41" , 0x2000000, 0x0800000, CRC(ba857872) SHA1(c07ff7955d3d07f2a60d9761b4bd692c0a9c9353))
630		ROM_LOAD("mpr-23091.ic42" , 0x2800000, 0x0800000, CRC(66a73e27) SHA1(c4e7d190a80499225a78b7f788c2abc7ec4ebdca))
631		ROM_LOAD("mpr-23092.ic43" , 0x3000000, 0x0800000, CRC(4f20a0f5) SHA1(0580feba6a6dd01a21d09ec2503ccf77030f8d2a))
632		ROM_LOAD("mpr-23093.ic44" , 0x3800000, 0x0800000, CRC(e74d7d64) SHA1(c28e44319bf08aedd9aed625a12834ec76f1e5e0))
633		ROM_LOAD("mpr-23094.ic45" , 0x4000000, 0x0800000, CRC(90f04c14) SHA1(b55846ea1edd920fd527e3257b13fea8df1f713f))
634		ROM_LOAD("mpr-23095.ic46" , 0x4800000, 0x0800000, CRC(cc67cb5b) SHA1(85e99ec22d1c65139685a94f1ba0c52a0eb33a2e))
635		ROM_LOAD("mpr-23096.ic47" , 0x5000000, 0x0800000, CRC(799ab79e) SHA1(c0ac85ad7f4cf46ff162f1ec2e85a3f22817de5e))
636		ROM_LOAD("mpr-23097.ic48" , 0x5800000, 0x0800000, CRC(f68439de) SHA1(475d0f22e78e3c86431b742e37cbfd764ca8acee))
637		ROM_LOAD("mpr-23098.ic49" , 0x6000000, 0x0800000, CRC(a1e2009c) SHA1(c6a600d47fd2a96d28c637631862150e6f303c3d))
638		ROM_LOAD("mpr-23099.ic50" , 0x6800000, 0x0800000, CRC(ce36f642) SHA1(6cb2e69095efc7969255ebc637e2597c56442751))
639		ROM_LOAD("mpr-23100.ic51" , 0x7000000, 0x0800000, CRC(0f966653) SHA1(1544af662188ea734e0a2e559e05e5f782fb292d))
640		ROM_LOAD("mpr-23101.ic52" , 0x7800000, 0x0800000, CRC(2640fbaa) SHA1(59e9bd143734c71968beb9953122680d3350e69c))
641		ROM_LOAD("mpr-23102.ic53" , 0x8000000, 0x0800000, CRC(080c5bcb) SHA1(0cf54348420ae9866edd64422cb82464990f1f2f))
642		ROM_LOAD("mpr-23103.ic54" , 0x8800000, 0x0800000, CRC(19c7758f) SHA1(fed7f45dd91e1cb6bba7d8e80ed17dca27d92e43))
643		ROM_LOAD("mpr-23104.ic55" , 0x9000000, 0x0800000, CRC(4ca74216) SHA1(0e65971359ba0e2b4fc032a26d1c10d8efadc205))
644		ROM_LOAD("mpr-23105.ic56" , 0x9800000, 0x0800000, CRC(e2dd35ba) SHA1(2213e3195a49532a177086de8134ce8b753fc7ce))
645		ROM_LOAD("mpr-23106.ic57" , 0xa000000, 0x0800000, CRC(dd325515) SHA1(8144e1a87f7d72a18791d1d452123a91cfb354dd))
646		ROM_LOAD("mpr-23107.ic58" , 0xa800000, 0x0800000, CRC(a527a22a) SHA1(54c105b21797c9b0a2a6b2c7091de726c49a55e8))
647		ROM_LOAD("mpr-23108.ic59" , 0xb000000, 0x0800000, CRC(47817d9a) SHA1(d2c6f1b2e800448eaf694d550733bba2280b6746))
648		ROM_LOAD("mpr-23109.ic60" , 0xb800000, 0x0800000, CRC(8c61dec4) SHA1(25a1a5b236b3aed013fc94bd9695906ae5d7f305))
649		ROM_LOAD("mpr-23110.ic61" , 0xc000000, 0x0800000, CRC(4ddae9f1) SHA1(d1c5e3f18932af806f166779cf14909ab17d052c))
650		ROM_LOAD("mpr-23111.ic62" , 0xc800000, 0x0800000, CRC(c404cb1c) SHA1(e14855ec8a5a5ba243a2339c571928fdcc187157))
651		ROM_LOAD("mpr-23112.ic63" , 0xd000000, 0x0800000, CRC(d001fe59) SHA1(ab395d2933b5d691259221168dfaa063cf9a4d1c))
652		ROM_LOAD("mpr-23113.ic64" , 0xd800000, 0x0800000, CRC(f241cfd5) SHA1(5b85e8b50559becff7a76565c95487825bbd9351))
653		ROM_LOAD("mpr-23114.ic65" , 0xe000000, 0x0800000, CRC(80049d7c) SHA1(56aab53e9317b1b5d10bd2af78fd83e7422d8939))
654		ROM_LOAD("mpr-23115.ic66" , 0xe800000, 0x0800000, CRC(4fc540fe) SHA1(df580421d856566e067c2b319c8ac4671629682f))
655		ROM_LOAD("mpr-23116.ic67" , 0xf000000, 0x0800000, CRC(9f567fce) SHA1(c35bcf968f139557e50ceafa9c6bad4deb87154f))
656		ROM_LOAD("mpr-23117.ic68" , 0xf800000, 0x0800000, CRC(9d4d3529) SHA1(66008445629681ebf2f26b3f181d8524a8576d2f))
	633	ROM_LOAD32_WORD("mpr-23086.ic37" ,  0x0000000, 0x0800000, CRC(ef6f20f1) SHA1(11fb66bf71223b4c6650d3adaea21e8709b8d67b))
	634	ROM_LOAD32_WORD("mpr-23087.ic38" ,  0x0000002, 0x0800000, CRC(54389822) SHA1(6357f0aa77ef0a5a08a751e085fa026d26ba47d1))
	635	ROM_LOAD32_WORD("mpr-23088.ic39" ,  0x1000000, 0x0800000, CRC(9f1a382e) SHA1(b846c3a091d04e49cc1e731237c9326ccac39a64))
	636	ROM_LOAD32_WORD("mpr-23089.ic40" ,  0x1000002, 0x0800000, CRC(6aae64fc) SHA1(392b6fba25d20bb41fd72be3a3a9ce95b2374065))
	637	ROM_LOAD32_WORD("mpr-23090.ic41" ,  0x2000000, 0x0800000, CRC(ba857872) SHA1(c07ff7955d3d07f2a60d9761b4bd692c0a9c9353))
	638	ROM_LOAD32_WORD("mpr-23091.ic42" ,  0x2000002, 0x0800000, CRC(66a73e27) SHA1(c4e7d190a80499225a78b7f788c2abc7ec4ebdca))
	639	ROM_LOAD32_WORD("mpr-23092.ic43" ,  0x3000000, 0x0800000, CRC(4f20a0f5) SHA1(0580feba6a6dd01a21d09ec2503ccf77030f8d2a))
	640	ROM_LOAD32_WORD("mpr-23093.ic44" ,  0x3000002, 0x0800000, CRC(e74d7d64) SHA1(c28e44319bf08aedd9aed625a12834ec76f1e5e0))
	641	ROM_LOAD32_WORD("mpr-23094.ic45" ,  0x4000000, 0x0800000, CRC(90f04c14) SHA1(b55846ea1edd920fd527e3257b13fea8df1f713f))
	642	ROM_LOAD32_WORD("mpr-23095.ic46" ,  0x4000002, 0x0800000, CRC(cc67cb5b) SHA1(85e99ec22d1c65139685a94f1ba0c52a0eb33a2e))
	643	ROM_LOAD32_WORD("mpr-23096.ic47" ,  0x5000000, 0x0800000, CRC(799ab79e) SHA1(c0ac85ad7f4cf46ff162f1ec2e85a3f22817de5e))
	644	ROM_LOAD32_WORD("mpr-23097.ic48" ,  0x5000002, 0x0800000, CRC(f68439de) SHA1(475d0f22e78e3c86431b742e37cbfd764ca8acee))
	645	ROM_LOAD32_WORD("mpr-23098.ic49" ,  0x6000000, 0x0800000, CRC(a1e2009c) SHA1(c6a600d47fd2a96d28c637631862150e6f303c3d))
	646	ROM_LOAD32_WORD("mpr-23099.ic50" ,  0x6000002, 0x0800000, CRC(ce36f642) SHA1(6cb2e69095efc7969255ebc637e2597c56442751))
	647	ROM_LOAD32_WORD("mpr-23100.ic51" ,  0x7000000, 0x0800000, CRC(0f966653) SHA1(1544af662188ea734e0a2e559e05e5f782fb292d))
	648	ROM_LOAD32_WORD("mpr-23101.ic52" ,  0x7000002, 0x0800000, CRC(2640fbaa) SHA1(59e9bd143734c71968beb9953122680d3350e69c))
	649	ROM_LOAD32_WORD("mpr-23102.ic53s" , 0x8000000, 0x0800000, CRC(080c5bcb) SHA1(0cf54348420ae9866edd64422cb82464990f1f2f))
	650	ROM_LOAD32_WORD("mpr-23103.ic54s" , 0x8000002, 0x0800000, CRC(19c7758f) SHA1(fed7f45dd91e1cb6bba7d8e80ed17dca27d92e43))
	651	ROM_LOAD32_WORD("mpr-23104.ic55s" , 0x9000000, 0x0800000, CRC(4ca74216) SHA1(0e65971359ba0e2b4fc032a26d1c10d8efadc205))
	652	ROM_LOAD32_WORD("mpr-23105.ic56s" , 0x9000002, 0x0800000, CRC(e2dd35ba) SHA1(2213e3195a49532a177086de8134ce8b753fc7ce))
	653	ROM_LOAD32_WORD("mpr-23106.ic57s" , 0xa000000, 0x0800000, CRC(dd325515) SHA1(8144e1a87f7d72a18791d1d452123a91cfb354dd))
	654	ROM_LOAD32_WORD("mpr-23107.ic58s" , 0xa000002, 0x0800000, CRC(a527a22a) SHA1(54c105b21797c9b0a2a6b2c7091de726c49a55e8))
	655	ROM_LOAD32_WORD("mpr-23108.ic59s" , 0xb000000, 0x0800000, CRC(47817d9a) SHA1(d2c6f1b2e800448eaf694d550733bba2280b6746))
	656	ROM_LOAD32_WORD("mpr-23109.ic60s" , 0xb000002, 0x0800000, CRC(8c61dec4) SHA1(25a1a5b236b3aed013fc94bd9695906ae5d7f305))
	657	ROM_LOAD32_WORD("mpr-23110.ic61s" , 0xc000000, 0x0800000, CRC(4ddae9f1) SHA1(d1c5e3f18932af806f166779cf14909ab17d052c))
	658	ROM_LOAD32_WORD("mpr-23111.ic62s" , 0xc000002, 0x0800000, CRC(c404cb1c) SHA1(e14855ec8a5a5ba243a2339c571928fdcc187157))
	659	ROM_LOAD32_WORD("mpr-23112.ic63s" , 0xd000000, 0x0800000, CRC(d001fe59) SHA1(ab395d2933b5d691259221168dfaa063cf9a4d1c))
	660	ROM_LOAD32_WORD("mpr-23113.ic64s" , 0xd000002, 0x0800000, CRC(f241cfd5) SHA1(5b85e8b50559becff7a76565c95487825bbd9351))
	661	ROM_LOAD32_WORD("mpr-23114.ic65s" , 0xe000000, 0x0800000, CRC(80049d7c) SHA1(56aab53e9317b1b5d10bd2af78fd83e7422d8939))
	662	ROM_LOAD32_WORD("mpr-23115.ic66s" , 0xe000002, 0x0800000, CRC(4fc540fe) SHA1(df580421d856566e067c2b319c8ac4671629682f))
	663	ROM_LOAD32_WORD("mpr-23116.ic67s" , 0xf000000, 0x0800000, CRC(9f567fce) SHA1(c35bcf968f139557e50ceafa9c6bad4deb87154f))
	664	ROM_LOAD32_WORD("mpr-23117.ic68s" , 0xf000002, 0x0800000, CRC(9d4d3529) SHA1(66008445629681ebf2f26b3f181d8524a8576d2f))
	665
	666	// current 315-5881 decryption simulation code can't produce valid output data with any of keys
	667	ROM_REGION( 4, "rom_key", ROMREGION_ERASE00 )
657	668	ROM_END
658	669
659	670	ROM_START( braveff )
r242413	r242414
661	672	HIKARU_BIOS
662	673
663	674	ROM_REGION( 0x2000000, "user1", 0)
664		ROM_LOAD32_WORD( "epr-21994.ic29", 0x000000, 0x200000, CRC(31b0a754) SHA1(b49c998a15fbc790b780ed6665a56681d4edd369) )
665		ROM_LOAD32_WORD( "epr-21995.ic30", 0x000002, 0x200000, CRC(bcccb56b) SHA1(6e7a69934e5b47495ae8e90c57759573bc519d24) )
666		ROM_LOAD32_WORD( "epr-21996.ic31", 0x400000, 0x200000, CRC(a8f88e17) SHA1(dbbd2a73335c740bcf2ff9680c575841af29b340) )
667		ROM_LOAD32_WORD( "epr-21997.ic32", 0x400002, 0x200000, CRC(36641a7f) SHA1(37931bde1ddebef61fa6d8caca3cb67328fd0b90) )
668		ROM_LOAD32_WORD( "epr-21998.ic33", 0x800000, 0x200000, CRC(bd1df696) SHA1(fd937894763fab5cb50f33c40f8047e0d3adc93b) )
669		ROM_LOAD32_WORD( "epr-21999.ic34", 0x800002, 0x200000, CRC(9425eee0) SHA1(0f6a23163022bbd7ec54dd638094f3e317a87919) )
	675	ROM_LOAD32_WORD( "epr-21994.ic29", 0x0000000, 0x200000, CRC(31b0a754) SHA1(b49c998a15fbc790b780ed6665a56681d4edd369) )
	676	ROM_LOAD32_WORD( "epr-21995.ic30", 0x0000002, 0x200000, CRC(bcccb56b) SHA1(6e7a69934e5b47495ae8e90c57759573bc519d24) )
	677	ROM_LOAD32_WORD( "epr-21996.ic31", 0x0800000, 0x200000, CRC(a8f88e17) SHA1(dbbd2a73335c740bcf2ff9680c575841af29b340) )
	678	ROM_LOAD32_WORD( "epr-21997.ic32", 0x0800002, 0x200000, CRC(36641a7f) SHA1(37931bde1ddebef61fa6d8caca3cb67328fd0b90) )
	679	ROM_LOAD32_WORD( "epr-21998.ic33", 0x1000000, 0x200000, CRC(bd1df696) SHA1(fd937894763fab5cb50f33c40f8047e0d3adc93b) )
	680	ROM_LOAD32_WORD( "epr-21999.ic34", 0x1000002, 0x200000, CRC(9425eee0) SHA1(0f6a23163022bbd7ec54dd638094f3e317a87919) )
670	681	/* ic35 unpopulated */
671	682	/* ic36 unpopulated */
672	683
673	684	/* ROM board using 64M SOP44 MASKROM */
674	685	ROM_REGION( 0xc000000, "user2", ROMREGION_ERASE00)
675		ROM_LOAD( "mpr-22000.ic37",  0x0000000, 0x800000, CRC(53d641d6) SHA1(f47d7c77d0e36c4ec3b7171fd7a017f9f58ca5a0) )
676		ROM_LOAD( "mpr-22001.ic38",  0x0800000, 0x800000, CRC(234bc48f) SHA1(177c46884de0ba4bac1f9b778f99c905410a9345) )
677		ROM_LOAD( "mpr-22002.ic39",  0x1000000, 0x800000, CRC(d8f3aa9e) SHA1(f73208034fdd51fed086e912cb8580d2270122b6) )
678		ROM_LOAD( "mpr-22003.ic40",  0x1800000, 0x800000, CRC(2560fe98) SHA1(9bb5ffb6212ec6aa3f92e437eb424141f3b15e43) )
679		ROM_LOAD( "mpr-22004.ic41",  0x2000000, 0x800000, CRC(4e24d71d) SHA1(503344dd8cdd8e65ec7c801b0efae83b3f1f9ae2) )
680		ROM_LOAD( "mpr-22005.ic42",  0x2800000, 0x800000, CRC(2b96c97f) SHA1(707070c85f4b044236694daa13970c241b242d4d) )
681		ROM_LOAD( "mpr-22006.ic43",  0x3000000, 0x800000, CRC(f793a3ba) SHA1(80acd1d4f71cafd7328ff9b9ce30e5169b8f4f8c) )
682		ROM_LOAD( "mpr-22007.ic44",  0x3800000, 0x800000, CRC(62616e31) SHA1(dbe0d4b8fc085ed97884c105fd527af5cd8fbe79) )
683		ROM_LOAD( "mpr-22008.ic45",  0x4000000, 0x800000, CRC(e6905de8) SHA1(6bb4e43b1394788add15f0b78ccd5ab14f86516c) )
684		ROM_LOAD( "mpr-22009.ic46",  0x4800000, 0x800000, CRC(c37dfa5c) SHA1(5a3a5f2eb5a13831e36ca215147ec3c9740c50fc) )
685		ROM_LOAD( "mpr-22010.ic47",  0x5000000, 0x800000, CRC(b570b46c) SHA1(6e512fd1a2c8835f6aee307865b42d57ddf90ef5) )
686		ROM_LOAD( "mpr-22011.ic48",  0x5800000, 0x800000, CRC(d1f5fb58) SHA1(08a1282e00bda52d8d938225c65f67d22abfea05) )
687		ROM_LOAD( "mpr-22012.ic49",  0x6000000, 0x800000, CRC(3ab79029) SHA1(d4708446ba700d5f7c89827c80177ad2d1c0b222) )
688		ROM_LOAD( "mpr-22013.ic50",  0x6800000, 0x800000, CRC(42d8d00b) SHA1(ddce3c95258d8cf51792f2115f89ca658ffe97b6) )
689		ROM_LOAD( "mpr-22014.ic51",  0x7000000, 0x800000, CRC(0f49c00f) SHA1(877c654268edc9526ae3e21e21e3ecca706f300b) )
690		ROM_LOAD( "mpr-22015.ic52",  0x7800000, 0x800000, CRC(d3696e61) SHA1(247161c99c7061b8f391543af1812764a82399cb) )
691		ROM_LOAD( "mpr-22016.ic53s", 0x8000000, 0x800000, CRC(c1015e00) SHA1(f2ce2009d4f4f0f3cbfcce7a36fab2c54e738b07) )
692		ROM_LOAD( "mpr-22017.ic54s", 0x8800000, 0x800000, CRC(222a7cb0) SHA1(9f98ae3f13f85fae4596b671ea508b07c2116ab6) )
693		ROM_LOAD( "mpr-22018.ic55s", 0x9000000, 0x800000, CRC(f160e115) SHA1(ecf7f9f58fce6bff220568972ba7763537c9d7d7) )
694		ROM_LOAD( "mpr-22019.ic56s", 0x9800000, 0x800000, CRC(468b2f10) SHA1(f3fc0af7d4dd3f30ba84e684f3d9c217730564bb) )
695		ROM_LOAD( "mpr-22020.ic57s", 0xa000000, 0x800000, CRC(0c018d8a) SHA1(0447d7ad64061cca4c1231733e660ba51de5a216) )
696		ROM_LOAD( "mpr-22021.ic58s", 0xa800000, 0x800000, CRC(43b08604) SHA1(681142d8b95b2f9664d70b23262a64938774d4e3) )
697		ROM_LOAD( "mpr-22022.ic59s", 0xb000000, 0x800000, CRC(abd3d888) SHA1(9654c3a38feab46b4983a602831fb29cccdd0526) )
698		ROM_LOAD( "mpr-22023.ic60s", 0xb800000, 0x800000, CRC(07f00869) SHA1(92282d09d72d3e65a91128e06bb0d4426bb90be5) )
	686	ROM_LOAD32_WORD( "mpr-22000.ic37",  0x0000000, 0x800000, CRC(53d641d6) SHA1(f47d7c77d0e36c4ec3b7171fd7a017f9f58ca5a0) )
	687	ROM_LOAD32_WORD( "mpr-22001.ic38",  0x0000002, 0x800000, CRC(234bc48f) SHA1(177c46884de0ba4bac1f9b778f99c905410a9345) )
	688	ROM_LOAD32_WORD( "mpr-22002.ic39",  0x1000000, 0x800000, CRC(d8f3aa9e) SHA1(f73208034fdd51fed086e912cb8580d2270122b6) )
	689	ROM_LOAD32_WORD( "mpr-22003.ic40",  0x1000002, 0x800000, CRC(2560fe98) SHA1(9bb5ffb6212ec6aa3f92e437eb424141f3b15e43) )
	690	ROM_LOAD32_WORD( "mpr-22004.ic41",  0x2000000, 0x800000, CRC(4e24d71d) SHA1(503344dd8cdd8e65ec7c801b0efae83b3f1f9ae2) )
	691	ROM_LOAD32_WORD( "mpr-22005.ic42",  0x2000002, 0x800000, CRC(2b96c97f) SHA1(707070c85f4b044236694daa13970c241b242d4d) )
	692	ROM_LOAD32_WORD( "mpr-22006.ic43",  0x3000000, 0x800000, CRC(f793a3ba) SHA1(80acd1d4f71cafd7328ff9b9ce30e5169b8f4f8c) )
	693	ROM_LOAD32_WORD( "mpr-22007.ic44",  0x3000002, 0x800000, CRC(62616e31) SHA1(dbe0d4b8fc085ed97884c105fd527af5cd8fbe79) )
	694	ROM_LOAD32_WORD( "mpr-22008.ic45",  0x4000000, 0x800000, CRC(e6905de8) SHA1(6bb4e43b1394788add15f0b78ccd5ab14f86516c) )
	695	ROM_LOAD32_WORD( "mpr-22009.ic46",  0x4000002, 0x800000, CRC(c37dfa5c) SHA1(5a3a5f2eb5a13831e36ca215147ec3c9740c50fc) )
	696	ROM_LOAD32_WORD( "mpr-22010.ic47",  0x5000000, 0x800000, CRC(b570b46c) SHA1(6e512fd1a2c8835f6aee307865b42d57ddf90ef5) )
	697	ROM_LOAD32_WORD( "mpr-22011.ic48",  0x5000002, 0x800000, CRC(d1f5fb58) SHA1(08a1282e00bda52d8d938225c65f67d22abfea05) )
	698	ROM_LOAD32_WORD( "mpr-22012.ic49",  0x6000000, 0x800000, CRC(3ab79029) SHA1(d4708446ba700d5f7c89827c80177ad2d1c0b222) )
	699	ROM_LOAD32_WORD( "mpr-22013.ic50",  0x6000002, 0x800000, CRC(42d8d00b) SHA1(ddce3c95258d8cf51792f2115f89ca658ffe97b6) )
	700	ROM_LOAD32_WORD( "mpr-22014.ic51",  0x7000000, 0x800000, CRC(0f49c00f) SHA1(877c654268edc9526ae3e21e21e3ecca706f300b) )
	701	ROM_LOAD32_WORD( "mpr-22015.ic52",  0x7000002, 0x800000, CRC(d3696e61) SHA1(247161c99c7061b8f391543af1812764a82399cb) )
	702	ROM_LOAD32_WORD( "mpr-22016.ic53s", 0x8000000, 0x800000, CRC(c1015e00) SHA1(f2ce2009d4f4f0f3cbfcce7a36fab2c54e738b07) )
	703	ROM_LOAD32_WORD( "mpr-22017.ic54s", 0x8000002, 0x800000, CRC(222a7cb0) SHA1(9f98ae3f13f85fae4596b671ea508b07c2116ab6) )
	704	ROM_LOAD32_WORD( "mpr-22018.ic55s", 0x9000000, 0x800000, CRC(f160e115) SHA1(ecf7f9f58fce6bff220568972ba7763537c9d7d7) )
	705	ROM_LOAD32_WORD( "mpr-22019.ic56s", 0x9000002, 0x800000, CRC(468b2f10) SHA1(f3fc0af7d4dd3f30ba84e684f3d9c217730564bb) )
	706	ROM_LOAD32_WORD( "mpr-22020.ic57s", 0xa000000, 0x800000, CRC(0c018d8a) SHA1(0447d7ad64061cca4c1231733e660ba51de5a216) )
	707	ROM_LOAD32_WORD( "mpr-22021.ic58s", 0xa000002, 0x800000, CRC(43b08604) SHA1(681142d8b95b2f9664d70b23262a64938774d4e3) )
	708	ROM_LOAD32_WORD( "mpr-22022.ic59s", 0xb000000, 0x800000, CRC(abd3d888) SHA1(9654c3a38feab46b4983a602831fb29cccdd0526) )
	709	ROM_LOAD32_WORD( "mpr-22023.ic60s", 0xb000002, 0x800000, CRC(07f00869) SHA1(92282d09d72d3e65a91128e06bb0d4426bb90be5) )
	710
	711	// 315-5881 not populated
	712	ROM_REGION( 4, "rom_key", ROMREGION_ERASE00 )
699	713	ROM_END
700	714
701	715	ROM_START( sgnascar )
r242413	r242414
708	722
709	723	/* ROM board using 128M TSOP48 MASKROMs */
710	724	ROM_REGION( 0x10000000, "user2", ROMREGION_ERASE00)
711		ROM_LOAD( "mpr-23469.ic19", 0x0000000, 0x1000000, CRC(89cbad8d) SHA1(e4f103b96a3a842a90182172ddcf3bc5dfe6cca8) )
712		ROM_LOAD( "mpr-23473.ic20", 0x1000000, 0x1000000, CRC(977b87d6) SHA1(079eeebc6f9c60d0a016a46386bbe846d8a354da) )
713		ROM_LOAD( "mpr-23470.ic21", 0x2000000, 0x1000000, CRC(faf4940f) SHA1(72fee9ea5b78da260ed99ebe80ca6300f62cdbd7) )
714		ROM_LOAD( "mpr-23474.ic22", 0x3000000, 0x1000000, CRC(faf69ac5) SHA1(875c748151bf0e9cd73d86384665414b2f7b6f5a) )
715		ROM_LOAD( "mpr-23471.ic23", 0x4000000, 0x1000000, CRC(a3aad8ac) SHA1(afc8f3d1546e50afab4f540d59c87fe27cfb2cdd) )
716		ROM_LOAD( "mpr-23475.ic24", 0x5000000, 0x1000000, CRC(5f51597c) SHA1(02c0a5d463714082b7ebb2bec4d0f88aff186f82) )
717		ROM_LOAD( "mpr-23472.ic25", 0x6000000, 0x1000000, CRC(2495f678) SHA1(94b3160aabaea0596855c38ab1b63b16b20f2bae) )
718		ROM_LOAD( "mpr-23476.ic26", 0x7000000, 0x1000000, CRC(927cf31c) SHA1(7cab22a4113d92080a52e1d235bf075ce95f985f) )
719		ROM_LOAD( "mpr-23477.ic27", 0x8000000, 0x1000000, CRC(b4b7c477) SHA1(bcbfe081d509f0b87c6685b9b6617ae146987fe7) )
720		ROM_LOAD( "mpr-23481.ic28", 0x9000000, 0x1000000, CRC(27b8eb7d) SHA1(087b1ed13a3e2a0dbda82c454243214784429d24) )
721		ROM_LOAD( "mpr-23478.ic29", 0xa000000, 0x1000000, CRC(1fac431c) SHA1(2e3903c8cfd55d414555a1d23ba3a97c335991b3) )
722		ROM_LOAD( "mpr-23482.ic30", 0xb000000, 0x1000000, CRC(2e9a0420) SHA1(376d5f0b8274d741a702dc08da50ea5679991740) )
723		ROM_LOAD( "mpr-23479.ic31", 0xc000000, 0x1000000, CRC(9704e393) SHA1(0cb1403f4a268def3ce88db42e55d89ca913e2a0) )
724		ROM_LOAD( "mpr-23483.ic32", 0xd000000, 0x1000000, CRC(c37adebe) SHA1(e84f6d2cc364c743f7f3b73d8c8d0271952bb093) )
725		ROM_LOAD( "mpr-23480.ic33", 0xe000000, 0x1000000, CRC(f517b8b3) SHA1(c04740adb612473c4c9f8186e7e93d2f73d1bb1a) )
726		ROM_LOAD( "mpr-23484.ic34", 0xf000000, 0x1000000, CRC(2ebe1aa1) SHA1(16b39f7422da1a334dde27169c2949e1d95bddb3) )
	725	ROM_LOAD32_WORD( "mpr-23469.ic19", 0x0000000, 0x1000000, CRC(89cbad8d) SHA1(e4f103b96a3a842a90182172ddcf3bc5dfe6cca8) )
	726	ROM_LOAD32_WORD( "mpr-23473.ic20", 0x0000002, 0x1000000, CRC(977b87d6) SHA1(079eeebc6f9c60d0a016a46386bbe846d8a354da) )
	727	ROM_LOAD32_WORD( "mpr-23470.ic21", 0x2000000, 0x1000000, CRC(faf4940f) SHA1(72fee9ea5b78da260ed99ebe80ca6300f62cdbd7) )
	728	ROM_LOAD32_WORD( "mpr-23474.ic22", 0x2000002, 0x1000000, CRC(faf69ac5) SHA1(875c748151bf0e9cd73d86384665414b2f7b6f5a) )
	729	ROM_LOAD32_WORD( "mpr-23471.ic23", 0x4000000, 0x1000000, CRC(a3aad8ac) SHA1(afc8f3d1546e50afab4f540d59c87fe27cfb2cdd) )
	730	ROM_LOAD32_WORD( "mpr-23475.ic24", 0x4000002, 0x1000000, CRC(5f51597c) SHA1(02c0a5d463714082b7ebb2bec4d0f88aff186f82) )
	731	ROM_LOAD32_WORD( "mpr-23472.ic25", 0x6000000, 0x1000000, CRC(2495f678) SHA1(94b3160aabaea0596855c38ab1b63b16b20f2bae) )
	732	ROM_LOAD32_WORD( "mpr-23476.ic26", 0x6000002, 0x1000000, CRC(927cf31c) SHA1(7cab22a4113d92080a52e1d235bf075ce95f985f) )
	733	ROM_LOAD32_WORD( "mpr-23477.ic27", 0x8000000, 0x1000000, CRC(b4b7c477) SHA1(bcbfe081d509f0b87c6685b9b6617ae146987fe7) )
	734	ROM_LOAD32_WORD( "mpr-23481.ic28", 0x8000002, 0x1000000, CRC(27b8eb7d) SHA1(087b1ed13a3e2a0dbda82c454243214784429d24) )
	735	ROM_LOAD32_WORD( "mpr-23478.ic29", 0xa000000, 0x1000000, CRC(1fac431c) SHA1(2e3903c8cfd55d414555a1d23ba3a97c335991b3) )
	736	ROM_LOAD32_WORD( "mpr-23482.ic30", 0xa000002, 0x1000000, CRC(2e9a0420) SHA1(376d5f0b8274d741a702dc08da50ea5679991740) )
	737	ROM_LOAD32_WORD( "mpr-23479.ic31", 0xc000000, 0x1000000, CRC(9704e393) SHA1(0cb1403f4a268def3ce88db42e55d89ca913e2a0) )
	738	ROM_LOAD32_WORD( "mpr-23483.ic32", 0xc000002, 0x1000000, CRC(c37adebe) SHA1(e84f6d2cc364c743f7f3b73d8c8d0271952bb093) )
	739	ROM_LOAD32_WORD( "mpr-23480.ic33", 0xe000000, 0x1000000, CRC(f517b8b3) SHA1(c04740adb612473c4c9f8186e7e93d2f73d1bb1a) )
	740	ROM_LOAD32_WORD( "mpr-23484.ic34", 0xe000002, 0x1000000, CRC(2ebe1aa1) SHA1(16b39f7422da1a334dde27169c2949e1d95bddb3) )
727	741	ROM_END
728	742
729	743	GAME( 2000, hikaru,   0,        hikaru,   hikaru, driver_device,   0, ROT0, "Sega",            "Hikaru Bios", GAME_NO_SOUND|GAME_NOT_WORKING|GAME_IS_BIOS_ROOT )

trunk/src/mame/drivers/igs009.c

r242413	r242414
510	510
511	511	static INPUT_PORTS_START( jingbell )
512	512	PORT_START("DSW1")
513		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
	513	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )   PORT_DIPLOCATION("DSW1:1")
514	514	PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
515	515	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
516		PORT_DIPNAME( 0x02, 0x00, "W-Up Bonus" )
	516	PORT_DIPNAME( 0x02, 0x00, "W-Up Bonus" )      PORT_DIPLOCATION("DSW1:2")
517	517	PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
518		PORT_DIPSETTING(    0x00, DEF_STR( On ) )   // it's shown in attract mode
519		PORT_DIPNAME( 0x04, 0x04, "Min Bet" )
	518	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	519	PORT_DIPNAME( 0x04, 0x04, "Min Bet" )         PORT_DIPLOCATION("DSW1:3")
520	520	PORT_DIPSETTING(    0x04, "1" )
521	521	PORT_DIPSETTING(    0x00, "8" )
522		PORT_DIPNAME( 0x08, 0x08, "Spin Speed" )
	522	PORT_DIPNAME( 0x08, 0x08, "Spin Speed" )      PORT_DIPLOCATION("DSW1:4")
523	523	PORT_DIPSETTING(    0x08, "Slow" )
524	524	PORT_DIPSETTING(    0x00, "Quick" )
525		PORT_DIPNAME( 0x10, 0x00, "Strip Girl" )
	525	PORT_DIPNAME( 0x10, 0x00, "Strip Girl" )      PORT_DIPLOCATION("DSW1:5")
526	526	PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
527	527	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
528		PORT_DIPNAME( 0x20, 0x20, "Payout Mode" )
	528	PORT_DIPNAME( 0x20, 0x20, "Payout Mode" )      PORT_DIPLOCATION("DSW1:6")
529	529	PORT_DIPSETTING(    0x20, DEF_STR( Normal ) )
530	530	PORT_DIPSETTING(    0x00, "Auto" )
531		PORT_DIPNAME( 0xc0, 0xc0, "Player's Panel" )
	531	PORT_DIPNAME( 0xc0, 0xc0, "Player's Panel" )   PORT_DIPLOCATION("DSW1:7,8")
532	532	PORT_DIPSETTING(    0x00, "Type A" )
533	533	PORT_DIPSETTING(    0xc0, "Type A" )
534	534	PORT_DIPSETTING(    0x80, "Type B" )
535	535	PORT_DIPSETTING(    0x40, "Type C" )
536	536
537	537	PORT_START("DSW2")
538		PORT_DIPNAME( 0x07, 0x07, "Main Game Rate (%)" )
539		PORT_DIPSETTING(    0x07, "89" )
540		PORT_DIPSETTING(    0x06, "90" )
541		PORT_DIPSETTING(    0x05, "91" )
542		PORT_DIPSETTING(    0x04, "92" )
543		PORT_DIPSETTING(    0x03, "93" )
544		PORT_DIPSETTING(    0x02, "94" )
545		PORT_DIPSETTING(    0x01, "95" )
546		PORT_DIPSETTING(    0x00, "96" )
547		PORT_DIPNAME( 0x38, 0x38, "W-Up Chance (%)" )
	538	PORT_DIPNAME( 0x07, 0x07, "Main Game Rate (%)" )   PORT_DIPLOCATION("DSW2:1,2,3")
	539	PORT_DIPSETTING(    0x07, "55" )
	540	PORT_DIPSETTING(    0x06, "60" )
	541	PORT_DIPSETTING(    0x05, "65" )
	542	PORT_DIPSETTING(    0x04, "70" )
	543	PORT_DIPSETTING(    0x03, "75" )
	544	PORT_DIPSETTING(    0x02, "80" )
	545	PORT_DIPSETTING(    0x01, "85" )
	546	PORT_DIPSETTING(    0x00, "90" )
	547	PORT_DIPNAME( 0x38, 0x38, "W-Up Chance (%)" )   PORT_DIPLOCATION("DSW2:4,5,6")
548	548	PORT_DIPSETTING(    0x38, "93" )
549	549	PORT_DIPSETTING(    0x30, "94" )
550	550	PORT_DIPSETTING(    0x28, "95" )
r242413	r242414
553	553	PORT_DIPSETTING(    0x10, "98" )
554	554	PORT_DIPSETTING(    0x08, "99" )
555	555	PORT_DIPSETTING(    0x00, "100" )
556		PORT_DIPNAME( 0xc0, 0xc0, "Key In Limit" )
	556	PORT_DIPNAME( 0xc0, 0xc0, "Key In Limit" )      PORT_DIPLOCATION("DSW2:7,8")
557	557	PORT_DIPSETTING(    0xc0, "1k" )
558	558	PORT_DIPSETTING(    0x80, "3k" )
559	559	PORT_DIPSETTING(    0x40, "5k" )
560	560	PORT_DIPSETTING(    0x00, "10k" )
561	561
562	562	PORT_START("DSW3")
563		PORT_DIPNAME( 0x07, 0x07, "Key In Rate" )
	563	PORT_DIPNAME( 0x07, 0x07, "Key In Rate" )      PORT_DIPLOCATION("DSW3:1,2,3")
564	564	PORT_DIPSETTING(    0x07, "1" )
565	565	PORT_DIPSETTING(    0x06, "5" )
566	566	PORT_DIPSETTING(    0x05, "10" )
r242413	r242414
569	569	PORT_DIPSETTING(    0x02, "100" )
570	570	PORT_DIPSETTING(    0x01, "200" )
571	571	PORT_DIPSETTING(    0x00, "500" )
572		PORT_DIPNAME( 0x38, 0x38, "Coin 1 Rate" )
	572	PORT_DIPNAME( 0x38, 0x38, "Coin 1 Rate" )      PORT_DIPLOCATION("DSW3:4,5,6")
573	573	PORT_DIPSETTING(    0x38, "1" )
574	574	PORT_DIPSETTING(    0x30, "2" )
575	575	PORT_DIPSETTING(    0x28, "5" )
r242413	r242414
578	578	PORT_DIPSETTING(    0x10, "25" )
579	579	PORT_DIPSETTING(    0x08, "50" )
580	580	PORT_DIPSETTING(    0x00, "100" )
581		PORT_DIPNAME( 0xc0, 0xc0, "System Limit" )
	581	PORT_DIPNAME( 0xc0, 0xc0, "System Limit" )      PORT_DIPLOCATION("DSW3:7,8")
582	582	PORT_DIPSETTING(    0xc0, "5k" )
583	583	PORT_DIPSETTING(    0x80, "10k" )
584	584	PORT_DIPSETTING(    0x40, "30k" )
585		PORT_DIPSETTING(    0x00, "50k" )
	585	PORT_DIPSETTING(    0x00, "Unlimited" )
586	586
587	587	PORT_START("DSW4")
588		PORT_DIPNAME( 0x01, 0x01, "Min Play For Fever" )
	588	PORT_DIPNAME( 0x01, 0x01, "Min Play For Fever" )   PORT_DIPLOCATION("DSW4:1")
589	589	PORT_DIPSETTING(    0x01, "8" )
590	590	PORT_DIPSETTING(    0x00, "16" )
591		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	591	PORT_DIPNAME( 0x02, 0x02, "Max Bet" )         PORT_DIPLOCATION("DSW4:2")
592	592	PORT_DIPSETTING(    0x02, "16" )
593	593	PORT_DIPSETTING(    0x00, "32" )
594		PORT_DIPNAME( 0x1c, 0x1c, "Coin 2 Rate" )
	594	PORT_DIPNAME( 0x1c, 0x1c, "Coin 2 Rate" )      PORT_DIPLOCATION("DSW4:3,4,5")
595	595	PORT_DIPSETTING(    0x1c, "1" )
596	596	PORT_DIPSETTING(    0x18, "2" )
597	597	PORT_DIPSETTING(    0x14, "5" )
r242413	r242414
600	600	PORT_DIPSETTING(    0x08, "40" )
601	601	PORT_DIPSETTING(    0x04, "50" )
602	602	PORT_DIPSETTING(    0x00, "100" )
603		PORT_DIPNAME( 0x60, 0x60, "Key Out Rate" )
	603	PORT_DIPNAME( 0x60, 0x60, "Key Out Rate" )      PORT_DIPLOCATION("DSW4:6,7")
604	604	PORT_DIPSETTING(    0x60, "1" )
605	605	PORT_DIPSETTING(    0x40, "10" )
606	606	PORT_DIPSETTING(    0x20, "50" )
607	607	PORT_DIPSETTING(    0x00, "100" )
608		PORT_DIPNAME( 0x80, 0x80, "Play Line" )
	608	PORT_DIPNAME( 0x80, 0x80, "Play Line" )         PORT_DIPLOCATION("DSW4:8")
609	609	PORT_DIPSETTING(    0x80, "8" )
610	610	PORT_DIPSETTING(    0x00, "16" )
611	611
	612	// These are from the manual for v201us - DSW1-DSW4 match but DSW5 doesn't seem to match or actuallly do anything
612	613	PORT_START("DSW5")
613		PORT_DIPUNKNOWN( 0x01, 0x01 )
614		PORT_DIPUNKNOWN( 0x02, 0x02 )
615		PORT_DIPUNKNOWN( 0x04, 0x04 )
616		PORT_DIPUNKNOWN( 0x08, 0x08 )
617		PORT_DIPUNKNOWN( 0x10, 0x10 )
618		PORT_DIPUNKNOWN( 0x20, 0x20 )
619		PORT_DIPUNKNOWN( 0x40, 0x40 )
620		PORT_DIPUNKNOWN( 0x80, 0x80 )
	614	PORT_DIPNAME( 0x03, 0x00, "Maximum Play" )      PORT_DIPLOCATION("DSW5:1,2")
	615	PORT_DIPSETTING(    0x00, "64" )
	616	PORT_DIPSETTING(    0x01, "32" )
	617	PORT_DIPSETTING(    0x02, "16" )
	618	PORT_DIPSETTING(    0x03, "8" )
	619	PORT_DIPNAME( 0x04, 0x04, "Skill Stop" )      PORT_DIPLOCATION("DSW5:3")
	620	PORT_DIPSETTING(    0x04, "On" )
	621	PORT_DIPSETTING(    0x00, "Off" )
	622	PORT_DIPNAME( 0x08, 0x00, "Hands Count" )      PORT_DIPLOCATION("DSW5:4")
	623	PORT_DIPSETTING(    0x08, "No" )
	624	PORT_DIPSETTING(    0x00, "Yes" )
	625	PORT_DIPNAME( 0x30, 0x00, "Hands Coin Rate" )   PORT_DIPLOCATION("DSW5:5,6")
	626	PORT_DIPSETTING(    0x00, "25" )
	627	PORT_DIPSETTING(    0x20, "10" )
	628	PORT_DIPSETTING(    0x10, "5" )
	629	PORT_DIPSETTING(    0x30, "1" )
	630	PORT_DIPNAME( 0x40, 0x40, "Hands Coin Value" )   PORT_DIPLOCATION("DSW5:7")
	631	PORT_DIPSETTING(    0x00, "40" )
	632	PORT_DIPSETTING(    0x40, "20" )
	633	PORT_DIPNAME( 0x80, 0x80, "Unused" )         PORT_DIPLOCATION("DSW5:8")
	634	PORT_DIPSETTING(    0x00, "On" )
	635	PORT_DIPSETTING(    0x80, "Off" )
621	636
622	637	PORT_START("SERVICE")
623	638	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
r242413	r242414
634	649	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN       )
635	650	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2         )
636	651	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_KEYIN  )
637		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Key Down")    // pays out
	652	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Key Down")
638	653	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
639	654	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
640	655	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
r242413	r242414
650	665	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
651	666
652	667	PORT_START("BUTTONS2")
653		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1      ) PORT_NAME("Start / H_Dup")
	668	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1      ) PORT_NAME("Start / Half D-Up Bet")
654	669	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_LOW  ) PORT_NAME("Small")
655		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1     ) PORT_NAME("Left Bet / D_Dup")
	670	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1     ) PORT_NAME("Left Bet / 2X D-Up Bet")
656	671	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE )
657		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2     ) PORT_NAME("Right Bet / Dup")
	672	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2     ) PORT_NAME("Right Bet / D-Up Bet")
658	673	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_HIGH ) PORT_NAME("Big")
659	674	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
660	675	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )

trunk/src/mame/drivers/lindbergh.c

r242413	r242414
353	353	MCFG_I82875P_HOST_ADD(            ":pci:00.0",                        0x103382c0, ":maincpu", 512*1024*1024)
354	354	MCFG_I82875P_AGP_ADD(             ":pci:01.0")
355	355	MCFG_GEFORCE_7600GS_ADD(          ":pci:01.0:00.0",                   0x10de02e1)
	356	MCFG_I82875P_OVERFLOW_ADD(        ":pci:06.0",                        0x103382c0)
356	357	MCFG_PCI_BRIDGE_ADD(              ":pci:1c.0",      0x808625ae, 0x02)
357	358	MCFG_I82541PI_ADD(                ":pci:1c.0:00.0",                   0x103382c0)
358	359	MCFG_USB_UHCI_ADD(                ":pci:1d.0",      0x808625a9, 0x02, 0x103382c0)

trunk/src/mame/drivers/mjkjidai.c

r242413	r242414
282	282	void mjkjidai_state::machine_start()
283	283	{
284	284	membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x8000, 0x4000);
	285
	286	save_item(NAME(m_adpcm_pos));
	287	save_item(NAME(m_adpcm_end));
	288	save_item(NAME(m_keyb));
	289	save_item(NAME(m_nmi_enable));
	290	save_item(NAME(m_display_enable));
285	291	}
286	292
287	293	void mjkjidai_state::machine_reset()
r242413	r242414
361	367	ROM_END
362	368
363	369
364		GAME( 1986, mjkjidai, 0, mjkjidai, mjkjidai, driver_device, 0, ROT0, "Sanritsu",  "Mahjong Kyou Jidai (Japan)", GAME_IMPERFECT_GRAPHICS )
	370	GAME( 1986, mjkjidai, 0, mjkjidai, mjkjidai, driver_device, 0, ROT0, "Sanritsu",  "Mahjong Kyou Jidai (Japan)", GAME_IMPERFECT_GRAPHICS | GAME_SUPPORTS_SAVE )

trunk/src/mame/drivers/naomi.c

r242413	r242414
263	263	Maze of the Kings The (prototype)               no cart  *       21 (64Mb)   present  315-6206  FRI           * flash-PCB, not dumped but known to exist
264	264	Samba de Amigo (prototype)                      no cart  *       21 (64Mb)   present  315-6206  317-0270-COM  * instead of EPROM have tiny PCB with 2 flashroms on it
265	265	Soul Surfer (Rev A)                           840-0095C  23838C  21 (64Mb)   present  315-6206  not present
266		Star Horse (server)                           840-0055C  23626   17 (64Mb)   present  315-6206  not present
	266	Star Horse (server)                           840-0055C  23626   17 (64Mb)   present  315-6206  not present   requires 837-13785 ARCNET&IO BD
267	267	The King of Route 66 (Rev A)                  840-0087C  23819A  20 (64Mb)   present  315-6206  not present   content is the same as regular 171-8132A cart
268	268	Virtua NBA (prototype)                          no cart  *       21 (64Mb)   present  315-6206  317-0271-COM  * instead of EPROM have tiny PCB with 2 flashroms on it
269	269	Virtua Tennis / Power Smash (prototype)         no cart  *       21 (64Mb)   present  315-6206  317-0263-COM  * flash-PCB, title screen have label "SOFT R&D Dept.#3", not dumped but known to exist
r242413	r242414
517	517	MushiKing - The King Of Beetle 2K5 1ST          840-0158C  24286    7 (128Mb)  315-6319A  315-6213  not present   requires 610-0669 barcode reader
518	518	Oinori-daimyoujin Matsuri                       840-0126B  24053    5 (128Mb)  315-6319A  315-6213  not present   requires 837-14274 "G2 EXPANSION BD" (similar to hopper 837-14381 but with ARC NET chip)
519	519	Samba de Amigo Ver. 2000                        840-0047C  23600   11 (128Mb)  315-6319A  315-6213  317-0295-COM
520		Star Horse (big screens)                        840-0054C  23625    4 (128Mb)  315-6319   315-6213  not present
521		Star Horse (client)                             840-0056C  23627    6 (128Mb)* 315-6319   315-6213  not present   * +1 (64Mb)
522		Star Horse Progress (Rev A)                     840-0123C  24122A   7 (128Mb)  315-6319A  315-6213  not present   requires an additional middle board n. 837-13785
	520	Star Horse (big screens)                        840-0054C  23625    4 (128Mb)  315-6319   315-6213  not present   requires 837-13785 ARCNET&IO BD
	521	Star Horse (satellite)                          840-0056C  23627    6 (128Mb)* 315-6319   315-6213  not present   * +1 (64Mb), requires 837-13785 ARCNET&IO BD
	522	Star Horse Progress (satellite) (Rev A)         840-0123C  24122A   7 (128Mb)  315-6319A  315-6213  not present   requires 837-13785 ARCNET&IO BD
523	523	The King of Route 66 (Rev A)                    840-0087C  23819A  10 (128Mb)  315-6319A  315-6213  not present
524	524	Virtua Striker 3 (Rev B)                        840-0061C  23663B  11 (128Mb)  315-6319A  315-6213  317-0310-COM
525	525	Virtua Striker 3 (Rev C)                        840-0061C  23663C  11 (128Mb)  315-6319A  315-6213  317-0310-COM
r242413	r242414
579	579	Poka Suka Ghost                                     840-0170C  not present  5 (512Mb)   present  317-0461-COM  present  requires 837-14672 sensor board (SH4 based)
580	580	Radirgy Noa                                         841-0062C  not present  4 (512Mb)   present  317-5138-JPN  present  IC2# is labeled "VER.2" - IC4# is marked "8A"
581	581	Rythm Tengoku                                       841-0177C  not present  4 (512Mb)   present  317-0503-JPN  present  IC2# is labeled "VER.2" - IC4# is marked "8A"
	582	Star Horse Progress Returns (satellite)             840-0186C  not present  2 (512Mb)   present  not present   present  IC2# is labeled "VER.2", requires 837-13785 ARCNET&IO BD
582	583	Shooting Love 2007                                  841-0057C  not present  4 (512Mb)   present  317-5129-JPN  present  IC2# is labeled "VER.2"
583	584	Touch De Zunou (Rev A)                              840-0166C  not present  2 (512Mb)   present  317-0435-JPN  present  IC4# is marked "18", requires 837-14672 sensor board (SH4 based)
584	585
r242413	r242414
5845	5846	NAOMI_DEFAULT_EEPROM
5846	5847
5847	5848	ROM_REGION( 0x10000000, "rom_board", ROMREGION_ERASEFF)
5848		// real encrypted ROM dump
5849	5849	ROM_LOAD( "fpr-24423.ic8",  0x00000000, 0x4000000, CRC(c85513ce) SHA1(88490fe64c0866059492b0c1c714b50f3f270676) )
5850		// decrypted version of IC8
5851		ROM_LOAD( "fpr-24423.ic8d", 0x00000000, 0x4000000, CRC(209a991c) SHA1(d76228a215c50ff3085708182b8e47fd2ebc6a47) )
5852	5850	ROM_LOAD( "fpr-24424.ic9",  0x04000000, 0x4000000, CRC(7bba2402) SHA1(94d637969c58d5dfa3ee64bc3cfb9495dbb97511) )
5853	5851	ROM_LOAD( "fpr-24425.ic10", 0x08000000, 0x4000000, CRC(6223ebac) SHA1(64c0ec61c108acbb557e7d3837f578deba832cb6) )
5854	5852	ROM_LOAD( "fpr-24426.ic11", 0x0c000000, 0x4000000, CRC(c78b0981) SHA1(f889acf9065566e11ff985a3b6c4824e364d57ae) )
r242413	r242414
5859	5857	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x04))
5860	5858	ROM_END
5861	5859
	5860	// this is satellite unit of the main game, server/control and lagre screen units required and need to be dumped
	5861	ROM_START( starhrpr )
	5862	NAOMI_BIOS
	5863	NAOMI_DEFAULT_EEPROM
	5864
	5865	ROM_REGION( 0x8000000, "rom_board", ROMREGION_ERASEFF)
	5866	ROM_LOAD( "fpr-24489.ic8",  0x00000000, 0x4000000, CRC(156797a4) SHA1(b20da57726974c5d772885fe809c4bbf89012db6) )
	5867	ROM_LOAD( "fpr-24790.ic9",  0x04000000, 0x4000000, CRC(b6c40348) SHA1(37b5b334c24536e5b2062c233423f0e3d338e1f2) )
	5868
	5869	// PIC not populated
	5870	ROM_REGION( 0x800, "pic_readout", ROMREGION_ERASE00 )
	5871
	5872	ROM_REGION(0x4, "boardid", ROMREGION_ERASEVAL(0x02))
	5873	ROM_END
	5874
5862	5875	/*
5863	5876
5864	5877	SYSTEMID: NAOMI
r242413	r242414
6528	6541	ROM_LOAD( "sflash.bin",   0x000000, 0x000084, CRC(4929e940) SHA1(f8c4277ca0ae5e36b2eed033cc731b8fc4fccafc) )
6529	6542	ROM_END
6530	6543
	6544	// this is satellite unit of the main game, server/control and lagre screen units required and need to be dumped
6531	6545	ROM_START( starhrsp )
6532	6546	NAOMI_BIOS
6533	6547	NAOMI_DEFAULT_EEPROM
r242413	r242414
6903	6917	ROM_LOAD("317-5092-jpn.pic", 0x00, 0x4000, CRC(7ad7b541) SHA1(45c1e3da030add3bb07797ee7f22003224ae3f7f) )
6904	6918	ROM_END
6905	6919
	6920	ROM_START( ggxxrlo )
	6921	NAOMIGD_BIOS
	6922	NAOMI_DEFAULT_EEPROM
	6923
	6924	DISK_REGION( "gdrom" )
	6925	DISK_IMAGE_READONLY( "gdl-0019", 0, SHA1(1915534f366934110e7cd6641bb817f47000150f) )
	6926
	6927	ROM_REGION( 0x4000, "pic", ROMREGION_ERASEFF)
	6928	//PIC16C622A (317-5092-JPN)
	6929	//(sticker 253-5509-5092J)
	6930	ROM_LOAD("317-5092-jpn.pic", 0x00, 0x4000, CRC(7ad7b541) SHA1(45c1e3da030add3bb07797ee7f22003224ae3f7f) )
	6931	ROM_END
	6932
6906	6933	ROM_START( tetkiwam )
6907	6934	NAOMIGD_BIOS
6908	6935	NAOMI_DEFAULT_EEPROM
r242413	r242414
8951	8978	/* 0052 */ GAME( 2000, derbyo2k, naomi,    naomim2, naomi,   naomi_state, naomi,   ROT0, "Sega", "Derby Owners Club 2000 (Rev A)", GAME_FLAGS )
8952	8979	/* 0054 */ GAME( 2000, starhrse, naomi,    naomim2, naomi,   naomi_state, naomi,   ROT0, "Sega", "Star Horse (big screens)", GAME_FLAGS )
8953	8980	/* 0055 */ GAME( 2000, starhrct, naomi,    naomim2, naomi,   naomi_state, naomi,   ROT0, "Sega", "Star Horse (server)", GAME_FLAGS )
8954		/* 0056 */ GAME( 2000, starhrcl, naomi,    naomim2, naomi,   naomi_state, naomi,  ROT0, "Sega", "Star Horse (client)", GAME_FLAGS )
	8981	/* 0056 */ GAME( 2000, starhrcl, naomi,    naomim2, naomi,   naomi_state, naomi,  ROT270,"Sega", "Star Horse (satellite)", GAME_FLAGS )
8955	8982	/* 0064 */ GAME( 2001, wrungp,   naomi,    naomim2, naomi,   naomi_state, naomi,   ROT0, "Sega", "Wave Runner GP", GAME_FLAGS )
8956	8983	/* 0068 */ GAME( 2001, crakndj2, naomi,    naomim2, crackndj,naomi_state, naomi,   ROT0, "Sega", "Crackin' DJ Part 2", GAME_FLAGS )
8957	8984	/* 0073 */ GAME( 2001, inunoos,  naomi,    naomim2, naomi,   naomi_state, naomi,   ROT0, "Sega", "Inu No Osanpo / Dog Walking (Rev A)", GAME_FLAGS )
r242413	r242414
8960	8987	/* 0088 */ GAME( 2001, derbyocw, naomi,    naomim2, naomi,   naomi_state, naomi,   ROT0, "Sega", "Derby Owners Club World Edition (JPN, USA, EXP, KOR, AUS) (Rev D)", GAME_FLAGS )
8961	8988	/* 0088 */ GAME( 2001, drbyocwc, derbyocw, naomim2, naomi,   naomi_state, naomi,   ROT0, "Sega", "Derby Owners Club World Edition (JPN, USA, EXP, KOR, AUS) (Rev C)", GAME_FLAGS )
8962	8989	/* 0098 */ GAME( 2002, shootopl, naomi,    naomim1, naomi,   naomi_state, naomi,   ROT0, "Sega", "Shootout Pool", GAME_FLAGS )
8963		/* 0123 */ GAME( 2003, starhrsp, naomi,    naomim2, naomi,   naomi_state, naomi,  ROT0, "Sega", "Star Horse Progress (Rev A)", GAME_FLAGS )
	8990	/* 0123 */ GAME( 2003, starhrsp, naomi,    naomim2, naomi,   naomi_state, naomi,  ROT270,"Sega", "Star Horse Progress (satellite) (Rev A)", GAME_FLAGS )
8964	8991	/* 0126 */ GAME( 2003, oinori,   naomi,    naomim2, naomi,   naomi_state, naomi,   ROT0, "Sega", "Oinori-daimyoujin Matsuri", GAME_FLAGS )
8965	8992	/* 0128 */ GAME( 2003, shootpl,  naomi,    naomim1, naomi,   naomi_state, naomi,   ROT0, "Sega", "Shootout Pool The Medal / Shootout Pool Prize (Rev A)", GAME_FLAGS )
8966	8993	/* 0130 */ GAME( 2002, hopper,   naomi,    naomi,   naomi,   naomi_state, naomi,   ROT0, "Sega", "SWP Hopper Board", GAME_FLAGS )
r242413	r242414
8975	9002	/* 0170 */ GAME( 2007, pokasuka, manicpnc, naomim4, naomi,   naomi_state, naomi,   ROT0, "Sega", "Pokasuka Ghost", GAME_FLAGS )
8976	9003	/* 0175 */ GAME( 2007, asndynmt, naomi,    naomim4, naomi,   naomi_state, naomi,   ROT0, "Sega", "Asian Dynamite", GAME_FLAGS )
8977	9004	/* 0177 */ GAME( 2007, rhytngk,  naomi,    naomim4, naomi,   naomi_state, naomi,   ROT0, "Sega/Nintendo", "Rhythm Tengoku", GAME_FLAGS )
8978		// 01?? Star Horse Progress Returns
	9005	/* 0186 */ GAME( 2009, starhrpr, naomi,    naomim4, naomi,   naomi_state, naomi,  ROT270,"Sega", "Star Horse Progress Returns (satellite)", GAME_FLAGS )
8979	9006	// 00xx Mayjinsen (Formation Battle in May) - prototype, never released
8980	9007
8981	9008	/* Cartridge prototypes of games released on GD-ROM */
r242413	r242414
9145	9172	// 0016  Yonin Uchi Mahjong MJ
9146	9173	/* 0017  */ GAME( 2002, quizqgd, naomigd, naomigd, naomi, naomi_state,  naomigd,  ROT270,"Amedio (Taito license)","Quiz Keitai Q mode (GDL-0017)", GAME_FLAGS )
9147	9174	/* 0018  */ GAME( 2002, azumanga,naomigd, naomigd, naomi, naomi_state,  naomigd,  ROT0,"MOSS (Taito license)","Azumanga Daioh Puzzle Bobble (GDL-0018)", GAME_FLAGS )
9148		// 0019  Guilty Gear XX #Reload
	9175	/* 0019  */ GAME( 2003, ggxxrlo, ggxxrl,  naomigd, naomi, naomi_state,  ggxxrl,   ROT0,"Arc System Works","Guilty Gear XX #Reload (GDL-0019)", GAME_FLAGS )
9149	9176	/* 0019A */ GAME( 2003, ggxxrl,  naomigd, naomigd, naomi, naomi_state,  ggxxrl,   ROT0,"Arc System Works","Guilty Gear XX #Reload (Rev A) (GDL-0019A)", GAME_FLAGS )
9150	9177	/* 0020  */ GAME( 2004, tetkiwam,naomigd, naomigd, naomi, naomi_state,  naomigd,  ROT0,   "Success",      "Tetris Kiwamemichi (GDL-0020)", GAME_FLAGS )
9151	9178	/* 0021  */ GAME( 2003, shikgam2,naomigd, naomigd, naomi, naomi_state,  naomigd,  ROT270, "Alfa System",  "Shikigami No Shiro II / The Castle of Shikigami II (GDL-0021)", GAME_FLAGS )

trunk/src/mame/drivers/peplus.c

r242413	r242414
1834	1834	ROM_LOAD( "cap740.u50", 0x0000, 0x0100, CRC(6fe619c4) SHA1(49e43dafd010ce0fe9b2a63b96a4ddedcb933c6d) ) /* BPROM type DM74LS471 (compatible with N82S135N) verified */
1835	1835	ROM_END
1836	1836
1837		ROM_START( pepp0046b ) /* Normal board : 10's or Better (PP0043) */
	1837	ROM_START( pepp0046b ) /* Normal board : 10's or Better (PP0046) */
1838	1838	/*
1839	1839	PayTable  10s+  2PR  3K   STR  FL  FH  4K  SF  RF  (Bonus)
1840	1840	----------------------------------------------------------
r242413	r242414
4721	4721	ROM_LOAD( "cap656.u50", 0x0000, 0x0100, CRC(038cabc6) SHA1(c6514b4f9dbed6ab2631f563f7e00648661ebdbb) )
4722	4722	ROM_END
4723	4723
	4724	ROM_START( pemg0183 ) /* Normal board : Montana Choice Multi-Game MG0183 - Requires a Printer (not yet supported) */
	4725	/*
	4726	MG0183 has 4 poker games:
	4727	Jacks or Better
	4728	Joker Wild Poker
	4729	Four of a Kind Bonus Poker
	4730	Deuces Wild Poker
	4731
	4732	Came out of an IGT machine with belly glass calling it Montana Choice
	4733	*/
	4734	ROM_REGION( 0x10000, "maincpu", 0 )
	4735	ROM_LOAD( "mg0183_756-782.u68",   0x00000, 0x10000, CRC(b89bcf75) SHA1(f436eb604c81ba6f08e1d11029ce8fff4f50dc3e) ) /* Stalls with "PRINTER ERROR" */
	4736
	4737	ROM_REGION( 0x020000, "gfx1", 0 )
	4738	ROM_LOAD( "mro-cg1209.u72",   0x00000, 0x8000, CRC(39b0cc43) SHA1(0a95a7122e64fed7355e762ff2eda2a7246d4693) )
	4739	ROM_LOAD( "mgo-cg1209.u73",   0x08000, 0x8000, CRC(5285ffab) SHA1(e959bf2fec46ee62d7a625eb64f74635fd697643) )
	4740	ROM_LOAD( "mbo-cg1209.u74",   0x10000, 0x8000, CRC(4604ac16) SHA1(b3a7c6c807eb2be7f451d2fcbb6455a66c155a46) )
	4741	ROM_LOAD( "mxo-cg1209.u75",   0x18000, 0x8000, CRC(da344256) SHA1(1320c4a8b48a9e61a4607e0a9d08083fde2bd334) )
	4742
	4743	ROM_REGION( 0x100, "proms", 0 )
	4744	ROM_LOAD( "cap1144.u50", 0x0000, 0x0100, NO_DUMP )
	4745	ROM_LOAD( "cap1426.u50", 0x0000, 0x0100, CRC(6c7c3462) SHA1(b5481b548f4db460d27a4bfebb08188f36ca0c11) )
	4746
	4747	ROM_REGION( 0x1000, "printer", 0 ) /* ROM from the printer driver PCB */
	4748	ROM_LOAD( "lp_86.u9", 0x0000, 0x1000, CRC(cdd93c06) SHA1(96f0a6e231f355a0b82bb0e1e698edbd66ff3020) ) /* 2732 EPROM */
	4749	ROM_END
	4750
4724	4751	ROM_START( pemg0252 ) /* Normal board : Player's Choice Multi-Game MG0252 - Requires a Printer (not yet supported) */
4725	4752	/*
4726	4753	MG0252 has 4 poker games:
r242413	r242414
8033	8060	ROM_LOAD( "capx1321.u43", 0x0000, 0x0200, CRC(4b57569f) SHA1(fa29c0f627e7ce79951ec6dadec114864144f37d) )
8034	8061	ROM_END
8035	8062
	8063	ROM_START( pex2478p ) /* Superboard : Joker Poker - French (X002478P+XP000154) */
	8064	/*
	8065	w/J     w/oJ
	8066	PayTable   Ks+  2P  3K  STR  FL  FH  4K  SF  RF  5K  RF  (Bonus)
	8067	----------------------------------------------------------------
	8068	PI104A     1    1   2   3    5   7  15  50 100 300 400    800
	8069	% Range: 92.0-94.0%  Optimum: 96.0%  Hit Frequency: 44.5%
	8070	Programs Available: X002317P, X002478P
	8071	*/
	8072	ROM_REGION( 0x10000, "maincpu", 0 )
	8073	ROM_LOAD( "xp000154.u67",   0x00000, 0x10000, CRC(f5f9ba4d) SHA1(d59f477c0a22065a62ffbe44d802b19078fefbb8) )
	8074
	8075	ROM_REGION( 0x10000, "user1", 0 )
	8076	ROM_LOAD( "x002478p.u66",   0x00000, 0x10000, CRC(c667f425) SHA1(a47432af0915ac5369c0c2470bb8086f7f021058) ) /* Joker Poker - French */
	8077
	8078	ROM_REGION( 0x020000, "gfx1", 0 )
	8079	ROM_LOAD( "mro-cg2452.u77",  0x00000, 0x8000, CRC(188cdf9e) SHA1(b575ee8c140589ed7d3c5c6cd21c2ea4806136c5) )
	8080	ROM_LOAD( "mgo-cg2452.u78",  0x08000, 0x8000, CRC(eaae3a1c) SHA1(b46822c59f2176306fc7864f9c560e86d4237747) )
	8081	ROM_LOAD( "mbo-cg2452.u79",  0x10000, 0x8000, CRC(38c94e65) SHA1(2bba913ed305062c232e58349c2ffff8b2ded563) )
	8082	ROM_LOAD( "mxo-cg2452.u80",  0x18000, 0x8000, CRC(22080393) SHA1(885eecbd4a8255f8ffa01d3ad0f80ad6631c7c9a) )
	8083
	8084	ROM_REGION( 0x200, "proms", 0 )
	8085	ROM_LOAD( "capx2307.u43", 0x0000, 0x0200, CRC(58d81338) SHA1(f0044ebbd0128d6fb74d850528ef02730c180f00) )
	8086	ROM_END
	8087
	8088	ROM_START( pex2479p ) /* Superboard : Joker Poker - French (X002479P+XP000154) */
	8089	/*
	8090	w/J     w/oJ
	8091	PayTable   Ks+  2P  3K  STR  FL  FH  4K  SF  RF  5K  RF  (Bonus)
	8092	----------------------------------------------------------------
	8093	PI105A     1    1   2   3    4   5  20  40 100 200 400    800
	8094	% Range: 91.0-93.0%  Optimum: 95.0%  Hit Frequency: 44.5%
	8095	Programs Available: X002318P, X002479P
	8096	*/
	8097	ROM_REGION( 0x10000, "maincpu", 0 )
	8098	ROM_LOAD( "xp000154.u67",   0x00000, 0x10000, CRC(f5f9ba4d) SHA1(d59f477c0a22065a62ffbe44d802b19078fefbb8) )
	8099
	8100	ROM_REGION( 0x10000, "user1", 0 )
	8101	ROM_LOAD( "x002479p.u66",   0x00000, 0x10000, CRC(e95b3550) SHA1(8bd702fb81cef0b9782a9e6b404917fc302ae1ef) ) /* Joker Poker - French */
	8102
	8103	ROM_REGION( 0x020000, "gfx1", 0 )
	8104	ROM_LOAD( "mro-cg2452.u77",  0x00000, 0x8000, CRC(188cdf9e) SHA1(b575ee8c140589ed7d3c5c6cd21c2ea4806136c5) )
	8105	ROM_LOAD( "mgo-cg2452.u78",  0x08000, 0x8000, CRC(eaae3a1c) SHA1(b46822c59f2176306fc7864f9c560e86d4237747) )
	8106	ROM_LOAD( "mbo-cg2452.u79",  0x10000, 0x8000, CRC(38c94e65) SHA1(2bba913ed305062c232e58349c2ffff8b2ded563) )
	8107	ROM_LOAD( "mxo-cg2452.u80",  0x18000, 0x8000, CRC(22080393) SHA1(885eecbd4a8255f8ffa01d3ad0f80ad6631c7c9a) )
	8108
	8109	ROM_REGION( 0x200, "proms", 0 )
	8110	ROM_LOAD( "capx2307.u43", 0x0000, 0x0200, CRC(58d81338) SHA1(f0044ebbd0128d6fb74d850528ef02730c180f00) )
	8111	ROM_END
	8112
	8113	ROM_START( pex2480p ) /* Superboard : Joker Poker (Aces or Better) - French (X002480P+XP000154) */
	8114	/*
	8115	w/J     w/oJ
	8116	PayTable   As   2P  3K  STR  FL  FH  4K  SF  RF  5K  RF  (Bonus)
	8117	----------------------------------------------------------------
	8118	PI106B     1    1   2   3    5   6  20  50 100 200 500   1000
	8119	% Range: 89.5-91.5%  Optimum: 93.5%  Hit Frequency: 39.2%
	8120	Programs Available: X002320P, X002480P
	8121	*/
	8122	ROM_REGION( 0x10000, "maincpu", 0 )
	8123	ROM_LOAD( "xp000154.u67",   0x00000, 0x10000, CRC(f5f9ba4d) SHA1(d59f477c0a22065a62ffbe44d802b19078fefbb8) )
	8124
	8125	ROM_REGION( 0x10000, "user1", 0 )
	8126	ROM_LOAD( "x002480p.u66",   0x00000, 0x10000, CRC(a1ec5a5f) SHA1(a272f9f3f11756a78247fc5aa58f09ea83604fc0) ) /* Joker Poker - French */
	8127
	8128	ROM_REGION( 0x020000, "gfx1", 0 )
	8129	ROM_LOAD( "mro-cg2452.u77",  0x00000, 0x8000, CRC(188cdf9e) SHA1(b575ee8c140589ed7d3c5c6cd21c2ea4806136c5) )
	8130	ROM_LOAD( "mgo-cg2452.u78",  0x08000, 0x8000, CRC(eaae3a1c) SHA1(b46822c59f2176306fc7864f9c560e86d4237747) )
	8131	ROM_LOAD( "mbo-cg2452.u79",  0x10000, 0x8000, CRC(38c94e65) SHA1(2bba913ed305062c232e58349c2ffff8b2ded563) )
	8132	ROM_LOAD( "mxo-cg2452.u80",  0x18000, 0x8000, CRC(22080393) SHA1(885eecbd4a8255f8ffa01d3ad0f80ad6631c7c9a) )
	8133
	8134	ROM_REGION( 0x200, "proms", 0 )
	8135	ROM_LOAD( "capx2307.u43", 0x0000, 0x0200, CRC(58d81338) SHA1(f0044ebbd0128d6fb74d850528ef02730c180f00) )
	8136	ROM_END
	8137
	8138	ROM_START( pex2485p ) /* Superboard : Standard Draw Poker - French (X002480P+XP000154) */
	8139	/*
	8140	PayTable   Js+  2PR  3K   STR  FL  FH  4K  SF  RF  (Bonus)
	8141	----------------------------------------------------------
	8142	PI103B     1    2    3    4    5   7  22  50 300   1000
	8143	% Range: 90.4-92.4%  Optimum: 94.4%  Hit Frequency: 45.5%
	8144	Programs Available: X002485P
	8145	*/
	8146	ROM_REGION( 0x10000, "maincpu", 0 )
	8147	ROM_LOAD( "xp000154.u67",   0x00000, 0x10000, CRC(f5f9ba4d) SHA1(d59f477c0a22065a62ffbe44d802b19078fefbb8) )
	8148
	8149	ROM_REGION( 0x10000, "user1", 0 )
	8150	ROM_LOAD( "x002485p.u66",   0x00000, 0x10000, CRC(2ed40148) SHA1(f3c211955ef159da8ab14cfecbdfa2deaa3110ae) ) /* Standard Draw Poker - French */
	8151
	8152	ROM_REGION( 0x020000, "gfx1", 0 )
	8153	ROM_LOAD( "mro-cg2452.u77",  0x00000, 0x8000, CRC(188cdf9e) SHA1(b575ee8c140589ed7d3c5c6cd21c2ea4806136c5) )
	8154	ROM_LOAD( "mgo-cg2452.u78",  0x08000, 0x8000, CRC(eaae3a1c) SHA1(b46822c59f2176306fc7864f9c560e86d4237747) )
	8155	ROM_LOAD( "mbo-cg2452.u79",  0x10000, 0x8000, CRC(38c94e65) SHA1(2bba913ed305062c232e58349c2ffff8b2ded563) )
	8156	ROM_LOAD( "mxo-cg2452.u80",  0x18000, 0x8000, CRC(22080393) SHA1(885eecbd4a8255f8ffa01d3ad0f80ad6631c7c9a) )
	8157
	8158	ROM_REGION( 0x200, "proms", 0 )
	8159	ROM_LOAD( "capx2307.u43", 0x0000, 0x0200, CRC(58d81338) SHA1(f0044ebbd0128d6fb74d850528ef02730c180f00) )
	8160	ROM_END
	8161
8036	8162	ROM_START( pekoc766 ) /* Superboard : Standard Draw Poker (PP0766) English / Spanish - Key On Credit */
8037	8163	/*
8038	8164	PayTable   Js+  2PR  3K   STR  FL  FH  4K  SF  RF  (Bonus)
r242413	r242414
9049	9175	GAMEL(1987, peip0120,  peip0031, peplus,  peplus_poker, peplus_state, nonplus,  ROT0,  "IGT - International Game Technology", "Player's Edge Plus (IP0120) Standard Draw Poker - French",  0, layout_pe_poker )
9050	9176
9051	9177	/* Normal board : Multi-Game - Player's Choice - Some sets require a printer (not yet supported) */
	9178	GAMEL(1994, pemg0183,  0,        peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Montana Choice (MG0183) Multi-Game",                        GAME_NOT_WORKING, layout_pe_poker) /* Needs printer support */
9052	9179	GAMEL(1994, pemg0252,  0,        peplus,  peplus_poker, peplus_state, peplus,   ROT0,  "IGT - International Game Technology", "Player's Choice (MG0252) Multi-Game",                       GAME_NOT_WORKING, layout_pe_poker) /* Needs printer support */
9053	9180
9054	9181	/* Normal board : Blackjack */
r242413	r242414
9196	9323	GAMEL(1995, pex2421p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002421P+XP000064) Deuces Wild Bonus Poker - French", 0, layout_pe_poker )
9197	9324	GAMEL(1995, pex2440p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002440P+XP000053) Deuces Wild Poker",   0, layout_pe_poker )
9198	9325	GAMEL(1995, pex2461p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002461P+XP000055) Joker Poker (Two Pair or Better)", 0, layout_pe_poker )
	9326	GAMEL(1995, pex2478p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002478P+XP000154) Joker Poker - French", 0, layout_pe_poker )
	9327	GAMEL(1995, pex2479p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002479P+XP000154) Joker Poker - French", 0, layout_pe_poker )
	9328	GAMEL(1995, pex2480p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002480P+XP000154) Joker Poker (Aces or Better) - French", 0, layout_pe_poker )
	9329	GAMEL(1995, pex2485p,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (X002485P+XP000154) Standard Draw Poker - French", 0, layout_pe_poker )
9199	9330
9200	9331	/* Superboard : Poker (Key On Credit) */
9201	9332	GAMEL(1995, pekoc766,  0,         peplus,  peplus_poker, peplus_state, peplussb, ROT0,  "IGT - International Game Technology", "Player's Edge Plus (PP0766 A5W-A6F) Standard Draw Poker",  0, layout_pe_poker )

trunk/src/mame/drivers/viper.c

r242413	r242414
16	16	G?A30    2002    Tsurugi
17	17	GMA41    2001    Thrill Drive 2
18	18	G?A45    2001    Boxing Mania
19		G?B11    2001    Police 911 2 (USA) / Police 24/7 2 (World) / Keisatsukan Shinjuku 24ji 2 (Japan)
	19	G*B11    2001    Police 911 2 (USA) / Police 24/7 2 (World) / Keisatsukan Shinjuku 24ji 2 (Japan)
20	20	G?B33    2001    Mocap Golf
21	21	G?B41    2001    Jurassic Park 3
22	22	G?B4x    2002    Xtrial Racing
r242413	r242414
79	79	ADC0838 - National Semiconductor ADC0838 Serial I/O 8-Bit A/D Converters with Multiplexer Options (SOIC20 @ U13)
80	80	DS2430 - Dallas DS2430 256-bits 1-Wire EEPROM. Has 256 bits x8 EEPROM (32 bytes), 64 bits x8 (8 bytes)
81	81	one-time programmable application register and unique factory-lasered and tested 64-bit
82		registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) (TO-92 @ U37)
83		It appears the DS2430 is not protected from reading but the unique silicon serial number isn't
84		included in the 40 byte dump.
	82	registration number (8-bit family code + 48-bit serial number + 8-bit CRC) (TO-92 @ U37)
	83	The OTP application register on the common DS2430 and the Police 911 2 DS2430 are not programmed
	84	(application register reads all 0xFF and the status register reads back 0xFF), so it's probably safe
	85	to assume they're not used on any of them.
	86	It appears the DS2430 is not protected from reading and the unique silicon serial number is
	87	included in the 40 byte dump. This serial number is used as a check to verify the NVRAM and DS2430.
	88	In the Police 911 2 NVRAM dump the serial number of the DS2430 is located at 0x002A and 0x1026
	89	If the serial number in the NVRAM and DS2430 match then they are paired and the game accepts the NVRAM.
	90	If they don't match the game requires an external DS2430 (i.e. dongle) and flags the NVRAM as 'BAD'
	91	The serial number is not present in the CF card (2 different Police 911 2 cards of the same version
	92	were dumped and matched).
	93	When the lasered ROM is read from the DS2430, it comes out from LSB to MSB (family code, LSB of
	94	S/N->MSB of S/N, CRC)
	95	For Police 911 2 that is 0x14 0xB2 0xB7 0x4A 0x00 0x00 0x00 0x83
	96	Family code=0x14
	97	S/N=0x0000004AB7B2
	98	CRC=0x83
	99	In a DS2430 dump, the first 32 bytes is the EEPROM and the lasered ROM is 8 bytes and starts at 0x20h
	100	For Police 911 2 that is....
	101	00000000h CB 9B 56 EC A0 4C 87 53 51 46 28 E7 00 00 00 74
	102	00000010h 30 A9 C7 76 B9 85 A3 43 87 53 50 42 1A E7 FA CF
	103	00000020h 14 B2 B7 4A 00 00 00 83
	104	It may be possible to hand craft a DS2430 for a dongle-protected version of a game simply by using
	105	one of the existing DS2430 dumps and adjusting the serial number found in a dump of the NVRAM to pair them
	106	or adjusting the serial number in the NVRAM to match the serial number found in one of the dumped DS2430s.
	107	This Police 911 2 board was upgraded from Police 911 by plugging in the dongle and changing the CF card.
	108	The NVRAM had previously died and the board was dead. Normally for a Viper game that is fatal. Using
	109	the NVRAM from Police 911 allowed it to boot and then the NVRAM upgraded itself with some additional
	110	data (the original data remained untouched). This means the dongle does more than just protect the game.
	111	Another interesting fact about this upgrade is it has been discovered that the PCB can write to the
	112	external DS2430 in the dongle. This has been proven because the serial number of the DS2430 soldered
	113	on the PCB is present in the EEPROM area of the Police 911 2 DS2430.
	114	Here is a dump of the DS2430 from Police 911. Note the EEPROM area is empty and the serial number (from 0x20 onwards)
	115	is present in the above Police 911 2 DS2430 dump at locations 0x11, 0x10 and 0x0F
	116	00000000h FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
	117	00000010h FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
	118	00000020h 14 A9 30 74 00 00 00 E7
	119	This proves that the EEPROM area in the DS2430 is unused by an unprotected game and in fact the on-board
	120	DS2430 is completely unused by an unprotected game. That is why any unprotected game will work on any
	121	Viper PCB regardless of the on-board DS2430 serial number.
	122	The existing DS2430 'common' dump used in the unprotected games was actually from a (dongle-protected)
	123	Mahjong Fight Club PCB but that PCB was used to test and run all of the unprotected Viper games.
85	124	M48T58Y - ST Microelectronics M48T58Y Timekeeper RAM (DIP28 @ U39). When this dies (after 10 year lifespan)
86	125	the game will complain with error RTC BAD then reset. The data inside the RTC can not be hand created
87	126	(yet) so to revive the PCB the correct RTC data must be re-programmed to a new RTC and replaced
88	127	on the PCB.
	128	Regarding the RTC and protection-related checks....
	129	"RTC OK" checks 0x0000->0x0945 (i.e. I can clear the contents after 0x0945 and the game will still
	130	happily boot). The NVRAM contents are split into chunks, each of which are checksummed.  It is a 16-bit checksum,
	131	computed by summing two consecutive bytes as a 16-bit integer, where the final sum must add up to 0xFFFF (mod
	132	65536).  The last two bytes in the chunk are used to make the value 0xFFFF.  There doesn't appear to be a
	133	complete checksum over all the chunks (I can pick and choose chunks from various NVRAMs, as long as each chunk
	134	checksum checks out). The important chunks for booting are the first two.
	135	The first chunk goes from 0x0000-0x000F.  This seems to be a game/region identifier, and doesn't like its
	136	contents changed (I didn't try changing every byte, but several of the bytes would throw RTC errors, even with a
	137	fixed checksum).  I'd guess that the CF verifies this value, since it's different for every game (i.e. Mocap
	138	Boxing NVRAM would have a correct checksum, but shouldn't pass Police 911 checks).
	139	The second chunk goes from 0x0010-0x0079.  This seems to be a board identifier.  This has (optionally)
	140	several fields, each of which are 20 bytes long.  I'm unsure of the first 6 bytes, the following 6
	141	bytes are the DS2430A S/N, and the last 8 bytes are a game/region/dongle identifier.  If running
	142	without a dongle, only the first 20 byte field is present.  With a dongle, a second 20 byte field will
	143	be present.  Moving this second field into the place of the first field (and fixing the checksum)
	144	doesn't work, and the second field will be ignored if the first field is valid for the game (and in
	145	which case the dongle will be ignored).  For example, Police 911 will boot with a valid first field,
	146	with or without the second field, and with or without the dongle plugged in.  If you have both fields,
	147	and leave the dongle plugged in, you can switch between Police 911 and Police 911/2 by simply swapping
	148	CF cards.
89	149	29F002 - Fujitsu 29F002 256k x8 EEPROM stamped '941B01' (PLCC44 @ U25). Earlier revision stamped '941A01'
90	150	CN4/CN5 - RCA-type network connection jacks
91	151	CN7 - 80 pin connector (unused in all games?)
r242413	r242414
94	154	required and plugged in it overrides the DS2430 on the main board. Without the (on-board)
95	155	DS2430 the PCB will complain after the CF check with HARDWARE ERROR. If the DS2430 is not
96	156	correct for the game the error given is RTC BAD even if the RTC is correct. Most games don't require
97		a dongle and use the factory DS2430 on the main board.
	157	a dongle and accept any DS2430 on the main board.
98	158	CN12 - 4 pin connector (possibly stereo audio output?)
99	159	CN13 - Power connector for plug-in daughterboard
100	160	CN15/CN16 - Multi-pin IDC connectors for plug-in daughterboard (see detail below)
r242413	r242414
2131	2191	ROM_START(code1d) //*
2132	2192	VIPER_BIOS
2133	2193
2134		ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00)       /* DS2430 */
2135		ROM_LOAD("ds2430.u3", 0x00, 0x28, CRC(fada04dd) SHA1(49bd4e87d48f0404a091a79354bbc09cde739f5c))
	2194	ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00)       /* game-specific DS2430 on PCB */
	2195	ROM_LOAD("ds2430_code1d.u3", 0x00, 0x28, CRC(fada04dd) SHA1(49bd4e87d48f0404a091a79354bbc09cde739f5c))
2136	2196
2137	2197	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2138	2198	ROM_LOAD("nvram.u39", 0x00000, 0x2000, NO_DUMP )
r242413	r242414
2144	2204	ROM_START(code1db) //*
2145	2205	VIPER_BIOS
2146	2206
2147		ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00)       /* DS2430 */
2148		ROM_LOAD("ds2430.u3", 0x00, 0x28, CRC(fada04dd) SHA1(49bd4e87d48f0404a091a79354bbc09cde739f5c))
	2207	ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00)       /* game-specific DS2430 on PCB */
	2208	ROM_LOAD("ds2430_code1d.u3", 0x00, 0x28, CRC(fada04dd) SHA1(49bd4e87d48f0404a091a79354bbc09cde739f5c))
2149	2209
2150	2210	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2151	2211	ROM_LOAD("nvram.u39", 0x00000, 0x2000, NO_DUMP )
r242413	r242414
2296	2356	DISK_IMAGE( "a00jac02", 0, SHA1(d962d3a8ea84c380767d0fe336296911c289c224) )
2297	2357	ROM_END
2298	2358
2299		ROM_START(p9112) //*
	2359	ROM_START(p9112) /* dongle-protected version */
2300	2360	VIPER_BIOS
2301	2361
2302		ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00)       /* DS2430 */
2303		ROM_LOAD("ds2430.u3", 0x00, 0x28, CRC(f1511505) SHA1(ed7cd9b2763b3e377df9663943160f9871f65105))
	2362	ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00)       /* plug-in male DIN5 dongle containing a DS2430. The sticker on the dongle says 'GCB11-UA' */
	2363	ROM_LOAD("ds2430_p9112.u3", 0x00, 0x28, CRC(d745c6ee) SHA1(065C9D0DF1703B3BBB53A07F4923FDEE3B16F80E))
2304	2364
2305	2365	ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
2306		ROM_LOAD("nvram.u39", 0x000000, 0x2000, NO_DUMP )
	2366	ROM_LOAD("b11uad_nvram.u39", 0x000000, 0x2000, CRC(cda37033) SHA1(A94524824F21A0106928B4FE01D86F967BD5AA82))
2307	2367
2308	2368	DISK_REGION( "ata:0:hdd:image" )
2309	2369	DISK_IMAGE( "b11a02", 0, SHA1(57665664321b78c1913d01f0d2c0b8d3efd42e04) )
r242413	r242414
2564	2624	GAME(2001, p911kc,    p911,      viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Police 911 (ver KAC)", GAME_NOT_WORKING|GAME_NO_SOUND)
2565	2625	GAME(2001, p911e,     p911,      viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Police 24/7 (ver EAA)", GAME_NOT_WORKING|GAME_NO_SOUND)
2566	2626	GAME(2001, p911j,     p911,      viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Keisatsukan Shinjuku 24ji (ver JAC)", GAME_NOT_WORKING|GAME_NO_SOUND)
2567		GAME(2001, p9112,     kviper,    viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Police 911 2 (ver A)", GAME_NOT_WORKING|GAME_NO_SOUND)
	2627	GAME(2001, p9112,     kviper,    viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Police 911 2 (VER. UAA:B)", GAME_NOT_WORKING|GAME_NO_SOUND)
2568	2628	GAME(2003, popn9,     kviper,    viper, viper, viper_state, vipercf,  ROT0,  "Konami", "Pop'n Music 9 (ver JAB)", GAME_NOT_WORKING|GAME_NO_SOUND)
2569	2629	GAME(2001, sscopex,   kviper,    viper, viper, viper_state, vipercf,  ROT0,  "Konami", "Silent Scope EX (ver UAA)", GAME_NOT_WORKING|GAME_NO_SOUND)
2570	2630	GAME(2001, sogeki,    sscopex,   viper, viper, viper_state, vipercf,  ROT0,  "Konami", "Sogeki (ver JAA)", GAME_NOT_WORKING|GAME_NO_SOUND)

trunk/src/mame/drivers/wallc.c

r242413	r242414
58	58	public:
59	59	wallc_state(const machine_config &mconfig, device_type type, const char *tag)
60	60	: driver_device(mconfig, type, tag),
61		m_videoram(*this, "videoram"),
62	61	m_maincpu(*this, "maincpu"),
63		m_gfxdecode(*this, "gfxdecode") { }
	62	m_gfxdecode(*this, "gfxdecode"),
	63	m_videoram(*this, "videoram") { }
64	64
	65	required_device<cpu_device> m_maincpu;
	66	required_device<gfxdecode_device> m_gfxdecode;
	67
65	68	required_shared_ptr<UINT8> m_videoram;
	69
66	70	tilemap_t *m_bg_tilemap;
	71
67	72	DECLARE_WRITE8_MEMBER(wallc_videoram_w);
68	73	DECLARE_WRITE8_MEMBER(wallc_coin_counter_w);
69	74	DECLARE_DRIVER_INIT(wallc);
r242413	r242414
73	78	virtual void video_start();
74	79	DECLARE_PALETTE_INIT(wallc);
75	80	UINT32 screen_update_wallc(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
76		required_device<cpu_device> m_maincpu;
77		required_device<gfxdecode_device> m_gfxdecode;
78	81	};
79	82
80	83
r242413	r242414
143	146
144	147	WRITE8_MEMBER(wallc_state::wallc_videoram_w)
145	148	{
146		UINT8 *videoram = m_videoram;
147		videoram[offset] = data;
	149	m_videoram[offset] = data;
148	150	m_bg_tilemap->mark_tile_dirty(offset);
149	151	}
150	152
151	153	TILE_GET_INFO_MEMBER(wallc_state::get_bg_tile_info)
152	154	{
153		UINT8 *videoram = m_videoram;
154		SET_TILE_INFO_MEMBER(0, videoram[tile_index] + 0x100, 1, 0);
	155	SET_TILE_INFO_MEMBER(0, m_videoram[tile_index] + 0x100, 1, 0);
155	156	}
156	157
157	158	void wallc_state::video_start()
r242413	r242414
487	488
488	489	}
489	490
490		GAME( 1984, wallc,  0,      wallc,  wallc, wallc_state, wallc,  ROT0, "Midcoin", "Wall Crash (set 1)", 0 )
491		GAME( 1984, wallca, wallc,  wallc,  wallc, wallc_state, wallca, ROT0, "Midcoin", "Wall Crash (set 2)", 0 )
492		GAME( 1984, brkblast,wallc, wallc,  wallc, wallc_state, wallca, ROT0, "bootleg (Fadesa)", "Brick Blast (bootleg of Wall Crash)", 0 ) // Spanish bootleg board, Fadesa stickers / text on various components
	491	GAME( 1984, wallc,  0,      wallc,  wallc, wallc_state, wallc,  ROT0, "Midcoin", "Wall Crash (set 1)", GAME_SUPPORTS_SAVE )
	492	GAME( 1984, wallca, wallc,  wallc,  wallc, wallc_state, wallca, ROT0, "Midcoin", "Wall Crash (set 2)", GAME_SUPPORTS_SAVE )
	493	GAME( 1984, brkblast,wallc, wallc,  wallc, wallc_state, wallca, ROT0, "bootleg (Fadesa)", "Brick Blast (bootleg of Wall Crash)", GAME_SUPPORTS_SAVE ) // Spanish bootleg board, Fadesa stickers / text on various components
493	494
494		GAME( 1984, sidampkr,0,     wallc,  wallc, wallc_state, sidam,  ROT270, "Sidam", "unknown Sidam Poker", GAME_NOT_WORKING )
	495	GAME( 1984, sidampkr,0,     wallc,  wallc, wallc_state, sidam,  ROT270, "Sidam", "unknown Sidam Poker", GAME_NOT_WORKING | GAME_SUPPORTS_SAVE )

trunk/src/mame/includes/bwidow.h

r242413	r242414
16	16	int m_lastdata;
17	17	DECLARE_READ8_MEMBER(spacduel_IN3_r);
18	18	DECLARE_WRITE8_MEMBER(bwidow_misc_w);
	19	DECLARE_WRITE8_MEMBER(spacduel_coin_counter_w);
19	20	DECLARE_WRITE8_MEMBER(irq_ack_w);
20	21	DECLARE_CUSTOM_INPUT_MEMBER(clock_r);
21	22	required_device<cpu_device> m_maincpu;

trunk/src/mame/includes/stv.h

r242413	r242414
142	142	struct {
143	143	UINT8 status;
144	144	UINT8 data;
	145	UINT8 prev_data;
	146	UINT16 repeat_count;
145	147	}m_keyb;
146	148
147	149	/* Saturn specific*/

trunk/src/mame/layout/gts1.lay

r242413	r242414
29	29	</backdrop>
30	30
31	31	<!-- Top Row -->
32		<bezel name="digit8_0" element="digit8_">
	32	<bezel name="digit8_5" element="digit8_">
33	33	<bounds left="10" top="45" right="30" bottom="84" />
34	34	</bezel>
35		<bezel name="digit8_1" element="digit8_">
	35	<bezel name="digit8_4" element="digit8_">
36	36	<bounds left="34" top="45" right="54" bottom="84" />
37	37	</bezel>
38		<bezel name="digit8_2" element="digit8_">
	38	<bezel name="digit8_3" element="digit8_">
39	39	<bounds left="58" top="45" right="78" bottom="84" />
40	40	</bezel>
41		<bezel name="digit8_3" element="digit8_">
	41	<bezel name="digit8_2" element="digit8_">
42	42	<bounds left="87" top="45" right="107" bottom="84" />
43	43	</bezel>
44		<bezel name="digit8_4" element="digit8_">
	44	<bezel name="digit8_1" element="digit8_">
45	45	<bounds left="111" top="45" right="131" bottom="84" />
46	46	</bezel>
47		<bezel name="digit8_5" element="digit8_">
	47	<bezel name="digit8_0" element="digit8_">
48	48	<bounds left="135" top="45" right="155" bottom="84" />
49	49	</bezel>
50		<bezel name="digit8_8" element="digit8_">
	50	<bezel name="digit8_13" element="digit8_">
51	51	<bounds left="170" top="45" right="190" bottom="84" />
52	52	</bezel>
53		<bezel name="digit8_9" element="digit8_">
	53	<bezel name="digit8_12" element="digit8_">
54	54	<bounds left="194" top="45" right="214" bottom="84" />
55	55	</bezel>
56		<bezel name="digit8_10" element="digit8_">
	56	<bezel name="digit8_11" element="digit8_">
57	57	<bounds left="218" top="45" right="238" bottom="84" />
58	58	</bezel>
59		<bezel name="digit8_11" element="digit8_">
	59	<bezel name="digit8_10" element="digit8_">
60	60	<bounds left="247" top="45" right="267" bottom="84" />
61	61	</bezel>
62		<bezel name="digit8_12" element="digit8_">
	62	<bezel name="digit8_9" element="digit8_">
63	63	<bounds left="271" top="45" right="291" bottom="84" />
64	64	</bezel>
65		<bezel name="digit8_13" element="digit8_">
	65	<bezel name="digit8_8" element="digit8_">
66	66	<bounds left="295" top="45" right="315" bottom="84" />
67	67	</bezel>
68	68
69	69	<!-- Bottom Row -->
70		<bezel name="digit8_16" element="digit8_">
	70	<bezel name="digit8_21" element="digit8_">
71	71	<bounds left="10" top="100" right="30" bottom="139" />
72	72	</bezel>
73		<bezel name="digit8_17" element="digit8_">
	73	<bezel name="digit8_20" element="digit8_">
74	74	<bounds left="34" top="100" right="54" bottom="139" />
75	75	</bezel>
76		<bezel name="digit8_18" element="digit8_">
	76	<bezel name="digit8_19" element="digit8_">
77	77	<bounds left="58" top="100" right="78" bottom="139" />
78	78	</bezel>
79		<bezel name="digit8_19" element="digit8_">
	79	<bezel name="digit8_18" element="digit8_">
80	80	<bounds left="87" top="100" right="107" bottom="139" />
81	81	</bezel>
82		<bezel name="digit8_20" element="digit8_">
	82	<bezel name="digit8_17" element="digit8_">
83	83	<bounds left="111" top="100" right="131" bottom="139" />
84	84	</bezel>
85		<bezel name="digit8_21" element="digit8_">
	85	<bezel name="digit8_16" element="digit8_">
86	86	<bounds left="135" top="100" right="155" bottom="139" />
87	87	</bezel>
88	88	<!-- Digits 22 and 23 are not used -->
89		<bezel name="digit8_24" element="digit8_">
	89	<bezel name="digit8_29" element="digit8_">
90	90	<bounds left="170" top="100" right="190" bottom="139" />
91	91	</bezel>
92		<bezel name="digit8_25" element="digit8_">
	92	<bezel name="digit8_28" element="digit8_">
93	93	<bounds left="194" top="100" right="214" bottom="139" />
94	94	</bezel>
95		<bezel name="digit8_26" element="digit8_">
	95	<bezel name="digit8_27" element="digit8_">
96	96	<bounds left="218" top="100" right="238" bottom="139" />
97	97	</bezel>
98		<bezel name="digit8_27" element="digit8_">
	98	<bezel name="digit8_26" element="digit8_">
99	99	<bounds left="247" top="100" right="267" bottom="139" />
100	100	</bezel>
101		<bezel name="digit8_28" element="digit8_">
	101	<bezel name="digit8_25" element="digit8_">
102	102	<bounds left="271" top="100" right="291" bottom="139" />
103	103	</bezel>
104		<bezel name="digit8_29" element="digit8_">
	104	<bezel name="digit8_24" element="digit8_">
105	105	<bounds left="295" top="100" right="315" bottom="139" />
106	106	</bezel>
107	107	<!-- Digits 30 and 31 are not used -->
108	108
109	109	<!-- 4 digit display -->
110		<bezel name="digit7_6" element="digit7_">
	110	<bezel name="digit7_15" element="digit7_">
111	111	<bounds left="121" top="155" right="136" bottom="189" />
112	112	</bezel>
113		<bezel name="digit7_7" element="digit7_">
	113	<bezel name="digit7_14" element="digit7_">
114	114	<bounds left="140" top="155" right="155" bottom="189" />
115	115	</bezel>
116		<bezel name="digit7_14" element="digit7_">
	116	<bezel name="digit7_7" element="digit7_">
117	117	<bounds left="170" top="155" right="185" bottom="189" />
118	118	</bezel>
119		<bezel name="digit7_15" element="digit7_">
	119	<bezel name="digit7_6" element="digit7_">
120	120	<bounds left="189" top="155" right="204" bottom="189" />
121	121	</bezel>
122	122	</view>

trunk/src/mame/machine/atarigen.c

r242413	r242414
1195	1195
1196	1196	void atarigen_state::device_post_load()
1197	1197	{
1198		if (!m_slapstic_device)
	1198	if (m_slapstic_num != 0)
	1199	{
	1200	if (!m_slapstic_device)
1199	1201	fatalerror("Slapstic device is missing?\n");
1200
1201		slapstic_update_bank(m_slapstic_device->slapstic_bank());
	1202
	1203	slapstic_update_bank(m_slapstic_device->slapstic_bank());
	1204	}
1202	1205	}
1203	1206
1204	1207

trunk/src/mame/mame.lst

r242413	r242414
5343	5343	derbyo2k        // 2000.06 Derby Owners Club 2000 Ver.2 (Rev A)
5344	5344	starhrse        // 2000.?? Star Horse (big screens)
5345	5345	starhrct        // 2000.12 Star Horse (server)
5346		starhrcl        // 2000.?? Star Horse (client)
	5346	starhrcl        // 2000.11.28 Star Horse (satellite)
5347	5347	vonot           // 2000.06 Virtual-on Oratorio Tangram M.S.B.S. Ver.5.66 2000 Edition
5348	5348	ggx             // 2000.07 Guilty Gear X
5349	5349	slasho          // 2000.07 Slashout
r242413	r242414
5424	5424	shootpl         // 2003.?? Shootout Pool The Medal / Shootout Pool Prize (Rev A)
5425	5425	mtkob2          // 2003.02 MushiKing The King Of Beetle
5426	5426	// 2003.03 Sega Network Taisen Mahjong MJ
	5427	ggxxrlo         // 2003.02 Guilty Gear XX # Reload
5427	5428	ggxxrl          // 2003.03 Guilty Gear XX # Reload (Rev A)
5428	5429	shikgam2        // 2003.04 Shikigami No Shiro II / The Castle of Shikigami II
5429	5430	bdrdown         // 2003.04 Border Down (Rev A)
r242413	r242414
5432	5433	oinori          // 2003.08 Oinori-daimyoujin Matsuri
5433	5434	psyvar2         // 2003.11 Psyvariar 2 - The Will To Fabricate
5434	5435	puyofev         // 2003.11 Puyo Puyo Fever
5435		starhrsp        // 2003.12 Star Horse Progress (Rev A)
	5436	starhrsp        // 2003.12.01 Star Horse Progress (satellite) (Rev A)
5436	5437	puyofevp        // 2003.?? Puyo Puyo Fever (prototype)
5437	5438	// 2003.?? Dragon Treasure
5438	5439	// 2003.?? Rabbit 2
r242413	r242414
5488	5489	mbaa            // 2008.09 Melty Blood Actress Again
5489	5490	mbaaa           // 2008.12 Melty Blood Actress Again Ver.A
5490	5491	radirgyn        // 2009.06 Radirgy Noa
	5492	starhrpr        // 2009.07.27 Star Horse Progress Returns (satellite)
5491	5493	// 2009.?? Project Cerberus (planned to be released in 2009)
5492	5494
5493	5495	// NAOMI based (System SP)
r242413	r242414
6936	6938	tempest1r       // 136002           (c) 1980
6937	6939	temptube        // (hack)
6938	6940	spacduel        // 136006           (c) 1980
	6941	spacduel1       // 136006           (c) 1980
	6942	spacduel0       // 136006           (c) 1980
6939	6943	gravitar        // 136010           (c) 1982
6940	6944	gravitar2       // 136010           (c) 1982
6941	6945	gravitar1       // 136010           (c) 1982
r242413	r242414
11172	11176	peip0116        // (c) 1987 IGT - International Game Technology
11173	11177	peip0118        // (c) 1987 IGT - International Game Technology
11174	11178	peip0120        // (c) 1987 IGT - International Game Technology
	11179	pemg0183        // (c) 1994 IGT - International Game Technology
11175	11180	pemg0252        // (c) 1994 IGT - International Game Technology
11176	11181	pebe0014        // (c) 1994 IGT - International Game Technology
11177	11182	peke0017        // (c) 1994 IGT - International Game Technology
r242413	r242414
11311	11316	pex2421p        // (c) 1995 IGT - International Game Technology
11312	11317	pex2440p        // (c) 1995 IGT - International Game Technology
11313	11318	pex2461p        // (c) 1995 IGT - International Game Technology
	11319	pex2478p        // (c) 1995 IGT - International Game Technology
	11320	pex2479p        // (c) 1995 IGT - International Game Technology
	11321	pex2480p        // (c) 1995 IGT - International Game Technology
	11322	pex2485p        // (c) 1995 IGT - International Game Technology
11314	11323	pekoc766        // (c) 1997 IGT - International Game Technology
11315	11324	pekoc801        // (c) 1997 IGT - International Game Technology
11316	11325	pekoc802        // (c) 1997 IGT - International Game Technology

trunk/src/mame/mame.mak

r242413	r242414
499	499	MACHINES += PIC8259
500	500	MACHINES += PIT8253
501	501	MACHINES += PLA
	502	#MACHINES += PROFILE
	503	MACHINES += R10696
502	504	MACHINES += R10788
503		#MACHINES += PROFILE
	505	MACHINES += RA17XX
504	506	#MACHINES += R64H156
505	507	MACHINES += RF5C296
506	508	#MACHINES += RIOT6532

trunk/src/mess/drivers/a5105.c

r242413	r242414
73	73	DECLARE_WRITE8_MEMBER( a5105_upd765_w );
74	74	DECLARE_WRITE8_MEMBER(pcg_addr_w);
75	75	DECLARE_WRITE8_MEMBER(pcg_val_w);
76		required_shared_ptr<UINT8> m_video_ram;
	76	required_shared_ptr<UINT16> m_video_ram;
77	77	UINT8 *m_ram_base;
78	78	UINT8 *m_rom_base;
79	79	UINT8 *m_char_ram;
r242413	r242414
100	100	int xi,gfx;
101	101	UINT8 pen;
102	102
103		gfx = m_video_ram[address & 0x1ffff];
	103	gfx = m_video_ram[(address & 0x1ffff) >> 1];
104	104
105		for(xi=0;xi<8;xi++)
	105	for(xi=0;xi<16;xi++)
106	106	{
107	107	pen = ((gfx >> xi) & 1) ? 7 : 0;
108	108
r242413	r242414
120	120
121	121	for( x = 0; x < pitch; x++ )
122	122	{
123		tile = (m_video_ram[((addr+x)*2) & 0x1ffff] & 0xff);
124		color = (m_video_ram[((addr+x)*2+1) & 0x1ffff] & 0x0f);
	123	tile = (m_video_ram[(((addr+x)*2) & 0x1ffff) >> 1] & 0xff);
	124	color = ((m_video_ram[(((addr+x)*2) & 0x1ffff) >> 1] >> 8) & 0x0f);
125	125
126	126	for( yi = 0; yi < lr; yi++)
127	127	{
r242413	r242414
533	533	m_char_ram = memregion("pcg")->base();
534	534	}
535	535
536		static ADDRESS_MAP_START( upd7220_map, AS_0, 8, a5105_state)
	536	static ADDRESS_MAP_START( upd7220_map, AS_0, 16, a5105_state)
537	537	ADDRESS_MAP_GLOBAL_MASK(0x1ffff)
538	538	AM_RANGE(0x00000, 0x1ffff) AM_RAM AM_SHARE("video_ram")
539	539	ADDRESS_MAP_END

trunk/src/mess/drivers/ampro.c

r242413	r242414
181	181	MCFG_TIMER_DRIVER_ADD_PERIODIC("ctc_tick", ampro_state, ctc_tick, attotime::from_hz(XTAL_16MHz / 8))
182	182	MCFG_WD1772x_ADD("fdc", XTAL_16MHz / 2)
183	183	MCFG_FLOPPY_DRIVE_ADD("fdc:0", ampro_floppies, "525dd", floppy_image_device::default_floppy_formats)
	184	MCFG_SOFTWARE_LIST_ADD("flop_list", "ampro")
184	185	MACHINE_CONFIG_END
185	186
186	187	/* ROM definition */

trunk/src/mess/drivers/apc.c

r242413	r242414
99	99	UINT8 *m_char_rom;
100	100	UINT8 *m_aux_pcg;
101	101
102		required_shared_ptr<UINT8> m_video_ram_1;
103		required_shared_ptr<UINT8> m_video_ram_2;
	102	required_shared_ptr<UINT16> m_video_ram_1;
	103	required_shared_ptr<UINT16> m_video_ram_2;
104	104
105	105	required_device<palette_device> m_palette;
106	106
r242413	r242414
210	210	//      tile_addr = addr+(x*(m_video_ff[WIDTH40_REG]+1));
211	211	tile_addr = addr+(x*(1));
212	212
213		tile = m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0x00ff;
214		tile_sel = m_video_ram_1[(tile_addr*2) & 0x1fff] & 0x00ff;
215		attr = (m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0x00ff);
	213	tile = (m_video_ram_1[((tile_addr*2) & 0x1fff) >> 1] >> 8) & 0x00ff;
	214	tile_sel = m_video_ram_1[((tile_addr*2) & 0x1fff) >> 1] & 0x00ff;
	215	attr = (m_video_ram_1[((tile_addr*2 & 0x1fff) | 0x2000) >> 1] & 0x00ff);
216	216
217	217	u_line = attr & 0x01;
218	218	o_line = attr & 0x02;
r242413	r242414
784	784
785	785
786	786
787		static ADDRESS_MAP_START( upd7220_1_map, AS_0, 8, apc_state)
	787	static ADDRESS_MAP_START( upd7220_1_map, AS_0, 16, apc_state)
788	788	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram_1")
789	789	ADDRESS_MAP_END
790	790
791		static ADDRESS_MAP_START( upd7220_2_map, AS_0, 8, apc_state )
	791	static ADDRESS_MAP_START( upd7220_2_map, AS_0, 16, apc_state )
792	792	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram_2")
793	793	ADDRESS_MAP_END
794	794

trunk/src/mess/drivers/apple2.c

r242413	r242414
501	501
502	502	case 0x10:  // reads any key down, clears strobe
503	503	{
504		UINT8 rv = m_transchar | m_anykeydown;
	504	UINT8 rv = m_transchar | (m_anykeydown ? 0x80 : 0x00);
505	505	m_strobe = 0;
506	506	return rv;
507	507	}

trunk/src/mess/drivers/apple2e.c

r242413	r242414
682	682	save_item(NAME(m_exp_liveptr));
683	683	save_item(NAME(m_exp_bankhior));
684	684	save_item(NAME(m_exp_addrmask));
	685	save_item(NAME(m_lcram));
	686	save_item(NAME(m_lcram2));
	687	save_item(NAME(m_lcwriteenable));
685	688	}
686	689
687	690	void apple2e_state::machine_reset()
r242413	r242414
826	829	{
827	830	if (m_video->m_mix)
828	831	{
829		if (m_video->m_dhires)
	832	if ((m_video->m_dhires) && (m_video->m_80col))
830	833	{
831	834	m_video->dhgr_update(screen, bitmap, cliprect, 0, 159);
832	835	}
r242413	r242414
838	841	}
839	842	else
840	843	{
841		if (m_video->m_dhires)
	844	if ((m_video->m_dhires) && (m_video->m_80col))
842	845	{
843	846	m_video->dhgr_update(screen, bitmap, cliprect, 0, 191);
844	847	}
r242413	r242414
852	855	{
853	856	if (m_video->m_mix)
854	857	{
855		if (m_video->m_dhires)
	858	if ((m_video->m_dhires) && (m_video->m_80col))
856	859	{
857	860	m_video->dlores_update(screen, bitmap, cliprect, 0, 159);
858	861	}
r242413	r242414
865	868	}
866	869	else
867	870	{
868		if (m_video->m_dhires)
	871	if ((m_video->m_dhires) && (m_video->m_80col))
869	872	{
870	873	m_video->dlores_update(screen, bitmap, cliprect, 0, 191);
871	874	}
r242413	r242414
1260	1263
1261	1264	case 0x10:  // read any key down, reset keyboard strobe
1262	1265	{
1263		UINT8 rv = m_transchar | m_anykeydown;
	1266	UINT8 rv = m_transchar | (m_anykeydown ? 0x80 : 0x00);
1264	1267	m_strobe = 0;
1265	1268	return rv;
1266	1269	}
r242413	r242414
1509	1512
1510	1513	case 0x10:  // read any key down, reset keyboard strobe
1511	1514	{
1512		UINT8 rv = m_transchar | m_anykeydown;
	1515	UINT8 rv = m_transchar | (m_anykeydown ? 0x80 : 0x00);
1513	1516	m_strobe = 0;
1514	1517	return rv;
1515	1518	}

trunk/src/mess/drivers/asst128.c

r242413	r242414
84	84	ADDRESS_MAP_END
85	85
86	86	static SLOT_INTERFACE_START( asst128_floppies )
87		SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
	87	SLOT_INTERFACE( "525ssqd", FLOPPY_525_SSQD )
88	88	SLOT_INTERFACE_END
89	89
90	90	FLOPPY_FORMATS_MEMBER( asst128_state::asst128_formats )

trunk/src/mess/drivers/bigbord2.c

r242413	r242414
107	107	m_maincpu(*this, Z80_TAG),
108	108	m_6845(*this, "crtc"),
109	109	m_ctca(*this, Z80CTCA_TAG),
110		m_ctcb(*this, Z80CTCA_TAG),
	110	m_ctcb(*this, Z80CTCB_TAG),
111	111	m_dma(*this, Z80DMA_TAG),
112	112	m_fdc(*this, "fdc"),
113	113	m_floppy0(*this, "fdc:0"),

trunk/src/mess/drivers/bitgraph.c

r0	r242414
	1	/***************************************************************************
	2
	3	BBN BitGraph -- monochrome, raster graphics (768x1024), serial terminal.
	4
	5	Apparently had at least four hardware revisions, A-D, but which ROM
	6	revisions support which hardware is unclear.  A Versabus slot, and
	7	various hardware and software options are mentioned in the docs.  Best
	8	guesses follow.
	9
	10	Onboard hardware (common to all revisions) is
	11	- 32K ROM
	12	- 128K RAM (includes frame buffer)
	13	- 3 serial ports, each driven by 6850 ACIA
	14	- some kind of baud rate generator, possibly COM8016
	15	- sync serial port, driven by 6854 but apparently never supported by ROM
	16	- 682x PIA
	17	- AY-3-891x PSG
	18	- ER2055 EAROM
	19	- DEC VT100 keyboard interface
	20
	21	Rev A has additional 4th serial port for mouse (not supported by ROM 1.25).
	22	Rev A has 40 hz realtime clock, the rest use 1040 hz.
	23	Rev A-C use AY-3-8912 (with one external PIO port, to connect the EAROM).
	24	Rev D uses AY-3-8913 (no external ports; EAROM is wired to TBD).
	25	Rev B-D have onboard 8035 to talk to parallel printer and mouse.
	26	Rev B-D have more memory (at least up to 512K).
	27
	28	ROM 1.25 doesn't support mouse, setup mode, pixel data upload and autowrap.
	29
	30	Missing/incorrect emulation:
	31	Bidirectional keyboard interface (to drive LEDs and speaker).
	32	8035.
	33	EAROM.
	34	1.25 only -- clksync() is dummied out -- causes watchdog resets.
	35	Selectable memory size.
	36	Video enable/reverse video switch.
	37
	38	****************************************************************************/
	39
	40	#include "emu.h"
	41
	42	#include "bus/centronics/ctronics.h"
	43	#include "bus/rs232/rs232.h"
	44	#include "cpu/m68000/m68000.h"
	45	#include "cpu/mcs48/mcs48.h"
	46	#include "machine/6821pia.h"
	47	#include "machine/6850acia.h"
	48	#include "machine/clock.h"
	49	#include "machine/com8116.h"
	50	#include "machine/er2055.h"
	51	#include "machine/i8243.h"
	52	#include "machine/mc6854.h"
	53	#include "machine/ram.h"
	54	#include "sound/ay8910.h"
	55
	56	#include "bitgrpha.lh"
	57	#include "bitgrphb.lh"
	58
	59	#define M68K_TAG "maincpu"
	60	#define PPU_TAG "ppu"
	61
	62	#define ACIA0_TAG "acia0"
	63	#define ACIA1_TAG "acia1"
	64	#define ACIA2_TAG "acia2"
	65	#define ACIA3_TAG "acia3"
	66	#define RS232_H_TAG "rs232host"
	67	#define RS232_K_TAG "rs232kbd"
	68	#define RS232_D_TAG "rs232debug"
	69	#define RS232_M_TAG "rs232mouse"
	70	#define COM8116_A_TAG "com8116_a"
	71	#define COM8116_B_TAG "com8116_b"
	72	#define ADLC_TAG "adlc"
	73	#define PIA_TAG "pia"
	74	#define PSG_TAG "psg"
	75	#define EAROM_TAG "earom"
	76
	77	#define VERBOSE_DBG 1       /* general debug messages */
	78
	79	#define DBG_LOG(N,M,A) \
	80	do { \
	81	if(VERBOSE_DBG>=N) \
	82	{ \
	83	if( M ) \
	84	logerror("%11.6f at %s: %-24s",machine().time().as_double(),machine().describe_context(),(char*)M ); \
	85	logerror A; \
	86	} \
	87	} while (0)
	88
	89	class bitgraph_state : public driver_device
	90	{
	91	public:
	92	bitgraph_state(const machine_config &mconfig, device_type type, const char *tag)
	93	: driver_device(mconfig, type, tag)
	94	, m_maincpu(*this, M68K_TAG)
	95	, m_ram(*this, RAM_TAG)
	96	, m_acia0(*this, ACIA0_TAG)
	97	, m_acia1(*this, ACIA1_TAG)
	98	, m_acia2(*this, ACIA2_TAG)
	99	, m_acia3(*this, ACIA3_TAG)
	100	, m_adlc(*this, ADLC_TAG)
	101	, m_dbrga(*this, COM8116_A_TAG)
	102	, m_dbrgb(*this, COM8116_B_TAG)
	103	, m_pia(*this, PIA_TAG)
	104	, m_psg(*this, PSG_TAG)
	105	, m_earom(*this, EAROM_TAG)
	106	, m_centronics(*this, "centronics")
	107	, m_screen(*this, "screen")
	108	{ }
	109
	110	DECLARE_READ8_MEMBER( pia_r );
	111	DECLARE_WRITE8_MEMBER( pia_w );
	112	DECLARE_READ8_MEMBER( pia_pa_r );
	113	DECLARE_READ8_MEMBER( pia_pb_r );
	114	DECLARE_WRITE8_MEMBER( pia_pa_w );
	115	DECLARE_WRITE8_MEMBER( pia_pb_w );
	116	DECLARE_READ_LINE_MEMBER( pia_ca1_r );
	117	DECLARE_READ_LINE_MEMBER( pia_cb1_r );
	118	DECLARE_WRITE_LINE_MEMBER( pia_ca2_w );
	119	DECLARE_WRITE_LINE_MEMBER( pia_cb2_w );
	120
	121	DECLARE_WRITE16_MEMBER( baud_write );
	122	DECLARE_WRITE_LINE_MEMBER( com8116_a_fr_w );
	123	DECLARE_WRITE_LINE_MEMBER( com8116_a_ft_w );
	124	DECLARE_WRITE_LINE_MEMBER( com8116_b_fr_w );
	125	DECLARE_WRITE_LINE_MEMBER( com8116_b_ft_w );
	126
	127	DECLARE_READ8_MEMBER( adlc_r );
	128	DECLARE_WRITE8_MEMBER( adlc_w );
	129
	130	DECLARE_WRITE8_MEMBER( earom_write );
	131	DECLARE_WRITE8_MEMBER( misccr_write );
	132	DECLARE_WRITE_LINE_MEMBER( system_clock_write );
	133
	134	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	135
	136	DECLARE_READ8_MEMBER( ppu_read );
	137	DECLARE_WRITE8_MEMBER( ppu_write );
	138	DECLARE_WRITE8_MEMBER( ppu_i8243_w );
	139
	140	private:
	141	virtual void machine_start();
	142	virtual void machine_reset();
	143	required_device<cpu_device> m_maincpu;
	144	required_device<ram_device> m_ram;
	145	required_device<acia6850_device> m_acia0;
	146	required_device<acia6850_device> m_acia1;
	147	required_device<acia6850_device> m_acia2;
	148	optional_device<acia6850_device> m_acia3;
	149	optional_device<mc6854_device> m_adlc;
	150	required_device<com8116_device> m_dbrga;
	151	required_device<com8116_device> m_dbrgb;
	152	required_device<pia6821_device> m_pia;
	153	required_device<ay8912_device> m_psg;
	154	required_device<er2055_device> m_earom;
	155	optional_device<centronics_device> m_centronics;
	156	required_device<screen_device> m_screen;
	157
	158	UINT8 *m_videoram;
	159	UINT8 m_misccr;
	160	UINT8 m_pia_a;
	161	UINT8 m_pia_b;
	162	UINT8 m_ppu[4];
	163	};
	164
	165	static ADDRESS_MAP_START(bitgrapha_mem, AS_PROGRAM, 16, bitgraph_state)
	166	ADDRESS_MAP_UNMAP_HIGH
	167	AM_RANGE(0x000000, 0x007fff) AM_ROM
	168	AM_RANGE(0x010000, 0x010001) AM_DEVREADWRITE8(ACIA0_TAG, acia6850_device, data_r, data_w, 0xff00)   // HOST
	169	AM_RANGE(0x010002, 0x010003) AM_DEVREADWRITE8(ACIA0_TAG, acia6850_device, status_r, control_w, 0xff00)
	170	AM_RANGE(0x010008, 0x010009) AM_DEVREADWRITE8(ACIA1_TAG, acia6850_device, data_r, data_w, 0x00ff)   // KEYBOARD
	171	AM_RANGE(0x01000a, 0x01000b) AM_DEVREADWRITE8(ACIA1_TAG, acia6850_device, status_r, control_w, 0x00ff)
	172	AM_RANGE(0x010010, 0x010011) AM_DEVREADWRITE8(ACIA2_TAG, acia6850_device, data_r, data_w, 0x00ff)   // DEBUGGER
	173	AM_RANGE(0x010012, 0x010013) AM_DEVREADWRITE8(ACIA2_TAG, acia6850_device, status_r, control_w, 0x00ff)
	174	AM_RANGE(0x010018, 0x010019) AM_DEVREADWRITE8(ACIA3_TAG, acia6850_device, data_r, data_w, 0x00ff)   // POINTER
	175	AM_RANGE(0x01001a, 0x01001b) AM_DEVREADWRITE8(ACIA3_TAG, acia6850_device, status_r, control_w, 0x00ff)
	176	AM_RANGE(0x010020, 0x010027) AM_READWRITE8(adlc_r, adlc_w, 0xff00)
	177	AM_RANGE(0x010028, 0x01002f) AM_READWRITE8(pia_r, pia_w, 0xff00)   // EAROM, PSG
	178	AM_RANGE(0x010030, 0x010031) AM_WRITE(baud_write)
	179	AM_RANGE(0x3e0000, 0x3fffff) AM_RAM
	180	ADDRESS_MAP_END
	181
	182	static ADDRESS_MAP_START(bitgraphb_mem, AS_PROGRAM, 16, bitgraph_state)
	183	ADDRESS_MAP_UNMAP_HIGH
	184	AM_RANGE(0x000000, 0x007fff) AM_ROM
	185	AM_RANGE(0x010000, 0x010001) AM_DEVREADWRITE8(ACIA0_TAG, acia6850_device, data_r, data_w, 0xff00)   // HOST
	186	AM_RANGE(0x010002, 0x010003) AM_DEVREADWRITE8(ACIA0_TAG, acia6850_device, status_r, control_w, 0xff00)
	187	AM_RANGE(0x010008, 0x010009) AM_DEVREADWRITE8(ACIA1_TAG, acia6850_device, data_r, data_w, 0x00ff)   // KEYBOARD
	188	AM_RANGE(0x01000a, 0x01000b) AM_DEVREADWRITE8(ACIA1_TAG, acia6850_device, status_r, control_w, 0x00ff)
	189	AM_RANGE(0x010010, 0x010011) AM_DEVREADWRITE8(ACIA2_TAG, acia6850_device, data_r, data_w, 0x00ff)   // DEBUGGER
	190	AM_RANGE(0x010012, 0x010013) AM_DEVREADWRITE8(ACIA2_TAG, acia6850_device, status_r, control_w, 0x00ff)
	191	AM_RANGE(0x01001a, 0x01001b) AM_WRITE8(misccr_write, 0x00ff)
	192	AM_RANGE(0x010020, 0x010027) AM_READWRITE8(adlc_r, adlc_w, 0xff00)
	193	AM_RANGE(0x010028, 0x01002f) AM_READWRITE8(pia_r, pia_w, 0xff00)   // EAROM, PSG
	194	AM_RANGE(0x010030, 0x010031) AM_WRITE(baud_write)
	195	//   AM_RANGE(0x010030, 0x010037) AM_READ8(ppu_read, 0x00ff)
	196	//   AM_RANGE(0x010038, 0x01003f) AM_WRITE8(ppu_write, 0x00ff)
	197	AM_RANGE(0x380000, 0x3fffff) AM_RAM
	198	ADDRESS_MAP_END
	199
	200	static INPUT_PORTS_START(bitgraph)
	201	INPUT_PORTS_END
	202
	203	READ8_MEMBER(bitgraph_state::pia_r)
	204	{
	205	DBG_LOG(3,"PIA", ("R %d\n", offset));
	206	return m_pia->read(space, 3-offset);
	207	}
	208
	209	WRITE8_MEMBER(bitgraph_state::pia_w)
	210	{
	211	DBG_LOG(3,"PIA", ("W %d < %02X\n", offset, data));
	212	return m_pia->write(space, 3-offset, data);
	213	}
	214
	215	READ_LINE_MEMBER(bitgraph_state::pia_ca1_r)
	216	{
	217	return m_screen->frame_number() & 1;
	218	}
	219
	220	WRITE_LINE_MEMBER(bitgraph_state::pia_cb2_w)
	221	{
	222	// XXX shut up verbose log
	223	}
	224
	225	READ8_MEMBER(bitgraph_state::pia_pa_r)
	226	{
	227	UINT8 data = BIT(m_pia_b, 3) ? m_earom->data() : m_pia_a;
	228	DBG_LOG(2,"PIA", ("A == %02X (%s)\n", data, BIT(m_pia_b, 3) ? "earom" : "pia"));
	229	return data;
	230	}
	231
	232	WRITE8_MEMBER(bitgraph_state::pia_pa_w)
	233	{
	234	DBG_LOG(2,"PIA", ("A <- %02X\n", data));
	235	m_pia_a = data;
	236	}
	237
	238	/*
	239	B0          O: BC1  to noisemaker.
	240	B1          O: BDIR to noisemaker.
	241	B2          O: Clock for EAROM.
	242	B3          O: CS1   for EAROM.
	243	B4          O: Enable HDLC Xmt interrupt.
	244	B5          O: Enable HDLC Rcv interrupt.
	245	B6          O: Clear Clock interrupt.  Must write a 0 [clear interrupt], then a 1.
	246	B7          I: EVEN field ??
	247	*/
	248	READ8_MEMBER(bitgraph_state::pia_pb_r)
	249	{
	250	DBG_LOG(2,"PIA", ("B == %02X\n", m_pia_b));
	251	return m_pia_b;
	252	}
	253
	254	WRITE8_MEMBER(bitgraph_state::pia_pb_w)
	255	{
	256	DBG_LOG(2,"PIA", ("B <- %02X\n", data));
	257	m_pia_b = data;
	258
	259	switch (m_pia_b & 0x03) {
	260	case 2:   m_psg->data_w(space, 0, m_pia_a); break;
	261	case 3:   m_psg->address_w(space, 0, m_pia_a); break;
	262	}
	263
	264	if (BIT(m_pia_b, 3)) {
	265	DBG_LOG(2,"EAROM", ("data <- %02X\n", m_pia_a));
	266	m_earom->set_data(m_pia_a);
	267	}
	268	// CS1, ~CS2, C1, C2, CK
	269	m_earom->set_control(BIT(m_pia_b, 3), BIT(m_pia_b, 3), BIT(m_pia_a, 6), BIT(m_pia_a, 7), BIT(m_pia_b, 2));
	270
	271	if (!BIT(m_pia_b, 6)) {
	272	m_maincpu->set_input_line(M68K_IRQ_6, CLEAR_LINE);
	273	}
	274	}
	275
	276	WRITE8_MEMBER(bitgraph_state::earom_write)
	277	{
	278	DBG_LOG(2,"EAROM", ("addr <- %02X (%02X)\n", data & 0x3f, data));
	279	m_earom->set_address(data & 0x3f);
	280	}
	281
	282	// written once and never changed
	283	WRITE8_MEMBER(bitgraph_state::misccr_write)
	284	{
	285	DBG_LOG(1,"MISCCR", ("<- %02X (DTR %d MAP %d)\n", data, BIT(data, 3), (data & 3)));
	286	m_misccr = data;
	287	}
	288
	289	WRITE_LINE_MEMBER(bitgraph_state::system_clock_write)
	290	{
	291	if (!BIT(m_pia_b, 6)) {
	292	m_maincpu->set_input_line(M68K_IRQ_6, CLEAR_LINE);
	293	return;
	294	}
	295	if (state) {
	296	m_maincpu->set_input_line_and_vector(M68K_IRQ_6, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR);
	297	} else {
	298	m_maincpu->set_input_line(M68K_IRQ_6, CLEAR_LINE);
	299	}
	300	}
	301
	302	WRITE16_MEMBER(bitgraph_state::baud_write)
	303	{
	304	DBG_LOG(1,"Baud", ("%04X\n", data));
	305	m_dbrgb->str_w(data & 15);      // 2 DBG
	306	m_dbrga->stt_w((data >> 4) & 15);   // 1 KBD
	307	m_dbrgb->stt_w((data >> 8) & 15);   // 3 PNT
	308	m_dbrga->str_w((data >> 12) & 15);   // 0 HOST
	309	}
	310
	311	WRITE_LINE_MEMBER(bitgraph_state::com8116_a_fr_w)
	312	{
	313	m_acia0->write_txc(state);
	314	m_acia0->write_rxc(state);
	315	}
	316
	317	WRITE_LINE_MEMBER(bitgraph_state::com8116_a_ft_w)
	318	{
	319	m_acia1->write_txc(state);
	320	m_acia1->write_rxc(state);
	321	}
	322
	323	WRITE_LINE_MEMBER(bitgraph_state::com8116_b_fr_w)
	324	{
	325	m_acia2->write_txc(state);
	326	m_acia2->write_rxc(state);
	327	}
	328
	329	WRITE_LINE_MEMBER(bitgraph_state::com8116_b_ft_w)
	330	{
	331	if (m_acia3) {
	332	m_acia3->write_txc(state);
	333	m_acia3->write_rxc(state);
	334	}
	335	}
	336
	337	READ8_MEMBER(bitgraph_state::adlc_r)
	338	{
	339	DBG_LOG(1,"ADLC", ("R %d\n", offset));
	340	return m_adlc ? m_adlc->read(space, 3-offset) : 0xff;
	341	}
	342
	343	WRITE8_MEMBER(bitgraph_state::adlc_w)
	344	{
	345	DBG_LOG(1,"ADLC", ("W %d < %02X\n", offset, data));
	346	if (m_adlc) return m_adlc->write(space, 3-offset, data);
	347	}
	348
	349	UINT32 bitgraph_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	350	{
	351	UINT8 gfx=0;
	352	int x,y;
	353
	354	for (y = 0; y < 768; y++)
	355	{
	356	UINT16 *p = &bitmap.pix16(y);
	357
	358	for (x = 0; x < 1024/8; x+=2)
	359	{
	360	gfx = m_videoram[ (x+1) | (y<<7)];
	361
	362	*p++ = BIT(gfx, 7);
	363	*p++ = BIT(gfx, 6);
	364	*p++ = BIT(gfx, 5);
	365	*p++ = BIT(gfx, 4);
	366	*p++ = BIT(gfx, 3);
	367	*p++ = BIT(gfx, 2);
	368	*p++ = BIT(gfx, 1);
	369	*p++ = BIT(gfx, 0);
	370
	371	gfx = m_videoram[ x | (y<<7)];
	372
	373	*p++ = BIT(gfx, 7);
	374	*p++ = BIT(gfx, 6);
	375	*p++ = BIT(gfx, 5);
	376	*p++ = BIT(gfx, 4);
	377	*p++ = BIT(gfx, 3);
	378	*p++ = BIT(gfx, 2);
	379	*p++ = BIT(gfx, 1);
	380	*p++ = BIT(gfx, 0);
	381	}
	382	}
	383	return 0;
	384	}
	385
	386	READ8_MEMBER(bitgraph_state::ppu_read)
	387	{
	388	UINT8 data = m_ppu[offset];
	389	DBG_LOG(1,"PPU", ("%d == %02X\n", offset, data));
	390	return data;
	391	}
	392
	393	WRITE8_MEMBER(bitgraph_state::ppu_write)
	394	{
	395	DBG_LOG(1,"PPU", ("%d <- %02X\n", offset, data));
	396	m_ppu[offset] = data;
	397	}
	398
	399	#ifdef UNUSED_FUNCTION
	400	static ADDRESS_MAP_START(ppu_io, AS_IO, 8, bitgraph_state)
	401	//   AM_RANGE(0x00, 0x00) AM_READ(ppu_irq)
	402	//   AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1)
	403	//   AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ(ppu_t0_r)
	404	AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE("i8243", i8243_device, i8243_prog_w)
	405	ADDRESS_MAP_END
	406	#endif
	407
	408	/*
	409	p4   O: Centronics data 3..0
	410	p5   O: Centronics data 7..4
	411	p6   O: Centronics control
	412	p7   I: Centronics status
	413	*/
	414	WRITE8_MEMBER(bitgraph_state::ppu_i8243_w)
	415	{
	416	DBG_LOG(1,"PPU", ("8243 %d <- %02X\n", offset + 4, data));
	417	switch (offset) {
	418	case 0:
	419	m_centronics->write_data0(BIT(data, 0));
	420	m_centronics->write_data1(BIT(data, 1));
	421	m_centronics->write_data2(BIT(data, 2));
	422	m_centronics->write_data3(BIT(data, 3));
	423	break;
	424	case 1:
	425	m_centronics->write_data4(BIT(data, 0));
	426	m_centronics->write_data5(BIT(data, 1));
	427	m_centronics->write_data6(BIT(data, 2));
	428	m_centronics->write_data7(BIT(data, 3));
	429	break;
	430	case 2:
	431	m_centronics->write_strobe(BIT(data, 0));
	432	// 1: Paper instruction
	433	m_centronics->write_init(BIT(data, 2));
	434	break;
	435	case 3:
	436	m_centronics->write_ack(BIT(data, 0));
	437	m_centronics->write_busy(BIT(data, 1));
	438	m_centronics->write_perror(BIT(data, 2));
	439	m_centronics->write_select(BIT(data, 3));
	440	break;
	441	}
	442	}
	443
	444
	445	void bitgraph_state::machine_start()
	446	{
	447	m_videoram = (UINT8 *)m_maincpu->space(AS_PROGRAM).get_write_ptr(0x3e0000);
	448	}
	449
	450	void bitgraph_state::machine_reset()
	451	{
	452	m_maincpu->reset();
	453	m_misccr = 0;
	454	m_pia_a = 0;
	455	m_pia_b = 0;
	456	memset(m_ppu, sizeof(m_ppu), 0);
	457	}
	458
	459
	460	static MACHINE_CONFIG_FRAGMENT( bg_motherboard )
	461	MCFG_SCREEN_ADD("screen", RASTER)
	462	MCFG_SCREEN_REFRESH_RATE(40)
	463	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
	464	MCFG_SCREEN_SIZE(1024, 768)
	465	MCFG_SCREEN_VISIBLE_AREA(0, 1024-1, 0, 768-1)
	466	MCFG_SCREEN_UPDATE_DRIVER(bitgraph_state, screen_update)
	467
	468	MCFG_SCREEN_PALETTE("palette")
	469	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
	470
	471	MCFG_DEVICE_ADD(ACIA0_TAG, ACIA6850, 0)
	472	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE(RS232_H_TAG, rs232_port_device, write_txd))
	473	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE(RS232_H_TAG, rs232_port_device, write_rts))
	474	MCFG_ACIA6850_IRQ_HANDLER(DEVWRITELINE(M68K_TAG, m68000_device, write_irq1))
	475
	476	MCFG_RS232_PORT_ADD(RS232_H_TAG, default_rs232_devices, "null_modem")
	477	MCFG_RS232_RXD_HANDLER(DEVWRITELINE(ACIA0_TAG, acia6850_device, write_rxd))
	478	MCFG_RS232_DCD_HANDLER(DEVWRITELINE(ACIA0_TAG, acia6850_device, write_dcd))
	479	MCFG_RS232_CTS_HANDLER(DEVWRITELINE(ACIA0_TAG, acia6850_device, write_cts))
	480
	481	MCFG_DEVICE_ADD(ACIA1_TAG, ACIA6850, 0)
	482	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE(RS232_K_TAG, rs232_port_device, write_txd))
	483	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE(RS232_K_TAG, rs232_port_device, write_rts))
	484	MCFG_ACIA6850_IRQ_HANDLER(DEVWRITELINE(M68K_TAG, m68000_device, write_irq1))
	485
	486	MCFG_RS232_PORT_ADD(RS232_K_TAG, default_rs232_devices, "keyboard")
	487	MCFG_RS232_RXD_HANDLER(DEVWRITELINE(ACIA1_TAG, acia6850_device, write_rxd))
	488	MCFG_RS232_DCD_HANDLER(DEVWRITELINE(ACIA1_TAG, acia6850_device, write_dcd))
	489	MCFG_RS232_CTS_HANDLER(DEVWRITELINE(ACIA1_TAG, acia6850_device, write_cts))
	490
	491	MCFG_DEVICE_ADD(ACIA2_TAG, ACIA6850, 0)
	492	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE(RS232_D_TAG, rs232_port_device, write_txd))
	493	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE(RS232_D_TAG, rs232_port_device, write_rts))
	494	MCFG_ACIA6850_IRQ_HANDLER(DEVWRITELINE(M68K_TAG, m68000_device, write_irq1))
	495
	496	MCFG_RS232_PORT_ADD(RS232_D_TAG, default_rs232_devices, NULL)
	497	MCFG_RS232_RXD_HANDLER(DEVWRITELINE(ACIA2_TAG, acia6850_device, write_rxd))
	498	MCFG_RS232_DCD_HANDLER(DEVWRITELINE(ACIA2_TAG, acia6850_device, write_dcd))
	499	MCFG_RS232_CTS_HANDLER(DEVWRITELINE(ACIA2_TAG, acia6850_device, write_cts))
	500
	501	// XXX actual part may be something else
	502	MCFG_DEVICE_ADD(COM8116_A_TAG, COM8116, XTAL_5_0688MHz)
	503	MCFG_COM8116_FR_HANDLER(WRITELINE(bitgraph_state, com8116_a_fr_w))
	504	MCFG_COM8116_FT_HANDLER(WRITELINE(bitgraph_state, com8116_a_ft_w))
	505
	506	MCFG_DEVICE_ADD(COM8116_B_TAG, COM8116, XTAL_5_0688MHz)
	507	MCFG_COM8116_FR_HANDLER(WRITELINE(bitgraph_state, com8116_b_fr_w))
	508	MCFG_COM8116_FT_HANDLER(WRITELINE(bitgraph_state, com8116_b_ft_w))
	509
	510	MCFG_DEVICE_ADD(PIA_TAG, PIA6821, 0)
	511	MCFG_PIA_READCA1_HANDLER(READLINE(bitgraph_state, pia_ca1_r))
	512	MCFG_PIA_CB2_HANDLER(WRITELINE(bitgraph_state, pia_cb2_w))
	513	MCFG_PIA_READPA_HANDLER(READ8(bitgraph_state, pia_pa_r))
	514	MCFG_PIA_WRITEPA_HANDLER(WRITE8(bitgraph_state, pia_pa_w))
	515	MCFG_PIA_READPB_HANDLER(READ8(bitgraph_state, pia_pb_r))
	516	MCFG_PIA_WRITEPB_HANDLER(WRITE8(bitgraph_state, pia_pb_w))
	517
	518	MCFG_ER2055_ADD(EAROM_TAG)
	519
	520	MCFG_SPEAKER_STANDARD_MONO("mono")
	521	MCFG_SOUND_ADD(PSG_TAG, AY8912, XTAL_1_2944MHz)
	522	MCFG_AY8910_PORT_A_WRITE_CB(WRITE8(bitgraph_state, earom_write))
	523	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
	524	MACHINE_CONFIG_END
	525
	526	#ifdef UNUSED_FUNCTION
	527	static MACHINE_CONFIG_FRAGMENT( bg_ppu )
	528	MCFG_CPU_ADD(PPU_TAG, I8035, XTAL_6_9MHz)
	529	MCFG_CPU_IO_MAP(ppu_io)
	530
	531	MCFG_I8243_ADD("i8243", NOOP, WRITE8(bitgraph_state, ppu_i8243_w))
	532
	533	MCFG_CENTRONICS_ADD("centronics", centronics_devices, "printer")
	534	MCFG_CENTRONICS_ACK_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit6))
	535	MCFG_CENTRONICS_BUSY_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit7))
	536	MCFG_CENTRONICS_FAULT_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit4))
	537	MCFG_CENTRONICS_PERROR_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit5))
	538
	539	MCFG_DEVICE_ADD("cent_status_in", INPUT_BUFFER, 0)
	540
	541	MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
	542	MACHINE_CONFIG_END
	543	#endif
	544
	545	static MACHINE_CONFIG_START( bitgrpha, bitgraph_state )
	546	MCFG_CPU_ADD(M68K_TAG, M68000, XTAL_6_9MHz)
	547	MCFG_CPU_PROGRAM_MAP(bitgrapha_mem)
	548
	549	MCFG_FRAGMENT_ADD(bg_motherboard)
	550
	551	MCFG_DEVICE_ADD("system_clock", CLOCK, 40)
	552	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(bitgraph_state, system_clock_write))
	553
	554	MCFG_DEVICE_ADD(ACIA3_TAG, ACIA6850, 0)
	555	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE(RS232_M_TAG, rs232_port_device, write_txd))
	556	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE(RS232_M_TAG, rs232_port_device, write_rts))
	557	MCFG_ACIA6850_IRQ_HANDLER(DEVWRITELINE(M68K_TAG, m68000_device, write_irq1))
	558
	559	MCFG_RS232_PORT_ADD(RS232_M_TAG, default_rs232_devices, NULL)
	560	MCFG_RS232_RXD_HANDLER(DEVWRITELINE(ACIA3_TAG, acia6850_device, write_rxd))
	561	MCFG_RS232_DCD_HANDLER(DEVWRITELINE(ACIA3_TAG, acia6850_device, write_dcd))
	562	MCFG_RS232_CTS_HANDLER(DEVWRITELINE(ACIA3_TAG, acia6850_device, write_cts))
	563
	564	MCFG_DEFAULT_LAYOUT(layout_bitgrpha)
	565
	566	MCFG_RAM_ADD(RAM_TAG)
	567	MCFG_RAM_DEFAULT_SIZE("128K")
	568	MACHINE_CONFIG_END
	569
	570	static MACHINE_CONFIG_START( bitgrphb, bitgraph_state )
	571	MCFG_CPU_ADD(M68K_TAG, M68000, XTAL_6_9MHz)
	572	MCFG_CPU_PROGRAM_MAP(bitgraphb_mem)
	573
	574	MCFG_FRAGMENT_ADD(bg_motherboard)
	575	//   MCFG_FRAGMENT_ADD(bg_ppu)
	576
	577	MCFG_DEVICE_ADD("system_clock", CLOCK, 1040)
	578	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(bitgraph_state, system_clock_write))
	579
	580	MCFG_DEFAULT_LAYOUT(layout_bitgrphb)
	581
	582	MCFG_RAM_ADD(RAM_TAG)
	583	MCFG_RAM_DEFAULT_SIZE("512K")
	584	MACHINE_CONFIG_END
	585
	586	/* ROM definition */
	587	ROM_START( bitgrpha )
	588	ROM_REGION16_BE( 0x8000, M68K_TAG, 0 )
	589	ROM_LOAD( "bg125.rom", 0x000000, 0x008000, CRC(b86c974e) SHA1(5367db80a856444c2a55de22b69a13f97a62f602))
	590	ROM_FILL( 0x38e4, 1, 0x4e ) // disable clksync()
	591	ROM_FILL( 0x38e5, 1, 0x75 )
	592	ROM_END
	593
	594	ROM_START( bitgrphb )
	595	ROM_REGION16_BE( 0x8000, M68K_TAG, 0 )
	596	ROM_DEFAULT_BIOS("2.33A")
	597
	598	ROM_SYSTEM_BIOS(0, "2.33A", "rev 2.33 Alpha' ROM")
	599	ROMX_LOAD( "bg2.32lo_u10.bin", 0x004001, 0x002000, CRC(6a702a96) SHA1(acdf1ba34038b4ccafb5b8069e70ae57a3b8a7e0), ROM_BIOS(1)|ROM_SKIP(1))
	600	ROMX_LOAD( "bg2.32hi_u12.bin", 0x004000, 0x002000, CRC(a282a2c8) SHA1(ea7e4d4e197201c8944acef54479d5c2b26d409f), ROM_BIOS(1)|ROM_SKIP(1))
	601	ROMX_LOAD( "bg2.32lo_u11.bin", 0x000001, 0x002000, CRC(46912afd) SHA1(c1f771adc1ef62b1fb1b904ed1d2a61009e24f55), ROM_BIOS(1)|ROM_SKIP(1))
	602	ROMX_LOAD( "bg2.32hi_u13.bin", 0x000000, 0x002000, CRC(731df44f) SHA1(8c238b5943b8864e539f92891a0ffa6ddd4fc779), ROM_BIOS(1)|ROM_SKIP(1))
	603
	604	ROM_SYSTEM_BIOS(1, "3.0P", "rev 3.0P ROM")
	605	ROMX_LOAD( "bg5173_u10.bin", 0x004001, 0x002000, CRC(40014850) SHA1(ef0b7da58a5183391a3a03947882197f25694518), ROM_BIOS(2)|ROM_SKIP(1))
	606	ROMX_LOAD( "bg5175_u12.bin", 0x004000, 0x002000, CRC(c2c4cc6c) SHA1(dbbce7cb58b4cef1557a834cbb07b3ace298cb8b), ROM_BIOS(2)|ROM_SKIP(1))
	607	ROMX_LOAD( "bg5174_u11.bin", 0x000001, 0x002000, CRC(639768b9) SHA1(68f623bcf3bb75390ba2b17efc067cf25f915ec0), ROM_BIOS(2)|ROM_SKIP(1))
	608	ROMX_LOAD( "bg5176_u13.bin", 0x000000, 0x002000, CRC(984e7e8c) SHA1(dd13cbaff96a8b9936ae8cb07205c6abe8b27b6e), ROM_BIOS(2)|ROM_SKIP(1))
	609
	610	ROM_SYSTEM_BIOS(2, "ramtest", "RAM test")
	611	ROMX_LOAD( "ramtest.rom", 0x000000, 0x004000, CRC(fabe3b34) SHA1(4d892a2ed2b7ea12d83843609981be9069611d43), ROM_BIOS(3))
	612
	613	ROM_REGION( 0x800, PPU_TAG, 0 )
	614	ROM_LOAD( "bg_mouse_u9.bin", 0x0000, 0x0800, CRC(fd827ff5) SHA1(6d4a8e9b18c7610c5cfde40464826d144d387601))
	615	ROM_END
	616
	617	/* Driver */
	618	/*       YEAR  NAME      PARENT  COMPAT   MACHINE    INPUT    CLASS          INIT     COMPANY          FULLNAME       FLAGS */
	619	COMP( 1981, bitgrpha, 0, 0, bitgrpha, bitgraph, driver_device, 0, "BBN", "BitGraph rev A", GAME_IMPERFECT_KEYBOARD)
	620	COMP( 1982, bitgrphb, 0, 0, bitgrphb, bitgraph, driver_device, 0, "BBN", "BitGraph rev B", GAME_NOT_WORKING|GAME_IMPERFECT_KEYBOARD)

trunk/src/mess/drivers/compis.c

r242413	r242414
312	312	//  ADDRESS_MAP( upd7220_map )
313	313	//-------------------------------------------------
314	314
315		static ADDRESS_MAP_START( upd7220_map, AS_0, 8, compis_state )
	315	static ADDRESS_MAP_START( upd7220_map, AS_0, 16, compis_state )
316	316	ADDRESS_MAP_GLOBAL_MASK(0x7fff)
317	317	AM_RANGE(0x00000, 0x7fff) AM_RAM AM_SHARE("video_ram")
318	318	ADDRESS_MAP_END
r242413	r242414
451	451
452	452	UPD7220_DISPLAY_PIXELS_MEMBER( compis_state::hgdc_display_pixels )
453	453	{
454		UINT8 i,gfx = m_video_ram[(address & 0x7fff)];
	454	UINT16 i,gfx = m_video_ram[(address & 0x7fff) >> 1];
455	455	const pen_t *pen = m_palette->pens();
456	456
457		for(i=0; i<8; i++)
458		bitmap.pix32(y, x + i) = pen[BIT(gfx, 7 - i)];
	457	for(i=0; i<16; i++)
	458	bitmap.pix32(y, x + i) = pen[BIT(gfx, i)];
459	459	}
460	460
461	461

trunk/src/mess/drivers/dmv.c

r242413	r242414
73	73	required_device<floppy_connector> m_floppy1;
74	74	required_device<dmv_keyboard_device> m_keyboard;
75	75	required_device<speaker_sound_device> m_speaker;
76		required_shared_ptr<UINT8> m_video_ram;
	76	required_shared_ptr<UINT16> m_video_ram;
77	77	required_device<palette_device> m_palette;
78	78	required_memory_region m_ram;
79	79	required_memory_region m_bootrom;
r242413	r242414
286	286	if (m_color_mode)
287	287	{
288	288	// 96KB videoram (32KB green + 32KB red + 32KB blue)
289		UINT8 green = m_video_ram[0x00000 + (address & 0x7fff)];
290		UINT8 red   = m_video_ram[0x08000 + (address & 0x7fff)];
291		UINT8 blue  = m_video_ram[0x10000 + (address & 0x7fff)];
	289	UINT16 green = m_video_ram[(0x00000 + (address & 0x7fff)) >> 1];
	290	UINT16 red   = m_video_ram[(0x08000 + (address & 0x7fff)) >> 1];
	291	UINT16 blue  = m_video_ram[(0x10000 + (address & 0x7fff)) >> 1];
292	292
293		for(int xi=0; xi<8; xi++)
	293	for(int xi=0; xi<16; xi++)
294	294	{
295		int r = ((red   >> (7-xi)) & 1) ? 255 : 0;
296		int g = ((green >> (7-xi)) & 1) ? 255 : 0;
297		int b = ((blue  >> (7-xi)) & 1) ? 255 : 0;
	295	int r = ((red   >> xi) & 1) ? 255 : 0;
	296	int g = ((green >> xi) & 1) ? 255 : 0;
	297	int b = ((blue  >> xi) & 1) ? 255 : 0;
298	298
299	299	if (bitmap.cliprect().contains(x + xi, y))
300	300	bitmap.pix32(y, x + xi) = rgb_t(r, g, b);
r242413	r242414
305	305	const rgb_t *palette = m_palette->palette()->entry_list_raw();
306	306
307	307	// 32KB videoram
308		UINT8 gfx = m_video_ram[address & 0xffff];
	308	UINT16 gfx = m_video_ram[(address & 0xffff) >> 1];
309	309
310		for(int xi=0;xi<8;xi++)
	310	for(int xi=0;xi<16;xi++)
311	311	{
312	312	if (bitmap.cliprect().contains(x + xi, y))
313		bitmap.pix32(y, x + xi) = ((gfx >> (7-xi)) & 1) ? palette[1] : palette[0];
	313	bitmap.pix32(y, x + xi) = ((gfx >> xi) & 1) ? palette[1] : palette[0];
314	314	}
315	315	}
316	316	}
r242413	r242414
319	319	{
320	320	for( int x = 0; x < pitch; x++ )
321	321	{
322		UINT8 tile = m_video_ram[((addr+x)*2) & 0x1ffff] & 0xff;
323		UINT8 attr = m_video_ram[((addr+x)*2 + 1) & 0x1ffff] & 0xff;
	322	UINT8 tile = m_video_ram[(((addr+x)*2) & 0x1ffff) >> 1] & 0xff;
	323	UINT8 attr = m_video_ram[(((addr+x)*2) & 0x1ffff) >> 1] >> 8;
324	324
325	325	rgb_t bg, fg;
326	326	if (m_color_mode)
r242413	r242414
554	554	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_WRITE(kb_mcu_port2_w)
555	555	ADDRESS_MAP_END
556	556
557		static ADDRESS_MAP_START( upd7220_map, AS_0, 8, dmv_state )
	557	static ADDRESS_MAP_START( upd7220_map, AS_0, 16, dmv_state )
558	558	ADDRESS_MAP_GLOBAL_MASK(0x1ffff)
559	559	AM_RANGE(0x00000, 0x1ffff) AM_RAM  AM_SHARE("video_ram")
560	560	ADDRESS_MAP_END

trunk/src/mess/drivers/ec184x.c

r242413	r242414
202	202
203	203	static ADDRESS_MAP_START( ec1847_io, AS_IO, 8, ec184x_state )
204	204	ADDRESS_MAP_UNMAP_HIGH
205		//  AM_RANGE(0x0210, 0x021f) AM_RAM // internal (non-standard?) bus extender
	205	//   AM_RANGE(0x0210, 0x021f) AM_RAM // internal (non-standard?) bus extender
206	206	ADDRESS_MAP_END
207	207
208	208
r242413	r242414
252	252	MCFG_CPU_IO_MAP(ec1841_io)
253	253	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("mb:pic8259", pic8259_device, inta_cb)
254	254
255		//  MCFG_MACHINE_START_OVERRIDE(ec184x_state, ec184x)
256	255	MCFG_MACHINE_RESET_OVERRIDE(ec184x_state, ec184x)
257	256
258	257	MCFG_EC1841_MOTHERBOARD_ADD("mb", "maincpu")

trunk/src/mess/drivers/excali64.c

r242413	r242414
3	3	/***************************************************************************
4	4
5	5	Excalibur 64 kit computer, designed and sold in Australia by BGR Computers.
	6	The official schematics have a LOT of errors and omissions.
6	7
7	8	Skeleton driver created on 2014-12-09.
8	9
9	10	Chips: Z80A, 8251, 8253, 8255, 6845
	11	We have Basic 1.1. Other known versions are 1.01, 2.1
	12	There are 2 versions of the colour prom, which have different palettes.
	13	We have the later version.
10	14
	15	Control W then Enter will switch between 40 and 80 characters per line.
	16
11	17	ToDo:
12		- Some keys can be connected to more than one position in the matrix. Need to
13		determine the correct positions.
14		- The position of the "Line Insert" key is unknown.
15		- The video section has attributes and colour, none of this is done.
	18	- Colours are approximate.
16	19	- Disk controller
17		- Banking
	20	- Graphics commands such as LINE and CIRCLE produce a syntax error.
	21	- Some commands such as HGRCLS are missing from the rom. Perhaps we need a later version?
	22	- SET command produces random graphics instead of the expected lo-res dot.
18	23	- The schematic shows the audio counter connected to 2MHz, but this produces
19	24	sounds that are too high. Connected to 1MHz for now.
20	25	- Serial
21	26	- Parallel / Centronics
22	27	- Need software
	28	- Pasting can sometimes drop a character.
23	29
24	30	****************************************************************************/
25	31
r242413	r242414
45	51	, m_palette(*this, "palette")
46	52	, m_maincpu(*this, "maincpu")
47	53	, m_cass(*this, "cassette")
	54	, m_crtc(*this, "crtc")
48	55	, m_io_keyboard(*this, "KEY")
49	56	{ }
50	57
51		DECLARE_DRIVER_INIT(excali64);
	58	DECLARE_PALETTE_INIT(excali64);
52	59	DECLARE_WRITE8_MEMBER(ppib_w);
53	60	DECLARE_READ8_MEMBER(ppic_r);
54	61	DECLARE_WRITE8_MEMBER(ppic_w);
55	62	DECLARE_READ8_MEMBER(port00_r);
56	63	DECLARE_READ8_MEMBER(port50_r);
57	64	DECLARE_WRITE8_MEMBER(port70_w);
58		DECLARE_WRITE8_MEMBER(video_w);
59	65	MC6845_UPDATE_ROW(update_row);
60	66	DECLARE_WRITE_LINE_MEMBER(crtc_de);
61	67	DECLARE_WRITE_LINE_MEMBER(crtc_vs);
62
	68	DECLARE_MACHINE_RESET(excali64);
63	69	required_device<palette_device> m_palette;
64	70
65	71	private:
66	72	const UINT8 *m_p_chargen;
67	73	UINT8 *m_p_videoram;
	74	UINT8 *m_p_hiresram;
68	75	UINT8 m_sys_status;
69	76	UINT8 m_kbdrow;
70	77	bool m_crtc_vs;
71	78	bool m_crtc_de;
72	79	required_device<cpu_device> m_maincpu;
73	80	required_device<cassette_image_device> m_cass;
	81	required_device<mc6845_device> m_crtc;
74	82	required_ioport_array<8> m_io_keyboard;
75	83	};
76	84
77	85	static ADDRESS_MAP_START(excali64_mem, AS_PROGRAM, 8, excali64_state)
78		AM_RANGE(0x0000, 0x1FFF) AM_ROM
79		AM_RANGE(0x2000, 0x3FFF) AM_ROM AM_WRITE(video_w)
80		AM_RANGE(0x4000, 0xFFFF) AM_RAM
	86	AM_RANGE(0x0000, 0x1FFF) AM_READ_BANK("bankr1") AM_WRITE_BANK("bankw1")
	87	AM_RANGE(0x2000, 0x2FFF) AM_READ_BANK("bankr2") AM_WRITE_BANK("bankw2")
	88	AM_RANGE(0x3000, 0x3FFF) AM_READ_BANK("bankr3") AM_WRITE_BANK("bankw3")
	89	AM_RANGE(0x4000, 0x4FFF) AM_READ_BANK("bankr4") AM_WRITE_BANK("bankw4")
	90	AM_RANGE(0x5000, 0xFFFF) AM_RAM AM_REGION("rambank", 0x5000)
81	91	ADDRESS_MAP_END
82	92
83	93	static ADDRESS_MAP_START(excali64_io, AS_IO, 8, excali64_state)
r242413	r242414
94	104	ADDRESS_MAP_END
95	105
96	106
97		/* Input ports */
98	107	static INPUT_PORTS_START( excali64 )
99		//PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("LINEFEED") PORT_CODE(KEYCODE_ENTER_PAD) PORT_CHAR(0x0a)//H
100		//PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("REPT") PORT_CODE(KEYCODE_LALT)//0x11
101		//PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Down)") PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))//B
102		//PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Up)") PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
103		//PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Fire)") PORT_CODE(KEYCODE_INSERT) PORT_CHAR(UCHAR_MAMEKEY(INSERT))
104		//PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("\\ |")PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|') PORT_CHAR(0x1c)
105		//PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Right)") PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
106		//PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("BRK") PORT_CODE(KEYCODE_NUMLOCK) PORT_CHAR(0x03)
107		//PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Left)") PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
108
109	108	PORT_START("KEY.0")    /* line 0 */
110		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('R') PORT_CHAR('R') PORT_CHAR(0x12)
111		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_CHAR('W') PORT_CHAR(0x17)
	109	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') PORT_CHAR(0x12)
	110	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W') PORT_CHAR(0x17)
112	111	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
113		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('E') PORT_CHAR('E') PORT_CHAR(0x05)
	112	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E') PORT_CHAR(0x05)
114	113	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB) PORT_CHAR(0x09)
115	114	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CAPSLOCK") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE
116		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('A') PORT_CHAR('A') PORT_CHAR(0x01)
117		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') PORT_CHAR('Q') PORT_CHAR(0x11)
	115	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') PORT_CHAR(0x01)
	116	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q') PORT_CHAR(0x11)
118	117
119	118	PORT_START("KEY.1")    /* line 1 */
120	119	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F3") PORT_CODE(KEYCODE_F3)
121	120	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F2") PORT_CODE(KEYCODE_F2)
122	121	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F4") PORT_CODE(KEYCODE_F4)
123	122	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Space") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
124		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)//=
	123	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
125	124	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED) // space
126	125	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F1") PORT_CODE(KEYCODE_F1)
127	126	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) // F1
128	127
129	128	PORT_START("KEY.2")    /* line 2 */
130	129	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(". >") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
131		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('M') PORT_CHAR('M') PORT_CHAR(0x0d)
	130	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M') PORT_CHAR(0x0d)
132	131	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("/ ?") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
133	132	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(", <") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
134		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('B') PORT_CHAR('B') PORT_CHAR(0x02)
	133	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B') PORT_CHAR(0x02)
135	134	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED) //B
136		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('N') PORT_CHAR('N') PORT_CHAR(0x0e)
	135	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N') PORT_CHAR(0x0e)
137	136	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) //N
138	137
139	138	PORT_START("KEY.3")    /* line 3 */
140	139	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("' \"") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(0x27) PORT_CHAR(0x22) PORT_CHAR(0x27)
141		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('L') PORT_CHAR('L') PORT_CHAR(0x0c)
	140	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L') PORT_CHAR(0x0c)
142	141	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("RETURN") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(0x0d)
143	142	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("; :") PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
144		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('J') PORT_CHAR('J') PORT_CHAR(0x0a)
145		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('G') PORT_CHAR('G') PORT_CHAR(0x07)
146		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('K') PORT_CHAR('K') PORT_CHAR(0x0b)
147		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('H') PORT_CHAR('H') PORT_CHAR(0x08)
	143	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J') PORT_CHAR(0x0a)
	144	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G') PORT_CHAR(0x07)
	145	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') PORT_CHAR(0x0b)
	146	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') PORT_CHAR(0x08)
148	147
149	148	PORT_START("KEY.4")    /* line 4 */
150	149	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("4 $") PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
r242413	r242414
154	153	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("DEL") PORT_CODE(KEYCODE_DEL) PORT_CHAR(0x7f) PORT_CHAR(0x7f) PORT_CHAR(0x1f)
155	154	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC) PORT_CHAR(0x1b)
156	155	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("1 !") PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
157		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) //1
	156	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("INS") PORT_CODE(KEYCODE_INSERT)
158	157
159	158	PORT_START("KEY.5")    /* line 5 */
160	159	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("[ {") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{') PORT_CHAR(0x1b)
161		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_CHAR('O') PORT_CHAR(0x0f)
	160	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O') PORT_CHAR(0x0f)
162	161	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("] }") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}') PORT_CHAR(0x1d)
163		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('P') PORT_CHAR('P') PORT_CHAR(0x10)
164		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('U') PORT_CHAR('U') PORT_CHAR(0x15)
165		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('T') PORT_CHAR('T') PORT_CHAR(0x14)
166		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('I') PORT_CHAR('I') PORT_CHAR(0x09)//0x12
167		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') PORT_CHAR('Y') PORT_CHAR(0x19)//0x14
	162	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P') PORT_CHAR(0x10)
	163	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U') PORT_CHAR(0x15)
	164	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T') PORT_CHAR(0x14)
	165	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') PORT_CHAR(0x09)
	166	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') PORT_CHAR(0x19)
168	167
169	168	PORT_START("KEY.6")    /* line 6 */
170		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('F') PORT_CHAR('F') PORT_CHAR(0x06)
171		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('X') PORT_CHAR('X') PORT_CHAR(0x18)
172		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('V') PORT_CHAR('V') PORT_CHAR(0x16)
173		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('C') PORT_CHAR('C') PORT_CHAR(0x03)
174		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('D') PORT_CHAR('D') PORT_CHAR(0x04)
175		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('S') PORT_CHAR('S') PORT_CHAR(0x13)
176		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') PORT_CHAR('Z') PORT_CHAR(0x1a)
	169	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F') PORT_CHAR(0x06)
	170	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X') PORT_CHAR(0x18)
	171	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V') PORT_CHAR(0x16)
	172	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C') PORT_CHAR(0x03)
	173	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') PORT_CHAR(0x04)
	174	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') PORT_CHAR(0x13)
	175	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z') PORT_CHAR(0x1a)
177	176	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) //Z
178	177
179	178	PORT_START("KEY.7")    /* line 7 */
r242413	r242414
199	198	return data;
200	199	}
201	200
	201	WRITE8_MEMBER( excali64_state::ppic_w )
	202	{
	203	m_cass->output(BIT(data, 7) ? -1.0 : +1.0);
	204	}
	205
202	206	READ8_MEMBER( excali64_state::port00_r )
203	207	{
204	208	UINT8 data = 0xff;
r242413	r242414
216	220	d0 : /rom ; screen
217	221	d1 : ram on
218	222	d2 : /low ; high res
219		d3 : dispen
	223	d3 : 2nd colour set (previously, dispen, which is a mistake in hardware and schematic)
220	224	d4 : vsync
	225	d5 : rombank
221	226	*/
222	227	READ8_MEMBER( excali64_state::port50_r )
223	228	{
224		UINT8 data = m_sys_status & 7;
	229	UINT8 data = m_sys_status & 0x2f;
225	230	data |= (UINT8)m_crtc_vs << 4;
226		data |= (UINT8)m_crtc_de << 5;
227	231	return data;
228	232	}
229	233
230		WRITE8_MEMBER( excali64_state::ppic_w )
231		{
232		m_cass->output(BIT(data, 7) ? -1.0 : +1.0);
233		}
234
235	234	/*
236		d0,1,2 : same as port50
237		d7 : 2nd col
	235	d0,1,2,3,5 : same as port50
	236	(schematic wrongly says d7 used for 2nd colour set)
238	237	*/
239	238	WRITE8_MEMBER( excali64_state::port70_w )
240	239	{
241	240	m_sys_status = data;
	241	m_crtc->set_unscaled_clock(BIT(data, 2) ? 2e6 : 1e6);
	242	if BIT(data, 1)
	243	{
	244	// select 64k ram
	245	membank("bankr1")->set_entry(0);
	246	membank("bankr2")->set_entry(0);
	247	membank("bankr3")->set_entry(0);
	248	membank("bankw2")->set_entry(0);
	249	membank("bankw3")->set_entry(0);
	250	membank("bankw4")->set_entry(0);
	251	}
	252	else
	253	if BIT(data, 0)
	254	{
	255	// select videoram and hiresram for writing, and ROM for reading
	256	membank("bankr1")->set_entry(1);
	257	membank("bankr2")->set_entry(1);
	258	membank("bankr3")->set_entry(1);
	259	membank("bankw2")->set_entry(2);
	260	membank("bankw3")->set_entry(2);
	261	membank("bankw4")->set_entry(2);
	262	}
	263	else
	264	{
	265	// as above, except 4000-4FFF is main ram
	266	membank("bankr1")->set_entry(1);
	267	membank("bankr2")->set_entry(1);
	268	membank("bankr3")->set_entry(1);
	269	membank("bankw2")->set_entry(2);
	270	membank("bankw3")->set_entry(2);
	271	membank("bankw4")->set_entry(0);
	272	}
	273
	274	// other half of ROM_1
	275	if ((data & 0x22) == 0x20)
	276	membank("bankr1")->set_entry(2);
242	277	}
243	278
244		WRITE8_MEMBER( excali64_state::video_w )
	279	MACHINE_RESET_MEMBER( excali64_state, excali64 )
245	280	{
246		m_p_videoram[offset] = data;
	281	membank("bankr1")->set_entry(1); // read from ROM
	282	membank("bankr2")->set_entry(1); // read from ROM
	283	membank("bankr3")->set_entry(1); // read from ROM
	284	membank("bankr4")->set_entry(0); // read from RAM
	285	membank("bankw1")->set_entry(0); // write to RAM
	286	membank("bankw2")->set_entry(2); // write to videoram
	287	membank("bankw3")->set_entry(2); // write to hiresram
	288	membank("bankw4")->set_entry(0); // write to RAM
	289	m_maincpu->reset();
247	290	}
248	291
249	292	WRITE_LINE_MEMBER( excali64_state::crtc_de )
r242413	r242414
256	299	m_crtc_vs = state;
257	300	}
258	301
259		DRIVER_INIT_MEMBER( excali64_state, excali64 )
	302	/* F4 Character Displayer */
	303	static const gfx_layout excali64_charlayout =
260	304	{
	305	8, 12,                  /* 8 x 12 characters */
	306	256,                    /* 256 characters */
	307	1,                      /* 1 bits per pixel */
	308	{ 0 },                  /* no bitplanes */
	309	/* x offsets */
	310	{ 7, 6, 5, 4, 3, 2, 1, 0 },
	311	/* y offsets */
	312	{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8, 9*8, 10*8, 11*8 },
	313	8*16                    /* every char takes 16 bytes */
	314	};
	315
	316	static GFXDECODE_START( excali64 )
	317	GFXDECODE_ENTRY( "chargen", 0x0000, excali64_charlayout, 0, 1 )
	318	GFXDECODE_END
	319
	320	// The prom, the schematic, and the manual all contradict each other,
	321	// so the colours can only be described as wild guesses. Further, the 38
	322	// colour-load resistors are missing labels and values.
	323	PALETTE_INIT_MEMBER( excali64_state, excali64 )
	324	{
	325	// do this here because driver_init hasn't run yet
	326	m_p_videoram = memregion("videoram")->base();
261	327	m_p_chargen = memregion("chargen")->base();
262		m_p_videoram = memregion("videoram")->base();
	328	m_p_hiresram = memregion("hiresram")->base();
	329	UINT8 *main = memregion("roms")->base();
	330	UINT8 *ram = memregion("rambank")->base();
	331
	332	// main ram (cp/m mode)
	333	membank("bankr1")->configure_entry(0, &ram[0x0000]);
	334	membank("bankr2")->configure_entry(0, &ram[0x2000]);
	335	membank("bankr3")->configure_entry(0, &ram[0x3000]);
	336	membank("bankr4")->configure_entry(0, &ram[0x4000]);//boot
	337	membank("bankw1")->configure_entry(0, &ram[0x0000]);//boot
	338	membank("bankw2")->configure_entry(0, &ram[0x2000]);
	339	membank("bankw3")->configure_entry(0, &ram[0x3000]);
	340	membank("bankw4")->configure_entry(0, &ram[0x4000]);//boot
	341	// rom_1
	342	membank("bankr1")->configure_entry(1, &main[0x0000]);//boot
	343	membank("bankr1")->configure_entry(2, &main[0x2000]);
	344	// rom_2
	345	membank("bankr2")->configure_entry(1, &main[0x4000]);//boot
	346	membank("bankr3")->configure_entry(1, &main[0x5000]);//boot
	347	// videoram
	348	membank("bankw2")->configure_entry(2, &m_p_videoram[0x0000]);//boot
	349	// hiresram
	350	membank("bankw3")->configure_entry(2, &m_p_hiresram[0x0000]);//boot
	351	membank("bankw4")->configure_entry(2, &m_p_hiresram[0x0000]);
	352
	353	// Set up foreground palettes
	354	UINT8 r,g,b,i,code;
	355	for (i = 0; i < 32; i++)
	356	{
	357	code = m_p_chargen[0x1000+i];
	358	r = (BIT(code, 0) ? 38 : 0) + (BIT(code, 1) ? 73 : 0) + (BIT(code, 2) ? 144 : 0);
	359	b = (BIT(code, 3) ? 38 : 0) + (BIT(code, 4) ? 73 : 0) + (BIT(code, 5) ? 144 : 0);
	360	g = (BIT(code, 6) ? 85 : 0) + (BIT(code, 7) ? 170 : 0);
	361	palette.set_pen_color(i, r, g, b);
	362	}
	363
	364	// Background
	365	palette.set_pen_color(32, 0x00, 0x00, 0x00);  //  0 Black
	366	palette.set_pen_color(33, 0xff, 0x00, 0x00);  //  1 Red
	367	palette.set_pen_color(34, 0x00, 0x00, 0xff);  //  2 Blue
	368	palette.set_pen_color(35, 0xff, 0x00, 0xff);  //  3 Magenta
	369	palette.set_pen_color(36, 0x00, 0xff, 0x00);  //  4 Green
	370	palette.set_pen_color(37, 0xff, 0xff, 0x00);  //  5 Yellow
	371	palette.set_pen_color(38, 0x00, 0xff, 0xff);  //  6 Cyan
	372	palette.set_pen_color(39, 0xff, 0xff, 0xff);  //  7 White
263	373	}
264	374
265	375	MC6845_UPDATE_ROW( excali64_state::update_row )
266	376	{
267	377	const rgb_t *palette = m_palette->palette()->entry_list_raw();
268		UINT8 chr,gfx;
	378	UINT8 chr,gfx,col,bg,fg;
269	379	UINT16 mem,x;
	380	UINT8 col_base = BIT(m_sys_status, 3) ? 16 : 0;
270	381	UINT32 *p = &bitmap.pix32(y);
271	382
272	383	for (x = 0; x < x_count; x++)
273	384	{
274		UINT8 inv=0;
275		if (x == cursor_x) inv=0xff;
276		mem = (ma + x) & 0xfff;
	385	mem = (ma + x) & 0x7ff;
277	386	chr = m_p_videoram[mem];
278		gfx = m_p_chargen[(chr<<4) | ra] ^ inv;
	387	col = m_p_videoram[mem+0x800];
	388	fg = col_base + (col >> 4);
	389	bg = 32 + ((col >> 1) & 7);
279	390
	391	if (BIT(col, 0) & BIT(chr, 7))
	392	gfx = m_p_hiresram[(chr<<4) | ra]; // hires definition
	393	else
	394	gfx = m_p_chargen[(chr<<4) | ra]; // normal character
	395
	396	gfx ^= (x == cursor_x) ? 0xff : 0;
	397
280	398	/* Display a scanline of a character */
281		*p++ = palette[BIT(gfx, 0)];
282		*p++ = palette[BIT(gfx, 1)];
283		*p++ = palette[BIT(gfx, 2)];
284		*p++ = palette[BIT(gfx, 3)];
285		*p++ = palette[BIT(gfx, 4)];
286		*p++ = palette[BIT(gfx, 5)];
287		*p++ = palette[BIT(gfx, 6)];
288		*p++ = palette[BIT(gfx, 7)];
	399	*p++ = palette[BIT(gfx, 0) ? fg : bg];
	400	*p++ = palette[BIT(gfx, 1) ? fg : bg];
	401	*p++ = palette[BIT(gfx, 2) ? fg : bg];
	402	*p++ = palette[BIT(gfx, 3) ? fg : bg];
	403	*p++ = palette[BIT(gfx, 4) ? fg : bg];
	404	*p++ = palette[BIT(gfx, 5) ? fg : bg];
	405	*p++ = palette[BIT(gfx, 6) ? fg : bg];
	406	*p++ = palette[BIT(gfx, 7) ? fg : bg];
289	407	}
290	408	}
291	409
r242413	r242414
295	413	MCFG_CPU_PROGRAM_MAP(excali64_mem)
296	414	MCFG_CPU_IO_MAP(excali64_io)
297	415
	416	MCFG_MACHINE_RESET_OVERRIDE(excali64_state, excali64)
	417
298	418	MCFG_DEVICE_ADD("uart", I8251, 0)
299	419	//MCFG_I8251_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
300	420	//MCFG_I8251_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
r242413	r242414
328	448	MCFG_SCREEN_ADD("screen", RASTER)
329	449	MCFG_SCREEN_REFRESH_RATE(50)
330	450	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
331		MCFG_SCREEN_SIZE(80*8, 25*10)
332		MCFG_SCREEN_VISIBLE_AREA(0, 80*8-1, 0, 25*10-1)
	451	MCFG_SCREEN_SIZE(80*8, 24*12)
	452	MCFG_SCREEN_VISIBLE_AREA(0, 80*8-1, 0, 24*12-1)
333	453	MCFG_SCREEN_UPDATE_DEVICE("crtc", mc6845_device, screen_update)
334		MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
	454	MCFG_PALETTE_ADD("palette", 40)
	455	MCFG_PALETTE_INIT_OWNER(excali64_state, excali64)
	456	//MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
	457	MCFG_GFXDECODE_ADD("gfxdecode", "palette", excali64)
335	458	MCFG_MC6845_ADD("crtc", MC6845, "screen", XTAL_16MHz / 16) // 1MHz for lowres; 2MHz for highres
336	459	MCFG_MC6845_SHOW_BORDER_AREA(false)
337	460	MCFG_MC6845_CHAR_WIDTH(8)
r242413	r242414
345	468
346	469	/* ROM definition */
347	470	ROM_START( excali64 )
348		ROM_REGION(0x10000, "maincpu", 0)
349		ROM_LOAD( "rom_1.bin", 0x0000, 0x4000, CRC(e129a305) SHA1(e43ec7d040c2b2e548d22fd6bbc7df8b45a26e5a) )
350		ROM_LOAD( "rom_2.bin", 0x2000, 0x2000, CRC(916d9f5a) SHA1(91c527cce963481b7bebf077e955ca89578bb553) )
	471	ROM_REGION(0x6000, "roms", 0)
	472	ROM_LOAD( "rom_1.ic17", 0x0000, 0x4000, CRC(e129a305) SHA1(e43ec7d040c2b2e548d22fd6bbc7df8b45a26e5a) )
	473	ROM_LOAD( "rom_2.ic24", 0x4000, 0x2000, CRC(916d9f5a) SHA1(91c527cce963481b7bebf077e955ca89578bb553) )
	474	// fix a bug that causes screen to be filled with 'p'
	475	ROM_FILL(0x4ee, 1, 0)
	476	ROM_FILL(0x4ef, 1, 8)
	477	ROM_FILL(0x4f6, 1, 0)
	478	ROM_FILL(0x4f7, 1, 8)
351	479
352		ROM_REGION(0x2000, "videoram", ROMREGION_ERASE00)
	480	ROM_REGION(0x10000, "rambank", ROMREGION_ERASE00)
	481	ROM_REGION(0x1000, "videoram", ROMREGION_ERASE00)
	482	ROM_REGION(0x1000, "hiresram", ROMREGION_ERASE00)
353	483
354		ROM_REGION(0x1000, "chargen", 0)
355		ROM_LOAD( "genex_3.bin", 0x0000, 0x1000, CRC(b91619a9) SHA1(2ced636cb7b94ba9d329868d7ecf79963cefe9d9) )
	484	ROM_REGION(0x1020, "chargen", 0)
	485	ROM_LOAD( "genex_3.ic43", 0x0000, 0x1000, CRC(b91619a9) SHA1(2ced636cb7b94ba9d329868d7ecf79963cefe9d9) )
	486	ROM_LOAD( "hm7603.ic55",  0x1000, 0x0020, CRC(c74f47dc) SHA1(331ff3c913846191ddd97cacb80bd19438c1ff71) )
356	487	ROM_END
357	488
358	489	/* Driver */
359	490
360		/*    YEAR  NAME      PARENT  COMPAT   MACHINE    INPUT     CLASS             INIT        COMPANY         FULLNAME        FLAGS */
361		COMP( 1984, excali64, 0,      0,       excali64,  excali64, excali64_state, excali64,  "BGR Computers", "Excalibur 64", GAME_IS_SKELETON )
	491	/*    YEAR  NAME      PARENT  COMPAT   MACHINE    INPUT     CLASS         INIT        COMPANY         FULLNAME        FLAGS */
	492	COMP( 1984, excali64, 0,      0,       excali64,  excali64, driver_device, 0,  "BGR Computers", "Excalibur 64", GAME_NOT_WORKING )

trunk/src/mess/drivers/hp16500.c

r242413	r242414
1		/*
2		Hewlett-Packard HP16500b Logic Analyzer
	1	/***************************************************************************
	2
	3	Hewlett-Packard HP16500b Logic Analyzer
3	4
4	5	MC68EC030 @ 25 MHz
5	6
r242413	r242414
15	16	IRQ 5 = 814a
16	17	IRQ 6 = 35c8 (jump 840120)
17	18	IRQ 7 = 35d4 (jump 840120)
18		*/
19	19
	20	****************************************************************************/
20	21
21	22	#include "emu.h"
22	23	#include "cpu/m68000/m68000.h"
23	24
24
25	25	class hp16500_state : public driver_device
26	26	{
27	27	public:
28	28	hp16500_state(const machine_config &mconfig, device_type type, const char *tag)
29		: driver_device(mconfig, type, tag) ,
30		m_maincpu(*this, "maincpu") { }
	29	: driver_device(mconfig, type, tag),
	30	m_maincpu(*this, "maincpu"),
	31	m_vram(*this, "vram")
	32	{ }
31	33
32	34	virtual void video_start();
33	35	UINT32 screen_update_hp16500(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	36
34	37	required_device<cpu_device> m_maincpu;
	38	required_shared_ptr<UINT32> m_vram;
	39
	40
	41	DECLARE_WRITE32_MEMBER(palette_w);
	42
	43	private:
	44	UINT32 m_palette[256], m_colors[3], m_count, m_clutoffs;
35	45	};
36	46
37
38	47	static ADDRESS_MAP_START(hp16500_map, AS_PROGRAM, 32, hp16500_state)
39	48	AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_REGION("bios", 0)
40		AM_RANGE(0x00600000, 0x0063ffff) AM_RAM
	49	AM_RANGE(0x0020f000, 0x0020f003) AM_WRITE(palette_w)
	50	AM_RANGE(0x00600000, 0x0063ffff) AM_RAM AM_SHARE("vram")
41	51	AM_RANGE(0x00800000, 0x009fffff) AM_RAM     // 284e end of test - d0 = 0 for pass
42	52	ADDRESS_MAP_END
43	53
44	54	void hp16500_state::video_start()
45	55	{
	56	m_count = 0;
	57	m_clutoffs = 0;
	58	memset(m_palette, 0, sizeof(m_palette));
46	59	}
47	60
	61	WRITE32_MEMBER(hp16500_state::palette_w)
	62	{
	63	if (mem_mask == 0xff000000)
	64	{
	65	m_clutoffs = (data>>24) & 0xff;
	66	}
	67	else if (mem_mask == 0x00ff0000)
	68	{
	69	UINT8 tmpcolor = (data>>16) & 0xff;
	70
	71	if ((tmpcolor & 0xf0) == 0x00)
	72	{
	73	tmpcolor |= (tmpcolor << 4);
	74	}
	75
	76	m_colors[m_count++] = tmpcolor;
	77
	78	if (m_count == 3)
	79	{
	80	m_palette[m_clutoffs] = rgb_t(m_colors[0], m_colors[1], m_colors[2]);
	81	m_clutoffs++;
	82	if (m_clutoffs > 255)
	83	{
	84	m_clutoffs = 0;
	85	}
	86	m_count = 0;
	87	}
	88	}
	89	}
	90
	91	// 4 bpp
	92	// addr = ((Y * 0xfc0) + 0x360) + (X * 4)
48	93	UINT32 hp16500_state::screen_update_hp16500(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
49	94	{
	95	UINT32 *scanline;
	96	int x, y;
	97	UINT32 pixels;
	98
	99	for (y = 0; y < 400; y++)
	100	{
	101	scanline = &bitmap.pix32(y);
	102
	103	for (x = 0; x < 576/8; x++)
	104	{
	105	pixels = m_vram[(y * (288/4)) + x];
	106
	107	UINT8 gfx = ((pixels & 0xf0000) >> 12) | (pixels & 15);
	108	*scanline++ = m_palette[BIT(gfx, 7) ? 2 : 0];
	109	*scanline++ = m_palette[BIT(gfx, 6) ? 2 : 0];
	110	*scanline++ = m_palette[BIT(gfx, 5) ? 2 : 0];
	111	*scanline++ = m_palette[BIT(gfx, 4) ? 2 : 0];
	112	*scanline++ = m_palette[BIT(gfx, 3) ? 2 : 0];
	113	*scanline++ = m_palette[BIT(gfx, 2) ? 2 : 0];
	114	*scanline++ = m_palette[BIT(gfx, 1) ? 2 : 0];
	115	*scanline++ = m_palette[BIT(gfx, 0) ? 2 : 0];
	116	#if 0
	117	*scanline++ = m_palette[((pixels&0xf0000000)>>28)];
	118	*scanline++ = m_palette[((pixels&0xf000000)>>24)];
	119	*scanline++ = m_palette[((pixels&0xf00000)>>20)];
	120	*scanline++ = m_palette[((pixels&0xf0000)>>16)];
	121	*scanline++ = m_palette[((pixels&0xf000)>>12)];
	122	*scanline++ = m_palette[((pixels&0xf00)>>8)];
	123	*scanline++ = m_palette[((pixels&0xf0)>>4)];
	124	*scanline++ = m_palette[(pixels&0xf)];
	125	#endif
	126	}
	127	}
	128
50	129	return 0;
51	130	}
52	131
r242413	r242414
56	135	MCFG_CPU_PROGRAM_MAP(hp16500_map)
57	136
58	137	MCFG_SCREEN_ADD("screen", RASTER)
59		MCFG_SCREEN_RAW_PARAMS(25175000, 800, 0, 640, 525, 0, 480)
60		MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
61		MCFG_SCREEN_SIZE(1024, 768)
62		MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
63	138	MCFG_SCREEN_UPDATE_DRIVER(hp16500_state, screen_update_hp16500)
	139	MCFG_SCREEN_SIZE(576,400)
	140	MCFG_SCREEN_VISIBLE_AREA(0, 576-1, 0, 400-1)
	141	MCFG_SCREEN_REFRESH_RATE(60)
64	142
65		MCFG_PALETTE_ADD("palette", 256)
66
67
68	143	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
69	144	MACHINE_CONFIG_END
70	145

trunk/src/mess/drivers/hp9k_3xx.c

r0	r242414
	1	// license:BSD-3-Clause
	2	// copyright-holders:R. Belmont
	3	/***************************************************************************
	4
	5	hp9k3xx.c: preliminary driver for HP9000 300 Series (aka HP9000/3xx)
	6
	7	Currently supporting:
	8
	9	320:
	10	MC68020 CPU @ 16.67 MHz
	11	HP custom MMU
	12	MC68881 FPU
	13
	14	330:
	15	MC68020 CPU @ 16.67 MHz
	16	MC68851 MMU
	17	MC68881 FPU
	18
	19	All models have an MC6840 PIT on IRQ6 clocked at 250 kHz.
	20
	21	TODO:
	22	BBCADDR   0x420000
	23	RTC_DATA: 0x420001
	24	RTC_CMD:  0x420003
	25	HIL:      0x428000
	26	HPIB:     0x478000
	27	KBDNMIST: 0x478005
	28	DMA:      0x500000
	29	FRAMEBUF: 0x560000
	30
	31	6840:     0x5F8001/3/5/7/9, IRQ 6
	32
	33	****************************************************************************/
	34
	35	#include "emu.h"
	36	#include "cpu/m68000/m68000.h"
	37	#include "machine/6840ptm.h"
	38
	39	#define MAINCPU_TAG "maincpu"
	40	#define PTM6840_TAG "ptm"
	41
	42	class hp9k3xx_state : public driver_device
	43	{
	44	public:
	45	hp9k3xx_state(const machine_config &mconfig, device_type type, const char *tag)
	46	: driver_device(mconfig, type, tag),
	47	m_maincpu(*this, MAINCPU_TAG),
	48	m_vram(*this, "vram")
	49	{ }
	50
	51	required_device<cpu_device> m_maincpu;
	52	virtual void machine_reset();
	53
	54	optional_shared_ptr<UINT32> m_vram;
	55
	56	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	57	UINT32 hp98544_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	58
	59	DECLARE_READ32_MEMBER(buserror_r);
	60	DECLARE_WRITE32_MEMBER(buserror_w);
	61
	62	private:
	63	};
	64
	65	UINT32 hp9k3xx_state::hp98544_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	66	{
	67	UINT32 *scanline;
	68	int x, y;
	69	UINT32 pixels;
	70	UINT32 m_palette[2] = { 0x00000000, 0xffffffff };
	71
	72	for (y = 0; y < 768; y++)
	73	{
	74	scanline = &bitmap.pix32(y);
	75	for (x = 0; x < 1024/4; x++)
	76	{
	77	pixels = m_vram[(y * 256) + x];
	78
	79	*scanline++ = m_palette[(pixels>>24) & 1];
	80	*scanline++ = m_palette[(pixels>>16) & 1];
	81	*scanline++ = m_palette[(pixels>>8) & 1];
	82	*scanline++ = m_palette[(pixels & 1)];
	83	}
	84	}
	85
	86	return 0;
	87	}
	88
	89	// shared mappings for all 9000/3xx systems
	90	static ADDRESS_MAP_START(hp9k3xx_common, AS_PROGRAM, 32, hp9k3xx_state)
	91	AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_REGION("maincpu",0) AM_WRITENOP   // writes to 1fffc are the LED
	92
	93	AM_RANGE(0x00200000, 0x002fffff) AM_RAM AM_SHARE("vram")   // 98544 mono framebuffer
	94	AM_RANGE(0x00560000, 0x00563fff) AM_ROM AM_REGION("graphics", 0x0000)   // 98544 mono ROM
	95
	96	AM_RANGE(0x00510000, 0x00510003) AM_READWRITE(buserror_r, buserror_w)    // no "Alpha display"
	97	AM_RANGE(0x00538000, 0x00538003) AM_READWRITE(buserror_r, buserror_w)   // no "Graphics"
	98	AM_RANGE(0x005c0000, 0x005c0003) AM_READWRITE(buserror_r, buserror_w)   // no add-on FP coprocessor
	99	AM_RANGE(0x005f8000, 0x005f800f) AM_DEVREADWRITE8(PTM6840_TAG, ptm6840_device, read, write, 0x00ff00ff)
	100	ADDRESS_MAP_END
	101
	102	// 9000/320
	103	static ADDRESS_MAP_START(hp9k320_map, AS_PROGRAM, 32, hp9k3xx_state)
	104	AM_RANGE(0xffe00000, 0xffefffff) AM_READWRITE(buserror_r, buserror_w)
	105	AM_RANGE(0xfff00000, 0xffffffff) AM_RAM
	106
	107	AM_IMPORT_FROM(hp9k3xx_common)
	108	ADDRESS_MAP_END
	109
	110
	111	static ADDRESS_MAP_START(hp9k330_map, AS_PROGRAM, 32, hp9k3xx_state)
	112	AM_RANGE(0xffb00000, 0xffbfffff) AM_READWRITE(buserror_r, buserror_w)
	113	AM_RANGE(0xffc00000, 0xffffffff) AM_RAM
	114
	115	AM_IMPORT_FROM(hp9k3xx_common)
	116	ADDRESS_MAP_END
	117
	118	UINT32 hp9k3xx_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
	119	{
	120	return 0;
	121	}
	122
	123	/* Input ports */
	124	static INPUT_PORTS_START( hp9k330 )
	125	INPUT_PORTS_END
	126
	127
	128	void hp9k3xx_state::machine_reset()
	129	{
	130	}
	131
	132	READ32_MEMBER(hp9k3xx_state::buserror_r)
	133	{
	134	m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
	135	m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
	136	return 0;
	137	}
	138
	139	WRITE32_MEMBER(hp9k3xx_state::buserror_w)
	140	{
	141	m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
	142	m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
	143	}
	144
	145	static MACHINE_CONFIG_START( hp9k320, hp9k3xx_state )
	146	/* basic machine hardware */
	147	MCFG_CPU_ADD(MAINCPU_TAG, M68020, 16670000)
	148	MCFG_CPU_PROGRAM_MAP(hp9k320_map)
	149
	150	MCFG_DEVICE_ADD(PTM6840_TAG, PTM6840, 0)
	151	MCFG_PTM6840_INTERNAL_CLOCK(250000.0f)   // from oscillator module next to the 6840
	152	MCFG_PTM6840_EXTERNAL_CLOCKS(250000.0f, 250000.0f, 250000.0f)
	153
	154	MCFG_SCREEN_ADD( "screen", RASTER)
	155	MCFG_SCREEN_UPDATE_DRIVER(hp9k3xx_state, hp98544_update)
	156	MCFG_SCREEN_SIZE(1024,768)
	157	MCFG_SCREEN_VISIBLE_AREA(0, 1024-1, 0, 768-1)
	158	MCFG_SCREEN_REFRESH_RATE(70)
	159	MACHINE_CONFIG_END
	160
	161	static MACHINE_CONFIG_START( hp9k330, hp9k3xx_state )
	162	/* basic machine hardware */
	163	MCFG_CPU_ADD(MAINCPU_TAG, M68020PMMU, 16670000)
	164	MCFG_CPU_PROGRAM_MAP(hp9k330_map)
	165
	166	MCFG_DEVICE_ADD(PTM6840_TAG, PTM6840, 0)
	167	MCFG_PTM6840_INTERNAL_CLOCK(250000.0f)   // from oscillator module next to the 6840
	168	MCFG_PTM6840_EXTERNAL_CLOCKS(250000.0f, 250000.0f, 250000.0f)
	169
	170	MCFG_SCREEN_ADD( "screen", RASTER)
	171	MCFG_SCREEN_UPDATE_DRIVER(hp9k3xx_state, hp98544_update)
	172	MCFG_SCREEN_SIZE(1024,768)
	173	MCFG_SCREEN_VISIBLE_AREA(0, 1024-1, 0, 768-1)
	174	MCFG_SCREEN_REFRESH_RATE(70)
	175	MACHINE_CONFIG_END
	176
	177	ROM_START( hp9k320 )
	178	ROM_REGION( 0x20000, MAINCPU_TAG, 0 )
	179	ROM_LOAD16_BYTE( "5061-6538.bin", 0x000001, 0x004000, CRC(d6aafeb1) SHA1(88c6b0b2f504303cbbac0c496c26b85458ac5d63) )
	180	ROM_LOAD16_BYTE( "5061-6539.bin", 0x000000, 0x004000, CRC(a7ff104c) SHA1(c640fe68314654716bd41b04c6a7f4e560036c7e) )
	181	ROM_LOAD16_BYTE( "5061-6540.bin", 0x008001, 0x004000, CRC(4f6796d6) SHA1(fd254897ac1afb8628f40ea93213f60a082c8d36) )
	182	ROM_LOAD16_BYTE( "5061-6541.bin", 0x008000, 0x004000, CRC(39d32998) SHA1(6de1bda75187b0878c03c074942b807cf2924f0e) )
	183
	184	ROM_REGION( 0x4000, "graphics", ROMREGION_ERASEFF | ROMREGION_BE | ROMREGION_32BIT )
	185	ROM_LOAD16_BYTE( "98544_1818-1999.bin", 0x000001, 0x002000, CRC(8c7d6480) SHA1(d2bcfd39452c38bc652df39f84c7041cfdf6bd51) )
	186	ROM_END
	187
	188	ROM_START( hp9k330 )
	189	ROM_REGION( 0x20000, MAINCPU_TAG, 0 )
	190	ROM_LOAD16_BYTE( "1818-4416.bin", 0x000000, 0x010000, CRC(cd71e85e) SHA1(3e83a80682f733417fdc3720410e45a2cfdcf869) )
	191	ROM_LOAD16_BYTE( "1818-4417.bin", 0x000001, 0x010000, CRC(374d49db) SHA1(a12cbf6c151e2f421da4571000b5dffa3ef403b3) )
	192
	193	ROM_REGION( 0x4000, "graphics", ROMREGION_ERASEFF | ROMREGION_BE | ROMREGION_32BIT )
	194	ROM_LOAD16_BYTE( "98544_1818-1999.bin", 0x000001, 0x002000, CRC(8c7d6480) SHA1(d2bcfd39452c38bc652df39f84c7041cfdf6bd51) )
	195	ROM_END
	196
	197	/*    YEAR  NAME    PARENT  COMPAT  MACHINE   INPUT                 INIT    COMPANY          FULLNAME       FLAGS */
	198	COMP( 1985, hp9k320, 0,     0,      hp9k320,  hp9k330, driver_device, 0, "Hewlett-Packard", "HP9000/320", GAME_NOT_WORKING | GAME_NO_SOUND)
	199	COMP( 1987, hp9k330, 0,     0,      hp9k330,  hp9k330, driver_device, 0, "Hewlett-Packard", "HP9000/330", GAME_NOT_WORKING | GAME_NO_SOUND)

trunk/src/mess/drivers/if800.c

r242413	r242414
23	23
24	24	required_device<upd7220_device> m_hgdc;
25	25
26		required_shared_ptr<UINT8> m_video_ram;
	26	required_shared_ptr<UINT16> m_video_ram;
27	27	virtual void machine_start();
28	28	virtual void machine_reset();
29	29	required_device<cpu_device> m_maincpu;
r242413	r242414
38	38	int xi,gfx;
39	39	UINT8 pen;
40	40
41		gfx = m_video_ram[address];
	41	gfx = m_video_ram[address >> 1];
42	42
43		for(xi=0;xi<8;xi++)
	43	for(xi=0;xi<16;xi++)
44	44	{
45	45	pen = ((gfx >> xi) & 1) ? 1 : 0;
46	46
r242413	r242414
73	73	{
74	74	}
75	75
76		static ADDRESS_MAP_START( upd7220_map, AS_0, 8, if800_state )
	76	static ADDRESS_MAP_START( upd7220_map, AS_0, 16, if800_state )
77	77	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram")
78	78	ADDRESS_MAP_END
79	79

trunk/src/mess/drivers/iskr103x.c

r242413	r242414
77	77	MCFG_IBM5160_MOTHERBOARD_ADD("mb","maincpu")
78	78	MCFG_DEVICE_INPUT_DEFAULTS(iskr1030m)
79	79
80		MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", iskr103x_isa8_cards, "cga_iskr1030m", false)   // actually MDA?
	80	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", iskr103x_isa8_cards, "cga_iskr1030m", false)
81	81	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", iskr103x_isa8_cards, "fdc_xt", false)
82		MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", iskr103x_isa8_cards, NULL, false) // hdc is WIP
	82	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", iskr103x_isa8_cards, NULL, false)
83	83	MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", iskr103x_isa8_cards, NULL, false)
84	84	MCFG_ISA8_SLOT_ADD("mb:isa", "isa5", iskr103x_isa8_cards, NULL, false)
85	85	MCFG_ISA8_SLOT_ADD("mb:isa", "isa6", iskr103x_isa8_cards, NULL, false)
r242413	r242414
103	103
104	104	MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", iskr103x_isa8_cards, "cga_iskr1031", false)
105	105	MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", iskr103x_isa8_cards, "fdc_xt", false)
106		MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", iskr103x_isa8_cards, NULL, false) // hdc is WIP
	106	MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", iskr103x_isa8_cards, NULL, false)
107	107	MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", iskr103x_isa8_cards, NULL, false)
108	108	MCFG_ISA8_SLOT_ADD("mb:isa", "isa5", iskr103x_isa8_cards, NULL, false)
109	109	MCFG_ISA8_SLOT_ADD("mb:isa", "isa6", iskr103x_isa8_cards, NULL, false)

trunk/src/mess/drivers/leapster.c

r242413	r242414
215	215	public:
216	216	leapster_state(const machine_config &mconfig, device_type type, const char *tag)
217	217	: driver_device(mconfig, type, tag),
	218	m_maincpu(*this, "maincpu"),
218	219	m_cart(*this, "cartslot")
219	220	{ }
220	221
r242413	r242414
227	228	DECLARE_DRIVER_INIT(leapster);
228	229
229	230	protected:
	231	required_device<cpu_device> m_maincpu;
230	232	required_device<generic_slot_device> m_cart;
231	233
232	234	memory_region *m_cart_rom;
r242413	r242414
259	261	{
260	262	astring region_tag;
261	263	m_cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
262		membank("cartrom")->set_base(m_cart_rom->base());
	264
	265	if (m_cart_rom)
	266	{
	267	address_space &space = m_maincpu->space(AS_PROGRAM);
	268
	269	space.install_readwrite_bank(0x80000000, 0x807fffff, "cartrom");
	270	membank("cartrom")->set_base(m_cart_rom->base());
	271	}
263	272	}
264	273
265	274	void leapster_state::machine_reset()
r242413	r242414
268	277
269	278	static ADDRESS_MAP_START( leapster_map, AS_PROGRAM, 32, leapster_state )
270	279	AM_RANGE(0x00000000, 0x001fffff) AM_ROM AM_MIRROR(0x40000000) // pointers in the bios region seem to be to the 40xxxxxx region, either we mirror there or something (real bios?) is acutally missing
271		AM_RANGE(0x80000000, 0x807fffff) AM_ROMBANK("cartrom") // game ROM pointers are all to the 80xxxxxx region, so I assume it maps here
272
	280	//   AM_RANGE(0x80000000, 0x807fffff) AM_ROMBANK("cartrom") // game ROM pointers are all to the 80xxxxxx region, so I assume it maps here - installed if a cart is present
273	281	ADDRESS_MAP_END
274	282
275	283	static MACHINE_CONFIG_START( leapster, leapster_state )

trunk/src/mess/drivers/mathmagi.c

r242413	r242414
3	3	/***************************************************************************
4	4
5	5	APF Mathemagician
6		* TMS1100 MP1030
	6	* TMS1100 MP1030 - MCU
	7	* 2 x DS8870N - Hex LED Digit Driver
	8	* 2 x DS8861N - MOS-to-LED 5-Segment Driver
7	9
	10	This is a tabletop educational calculator. It came with plastic overlays
	11	for playing different kind of games. Refer to the manual on how to use it.
	12	In short, to start from scratch, press [SEL]. By default the device is in
	13	calculator teaching mode. If [SEL] is followed with 1-6 and then [NXT],
	14	one of the games is started.
	15
	16	1) Number Machine
	17	2) Countin' On
	18	3) Walk The Plank
	19	4) Gooey Gumdrop
	20	5) Football
	21	6) Lunar Lander
	22
	23
	24	TODO:
	25	- some of the led symbols are probably wrong, output PLA is unknown
	26	- microinstructions PLA is not verified
	27
8	28	***************************************************************************/
9	29
10	30	#include "emu.h"
r242413	r242414
26	46	m_button_matrix(*this, "IN")
27	47	{ }
28	48
29		required_device<cpu_device> m_maincpu;
30		optional_ioport_array<11> m_button_matrix;
	49	required_device<tms1xxx_cpu_device> m_maincpu;
	50	required_ioport_array<6> m_button_matrix;
31	51
32	52	UINT16 m_o;
33	53	UINT16 m_r;
r242413	r242414
48	68
49	69	READ8_MEMBER(mathmagi_state::read_k)
50	70	{
51		printf("r");
52
53	71	UINT8 k = 0;
54	72
55	73	// read selected button rows
56		for (int i = 0; i < 11; i++)
57		if (m_r >> i & 1)
	74	for (int i = 0; i < 6; i++)
	75	{
	76	const int ki[6] = { 3, 5, 6, 7, 9, 10 };
	77	if (m_r >> ki[i] & 1)
58	78	k |= m_button_matrix[i]->read();
	79	}
59	80
60	81	return k;
61	82	}
62	83
63	84	WRITE16_MEMBER(mathmagi_state::write_o)
64	85	{
	86	// O1-O7: led segments A-G
	87	// O0: N/C
65	88	m_o = data;
66
67		printf("\n%02X ",m_o);
68		for (int i=0;i<11;i++) printf("%d",m_r>>(10-i)&1);
69	89	}
70	90
71	91	WRITE16_MEMBER(mathmagi_state::write_r)
72	92	{
	93	// R3,R5-R7,R9,R10: input mux
	94	// and outputs:
	95	for (int i = 0; i < 11; i++)
	96	{
	97	if (data >> i & 1)
	98	{
	99	// R8: custom math symbols digit
	100	// R9: custom equals digit
	101	// R10: lamps
	102	if (i >= 8)
	103	for (int j = 0; j < 8; j++)
	104	output_set_lamp_value(i*10 + j, m_o >> j & 1);
	105
	106	// R0-R7: 7seg leds
	107	else
	108	output_set_digit_value(i, m_o >> 1 & 0x7f);
	109	}
	110	}
	111
73	112	m_r = data;
74
75		printf("\n%02X ",m_o);
76		for (int i=0;i<11;i++) printf("%d",m_r>>(10-i)&1);
77	113	}
78	114
79	115
r242413	r242414
94	130	*/
95	131
96	132	static INPUT_PORTS_START( mathmagi )
97		PORT_START("IN.0") // R0
98		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1)
99		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2)
100		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3)
101		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4)
	133	PORT_START("IN.0") // R3
	134	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("1")
	135	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("2")
	136	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
	137	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS_PAD) PORT_NAME("-")
102	138
103		PORT_START("IN.1") // R1
104		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5)
105		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6)
106		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7)
107		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8)
	139	PORT_START("IN.1") // R5
	140	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("0")
	141	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SPACE) PORT_NAME("_") // blank
	142	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_NAME("r")
	143	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_PLUS_PAD) PORT_NAME("+")
108	144
109		PORT_START("IN.2") // R2
110		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9)
111		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0)
112		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q)
113		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W)
	145	PORT_START("IN.2") // R6
	146	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("4")
	147	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("5")
	148	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
	149	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ASTERISK) PORT_NAME(UTF8_MULTIPLY)
114	150
115		PORT_START("IN.3") // R3
116		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E)
117		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R)
118		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T)
119		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y)
	151	PORT_START("IN.3") // R7
	152	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_NAME("SEL")
	153	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_NAME("NXT")
	154	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_NAME("?") // check
	155	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ENTER) PORT_CODE(KEYCODE_ENTER_PAD) PORT_NAME("=")
120	156
121		PORT_START("IN.4") // R4
122		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U)
123		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I)
124		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O)
125		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A)
	157	PORT_START("IN.4") // R9
	158	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("7")
	159	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("8")
	160	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
	161	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH_PAD) PORT_NAME(UTF8_DIVIDE)
126	162
127		PORT_START("IN.5") // R5
128		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S)
129		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D)
130		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F)
131		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G)
132
133		PORT_START("IN.6") // R6
134		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H)
135		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J)
136		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K)
137		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L)
138
139		PORT_START("IN.7") // R7
140		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z)
141		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X)
142		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C)
143		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V)
144
145		PORT_START("IN.8") // R8
146		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B)
147		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N)
148		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M)
149		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA)
150
151		PORT_START("IN.9") // R9
152		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0_PAD)
153		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1_PAD)
154		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2_PAD)
155		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3_PAD)
156
157		PORT_START("IN.10") // R10
158		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4_PAD) // 1P/2P switch?
159		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5_PAD)
160		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6_PAD)
161		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7_PAD)
	163	PORT_START("IN.5") // R10
	164	PORT_CONFNAME( 0x01, 0x00, "Players")
	165	PORT_CONFSETTING(    0x00, "1" )
	166	PORT_CONFSETTING(    0x01, "2" )
	167	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNUSED )
	168	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
	169	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
162	170	INPUT_PORTS_END
163	171
164	172
r242413	r242414
178	186	save_item(NAME(m_r));
179	187	}
180	188
	189	// LED segments A-G
	190	enum
	191	{
	192	lA = 0x02,
	193	lB = 0x04,
	194	lC = 0x08,
	195	lD = 0x10,
	196	lE = 0x20,
	197	lF = 0x40,
	198	lG = 0x80
	199	};
181	200
182	201	static const UINT16 mathmagi_output_pla[0x20] =
183	202	{
184		/* O output PLA configuration currently unknown */
185		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
186		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
187		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
188		0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
	203	lA+lB+lC+lD+lE+lF,      // 0
	204	lB+lC,                  // 1
	205	lA+lB+lG+lE+lD,         // 2
	206	lA+lB+lG+lC+lD,         // 3
	207	lF+lB+lG+lC,            // 4
	208	lA+lF+lG+lC+lD,         // 5
	209	lA+lF+lG+lC+lD+lE,      // 6
	210	lA+lB+lC,               // 7
	211	lA+lB+lC+lD+lE+lF+lG,   // 8
	212	lA+lB+lG+lF+lC+lD,      // 9
	213	lA+lB+lG+lE,            // question mark
	214	lE+lG,                  // r
	215	lD,                     // underscore?
	216	lA+lF+lG+lE+lD,         // E
	217	lG,                     // -
	218	0,                      // empty
	219	0,                      // empty
	220	lG,                     // lamp 4 or MATH -
	221	lD,                     // lamp 3
	222	lF+lE+lD+lC+lG,         // b
	223	lB,                     // lamp 2
	224	lB+lG,                  // MATH +
	225	lB+lC,                  // MATH mul
	226	lF+lG+lB+lC+lD,         // y
	227	lA,                     // lamp 1
	228	lA+lG,                  // MATH div
	229	lA+lD,                  // EQUALS
	230	0,                      // ?
	231	0,                      // ?
	232	lE+lD+lC+lG,            // o
	233	0,                      // ?
	234	lA+lF+lE+lD+lC          // G
189	235	};
190	236
191	237
192	238	static MACHINE_CONFIG_START( mathmagi, mathmagi_state )
193	239
194	240	/* basic machine hardware */
195		//   MCFG_CPU_ADD("maincpu", TMS1100, MASTER_CLOCK)
196		MCFG_CPU_ADD("maincpu", TMS1100, 10000) // temp
	241	MCFG_CPU_ADD("maincpu", TMS1100, MASTER_CLOCK)
197	242	MCFG_TMS1XXX_OUTPUT_PLA(mathmagi_output_pla)
198	243	MCFG_TMS1XXX_READ_K_CB(READ8(mathmagi_state, read_k))
199	244	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(mathmagi_state, write_o))
r242413	r242414
225	270	ROM_END
226	271
227	272
228		COMP( 1980, mathmagi, 0, 0, mathmagi, mathmagi, driver_device, 0, "APF Electronics Inc.", "Mathemagician", GAME_SUPPORTS_SAVE | GAME_NO_SOUND_HW | GAME_NOT_WORKING )
	273	COMP( 1980, mathmagi, 0, 0, mathmagi, mathmagi, driver_device, 0, "APF Electronics Inc.", "Mathemagician", GAME_SUPPORTS_SAVE | GAME_NO_SOUND_HW )

trunk/src/mess/drivers/mc1502.c

r242413	r242414
51	51	key |= ioport("Y10")->read();
52	52	key |= ioport("Y11")->read();
53	53	key |= ioport("Y12")->read();
54		//  DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, m_kbd.pulsing,
55		//          (key || m_kbd.pulsing) ? " will IRQ" : ""));
	54	//   DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, m_kbd.pulsing,
	55	//       (key || m_kbd.pulsing) ? " will IRQ" : ""));
56	56
57	57	/*
58	58	If a key is pressed and we're not pulsing yet, start pulsing the IRQ1;
r242413	r242414
73	73
74	74	WRITE8_MEMBER(mc1502_state::mc1502_ppi_portb_w)
75	75	{
76		//  DBG_LOG(2,"mc1502_ppi_portb_w",("( %02X )\n", data));
	76	//   DBG_LOG(2,"mc1502_ppi_portb_w",("( %02X )\n", data));
77	77	m_ppi_portb = data;
78	78	m_pit8253->write_gate2(BIT(data, 0));
79	79	mc1502_speaker_set_spkrdata(BIT(data, 1));
r242413	r242414
87	87	// bit 3: i8251 SYNDET pin triggers NMI (default = 1 = no)
88	88	WRITE8_MEMBER(mc1502_state::mc1502_ppi_portc_w)
89	89	{
90		//  DBG_LOG(2,"mc1502_ppi_portc_w",("( %02X )\n", data));
	90	//   DBG_LOG(2,"mc1502_ppi_portc_w",("( %02X )\n", data));
91	91	m_ppi_portc = data & 15;
92	92	}
93	93
94		//  0x80 -- serial RxD
95		//  0x40 -- CASS IN, also loops back T2OUT (gated by CASWR)
96		//  0x20 -- T2OUT
97		//  0x10 -- SNDOUT
	94	// 0x80 -- serial RxD
	95	// 0x40 -- CASS IN, also loops back T2OUT (gated by CASWR)
	96	// 0x20 -- T2OUT
	97	// 0x10 -- SNDOUT
98	98	READ8_MEMBER(mc1502_state::mc1502_ppi_portc_r)
99	99	{
100	100	int data = 0xff;
r242413	r242414
104	104	data = ( data & ~0x20 ) | ( m_pit_out2 ? 0x20 : 0x00 );
105	105	data = ( data & ~0x10 ) | ( (BIT(m_ppi_portb, 1) && m_pit_out2) ? 0x10 : 0x00 );
106	106
107		//  DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
108		//          data, tap_val, m_pit_out2, machine().describe_context()));
	107	//   DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
	108	//       data, tap_val, m_pit_out2, machine().describe_context()));
109	109	return data;
110	110	}
111	111
r242413	r242414
126	126	if (m_kbd.mask & 0x0400) { key |= ioport("Y11")->read(); }
127	127	if (m_kbd.mask & 0x0800) { key |= ioport("Y12")->read(); }
128	128	key ^= 0xff;
129		//  DBG_LOG(2,"mc1502_kppi_porta_r",("= %02X\n", key));
	129	//   DBG_LOG(2,"mc1502_kppi_porta_r",("= %02X\n", key));
130	130	return key;
131	131	}
132	132
r242413	r242414
138	138	m_kbd.mask |= 1 << 11;
139	139	else
140	140	m_kbd.mask &= ~(1 << 11);
141		//  DBG_LOG(2,"mc1502_kppi_portb_w",("( %02X -> %04X )\n", data, m_kbd.mask));
	141	//   DBG_LOG(2,"mc1502_kppi_portb_w",("( %02X -> %04X )\n", data, m_kbd.mask));
142	142	}
143	143
144	144	WRITE8_MEMBER(mc1502_state::mc1502_kppi_portc_w)
145	145	{
146	146	m_kbd.mask &= ~(7 << 8);
147	147	m_kbd.mask |= ((data ^ 7) & 7) << 8;
148		//  DBG_LOG(2,"mc1502_kppi_portc_w",("( %02X -> %04X )\n", data, m_kbd.mask));
	148	//   DBG_LOG(2,"mc1502_kppi_portc_w",("( %02X -> %04X )\n", data, m_kbd.mask));
149	149	}
150	150
151	151	WRITE_LINE_MEMBER(mc1502_state::mc1502_i8251_syndet)
r242413	r242414
219	219	ADDRESS_MAP_UNMAP_HIGH
220	220	AM_RANGE(0x00000, 0x97fff) AM_RAM   /* 96K on mainboard + 512K on extension card */
221	221	AM_RANGE(0xc0000, 0xfbfff) AM_NOP
222		//  AM_RANGE(0xe8000, 0xeffff) AM_ROM       /* BASIC */
223	222	AM_RANGE(0xfc000, 0xfffff) AM_ROM
224	223	ADDRESS_MAP_END
225	224
r242413	r242414
232	231
233	232	static ADDRESS_MAP_START(mc1502_io, AS_IO, 8, mc1502_state )
234	233	AM_RANGE(0x0020, 0x0021) AM_DEVREADWRITE("pic8259", pic8259_device, read, write)
235		AM_RANGE(0x0028, 0x0028) AM_DEVREADWRITE("upd8251", i8251_device, data_r, data_w)   // not working yet
	234	AM_RANGE(0x0028, 0x0028) AM_DEVREADWRITE("upd8251", i8251_device, data_r, data_w)
236	235	AM_RANGE(0x0029, 0x0029) AM_DEVREADWRITE("upd8251", i8251_device, status_r, control_w)
237	236	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE("pit8253", pit8253_device, read, write)
238	237	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255n1", i8255_device, read, write)
r242413	r242414
244	243	INPUT_PORTS_END
245	244
246	245	static MACHINE_CONFIG_START( mc1502, mc1502_state )
247		/* basic machine hardware */
248	246	MCFG_CPU_ADD("maincpu", I8088, XTAL_16MHz/3)
249	247	MCFG_CPU_PROGRAM_MAP(mc1502_map)
250	248	MCFG_CPU_IO_MAP(mc1502_io)

trunk/src/mess/drivers/merlin.c

r242413	r242414
34	34	#include "cpu/tms0980/tms0980.h"
35	35	#include "sound/speaker.h"
36	36
37		#include "merlin.lh"
	37	#include "merlin.lh" // clickable
38	38
39	39	// master clock is a single stage RC oscillator: R=33K, C=100pf,
40	40	// according to the TMS 1000 series data manual this is around 350kHz

trunk/src/mess/drivers/mz3500.c

r242413	r242414
61	61	required_device<upd7220_device> m_hgdc1;
62	62	required_device<upd7220_device> m_hgdc2;
63	63	required_device<upd765a_device> m_fdc;
64		required_shared_ptr<UINT8> m_video_ram;
	64	required_shared_ptr<UINT16> m_video_ram;
65	65	required_device<beep_device> m_beeper;
66	66	required_device<palette_device> m_palette;
67	67
r242413	r242414
174	174
175	175	for( x = 0; x < pitch; x++ )
176	176	{
177		tile = (m_video_ram[((addr+x)*2) & 0x1fff] & 0xff);
178		attr = (m_video_ram[((addr+x)*2+1) & 0x3ffff] & 0x0f);
	177	tile = (m_video_ram[(((addr+x)*2) & 0x1fff) >> 1] & 0xff);
	178	attr = ((m_video_ram[(((addr+x)*2+1) & 0x3ffff) >> 1] >> 8) & 0x0f);
179	179
180	180	//if(hires)
181	181	//  tile <<= 1;
r242413	r242414
796	796
797	797	}
798	798
799		static ADDRESS_MAP_START( upd7220_1_map, AS_0, 8, mz3500_state )
	799	static ADDRESS_MAP_START( upd7220_1_map, AS_0, 16, mz3500_state )
800	800	ADDRESS_MAP_GLOBAL_MASK(0x1fff)
801	801	AM_RANGE(0x00000, 0x00fff) AM_RAM AM_SHARE("video_ram")
802	802	ADDRESS_MAP_END
803	803
804		static ADDRESS_MAP_START( upd7220_2_map, AS_0, 8, mz3500_state )
	804	static ADDRESS_MAP_START( upd7220_2_map, AS_0, 16, mz3500_state )
805	805	AM_RANGE(0x00000, 0x3ffff) AM_RAM // AM_SHARE("video_ram_2")
806	806	ADDRESS_MAP_END
807	807

trunk/src/mess/drivers/mz6500.c

r242413	r242414
28	28	DECLARE_WRITE8_MEMBER(mz6500_vram_w);
29	29	void fdc_irq(bool state);
30	30	void fdc_drq(bool state);
31		required_shared_ptr<UINT8> m_video_ram;
	31	required_shared_ptr<UINT16> m_video_ram;
32	32	virtual void machine_reset();
33	33	virtual void video_start();
34	34	required_device<cpu_device> m_maincpu;
r242413	r242414
42	42	int gfx[3];
43	43	UINT8 i,pen;
44	44
45		gfx[0] = m_video_ram[address + 0x00000];
46		gfx[1] = m_video_ram[address + 0x10000];
47		gfx[2] = m_video_ram[address + 0x20000];
	45	gfx[0] = m_video_ram[(address + 0x00000) >> 1];
	46	gfx[1] = m_video_ram[(address + 0x10000) >> 1];
	47	gfx[2] = m_video_ram[(address + 0x20000) >> 1];
48	48
49		for(i=0; i<8; i++)
	49	for(i=0; i<16; i++)
50	50	{
51	51	pen = (BIT(gfx[0], i)) | (BIT(gfx[1], i) << 1) | (BIT(gfx[2], i) << 2);
52	52
r242413	r242414
62	62
63	63	READ8_MEMBER( mz6500_state::mz6500_vram_r )
64	64	{
65		return m_video_ram[offset];
	65	return m_video_ram[offset >> 1] >> ((offset & 1) ? 8 : 0);
66	66	}
67	67
68	68	WRITE8_MEMBER( mz6500_state::mz6500_vram_w )
69	69	{
70		m_video_ram[offset] = data;
	70	int mask = (offset & 1) ? 8 : 0;
	71	offset >>= 1;
	72	m_video_ram[offset] &= 0xff00 >> mask;
	73	m_video_ram[offset] |= data << mask;
71	74	}
72	75
73	76	static ADDRESS_MAP_START(mz6500_map, AS_PROGRAM, 16, mz6500_state)
r242413	r242414
126	129	SLOT_INTERFACE( "525hd", FLOPPY_525_HD )
127	130	SLOT_INTERFACE_END
128	131
129		static ADDRESS_MAP_START( upd7220_map, AS_0, 8, mz6500_state )
	132	static ADDRESS_MAP_START( upd7220_map, AS_0, 16, mz6500_state )
130	133	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram")
131	134	ADDRESS_MAP_END
132	135

trunk/src/mess/drivers/ngen.c

r242413	r242414
119	119	DECLARE_WRITE8_MEMBER( dma_3_dack_w ){  }
120	120	DECLARE_WRITE_LINE_MEMBER(fdc_irq_w);
121	121	DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
	122	DECLARE_WRITE8_MEMBER(fdc_control_w);
122	123
123	124	protected:
124	125	virtual void machine_reset();
r242413	r242414
379	380	}
380	381
381	382	// returns X-bus module ID (what is the low byte for?)
	383	// For now, we'll hard code a floppy disk module (or try to)
382	384	READ16_MEMBER(ngen_state::port00_r)
383	385	{
384	386	if(m_port00 > 0)
385	387	m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);
386	388	if(m_port00 == 0)
387		return 0x4000;  // module ID of 0x40 = dual floppy disk module (need hardware manual to find other module IDs)
	389	return 0x0040;  // module ID of 0x40 = dual floppy disk module (need hardware manual to find other module IDs)
388	390	else
389	391	return 0x0080;  // invalid device?
390	392	}
r242413	r242414
396	398
397	399	WRITE_LINE_MEMBER(ngen_state::fdc_drq_w)
398	400	{
399		// TODO
	401	m_dmac->dreq3_w(state);
400	402	}
401	403
	404	WRITE8_MEMBER(ngen_state::fdc_control_w)
	405	{
	406	m_fdc->set_floppy(m_fd0->get_device());
	407	m_fd0->get_device()->mon_w((~data) & 0x80);
	408	m_fdc->dden_w(~data & 0x04);
	409	}
	410
402	411	WRITE_LINE_MEMBER( ngen_state::dma_hrq_changed )
403	412	{
404	413	m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
r242413	r242414
474	483
475	484	void ngen_state::machine_reset()
476	485	{
	486	m_port00 = 0;
477	487	m_control = 0;
478	488	m_viduart->write_dsr(0);
479	489	m_viduart->write_cts(0);
	490	m_fd0->get_device()->set_rpm(300);
480	491	}
481	492
482	493	static ADDRESS_MAP_START( ngen_mem, AS_PROGRAM, 16, ngen_state )
r242413	r242414
490	501	static ADDRESS_MAP_START( ngen_io, AS_IO, 16, ngen_state )
491	502	AM_RANGE(0x0000, 0x0001) AM_READWRITE(port00_r,port00_w)
492	503	AM_RANGE(0x0100, 0x0107) AM_DEVREADWRITE8("fdc",wd2797_t,read,write,0x00ff)  // a guess for now
493		// port 0x0108 is used also, maybe for motor control/side select?
	504	AM_RANGE(0x0108, 0x0109) AM_WRITE8(fdc_control_w,0x00ff)
494	505	ADDRESS_MAP_END
495	506
496	507	static ADDRESS_MAP_START( ngen386_mem, AS_PROGRAM, 32, ngen_state )
r242413	r242414
517	528	SLOT_INTERFACE_END
518	529
519	530	static SLOT_INTERFACE_START( ngen_floppies )
520		SLOT_INTERFACE( "525hd", FLOPPY_525_HD )
	531	SLOT_INTERFACE( "525qd", FLOPPY_525_QD )
521	532	SLOT_INTERFACE_END
522	533
523	534	static MACHINE_CONFIG_START( ngen, ngen_state )
r242413	r242414
577	588	MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcdb_w))
578	589	MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, rib_w))
579	590
580		// TODO: SCN2652 MPCC, used for RS-422 cluster communications?
	591	// TODO: SCN2652 MPCC (not implemented), used for RS-422 cluster communications?
581	592
582	593	// video board
583	594	MCFG_SCREEN_ADD("screen", RASTER)
r242413	r242414
603	614	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(ngen_state,timer_clk_out))
604	615
605	616	// floppy disk / hard disk module (WD2797 FDC, WD1010 HDC, plus an 8253 timer for each)
606		MCFG_WD2797x_ADD("fdc", XTAL_20MHz / 10)
	617	MCFG_WD2797x_ADD("fdc", XTAL_20MHz / 20)
607	618	MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(ngen_state,fdc_irq_w))
608		MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(ngen_state,fdc_drq_w))
	619	MCFG_WD_FDC_DRQ_CALLBACK(DEVWRITELINE("maincpu",i80186_cpu_device,drq1_w))
	620	MCFG_WD_FDC_FORCE_READY
609	621	MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0)
610	622	// TODO: WD1010 HDC (not implemented)
611	623	MCFG_DEVICE_ADD("hdc_timer", PIT8253, 0)
612		MCFG_FLOPPY_DRIVE_ADD("fdc:0", ngen_floppies, "525hd", floppy_image_device::default_floppy_formats)
	624	MCFG_FLOPPY_DRIVE_ADD("fdc:0", ngen_floppies, "525qd", floppy_image_device::default_floppy_formats)
613	625
614	626	MACHINE_CONFIG_END
615	627

trunk/src/mess/drivers/pc6001.c

r242413	r242414
13	13	do some tight synch between the master CPU and a code simulation,but I think
14	14	it's not worth the effort...
15	15	- Identify and hook-up the FDC device, apparently PC-6001 and PC-6601 doesn't even use the same thing;
16		- PC-6601: mon r-0 type games doesn't seem to work at all on this version?
	16	- PC-6601: mon r-0 type games doesn't seem to work at all on this system?
17	17	- PC-6001SR: get it to boot, also implement MK-2 compatibility mode (it changes the memory map to behave like the older versions)
18	18	- Currently rewriting the video part without the MC6847 for two reasons:
19	19	A) the later models have a custom video chip in the place of the MC6847,
r242413	r242414
29	29	nothing is shown on screen, other emus behaves the same, bad dump?
30	30	- Dawn Patrol (cart): presumably too slow;
31	31	(Mk2 mode 5 games)
32		- 3D Golf Simulation Super Version: gameplay / inputs looks broken
	32	- 3D Golf Simulation Super Version: gameplay / inputs seems broken
33	33	- American Truck: Screen is offset at the loading screen, loading bug?
34	34	- Castle Excellent: copyright text drawing is quite bogus, scans text in vertical instead of horizontal?
35	35	- Dezeni Land (ALL versions) / Hurry Fox 1/2: asks you to "load something", can't do it with current cassette kludge, also, for Dezeni Land(s) keyboard irqs

trunk/src/mess/drivers/pc9801.c

r242413	r242414
416	416
417	417	#include "formats/pc98_dsk.h"
418	418	#include "formats/pc98fdi_dsk.h"
	419	#include "formats/fdd_dsk.h"
	420	#include "formats/dcp_dsk.h"
	421	#include "formats/dip_dsk.h"
	422	#include "formats/nfd_dsk.h"
419	423
420	424	#include "machine/pc9801_26.h"
421	425	#include "machine/pc9801_86.h"
r242413	r242414
481	485	optional_device<input_buffer_device> m_sasi_data_in;
482	486	optional_device<input_buffer_device> m_sasi_ctrl_in;
483	487	optional_device<ata_interface_device> m_ide;
484		required_shared_ptr<UINT8> m_video_ram_1;
485		required_shared_ptr<UINT8> m_video_ram_2;
486		optional_shared_ptr<UINT8> m_ext_gvram;
	488	required_shared_ptr<UINT16> m_video_ram_1;
	489	required_shared_ptr<UINT16> m_video_ram_2;
	490	optional_shared_ptr<UINT16> m_ext_gvram;
487	491	required_device<beep_device> m_beeper;
488	492	optional_device<ram_device> m_ram;
489	493	required_device<gfxdecode_device> m_gfxdecode;
r242413	r242414
505	509	UINT8 m_txt_scroll_reg[8];
506	510	UINT8 m_pal_clut[4];
507	511
508		UINT8 *m_tvram;
	512	UINT16 *m_tvram;
509	513
510	514	UINT16 m_font_addr;
511	515	UINT8 m_font_line;
r242413	r242414
539	543	UINT8 tile[4], tile_index;
540	544	}m_grcg;
541	545
	546	struct {
	547	UINT16 regs[8];
	548	UINT16 pat[4];
	549	UINT16 src[4];
	550	INT16 count;
	551	UINT16 leftover[4];
	552	bool first;
	553	} m_egc;
	554
542	555	/* PC9821 specific */
543	556	UINT8 m_sdip[24], m_sdip_bank;
544	557	UINT8 m_pc9821_window_bank;
r242413	r242414
554	567	DECLARE_WRITE8_MEMBER(txt_scrl_w);
555	568	DECLARE_READ8_MEMBER(grcg_r);
556	569	DECLARE_WRITE8_MEMBER(grcg_w);
	570	DECLARE_WRITE16_MEMBER(egc_w);
557	571	DECLARE_READ8_MEMBER(pc9801_a0_r);
558	572	DECLARE_WRITE8_MEMBER(pc9801_a0_w);
559	573	DECLARE_READ8_MEMBER(pc9801_fdc_2hd_r);
560	574	DECLARE_WRITE8_MEMBER(pc9801_fdc_2hd_w);
561	575	DECLARE_READ8_MEMBER(pc9801_fdc_2dd_r);
562	576	DECLARE_WRITE8_MEMBER(pc9801_fdc_2dd_w);
563		DECLARE_READ8_MEMBER(tvram_r);
564		DECLARE_WRITE8_MEMBER(tvram_w);
	577	DECLARE_READ16_MEMBER(tvram_r);
	578	DECLARE_WRITE16_MEMBER(tvram_w);
565	579	DECLARE_READ8_MEMBER(gvram_r);
566	580	DECLARE_WRITE8_MEMBER(gvram_w);
567	581	DECLARE_WRITE8_MEMBER(pc9801rs_mouse_freq_w);
568	582	DECLARE_CUSTOM_INPUT_MEMBER(system_type_r);
569		DECLARE_READ8_MEMBER(grcg_gvram_r);
570		DECLARE_WRITE8_MEMBER(grcg_gvram_w);
571		DECLARE_READ8_MEMBER(grcg_gvram0_r);
572		DECLARE_WRITE8_MEMBER(grcg_gvram0_w);
573		DECLARE_READ8_MEMBER(upd7220_grcg_r);
574		DECLARE_WRITE8_MEMBER(upd7220_grcg_w);
	583	DECLARE_READ16_MEMBER(grcg_gvram_r);
	584	DECLARE_WRITE16_MEMBER(grcg_gvram_w);
	585	DECLARE_READ16_MEMBER(grcg_gvram0_r);
	586	DECLARE_WRITE16_MEMBER(grcg_gvram0_w);
	587	DECLARE_READ16_MEMBER(upd7220_grcg_r);
	588	DECLARE_WRITE16_MEMBER(upd7220_grcg_w);
	589	void egc_blit_w(UINT32 offset, UINT16 data, UINT16 mem_mask);
	590	UINT16 egc_blit_r(UINT32 offset, UINT16 mem_mask);
	591	inline UINT16 egc_do_partial_op(int plane, UINT16 src, UINT16 pat, UINT16 dst);
575	592	UINT32 pc9801_286_a20(bool state);
576	593
577	594	DECLARE_READ8_MEMBER(ide_hack_r);
r242413	r242414
714	731
715	732	void pc9801_state::video_start()
716	733	{
717		m_tvram = auto_alloc_array(machine(), UINT8, 0x4000);
	734	m_tvram = auto_alloc_array(machine(), UINT16, 0x2000);
718	735
719	736	// find memory regions
720	737	m_char_rom = memregion("chargen")->base();
r242413	r242414
750	767
751	768	if(m_ex_video_ff[ANALOG_256_MODE])
752	769	{
753		for(xi=0;xi<8;xi++)
	770	for(xi=0;xi<16;xi++)
754	771	{
755	772	res_x = x + xi;
756	773	res_y = y;
r242413	r242414
758	775	if(!m_screen->visible_area().contains(res_x, res_y*2+0))
759	776	return;
760	777
761		pen = m_ext_gvram[(address*8+xi)+(m_vram_disp*0x40000)];
	778	pen = m_ext_gvram[((address*16+xi)+(m_vram_disp*0x40000)) >> 1];
762	779
763	780	bitmap.pix32(res_y*2+0, res_x) = palette[pen + 0x20];
764	781	if(m_screen->visible_area().contains(res_x, res_y*2+1))
r242413	r242414
767	784	}
768	785	else
769	786	{
770		for(xi=0;xi<8;xi++)
	787	for(xi=0;xi<16;xi++)
771	788	{
772	789	res_x = x + xi;
773	790	res_y = y;
774	791
775		pen = ((m_video_ram_2[(address & 0x7fff) + (0x08000) + (m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 1 : 0;
776		pen|= ((m_video_ram_2[(address & 0x7fff) + (0x10000) + (m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 2 : 0;
777		pen|= ((m_video_ram_2[(address & 0x7fff) + (0x18000) + (m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 4 : 0;
	792	pen = ((m_video_ram_2[((address & 0x7fff) + (0x08000) + (m_vram_disp*0x20000)) >> 1] >> xi) & 1) ? 1 : 0;
	793	pen|= ((m_video_ram_2[((address & 0x7fff) + (0x10000) + (m_vram_disp*0x20000)) >> 1] >> xi) & 1) ? 2 : 0;
	794	pen|= ((m_video_ram_2[((address & 0x7fff) + (0x18000) + (m_vram_disp*0x20000)) >> 1] >> xi) & 1) ? 4 : 0;
778	795	if(m_ex_video_ff[ANALOG_16_MODE])
779		pen|= ((m_video_ram_2[(address & 0x7fff) + (0) + (m_vram_disp*0x20000)] >> (7-xi)) & 1) ? 8 : 0;
	796	pen|= ((m_video_ram_2[((address & 0x7fff) + (0) + (m_vram_disp*0x20000)) >> 1] >> xi) & 1) ? 8 : 0;
780	797
781	798	if(interlace_on)
782	799	{
r242413	r242414
826	843	kanji_sel = 0;
827	844	kanji_lr = 0;
828	845
829		tile = m_video_ram_1[(tile_addr*2) & 0x1fff] & 0xff;
830		knj_tile = m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0xff;
	846	tile = m_video_ram_1[tile_addr & 0xfff] & 0xff;
	847	knj_tile = m_video_ram_1[tile_addr & 0xfff] >> 8;
831	848	if(knj_tile)
832	849	{
833	850	/* Note: bit 7 doesn't really count, if a kanji is enabled then the successive tile is always the second part of it.
r242413	r242414
848	865	else
849	866	x_step = 1;
850	867
851		attr = (m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0xff);
	868	attr = (m_video_ram_1[(tile_addr & 0xfff) | 0x1000] & 0xff);
852	869
853	870	secret = (attr & 1) ^ 1;
854	871	blink = attr & 2;
r242413	r242414
1279	1296
1280	1297
1281	1298	/* TODO: banking? */
1282		READ8_MEMBER(pc9801_state::tvram_r)
	1299	READ16_MEMBER(pc9801_state::tvram_r)
1283	1300	{
1284		UINT8 res;
	1301	UINT16 res;
1285	1302
1286		if((offset & 0x2000) && offset & 1)
1287		return 0xff;
	1303	if((offset & 0x1000) && (mem_mask == 0xff00))
	1304	return 0xffff;
1288	1305
1289	1306	res = m_tvram[offset];
1290	1307
1291	1308	return res;
1292	1309	}
1293	1310
1294		WRITE8_MEMBER(pc9801_state::tvram_w)
	1311	WRITE16_MEMBER(pc9801_state::tvram_w)
1295	1312	{
1296		if(offset < (0x3fe2) || m_video_ff[MEMSW_REG])
1297		m_tvram[offset] = data;
	1313	if(offset < (0x3fe2>>1) || m_video_ff[MEMSW_REG])
	1314	COMBINE_DATA(&m_tvram[offset]);
1298	1315
1299		m_video_ram_1[offset] = data; //TODO: check me
	1316	COMBINE_DATA(&m_video_ram_1[offset]); //TODO: check me
1300	1317	}
1301	1318
1302	1319	/* +0x8000 is trusted (bank 0 is actually used by 16 colors mode) */
1303	1320	READ8_MEMBER(pc9801_state::gvram_r)
1304	1321	{
1305		return m_video_ram_2[offset+0x08000+m_vram_bank*0x20000];
	1322	return BITSWAP8(m_video_ram_2[(offset>>1)+0x04000+m_vram_bank*0x10000] >> ((offset & 1) << 3),0,1,2,3,4,5,6,7);
1306	1323	}
1307	1324
1308	1325	WRITE8_MEMBER(pc9801_state::gvram_w)
1309	1326	{
1310		m_video_ram_2[offset+0x08000+m_vram_bank*0x20000] = data;
	1327	UINT16 ram = m_video_ram_2[(offset>>1)+0x04000+m_vram_bank*0x10000];
	1328	int mask = (offset & 1) << 3;
	1329	data = BITSWAP8(data,0,1,2,3,4,5,6,7);
	1330	m_video_ram_2[(offset>>1)+0x04000+m_vram_bank*0x10000] = (ram & (0xff00 >> mask)) | (data << mask);
1311	1331	}
1312	1332
1313		READ8_MEMBER(pc9801_state::upd7220_grcg_r)
	1333	inline UINT16 pc9801_state::egc_do_partial_op(int plane, UINT16 src, UINT16 pat, UINT16 dst)
1314	1334	{
1315		UINT8 res = 0;
	1335	UINT16 out = 0;
	1336	int src_off, dst_off;
	1337	UINT16 src_tmp = src;
1316	1338
1317		if(!(m_grcg.mode & 0x80))
	1339	if(m_egc.regs[6] & 0x1000)
	1340	{
	1341	src_off = 15 - (m_egc.regs[6] & 0xf);
	1342	dst_off = 15 - ((m_egc.regs[6] >> 4) & 0xf);
	1343	}
	1344	else
	1345	{
	1346	src_off = m_egc.regs[6] & 0xf;
	1347	dst_off = (m_egc.regs[6] >> 4) & 0xf;
	1348	}
	1349
	1350	if(src_off < dst_off)
	1351	{
	1352	src = src_tmp << (dst_off - src_off);
	1353	src |= m_egc.leftover[plane];
	1354	m_egc.leftover[plane] = src_tmp >> (16 - (dst_off - src_off));
	1355	}
	1356	else
	1357	{
	1358	src = src_tmp >> (src_off - dst_off);
	1359	src |= m_egc.leftover[plane];
	1360	m_egc.leftover[plane] = src_tmp << (16 - (src_off - dst_off));
	1361	}
	1362
	1363	for(int i = 7; i >= 0; i--)
	1364	{
	1365	if(BIT(m_egc.regs[2], i))
	1366	out |= src & pat & dst;
	1367	pat = ~pat;
	1368	dst = (!(i & 1)) ? ~dst : dst;
	1369	src = (i == 4) ? ~src : src;
	1370	}
	1371	return out;
	1372	}
	1373
	1374	void pc9801_state::egc_blit_w(UINT32 offset, UINT16 data, UINT16 mem_mask)
	1375	{
	1376	UINT16 mask = m_egc.regs[4] & mem_mask, out = 0;
	1377	bool dir = !(m_egc.regs[6] & 0x1000);
	1378	int dst_off = (m_egc.regs[6] >> 4) & 0xf;
	1379	offset &= 0x13fff;
	1380
	1381	if((((m_egc.regs[2] >> 11) & 3) == 1) || ((((m_egc.regs[2] >> 11) & 3) == 2) && !BIT(m_egc.regs[2], 10)))
	1382	{
	1383	UINT16 end_mask = 0xffff, start_mask = 0xffff;
	1384	// mask off the bits before the start
	1385	if(m_egc.first)
	1386	{
	1387	m_egc.leftover[0] = m_egc.leftover[1] = m_egc.leftover[2] = m_egc.leftover[3] = 0;
	1388	start_mask = dir ? ~((1 << dst_off) - 1) : ((1 << (15 - dst_off)) - 1);
	1389	}
	1390
	1391	// mask off the bits past the end of the blit
	1392	if(m_egc.count < 16)
	1393	{
	1394	end_mask = dir ? ((1 << m_egc.count) - 1) : ~((1 << (16 - m_egc.count)) - 1);
	1395	// if the blit is less than 16 bits, adjust the masks
	1396	if(start_mask != 0xffff)
	1397	{
	1398	if(dir)
	1399	end_mask <<= dst_off;
	1400	else
	1401	end_mask >>= (15 - dst_off);
	1402	}
	1403	}
	1404	mask &= end_mask & start_mask;
	1405	}
	1406
	1407	for(int i = 0; i < 4; i++)
	1408	{
	1409	if(!BIT(m_egc.regs[0], i))
	1410	{
	1411	UINT16 src = m_egc.src[i] & mem_mask, pat = m_egc.pat[i];
	1412	if(BIT(m_egc.regs[2], 10))
	1413	src = data;
	1414
	1415	if((m_egc.regs[2] & 0x300) == 0x200)
	1416	pat = m_video_ram_2[offset + (((i + 1) & 3) * 0x4000)];
	1417
	1418	switch((m_egc.regs[2] >> 11) & 3)
	1419	{
	1420	case 0:
	1421	out = data;
	1422	break;
	1423	case 1:
	1424	if(mem_mask == 0x00ff)
	1425	src = src | src << 8;
	1426	else if(mem_mask == 0xff00)
	1427	src = src | src >> 8;
	1428
	1429	out = egc_do_partial_op(i, src, pat, m_video_ram_2[offset + (((i + 1) & 3) * 0x4000)]);
	1430	break;
	1431	case 2:
	1432	out = pat;
	1433	break;
	1434	case 3:
	1435	logerror("Invalid EGC blit operation\n");
	1436	return;
	1437	}
	1438
	1439	m_video_ram_2[offset + (((i + 1) & 3) * 0x4000)] &= ~mask;
	1440	m_video_ram_2[offset + (((i + 1) & 3) * 0x4000)] |= out & mask;
	1441	}
	1442	}
	1443	if(mem_mask != 0xffff)
	1444	{
	1445	dst_off &= 7;
	1446	if(m_egc.first)
	1447	m_egc.count -= dir ? 8 - dst_off : (dst_off + 1);
	1448	else
	1449	m_egc.count -= 8;
	1450	}
	1451	else
	1452	{
	1453	if(m_egc.first)
	1454	m_egc.count -= dir ? 16 - dst_off : (dst_off + 1);
	1455	else
	1456	m_egc.count -= 16;
	1457	}
	1458
	1459	m_egc.first = false;
	1460
	1461	if(m_egc.count <= 0)
	1462	{
	1463	m_egc.first = true;
	1464	m_egc.count = (m_egc.regs[7] & 0xfff) + 1;
	1465	}
	1466	}
	1467
	1468	UINT16 pc9801_state::egc_blit_r(UINT32 offset, UINT16 mem_mask)
	1469	{
	1470	UINT32 plane_off = offset & 0x13fff;
	1471	if((m_egc.regs[2] & 0x300) == 0x100)
	1472	{
	1473	m_egc.pat[0] = m_video_ram_2[plane_off + 0x4000];
	1474	m_egc.pat[1] = m_video_ram_2[plane_off + (0x4000 * 2)];
	1475	m_egc.pat[2] = m_video_ram_2[plane_off + (0x4000 * 3)];
	1476	m_egc.pat[3] = m_video_ram_2[plane_off];
	1477	}
	1478	if(!BIT(m_egc.regs[2], 10))
	1479	{
	1480	m_egc.src[0] = m_video_ram_2[plane_off + 0x4000];
	1481	m_egc.src[1] = m_video_ram_2[plane_off + (0x4000 * 2)];
	1482	m_egc.src[2] = m_video_ram_2[plane_off + (0x4000 * 3)];
	1483	m_egc.src[3] = m_video_ram_2[plane_off];
	1484	}
	1485	if(BIT(m_egc.regs[2], 13))
	1486	return m_video_ram_2[offset];
	1487	else
	1488	return m_video_ram_2[plane_off + (((m_egc.regs[1] >> 8) + 1) & 3) * 0x4000];
	1489	}
	1490
	1491	READ16_MEMBER(pc9801_state::upd7220_grcg_r)
	1492	{
	1493	UINT16 res = 0;
	1494
	1495	if(!(m_grcg.mode & 0x80) || space.debugger_access())
1318	1496	res = m_video_ram_2[offset];
	1497	else if(m_ex_video_ff[2])
	1498	res = egc_blit_r(offset, mem_mask);
1319	1499	else if(!(m_grcg.mode & 0x40))
1320	1500	{
1321	1501	int i;
1322	1502
1323		offset &= ~(3 << 15);
	1503	offset &= 0x13fff;
1324	1504	res = 0;
1325	1505	for(i=0;i<4;i++)
1326	1506	{
1327	1507	if((m_grcg.mode & (1 << i)) == 0)
1328		res |= m_video_ram_2[offset | (((i + 1) & 3) * 0x8000)] ^ m_grcg.tile[i];
	1508	{
	1509	res |= m_video_ram_2[offset | (((i + 1) & 3) * 0x4000)] ^ (m_grcg.tile[i] | m_grcg.tile[i] << 8);
	1510	}
1329	1511	}
1330	1512
1331		res ^= 0xff;
	1513	res ^= 0xffff;
1332	1514	}
1333	1515
1334	1516	return res;
1335	1517	}
1336	1518
1337		WRITE8_MEMBER(pc9801_state::upd7220_grcg_w)
	1519	WRITE16_MEMBER(pc9801_state::upd7220_grcg_w)
1338	1520	{
1339		if((m_grcg.mode & 0x80) == 0)
1340		m_video_ram_2[offset] = data;
	1521	if(!(m_grcg.mode & 0x80))
	1522	COMBINE_DATA(&m_video_ram_2[offset]);
	1523	else if(m_ex_video_ff[2])
	1524	egc_blit_w(offset, data, mem_mask);
1341	1525	else
1342	1526	{
1343	1527	int i;
1344		offset &= ~(3 << 15);
	1528	UINT8 *vram = (UINT8 *)m_video_ram_2.target();
	1529	offset = (offset << 1) & 0x27fff;
1345	1530
1346	1531	if(m_grcg.mode & 0x40) // RMW
1347	1532	{
r242413	r242414
1349	1534	{
1350	1535	if((m_grcg.mode & (1 << i)) == 0)
1351	1536	{
1352		m_video_ram_2[offset | (((i + 1) & 3) * 0x8000)] &= ~data;
1353		m_video_ram_2[offset | (((i + 1) & 3) * 0x8000)] |= m_grcg.tile[i] & data;
	1537	if(mem_mask & 0xff)
	1538	{
	1539	vram[offset | (((i + 1) & 3) * 0x8000)] &= ~data;
	1540	vram[offset | (((i + 1) & 3) * 0x8000)] |= m_grcg.tile[i] & data;
	1541	}
	1542	if(mem_mask & 0xff00)
	1543	{
	1544	vram[offset | (((i + 1) & 3) * 0x8000) | 1] &= ~(data >> 8);
	1545	vram[offset | (((i + 1) & 3) * 0x8000) | 1] |= m_grcg.tile[i] & (data >> 8);
	1546	}
1354	1547	}
1355	1548	}
1356	1549	}
r242413	r242414
1360	1553	{
1361	1554	if((m_grcg.mode & (1 << i)) == 0)
1362	1555	{
1363		m_video_ram_2[offset | (((i + 1) & 3) * 0x8000)] = m_grcg.tile[i];
	1556	if(mem_mask & 0xff)
	1557	vram[offset | (((i + 1) & 3) * 0x8000)] = m_grcg.tile[i];
	1558	if(mem_mask & 0xff00)
	1559	vram[offset | (((i + 1) & 3) * 0x8000) | 1] = m_grcg.tile[i];
1364	1560	}
1365	1561	}
1366	1562	}
r242413	r242414
1491	1687
1492	1688	static ADDRESS_MAP_START( pc9801_map, AS_PROGRAM, 16, pc9801_state )
1493	1689	AM_RANGE(0x00000, 0x9ffff) AM_RAM //work RAM
1494		AM_RANGE(0xa0000, 0xa3fff) AM_READWRITE8(tvram_r,tvram_w,0xffff) //TVRAM
	1690	AM_RANGE(0xa0000, 0xa3fff) AM_READWRITE(tvram_r,tvram_w) //TVRAM
1495	1691	AM_RANGE(0xa8000, 0xbffff) AM_READWRITE8(gvram_r,gvram_w,0xffff) //bitmap VRAM
1496	1692	AM_RANGE(0xcc000, 0xcdfff) AM_ROM AM_REGION("sound_bios",0) //sound BIOS
1497	1693	AM_RANGE(0xd6000, 0xd6fff) AM_ROM AM_REGION("fdc_bios_2dd",0) //floppy BIOS 2dd
r242413	r242414
1674	1870	txt_scrl_w(space,offset,data);
1675	1871	}
1676	1872
	1873	WRITE16_MEMBER(pc9801_state::egc_w)
	1874	{
	1875	if(!m_ex_video_ff[2])
	1876	return;
	1877
	1878	COMBINE_DATA(&m_egc.regs[offset]);
	1879	switch(offset)
	1880	{
	1881	case 1:
	1882	case 3:
	1883	case 5:
	1884	{
	1885	UINT8 color = 0;
	1886	switch((m_egc.regs[1] >> 13) & 3)
	1887	{
	1888	case 1:
	1889	//back color
	1890	color = m_egc.regs[5];
	1891	break;
	1892	case 2:
	1893	//fore color
	1894	color = m_egc.regs[3];
	1895	break;
	1896	default:
	1897	return;
	1898	}
	1899	m_egc.pat[0] = (color & 1) ? 0xffff : 0;
	1900	m_egc.pat[1] = (color & 2) ? 0xffff : 0;
	1901	m_egc.pat[2] = (color & 4) ? 0xffff : 0;
	1902	m_egc.pat[3] = (color & 8) ? 0xffff : 0;
	1903	break;
	1904	}
	1905	case 6:
	1906	case 7:
	1907	m_egc.count = (m_egc.regs[7] & 0xfff) + 1;
	1908	m_egc.first = true;
	1909	break;
	1910	}
	1911	}
	1912
1677	1913	READ8_MEMBER(pc9801_state::pc9810rs_fdc_ctrl_r)
1678	1914	{
1679	1915	return (m_fdc_ctrl & 3) | 0xf0 | 8 | 4;
r242413	r242414
1885	2121	((offset >= 4) ? m_pic2 : m_pic1)->write(space, offset & 3, data);
1886	2122	}
1887	2123
1888		READ8_MEMBER(pc9801_state::grcg_gvram_r)
	2124	READ16_MEMBER(pc9801_state::grcg_gvram_r)
1889	2125	{
1890		return upd7220_grcg_r(space, (offset + 0x8000) | (m_vram_bank << 17), mem_mask);
	2126	UINT16 ret = upd7220_grcg_r(space, (offset + 0x4000) | (m_vram_bank << 16), mem_mask);
	2127	return BITSWAP16(ret,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7);
1891	2128	}
1892	2129
1893		WRITE8_MEMBER(pc9801_state::grcg_gvram_w)
	2130	WRITE16_MEMBER(pc9801_state::grcg_gvram_w)
1894	2131	{
1895		upd7220_grcg_w(space, (offset + 0x8000) | (m_vram_bank << 17), data, mem_mask);
	2132	data = BITSWAP16(data,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7);
	2133	upd7220_grcg_w(space, (offset + 0x4000) | (m_vram_bank << 16), data, mem_mask);
1896	2134	}
1897	2135
1898		READ8_MEMBER(pc9801_state::grcg_gvram0_r)
	2136	READ16_MEMBER(pc9801_state::grcg_gvram0_r)
1899	2137	{
1900		return upd7220_grcg_r(space, offset | (m_vram_bank << 17), mem_mask);
	2138	UINT16 ret = upd7220_grcg_r(space, offset | (m_vram_bank << 16), mem_mask);
	2139	return BITSWAP16(ret,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7);
1901	2140	}
1902	2141
1903		WRITE8_MEMBER(pc9801_state::grcg_gvram0_w)
	2142	WRITE16_MEMBER(pc9801_state::grcg_gvram0_w)
1904	2143	{
1905		upd7220_grcg_w(space, offset | (m_vram_bank << 17), data, mem_mask);
	2144	data = BITSWAP16(data,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7);
	2145	upd7220_grcg_w(space, offset | (m_vram_bank << 16), data, mem_mask);
1906	2146	}
1907	2147
1908	2148	static ADDRESS_MAP_START( pc9801ux_map, AS_PROGRAM, 16, pc9801_state )
1909	2149	AM_RANGE(0x000000, 0x09ffff) AM_RAMBANK("wram")
1910		AM_RANGE(0x0a0000, 0x0a3fff) AM_READWRITE8(tvram_r, tvram_w, 0xffff)
	2150	AM_RANGE(0x0a0000, 0x0a3fff) AM_READWRITE(tvram_r, tvram_w)
1911	2151	AM_RANGE(0x0a4000, 0x0a4fff) AM_READWRITE8(pc9801rs_knjram_r, pc9801rs_knjram_w, 0xffff)
1912		AM_RANGE(0x0a8000, 0x0bffff) AM_READWRITE8(grcg_gvram_r, grcg_gvram_w, 0xffff)
1913		AM_RANGE(0x0e0000, 0x0e7fff) AM_READWRITE8(grcg_gvram0_r,grcg_gvram0_w, 0xffff)
	2152	AM_RANGE(0x0a8000, 0x0bffff) AM_READWRITE(grcg_gvram_r, grcg_gvram_w)
	2153	AM_RANGE(0x0e0000, 0x0e7fff) AM_READWRITE(grcg_gvram0_r,grcg_gvram0_w)
1914	2154	AM_RANGE(0x0e0000, 0x0fffff) AM_READ8(pc9801rs_ipl_r, 0xffff)
1915	2155	ADDRESS_MAP_END
1916	2156
r242413	r242414
1927	2167	AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(a20_ctrl_r,      a20_ctrl_w,      0x00ff)
1928	2168	AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffff)
1929	2169	AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffff) //ROM/RAM bank
	2170	AM_RANGE(0x04a0, 0x04af) AM_WRITE(egc_w)
1930	2171	AM_RANGE(0x3fd8, 0x3fdf) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00)
1931	2172	//  AM_RANGE(0xa460, 0xa463) AM_READWRITE8(pc9801_ext_opna_r,  pc9801_ext_opna_w,  0xffff)
1932	2173	AM_IMPORT_FROM(pc9801_io)
r242413	r242414
2135	2376	static ADDRESS_MAP_START( pc9821_map, AS_PROGRAM, 32, pc9801_state )
2136	2377	AM_RANGE(0x00000000, 0x0009ffff) AM_RAMBANK("wram")
2137	2378	//AM_RANGE(0x00080000, 0x0009ffff) AM_READWRITE8(winram_r, winram_w, 0xffffffff)
2138		AM_RANGE(0x000a0000, 0x000a3fff) AM_READWRITE8(tvram_r, tvram_w, 0xffffffff)
	2379	AM_RANGE(0x000a0000, 0x000a3fff) AM_READWRITE16(tvram_r, tvram_w, 0xffffffff)
2139	2380	AM_RANGE(0x000a4000, 0x000a4fff) AM_READWRITE8(pc9801rs_knjram_r, pc9801rs_knjram_w, 0xffffffff)
2140		AM_RANGE(0x000a8000, 0x000bffff) AM_READWRITE8(grcg_gvram_r, grcg_gvram_w, 0xffffffff)
	2381	AM_RANGE(0x000a8000, 0x000bffff) AM_READWRITE16(grcg_gvram_r, grcg_gvram_w, 0xffffffff)
2141	2382	AM_RANGE(0x000cc000, 0x000cdfff) AM_ROM AM_REGION("sound_bios",0) //sound BIOS
2142	2383	AM_RANGE(0x000d8000, 0x000d9fff) AM_ROM AM_REGION("ide",0)
2143	2384	AM_RANGE(0x000da000, 0x000dbfff) AM_RAM // ide ram
2144		AM_RANGE(0x000e0000, 0x000e7fff) AM_READWRITE8(grcg_gvram0_r,grcg_gvram0_w, 0xffffffff)
	2385	AM_RANGE(0x000e0000, 0x000e7fff) AM_READWRITE16(grcg_gvram0_r,grcg_gvram0_w, 0xffffffff)
2145	2386	AM_RANGE(0x000e0000, 0x000fffff) AM_READ8(pc9801rs_ipl_r, 0xffffffff)
2146	2387	AM_RANGE(0x00f00000, 0x00f9ffff) AM_RAM AM_SHARE("ext_gvram")
2147	2388	AM_RANGE(0xffee0000, 0xffefffff) AM_READ8(pc9801rs_ipl_r, 0xffffffff)
r242413	r242414
2179	2420	//  AM_RANGE(0x043d, 0x043d) ROM/RAM bank (NEC)
2180	2421	AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffffffff) //ROM/RAM bank (EPSON)
2181	2422	AM_RANGE(0x0460, 0x0463) AM_READWRITE8(pc9821_window_bank_r,pc9821_window_bank_w, 0xffffffff)
2182		//  AM_RANGE(0x04a0, 0x04af) EGC
	2423	AM_RANGE(0x04a0, 0x04af) AM_WRITE16(egc_w, 0xffffffff)
2183	2424	//  AM_RANGE(0x04be, 0x04be) FDC "RPM" register
2184	2425	AM_RANGE(0x0640, 0x064f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
2185	2426	AM_RANGE(0x0740, 0x074f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
r242413	r242414
2229	2470	//  AM_RANGE(0xfcd0, 0xfcd3) MIDI port, option F / <undefined>
2230	2471	ADDRESS_MAP_END
2231	2472
2232		static ADDRESS_MAP_START( upd7220_1_map, AS_0, 8, pc9801_state )
	2473	static ADDRESS_MAP_START( upd7220_1_map, AS_0, 16, pc9801_state )
2233	2474	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram_1")
2234	2475	ADDRESS_MAP_END
2235	2476
2236		static ADDRESS_MAP_START( upd7220_2_map, AS_0, 8, pc9801_state )
	2477	static ADDRESS_MAP_START( upd7220_2_map, AS_0, 16, pc9801_state )
2237	2478	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram_2")
2238	2479	ADDRESS_MAP_END
2239	2480
2240		static ADDRESS_MAP_START( upd7220_grcg_2_map, AS_0, 8, pc9801_state )
	2481	static ADDRESS_MAP_START( upd7220_grcg_2_map, AS_0, 16, pc9801_state )
2241	2482	AM_RANGE(0x00000, 0x3ffff) AM_READWRITE(upd7220_grcg_r, upd7220_grcg_w) AM_SHARE("video_ram_2")
2242	2483	ADDRESS_MAP_END
2243	2484
r242413	r242414
2781	3022
2782	3023	MACHINE_RESET_MEMBER(pc9801_state,pc9801_common)
2783	3024	{
2784		memset(m_tvram, 0, sizeof(UINT8) * 0x4000);
	3025	memset(m_tvram, 0, sizeof(UINT16) * 0x2000);
2785	3026	/* this looks like to be some kind of backup ram, system will boot with green colors otherwise */
2786	3027	{
2787	3028	int i;
r242413	r242414
2792	3033	};
2793	3034
2794	3035	for(i=0;i<0x10;i++)
2795		m_tvram[(0x3fe0)+i*2] = default_memsw_data[i];
	3036	m_tvram[(0x3fe0>>1)+i] = default_memsw_data[i];
2796	3037	}
2797	3038
2798	3039	m_beeper->set_frequency(2400);
r242413	r242414
2802	3043	m_mouse.control = 0xff;
2803	3044	m_mouse.freq_reg = 0;
2804	3045	m_mouse.freq_index = 0;
	3046	memset(&m_egc, 0, sizeof(m_egc));
2805	3047	}
2806	3048
2807	3049	MACHINE_RESET_MEMBER(pc9801_state,pc9801f)
r242413	r242414
2869	3111
2870	3112	FLOPPY_FORMATS_MEMBER( pc9801_state::floppy_formats )
2871	3113	FLOPPY_PC98_FORMAT,
2872		FLOPPY_PC98FDI_FORMAT
	3114	FLOPPY_PC98FDI_FORMAT,
	3115	FLOPPY_FDD_FORMAT,
	3116	FLOPPY_DCP_FORMAT,
	3117	FLOPPY_DIP_FORMAT,
	3118	FLOPPY_NFD_FORMAT
2873	3119	FLOPPY_FORMATS_END
2874	3120
2875	3121	TIMER_DEVICE_CALLBACK_MEMBER( pc9801_state::mouse_irq_cb )

trunk/src/mess/drivers/qx10.c

r242413	r242414
88	88	required_device<rs232_port_device> m_kbd;
89	89	UINT8 m_vram_bank;
90	90	//required_shared_ptr<UINT8> m_video_ram;
91		UINT8 *m_video_ram;
	91	UINT16 *m_video_ram;
92	92
93	93	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
94	94
r242413	r242414
115	115	DECLARE_READ8_MEMBER( get_slave_ack );
116	116	DECLARE_READ8_MEMBER( vram_bank_r );
117	117	DECLARE_WRITE8_MEMBER( vram_bank_w );
118		DECLARE_READ8_MEMBER( vram_r );
119		DECLARE_WRITE8_MEMBER( vram_w );
	118	DECLARE_READ16_MEMBER( vram_r );
	119	DECLARE_WRITE16_MEMBER( vram_w );
120	120	DECLARE_READ8_MEMBER(memory_read_byte);
121	121	DECLARE_WRITE8_MEMBER(memory_write_byte);
122	122	DECLARE_WRITE_LINE_MEMBER(keyboard_clk);
r242413	r242414
159	159
160	160	if(m_color_mode)
161	161	{
162		gfx[0] = m_video_ram[(address) + 0x00000];
163		gfx[1] = m_video_ram[(address) + 0x20000];
164		gfx[2] = m_video_ram[(address) + 0x40000];
	162	gfx[0] = m_video_ram[((address) + 0x00000) >> 1];
	163	gfx[1] = m_video_ram[((address) + 0x20000) >> 1];
	164	gfx[2] = m_video_ram[((address) + 0x40000) >> 1];
165	165	}
166	166	else
167	167	{
168		gfx[0] = m_video_ram[address];
	168	gfx[0] = m_video_ram[(address) >> 1];
169	169	gfx[1] = 0;
170	170	gfx[2] = 0;
171	171	}
172	172
173		for(xi=0;xi<8;xi++)
	173	for(xi=0;xi<16;xi++)
174	174	{
175		pen = ((gfx[0] >> (7-xi)) & 1) ? 1 : 0;
176		pen|= ((gfx[1] >> (7-xi)) & 1) ? 2 : 0;
177		pen|= ((gfx[2] >> (7-xi)) & 1) ? 4 : 0;
	175	pen = ((gfx[0] >> xi) & 1) ? 1 : 0;
	176	pen|= ((gfx[1] >> xi) & 1) ? 2 : 0;
	177	pen|= ((gfx[2] >> xi) & 1) ? 4 : 0;
178	178
179	179	bitmap.pix32(y, x + xi) = palette[pen];
180	180	}
r242413	r242414
193	193
194	194	for( x = 0; x < pitch; x++ )
195	195	{
196		tile = m_video_ram[(addr+x)*2];
197		attr = m_video_ram[(addr+x)*2+1];
	196	tile = m_video_ram[((addr+x)*2) >> 1] & 0xff;
	197	attr = m_video_ram[((addr+x)*2) >> 1] >> 8;
198	198
199	199	color = (m_color_mode) ? 1 : (attr & 4) ? 2 : 1; /* TODO: color mode */
200	200
r242413	r242414
685	685	void qx10_state::video_start()
686	686	{
687	687	// allocate memory
688		m_video_ram = auto_alloc_array_clear(machine(), UINT8, 0x60000);
	688	m_video_ram = auto_alloc_array_clear(machine(), UINT16, 0x30000);
689	689
690	690	// find memory regions
691	691	m_char_rom = memregion("chargen")->base();
r242413	r242414
696	696	// ...
697	697	}
698	698
699		READ8_MEMBER( qx10_state::vram_r )
	699	READ16_MEMBER( qx10_state::vram_r )
700	700	{
701	701	int bank = 0;
702	702
r242413	r242414
707	707	return m_video_ram[offset + (0x20000 * bank)];
708	708	}
709	709
710		WRITE8_MEMBER( qx10_state::vram_w )
	710	WRITE16_MEMBER( qx10_state::vram_w )
711	711	{
712	712	int bank = 0;
713	713
r242413	r242414
715	715	else if(m_vram_bank & 2) { bank = 1; } // G
716	716	else if(m_vram_bank & 4) { bank = 2; } // R
717	717
718		m_video_ram[offset + (0x20000 * bank)] = data;
	718	COMBINE_DATA(&m_video_ram[offset + (0x20000 * bank)]);
719	719	}
720	720
721		static ADDRESS_MAP_START( upd7220_map, AS_0, 8, qx10_state )
	721	static ADDRESS_MAP_START( upd7220_map, AS_0, 16, qx10_state )
722	722	AM_RANGE(0x00000, 0x5ffff) AM_READWRITE(vram_r,vram_w)
723	723	ADDRESS_MAP_END
724	724

trunk/src/mess/drivers/simon.c

r242413	r242414
21	21	#include "cpu/tms0980/tms0980.h"
22	22	#include "sound/speaker.h"
23	23
24		#include "simon.lh"
	24	#include "simon.lh" // clickable
25	25
26	26	// master clock is a single stage RC oscillator: R=33K, C=100pf,
27	27	// according to the TMS 1000 series data manual this is around 350kHz

trunk/src/mess/drivers/tandy12.c

r0	r242414
	1	// license:BSD-3-Clause
	2	// copyright-holders:hap
	3	/***************************************************************************
	4
	5	Tandy Radio Shack Computerized Arcade (1981, 1982, 1995)
	6	* TMS1100 CD7282SL
	7
	8	This handheld contains 12 minigames. It looks and plays like "Fabulous Fred"
	9	by the Japanese company Mego Corp. in 1980, which in turn is a mix of Merlin
	10	and Simon. Unlike Merlin and Simon, spin-offs like these were not successful.
	11	There were releases with and without the prefix "Tandy-12", I don't know
	12	which name was more common. Also not worth noting is that it needed five
	13	batteries; 4 C-cells and a 9-volt.
	14
	15	Some of the games require accessories included with the toy (eg. the Baseball
	16	game is played with a board representing the playing field). To start a game,
	17	hold the [SELECT] button, then press [START] when the game button lights up.
	18	As always, refer to the official manual for more information.
	19
	20	See below at the input defs for a list of the games.
	21
	22
	23	TODO:
	24	- output PLA is not verified
	25	- microinstructions PLA is not verified
	26
	27	***************************************************************************/
	28
	29	#include "emu.h"
	30	#include "cpu/tms0980/tms0980.h"
	31	#include "sound/speaker.h"
	32
	33	#include "tandy12.lh" // clickable
	34
	35	// master clock is a single stage RC oscillator: R=39K, C=47pf,
	36	// according to the TMS 1000 series data manual this is around 400kHz
	37	#define MASTER_CLOCK (400000)
	38
	39
	40	class tandy12_state : public driver_device
	41	{
	42	public:
	43	tandy12_state(const machine_config &mconfig, device_type type, const char *tag)
	44	: driver_device(mconfig, type, tag),
	45	m_maincpu(*this, "maincpu"),
	46	m_button_matrix(*this, "IN"),
	47	m_speaker(*this, "speaker")
	48	{ }
	49
	50	required_device<tms1xxx_cpu_device> m_maincpu;
	51	required_ioport_array<5> m_button_matrix;
	52	required_device<speaker_sound_device> m_speaker;
	53
	54	UINT16 m_r;
	55
	56	DECLARE_READ8_MEMBER(read_k);
	57	DECLARE_WRITE16_MEMBER(write_o);
	58	DECLARE_WRITE16_MEMBER(write_r);
	59
	60	virtual void machine_start();
	61	};
	62
	63
	64	/***************************************************************************
	65
	66	I/O
	67
	68	***************************************************************************/
	69
	70	READ8_MEMBER(tandy12_state::read_k)
	71	{
	72	UINT8 k = 0;
	73
	74	// read selected button rows
	75	for (int i = 0; i < 5; i++)
	76	if (m_r >> (i+5) & 1)
	77	k |= m_button_matrix[i]->read();
	78
	79	return k;
	80	}
	81
	82	WRITE16_MEMBER(tandy12_state::write_o)
	83	{
	84	// O0-O7: button lamps 1-8
	85	for (int i = 0; i < 8; i++)
	86	output_set_lamp_value(i, data >> i & 1);
	87	}
	88
	89	WRITE16_MEMBER(tandy12_state::write_r)
	90	{
	91	// R0-R3: button lamps 9-12
	92	for (int i = 0; i < 4; i++)
	93	output_set_lamp_value(i + 8, data >> i & 1);
	94
	95	// R10: speaker out
	96	m_speaker->level_w(data >> 10 & 1);
	97
	98	// R5-R9: input mux
	99	m_r = data;
	100	}
	101
	102
	103
	104	/***************************************************************************
	105
	106	Inputs
	107
	108	***************************************************************************/
	109
	110	/* physical button layout and labels is like this:
	111
	112	REPEAT-2              SPACE-2
	113	[O]     OFF--ON       [O]
	114
	115	[purple]1     [blue]5       [l-green]9
	116	ORGAN         TAG-IT        TREASURE HUNT
	117
	118	[l-orange]2   [turquoise]6  [red]10
	119	SONG WRITER   ROULETTE      COMPETE
	120
	121	[pink]3       [yellow]7     [violet]11
	122	REPEAT        BASEBALL      FIRE AWAY
	123
	124	[green]4      [orange]8     [brown]12
	125	TORPEDO       REPEAT PLUS   HIDE 'N SEEK
	126
	127	[O]        [O]        [O]
	128	START      SELECT    PLAY-2/HIT-7
	129	*/
	130
	131	static INPUT_PORTS_START( tandy12 )
	132	PORT_START("IN.0") // R5
	133	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CODE(KEYCODE_PLUS_PAD) PORT_NAME("12")
	134	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CODE(KEYCODE_MINUS_PAD) PORT_NAME("11")
	135	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("10")
	136	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
	137
	138	PORT_START("IN.1") // R6
	139	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_NAME("Space-2")
	140	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_NAME("Play-2/Hit-7")
	141	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_NAME("Select")
	142	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_NAME("Start")
	143
	144	PORT_START("IN.2") // R7
	145	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_NAME("Repeat-2")
	146	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_UNUSED )
	147	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
	148	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
	149
	150	PORT_START("IN.3") // R8
	151	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("4")
	152	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
	153	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("2")
	154	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("1")
	155
	156	PORT_START("IN.4") // R9
	157	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("8")
	158	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("7")
	159	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
	160	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("5")
	161	INPUT_PORTS_END
	162
	163
	164
	165	/***************************************************************************
	166
	167	Machine Config
	168
	169	***************************************************************************/
	170
	171	void tandy12_state::machine_start()
	172	{
	173	m_r = 0;
	174	save_item(NAME(m_r));
	175	}
	176
	177
	178	static const UINT16 tandy12_output_pla[0x20] =
	179	{
	180	// these are certain
	181	0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40,
	182	0x80, 0x00, 0x00, 0x00, 0x00,
	183
	184	// rest is unused?
	185	0x00, 0x00, 0x00,
	186	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	187	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
	188	};
	189
	190
	191	static MACHINE_CONFIG_START( tandy12, tandy12_state )
	192
	193	/* basic machine hardware */
	194	MCFG_CPU_ADD("maincpu", TMS1100, MASTER_CLOCK)
	195	MCFG_TMS1XXX_OUTPUT_PLA(tandy12_output_pla)
	196	MCFG_TMS1XXX_READ_K_CB(READ8(tandy12_state, read_k))
	197	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(tandy12_state, write_o))
	198	MCFG_TMS1XXX_WRITE_R_CB(WRITE16(tandy12_state, write_r))
	199
	200	MCFG_DEFAULT_LAYOUT(layout_tandy12)
	201
	202	/* no video! */
	203
	204	/* sound hardware */
	205	MCFG_SPEAKER_STANDARD_MONO("mono")
	206	MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
	207	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
	208	MACHINE_CONFIG_END
	209
	210
	211
	212	/***************************************************************************
	213
	214	Game driver(s)
	215
	216	***************************************************************************/
	217
	218	ROM_START( tandy12 )
	219	ROM_REGION( 0x800, "maincpu", 0 )
	220	ROM_LOAD( "cd7282sl", 0x0000, 0x800, CRC(a10013dd) SHA1(42ebd3de3449f371b99937f9df39c240d15ac686) )
	221
	222	ROM_REGION( 867, "maincpu:mpla", 0 )
	223	ROM_LOAD( "tms1100_default_mpla.pla", 0, 867, BAD_DUMP CRC(62445fc9) SHA1(d6297f2a4bc7a870b76cc498d19dbb0ce7d69fec) ) // not verified
	224	ROM_REGION( 365, "maincpu:opla", 0 )
	225	ROM_LOAD( "tms1100_tandy12_opla.pla", 0, 365, NO_DUMP )
	226	ROM_END
	227
	228
	229	CONS( 1981, tandy12, 0, 0, tandy12, tandy12, driver_device, 0, "Tandy Radio Shack", "Tandy-12 - Computerized Arcade", GAME_SUPPORTS_SAVE )

trunk/src/mess/drivers/victor9k.c

r242413	r242414
13	13
14	14	TODO:
15	15
16		- centronics
	16	- keyboard
17	17	- expansion bus
18	18	- Z80 card
19	19	- Winchester DMA card (Xebec S1410 + Tandon TM502/TM603SE)
20	20	- RAM cards
21	21	- clock cards
22	22	- floppy 8048
23		- keyboard
24	23	- hires graphics
25	24	- brightness/contrast
26	25	- MC6852
r242413	r242414
41	40	//-------------------------------------------------
42	41
43	42	static ADDRESS_MAP_START( victor9k_mem, AS_PROGRAM, 8, victor9k_state )
44		//  AM_RANGE(0x00000, 0xdffff) AM_RAM
	43	AM_RANGE(0x00000, 0x1ffff) AM_RAM
45	44	AM_RANGE(0x20000, 0xdffff) AM_NOP
46		AM_RANGE(0xe0000, 0xe0001) AM_DEVREADWRITE(I8259A_TAG, pic8259_device, read, write)
47		AM_RANGE(0xe0020, 0xe0023) AM_DEVREADWRITE(I8253_TAG, pit8253_device, read, write)
48		AM_RANGE(0xe0040, 0xe0043) AM_DEVREADWRITE(UPD7201_TAG, upd7201_device, cd_ba_r, cd_ba_w)
	45	AM_RANGE(0xe0000, 0xe0001) AM_MIRROR(0x7f00) AM_DEVREADWRITE(I8259A_TAG, pic8259_device, read, write)
	46	AM_RANGE(0xe0020, 0xe0023) AM_MIRROR(0x7f00) AM_DEVREADWRITE(I8253_TAG, pit8253_device, read, write)
	47	AM_RANGE(0xe0040, 0xe0043) AM_MIRROR(0x7f00) AM_DEVREADWRITE(UPD7201_TAG, upd7201_device, cd_ba_r, cd_ba_w)
49	48	AM_RANGE(0xe8000, 0xe8000) AM_MIRROR(0x7f00) AM_DEVREADWRITE(HD46505S_TAG, mc6845_device, status_r, address_w)
50	49	AM_RANGE(0xe8001, 0xe8001) AM_MIRROR(0x7f00) AM_DEVREADWRITE(HD46505S_TAG, mc6845_device, register_r, register_w)
51	50	AM_RANGE(0xe8020, 0xe802f) AM_MIRROR(0x7f00) AM_DEVREADWRITE(M6522_1_TAG, via6522_device, read, write)
r242413	r242414
56	55	AM_RANGE(0xe80c0, 0xe80cf) AM_MIRROR(0x7f00) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs6_r, cs6_w)
57	56	AM_RANGE(0xe80e0, 0xe80ef) AM_MIRROR(0x7f00) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs7_r, cs7_w)
58	57	AM_RANGE(0xf0000, 0xf0fff) AM_MIRROR(0x1000) AM_RAM AM_SHARE("video_ram")
59		AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION(I8088_TAG, 0)
	58	AM_RANGE(0xf8000, 0xf9fff) AM_MIRROR(0x6000) AM_ROM AM_REGION(I8088_TAG, 0)
60	59	ADDRESS_MAP_END
61	60
62	61
r242413	r242414
169	168	{
170	169	m_ssda_irq = state;
171	170
172		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
	171	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
173	172	}
174	173
175	174
r242413	r242414
190	189
191	190	*/
192	191
	192	// centronics
	193	m_centronics->write_data0(BIT(data, 0));
	194	m_centronics->write_data1(BIT(data, 1));
	195	m_centronics->write_data2(BIT(data, 2));
	196	m_centronics->write_data3(BIT(data, 3));
	197	m_centronics->write_data4(BIT(data, 4));
	198	m_centronics->write_data5(BIT(data, 5));
	199	m_centronics->write_data6(BIT(data, 6));
	200	m_centronics->write_data7(BIT(data, 7));
	201
	202	// IEEE-488
193	203	m_ieee488->dio_w(data);
194	204	}
195	205
r242413	r242414
211	221
212	222	bit     description
213	223
214		PB0     DAV
215		PB1     EOI
	224	PB0     DAV / DATA STROBE
	225	PB1     EOI / VFU?
216	226	PB2     REN
217	227	PB3     ATN
218	228	PB4     IFC
r242413	r242414
222	232
223	233	*/
224	234
	235	// centronics
	236	m_centronics->write_strobe(BIT(data, 0));
	237
225	238	// IEEE-488
226	239	m_ieee488->dav_w(BIT(data, 0));
227	240	m_ieee488->eoi_w(BIT(data, 1));
r242413	r242414
241	254	{
242	255	m_via1_irq = state;
243	256
244		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
	257	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
245	258	}
246	259
247	260	WRITE8_MEMBER( victor9k_state::via2_pa_w )
r242413	r242414
304	317	}
305	318
306	319
307		WRITE_LINE_MEMBER( victor9k_state::via2_irq_w )
308		{
309		m_via2_irq = state;
310
311		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
312		}
313
314
315	320	/*
316	321	bit    description
317	322
r242413	r242414
348	353	{
349	354	m_via3_irq = state;
350	355
351		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
	356	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
352	357	}
353	358
354	359
r242413	r242414
359	364	WRITE_LINE_MEMBER( victor9k_state::kbrdy_w )
360	365	{
361	366	//logerror("KBRDY %u\n", state);
	367
362	368	m_via2->write_cb1(state);
363
364		m_pic->ir6_w(state ? CLEAR_LINE : ASSERT_LINE);
365	369	}
366	370
367	371	WRITE_LINE_MEMBER( victor9k_state::kbdata_w )
368	372	{
369	373	//logerror("KBDATA %u\n", state);
	374
370	375	m_via2->write_cb2(state);
371	376	m_via2->write_pa6(state);
372	377	}
r242413	r242414
376	381	{
377	382	m_fdc_irq = state;
378	383
379		m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
	384	m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
380	385	}
381	386
382	387
r242413	r242414
390	395	save_item(NAME(m_brt));
391	396	save_item(NAME(m_cont));
392	397	save_item(NAME(m_via1_irq));
393		save_item(NAME(m_via2_irq));
394	398	save_item(NAME(m_via3_irq));
395	399	save_item(NAME(m_fdc_irq));
396	400	save_item(NAME(m_ssda_irq));
397	401
398		// memory banking
399		address_space &program = m_maincpu->space(AS_PROGRAM);
400		program.install_ram(0x00000, m_ram->size() - 1, m_ram->pointer());
401
402	402	// patch out SCP self test
403	403	m_rom->base()[0x11ab] = 0xc3;
404	404
r242413	r242414
422	422	}
423	423
424	424
	425
425	426	//**************************************************************************
426	427	//  MACHINE CONFIGURATION
427	428	//**************************************************************************
r242413	r242414
446	447
447	448	MCFG_PALETTE_ADD_MONOCHROME_GREEN_HIGHLIGHT("palette")
448	449
449		MCFG_MC6845_ADD(HD46505S_TAG, HD6845, SCREEN_TAG, 1000000) // HD6845 == HD46505S
	450	MCFG_MC6845_ADD(HD46505S_TAG, HD6845, SCREEN_TAG, XTAL_30MHz/11) // HD6845 == HD46505S
450	451	MCFG_MC6845_SHOW_BORDER_AREA(true)
451	452	MCFG_MC6845_CHAR_WIDTH(10)
452	453	MCFG_MC6845_UPDATE_ROW_CB(victor9k_state, crtc_update_row)
r242413	r242414
501	502	MCFG_DEVICE_ADD(M6522_2_TAG, VIA6522, XTAL_30MHz/30)
502	503	MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor9k_state, via2_pa_w))
503	504	MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via2_pb_w))
504		MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via2_irq_w))
	505	MCFG_VIA6522_IRQ_HANDLER(DEVWRITELINE(I8259A_TAG, pic8259_device, ir6_w))
505	506
506	507	MCFG_DEVICE_ADD(M6522_3_TAG, VIA6522, XTAL_30MHz/30)
507	508	MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via3_pb_w))
508	509	MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via3_irq_w))
509	510
	511	MCFG_CENTRONICS_ADD(CENTRONICS_TAG, centronics_devices, "printer")
	512	MCFG_CENTRONICS_BUSY_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb5))
	513	MCFG_CENTRONICS_ACK_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb6))
	514	MCFG_CENTRONICS_SELECT_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb7))
	515
510	516	MCFG_RS232_PORT_ADD(RS232_A_TAG, default_rs232_devices, NULL)
511	517	MCFG_RS232_RXD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, rxa_w))
512	518	MCFG_RS232_DCD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, dcda_w))
r242413	r242414
521	527	MCFG_RS232_CTS_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, ctsb_w))
522	528	MCFG_RS232_DSR_HANDLER(DEVWRITELINE(M6522_2_TAG, via6522_device, write_pa5))
523	529
524		MCFG_DEVICE_ADD(VICTOR9K_KEYBOARD_TAG, VICTOR9K_KEYBOARD, 0)
	530	MCFG_DEVICE_ADD(KB_TAG, VICTOR9K_KEYBOARD, 0)
525	531	MCFG_VICTOR9K_KBRDY_HANDLER(WRITELINE(victor9k_state, kbrdy_w))
526	532	MCFG_VICTOR9K_KBDATA_HANDLER(WRITELINE(victor9k_state, kbdata_w))
527	533
r242413	r242414
533	539	// internal ram
534	540	MCFG_RAM_ADD(RAM_TAG)
535	541	MCFG_RAM_DEFAULT_SIZE("128K")
536		MCFG_RAM_EXTRA_OPTIONS("256K,384K,512K,640K,768K,896K")
537	542
538	543	// software list
539	544	MCFG_SOFTWARE_LIST_ADD("flop_list", "victor9k_flop")

trunk/src/mess/drivers/vt240.c

r242413	r242414
18	18	****************************************************************************/
19	19
20	20	#include "emu.h"
	21
	22	#include "bus/rs232/rs232.h"
21	23	#include "cpu/i8085/i8085.h"
22	24	#include "cpu/t11/t11.h"
	25	#include "machine/clock.h"
	26	#include "machine/dec_lk201.h"
	27	#include "machine/i8251.h"
	28	#include "machine/mc68681.h"
	29	#include "machine/ms7004.h"
23	30	#include "machine/ram.h"
24	31	#include "video/upd7220.h"
25	32
	33	#define VERBOSE_DBG 1       /* general debug messages */
26	34
	35	#define DBG_LOG(N,M,A) \
	36	do { \
	37	if(VERBOSE_DBG>=N) \
	38	{ \
	39	logerror("%11.6f at %s: ",machine().time().as_double(),machine().describe_context()); \
	40	logerror A; \
	41	} \
	42	} while (0)
	43
27	44	class vt240_state : public driver_device
28	45	{
29	46	public:
30	47	vt240_state(const machine_config &mconfig, device_type type, const char *tag)
31	48	: driver_device(mconfig, type, tag),
32	49	m_maincpu(*this, "maincpu"),
	50	m_i8251(*this, "i8251"),
	51	m_duart(*this, "duart"),
33	52	m_hgdc(*this, "upd7220"),
34	53	m_video_ram(*this, "video_ram"){ }
35	54
36	55	required_device<cpu_device> m_maincpu;
	56
	57	required_device<i8251_device> m_i8251;
	58	DECLARE_WRITE_LINE_MEMBER(write_keyboard_clock);
	59
	60	required_device<mc68681_device> m_duart;
	61
37	62	required_device<upd7220_device> m_hgdc;
38	63	DECLARE_READ8_MEMBER( test_r );
39	64	DECLARE_READ8_MEMBER( pcg_r );
r242413	r242414
43	68	//UINT8 m_pcg_internal_addr;
44	69	//UINT8 *m_char_rom;
45	70
46		required_shared_ptr<UINT8> m_video_ram;
	71	required_shared_ptr<UINT16> m_video_ram;
	72
47	73	DECLARE_DRIVER_INIT(vt240);
48	74	virtual void machine_reset();
49	75	INTERRUPT_GEN_MEMBER(vt240_irq);
50	76	UPD7220_DRAW_TEXT_LINE_MEMBER( hgdc_draw_text );
51	77	};
52	78
	79	WRITE_LINE_MEMBER(vt240_state::write_keyboard_clock)
	80	{
	81	m_i8251->write_txc(state);
	82	m_i8251->write_rxc(state);
	83	}
	84
53	85	/* TODO */
54	86	UPD7220_DRAW_TEXT_LINE_MEMBER( vt240_state::hgdc_draw_text )
55	87	{
r242413	r242414
101	133	}
102	134
103	135
104		static ADDRESS_MAP_START(vt240_mem, AS_PROGRAM, 8, vt240_state)
	136	// PDF page 78 (4-25)
	137	static ADDRESS_MAP_START( vt240_mem, AS_PROGRAM, 16, vt240_state )
105	138	ADDRESS_MAP_UNMAP_HIGH
106		AM_RANGE(0x0000, 0x3fff) AM_ROM AM_REGION("ipl", 0)
107		AM_RANGE(0x4000, 0x5fff) AM_ROM AM_REGION("ipl", 0x8000)
	139	AM_RANGE (0000000, 0077777) AM_ROM
	140	// 0170xxx MEM MAP/8085 decoder
	141	AM_RANGE (0171000, 0171003) AM_DEVREADWRITE8("i8251", i8251_device, data_r, data_w, 0x00ff)
	142	AM_RANGE (0171004, 0171007) AM_DEVREADWRITE8("i8251", i8251_device, status_r, control_w, 0x00ff)
	143	AM_RANGE (0172000, 0172077) AM_DEVREADWRITE8("duart", mc68681_device, read, write, 0xff)
	144	// 0173000 Video logic
	145	// 0174000 Video logic
	146	// 017500x Video logic
	147	// 0176xxx NVR
	148	// 017700x System comm logic
	149	ADDRESS_MAP_END
	150
	151	// PDF page 134 (6-9)
	152	#if 0
	153	static ADDRESS_MAP_START(vt240_char_mem, AS_PROGRAM, 8, vt240_state)
	154	ADDRESS_MAP_UNMAP_HIGH
	155	AM_RANGE(0x0000, 0x3fff) AM_ROM AM_REGION("charcpu", 0)
	156	AM_RANGE(0x4000, 0x5fff) AM_ROM AM_REGION("charcpu", 0x8000)
108	157	AM_RANGE(0x8000, 0x87ff) AM_RAM
109	158	ADDRESS_MAP_END
110	159
111		static ADDRESS_MAP_START(vt240_io, AS_IO, 8, vt240_state)
	160	static ADDRESS_MAP_START(vt240_char_io, AS_IO, 8, vt240_state)
112	161	ADDRESS_MAP_UNMAP_HIGH
113	162	ADDRESS_MAP_GLOBAL_MASK(0xff)
114	163	AM_RANGE(0x00, 0x01) AM_DEVREADWRITE("upd7220", upd7220_device, read, write)
115	164	AM_RANGE(0x20, 0x20) AM_READ(test_r)
116	165	//AM_RANGE(0x30, 0x30) AM_READWRITE(pcg_r,pcg_w) // 0x30 PCG
117	166	ADDRESS_MAP_END
	167	#endif
118	168
119
120		static ADDRESS_MAP_START( upd7220_map, AS_0, 8, vt240_state)
	169	static ADDRESS_MAP_START( upd7220_map, AS_0, 16, vt240_state)
121	170	AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram")
122	171	ADDRESS_MAP_END
123	172
r242413	r242414
135	184	//device.execute().set_input_line(I8085_RST65_LINE, ASSERT_LINE);
136	185	}
137	186
138		static const gfx_layout vt240_chars_8x8 =
	187	static const gfx_layout vt240_chars_8x10 =
139	188	{
140	189	8,10,
141	190	RGN_FRAC(1,1),
r242413	r242414
143	192	{ 0 },
144	193	{ STEP8(0,1) },
145	194	{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8, 9*8 },
146		8*16
	195	8*10
147	196	};
148	197
149	198	static GFXDECODE_START( vt240 )
150		GFXDECODE_ENTRY( "ipl", 0x0000, vt240_chars_8x8, 0, 8 )
	199	GFXDECODE_ENTRY( "charcpu", 0x338*10-2, vt240_chars_8x10, 0, 8 )
151	200	GFXDECODE_END
152	201
153		static MACHINE_CONFIG_START( vt240, vt240_state )
154		/* basic machine hardware */
155		MCFG_CPU_ADD("maincpu", I8085A, XTAL_16MHz / 4)
	202	static MACHINE_CONFIG_FRAGMENT( vt240_motherboard )
	203	MCFG_CPU_ADD("maincpu", T11, XTAL_7_3728MHz) // confirm
156	204	MCFG_CPU_PROGRAM_MAP(vt240_mem)
157		MCFG_CPU_IO_MAP(vt240_io)
	205	MCFG_T11_INITIAL_MODE(5 << 13)
	206
	207	/*
	208	MCFG_CPU_ADD("charcpu", I8085A, XTAL_16MHz / 4)
	209	MCFG_CPU_PROGRAM_MAP(vt240_char_mem)
	210	MCFG_CPU_IO_MAP(vt240_char_io)
158	211	MCFG_CPU_VBLANK_INT_DRIVER("screen", vt240_state, vt240_irq)
	212	*/
159	213
160
161		/* video hardware */
162	214	MCFG_SCREEN_ADD("screen", RASTER)
163	215	MCFG_SCREEN_REFRESH_RATE(50)
164	216	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
165	217	MCFG_SCREEN_SIZE(640, 480)
166	218	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
167		//  MCFG_VIDEO_START_OVERRIDE(vt240_state,vt240)
	219	//   MCFG_VIDEO_START_OVERRIDE(vt240_state,vt240)
168	220	MCFG_SCREEN_UPDATE_DEVICE("upd7220", upd7220_device, screen_update)
169	221	MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
170	222	MCFG_GFXDECODE_ADD("gfxdecode", "palette", vt240)
r242413	r242414
172	224	MCFG_DEVICE_ADD("upd7220", UPD7220, XTAL_4MHz / 4)
173	225	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_map)
174	226	MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(vt240_state, hgdc_draw_text)
	227
	228	MCFG_MC68681_ADD("duart", XTAL_3_6864MHz) /* 2681 duart (not 68681!) */
	229	//   MCFG_MC68681_IRQ_CALLBACK(WRITELINE(dectalk_state, dectalk_duart_irq_handler))
	230	MCFG_MC68681_A_TX_CALLBACK(DEVWRITELINE("rs232", rs232_port_device, write_txd))
	231	//   MCFG_MC68681_B_TX_CALLBACK(WRITELINE(dectalk_state, dectalk_duart_txa))
	232	//   MCFG_MC68681_INPORT_CALLBACK(READ8(dectalk_state, dectalk_duart_input))
	233	//   MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(dectalk_state, dectalk_duart_output))
	234	//   MCFG_I8251_DTR_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
	235	//   MCFG_I8251_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
	236
	237	MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "null_modem")
	238	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("duart", mc68681_device, rx_a_w))
	239	//   MCFG_RS232_DSR_HANDLER(DEVWRITELINE("duart", mc68681_device, ipX_w))
175	240	MACHINE_CONFIG_END
176	241
	242	static MACHINE_CONFIG_START( mc7105, vt240_state )
	243	MCFG_FRAGMENT_ADD(vt240_motherboard)
	244
	245	// serial connection to MS7004 keyboard
	246	MCFG_DEVICE_ADD("i8251", I8251, 0)
	247	//   MCFG_I8251_RXRDY_HANDLER(DEVWRITELINE("pic8259", pic8259_device, ir1_w))
	248
	249	MCFG_DEVICE_ADD("ms7004", MS7004, 0)
	250	MCFG_MS7004_TX_HANDLER(DEVWRITELINE("i8251", i8251_device, write_rxd))
	251
	252	// baud rate is supposed to be 4800 but keyboard is slightly faster
	253	MCFG_DEVICE_ADD("keyboard_clock", CLOCK, 4960*16)
	254	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(vt240_state, write_keyboard_clock))
	255	MACHINE_CONFIG_END
	256
177	257	/* ROM definition */
178	258	ROM_START( mc7105 )
179		ROM_REGION( 0x10000, "ipl", ROMREGION_ERASEFF )
	259	ROM_REGION( 0x10000, "charcpu", ROMREGION_ERASEFF )
180	260	ROM_LOAD( "027.bin", 0x8000, 0x8000, CRC(a159b412) SHA1(956097ccc2652d494258b3682498cfd3096d7d4f))
181	261	ROM_LOAD( "028.bin", 0x0000, 0x8000, CRC(b253151f) SHA1(22ffeef8eb5df3c38bfe91266f26d1e7822cdb53))
182	262
183		ROM_REGION( 0x20000, "subcpu", ROMREGION_ERASEFF )
	263	ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASEFF )
184	264	ROM_LOAD16_BYTE( "029.bin", 0x00000, 0x8000, CRC(4a6db217) SHA1(47637325609ea19ffab61fe31e2700d72fa50729))
185	265	ROM_LOAD16_BYTE( "031.bin", 0x00001, 0x8000, CRC(47129579) SHA1(39de9e2e26f90c5da5e72a09ff361c1a94b9008a))
186	266	ROM_LOAD16_BYTE( "030.bin", 0x10000, 0x8000, CRC(05fd7b75) SHA1(2ad8c14e76accfa1b9b8748c58e9ebbc28844a47))
r242413	r242414
190	270	/* Driver */
191	271	DRIVER_INIT_MEMBER(vt240_state,vt240)
192	272	{
193		UINT8 *ROM = memregion("ipl")->base();
	273	UINT8 *ROM = memregion("charcpu")->base();
194	274
195	275	/* patch T11 check */
196	276	ROM[0x09d] = 0x00;
197	277	ROM[0x09e] = 0x00;
198	278	ROM[0x09f] = 0x00;
199	279
200		/* ROM checksum*/
	280	/* ROM checksum */
201	281	ROM[0x15c] = 0x00;
202	282	ROM[0x15d] = 0x00;
203	283	ROM[0x15e] = 0x00;
r242413	r242414
206	286	/*    YEAR  NAME    PARENT  COMPAT   MACHINE    INPUT    INIT    COMPANY                      FULLNAME       FLAGS */
207	287	//COMP( 1983, vt240,  0,      0,       vt220,     vt220, driver_device,   0,  "Digital Equipment Corporation", "VT240", GAME_NOT_WORKING | GAME_NO_SOUND)
208	288	//COMP( 1983, vt241,  0,      0,       vt220,     vt220, driver_device,   0,  "Digital Equipment Corporation", "VT241", GAME_NOT_WORKING | GAME_NO_SOUND)
209		COMP( 1983, mc7105, 0,      0,       vt240,     vt240, vt240_state,   vt240,  "Elektronika",                  "MC7105", GAME_NOT_WORKING | GAME_NO_SOUND)
	289	COMP( 1983, mc7105, 0,      0,       mc7105,    vt240, vt240_state,   vt240,  "Elektronika",                  "MC7105", GAME_NOT_WORKING | GAME_NO_SOUND)

trunk/src/mess/drivers/vtech1.c

r242413	r242414
451	451	MCFG_CASSETTE_ADD( "cassette" )
452	452	MCFG_CASSETTE_FORMATS(vtech1_cassette_formats)
453	453	MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_PLAY)
	454	MCFG_CASSETTE_INTERFACE("vtech1_cass")
	455
	456	MCFG_SOFTWARE_LIST_ADD("cass_list", "vz_cass")
454	457	MACHINE_CONFIG_END
455	458
456	459	static MACHINE_CONFIG_DERIVED( laser200, laser110 )

trunk/src/mess/includes/compis.h

r242413	r242414
84	84	required_device<isbx_slot_device> m_isbx0;
85	85	required_device<isbx_slot_device> m_isbx1;
86	86	required_device<ram_device> m_ram;
87		required_shared_ptr<UINT8> m_video_ram;
	87	required_shared_ptr<UINT16> m_video_ram;
88	88	required_ioport m_s8;
89	89
90	90	virtual void machine_start();

trunk/src/mess/includes/genpc.h

r242413	r242414
154	154	MCFG_DEVICE_ADD(_tag, EC1841_MOTHERBOARD, 0) \
155	155	ec1841_mb_device::static_set_cputag(*device, _cputag);
156	156
157		// ======================> ibm5150_mb_device
158	157	class ec1841_mb_device : public ibm5160_mb_device
159	158	{
160	159	public:
r242413	r242414
177	176	virtual DECLARE_WRITE_LINE_MEMBER( keyboard_clock_w );
178	177	};
179	178
180
181		// device type definition
182	179	extern const device_type EC1841_MOTHERBOARD;
183	180
184	181	#define MCFG_PCNOPPI_MOTHERBOARD_ADD(_tag, _cputag) \

trunk/src/mess/includes/mc1502.h

r242413	r242414
77	77
78	78	private:
79	79	int m_pit_out2;
80
81		/*
82		TIMER_CALLBACK_MEMBER(fdc_motor_callback);
83		static struct {
84		int         fdc_motor_on;
85		emu_timer   *fdc_motor_timer;
86		} m_motor;
87		const char *m_cputag;
88		*/
89	80	};
90	81
91	82	#endif /* MC1502_H_ */

trunk/src/mess/includes/mikromik.h

r242413	r242414
81	81	required_memory_region m_rom;
82	82	required_memory_region m_mmu_rom;
83	83	required_memory_region m_char_rom;
84		required_shared_ptr<UINT8> m_video_ram;
	84	required_shared_ptr<UINT16> m_video_ram;
85	85
86	86	virtual void machine_start();
87	87	virtual void machine_reset();

trunk/src/mess/includes/victor9k.h

r242413	r242414
15	15	#define __VICTOR9K__
16	16
17	17	#include "bus/rs232/rs232.h"
	18	#include "bus/centronics/ctronics.h"
18	19	#include "cpu/i86/i86.h"
19	20	#include "formats/victor9k_dsk.h"
20	21	#include "imagedev/floppy.h"
r242413	r242414
47	48	#define RS232_A_TAG     "rs232a"
48	49	#define RS232_B_TAG     "rs232b"
49	50	#define SCREEN_TAG      "screen"
50		#define VICTOR9K_KEYBOARD_TAG   "victor9kb"
	51	#define KB_TAG         "kb"
51	52	#define FDC_TAG         "fdc"
52	53
53	54	class victor9k_state : public driver_device
r242413	r242414
66	67	m_cvsd(*this, HC55516_TAG),
67	68	m_crtc(*this, HD46505S_TAG),
68	69	m_ram(*this, RAM_TAG),
69		m_kb(*this, VICTOR9K_KEYBOARD_TAG),
	70	m_kb(*this, KB_TAG),
70	71	m_fdc(*this, FDC_TAG),
	72	m_centronics(*this, CENTRONICS_TAG),
71	73	m_rs232a(*this, RS232_A_TAG),
72	74	m_rs232b(*this, RS232_B_TAG),
73	75	m_palette(*this, "palette"),
r242413	r242414
76	78	m_brt(0),
77	79	m_cont(0),
78	80	m_via1_irq(CLEAR_LINE),
79		m_via2_irq(CLEAR_LINE),
80	81	m_via3_irq(CLEAR_LINE),
81	82	m_fdc_irq(CLEAR_LINE),
82	83	m_ssda_irq(CLEAR_LINE)
r242413	r242414
93	94	required_device<hc55516_device> m_cvsd;
94	95	required_device<mc6845_device> m_crtc;
95	96	required_device<ram_device> m_ram;
96		required_device<victor9k_keyboard_device> m_kb;
	97	required_device<victor_9000_keyboard_t> m_kb;
97	98	required_device<victor_9000_fdc_t> m_fdc;
	99	required_device<centronics_device> m_centronics;
98	100	required_device<rs232_port_device> m_rs232a;
99	101	required_device<rs232_port_device> m_rs232b;
100	102	required_device<palette_device> m_palette;
r242413	r242414
115	117	DECLARE_WRITE8_MEMBER( via2_pb_w );
116	118	DECLARE_WRITE_LINE_MEMBER( write_ria );
117	119	DECLARE_WRITE_LINE_MEMBER( write_rib );
118		DECLARE_WRITE_LINE_MEMBER( via2_irq_w );
119	120
120	121	DECLARE_WRITE8_MEMBER( via3_pb_w );
121	122	DECLARE_WRITE_LINE_MEMBER( via3_irq_w );
r242413	r242414
136	137
137	138	/* interrupts */
138	139	int m_via1_irq;
139		int m_via2_irq;
140	140	int m_via3_irq;
141	141	int m_fdc_irq;
142	142	int m_ssda_irq;

trunk/src/mess/layout/bitgrpha.lay

r0	r242414
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3	<view name="Standard">
	4	<screen index="0">
	5	<bounds left="0" top="0" right="767" bottom="1023" />
	6	<orientation rotate="90" />
	7	</screen>
	8	</view>
	9	</mamelayout>

trunk/src/mess/layout/bitgrphb.lay

r0	r242414
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3	<view name="Standard">
	4	<screen index="0">
	5	<bounds left="0" top="0" right="767" bottom="1023" />
	6	<orientation rotate="270" />
	7	</screen>
	8	</view>
	9	</mamelayout>

trunk/src/mess/layout/mathmagi.lay

r242413	r242414
31	31	<!-- build screen -->
32	32
33	33	<view name="Internal Layout">
34		<bounds left="0" right="100" top="0" bottom="15" />
	34	<bounds left="0" right="100" top="0" bottom="25" />
35	35
36	36	<bezel name="digit0" element="digit">
37		<bounds x="0" y="0" width="10" height="15" />
	37	<bounds x="0" y="10" width="10" height="15" />
38	38	</bezel>
39	39	<bezel name="digit1" element="digit">
40		<bounds x="10" y="0" width="10" height="15" />
	40	<bounds x="10" y="10" width="10" height="15" />
41	41	</bezel>
42	42
43	43	<bezel name="digit2" element="digit">
44		<bounds x="30" y="0" width="10" height="15" />
	44	<bounds x="30" y="10" width="10" height="15" />
45	45	</bezel>
46	46	<bezel name="digit3" element="digit">
47		<bounds x="40" y="0" width="10" height="15" />
	47	<bounds x="40" y="10" width="10" height="15" />
48	48	</bezel>
49	49
50	50	<bezel name="digit4" element="digit">
51		<bounds x="60" y="0" width="10" height="15" />
	51	<bounds x="60" y="10" width="10" height="15" />
52	52	</bezel>
53	53	<bezel name="digit5" element="digit">
54		<bounds x="70" y="0" width="10" height="15" />
	54	<bounds x="70" y="10" width="10" height="15" />
55	55	</bezel>
56	56	<bezel name="digit6" element="digit">
57		<bounds x="80" y="0" width="10" height="15" />
	57	<bounds x="80" y="10" width="10" height="15" />
58	58	</bezel>
59	59	<bezel name="digit7" element="digit">
60		<bounds x="90" y="0" width="10" height="15" />
	60	<bounds x="90" y="10" width="10" height="15" />
61	61	</bezel>
62	62
63		<!-- math symbols custom digit -->
	63	<!-- math symbols custom digit -->
64	64
65		<bezel name="lamp65" element="lamp_dash"><bounds x="21.5" y="7.25" width="7" height="0.5" /></bezel>
	65	<bezel name="lamp87" element="lamp_dash"><bounds x="21.5" y="17.25" width="7" height="0.5" /></bezel>
66	66
67		<bezel name="lamp61" element="lamp_slash"><bounds x="24" y="-0.5" width="5" height="7.5" /></bezel>
68		<bezel name="lamp64" element="lamp_slash"><bounds x="21" y="7" width="5" height="7.5" /></bezel>
	67	<bezel name="lamp82" element="lamp_slash"><bounds x="24" y="9.5" width="5" height="7.5" /></bezel>
	68	<bezel name="lamp82" element="lamp_slash"><bounds x="21" y="17" width="5" height="7.5" /></bezel>
69	69
70		<bezel name="lamp66" element="lamp_backslash"><bounds x="21" y="-0.5" width="5" height="7.5" /></bezel>
71		<bezel name="lamp62" element="lamp_backslash"><bounds x="24" y="7" width="5" height="7.5" /></bezel>
	70	<bezel name="lamp83" element="lamp_backslash"><bounds x="21" y="9.5" width="5" height="7.5" /></bezel>
	71	<bezel name="lamp83" element="lamp_backslash"><bounds x="24" y="17" width="5" height="7.5" /></bezel>
72	72
73		<bezel name="lamp60" element="lamp_dot"><bounds x="24.25" y="2.25" width="1.5" height="1.5" /></bezel>
74		<bezel name="lamp63" element="lamp_dot"><bounds x="24.25" y="11.75" width="1.5" height="1.5" /></bezel>
	73	<bezel name="lamp81" element="lamp_dot"><bounds x="24.25" y="12.25" width="1.5" height="1.5" /></bezel>
	74	<bezel name="lamp81" element="lamp_dot"><bounds x="24.25" y="21.75" width="1.5" height="1.5" /></bezel>
75	75
76		<!-- equals sign custom digit -->
	76	<!-- equals sign custom digit -->
77	77
	78	<bezel name="lamp91" element="lamp_dash"><bounds x="51.5" y="14.5" width="7" height="0.5" /></bezel>
	79	<bezel name="lamp94" element="lamp_dash"><bounds x="51.5" y="20.0" width="7" height="0.5" /></bezel>
78	80
	81	<!-- other lamps -->
	82
	83	<bezel name="lamp101" element="lamp_dot"><bounds x="1" y="1" width="4" height="4" /></bezel>
	84	<bezel name="lamp102" element="lamp_dot"><bounds x="26" y="1" width="4" height="4" /></bezel>
	85	<bezel name="lamp104" element="lamp_dot"><bounds x="51" y="1" width="4" height="4" /></bezel>
	86	<bezel name="lamp107" element="lamp_dot"><bounds x="76" y="1" width="4" height="4" /></bezel>
	87
	88
79	89	</view>
80	90	</mamelayout>

trunk/src/mess/layout/tandy12.lay

r0	r242414
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3
	4
	5	<!-- ugly layout is temp, will be improved soon -->
	6
	7
	8
	9
	10	<!-- define elements -->
	11
	12	<element name="lamp_dot" defstate="0">
	13	<disk state="1"><color red="1.0" green="0.3" blue="0.2" /></disk>
	14	<disk state="0"><color red="0.125490" green="0.035294" blue="0.0235294" /></disk>
	15	</element>
	16
	17
	18
	19	<!-- build screen -->
	20
	21	<view name="Internal Layout">
	22	<bounds left="0" right="100" top="0" bottom="100" />
	23
	24	<bezel name="lamp0" element="lamp_dot"><bounds x="10" y="10" width="5" height="5" /></bezel>
	25	<bezel name="lamp4" element="lamp_dot"><bounds x="20" y="10" width="5" height="5" /></bezel>
	26	<bezel name="lamp8" element="lamp_dot"><bounds x="30" y="10" width="5" height="5" /></bezel>
	27
	28	<bezel name="lamp1" element="lamp_dot"><bounds x="10" y="20" width="5" height="5" /></bezel>
	29	<bezel name="lamp5" element="lamp_dot"><bounds x="20" y="20" width="5" height="5" /></bezel>
	30	<bezel name="lamp9" element="lamp_dot"><bounds x="30" y="20" width="5" height="5" /></bezel>
	31
	32	<bezel name="lamp2" element="lamp_dot"><bounds x="10" y="30" width="5" height="5" /></bezel>
	33	<bezel name="lamp6" element="lamp_dot"><bounds x="20" y="30" width="5" height="5" /></bezel>
	34	<bezel name="lamp10" element="lamp_dot"><bounds x="30" y="30" width="5" height="5" /></bezel>
	35
	36	<bezel name="lamp3" element="lamp_dot"><bounds x="10" y="40" width="5" height="5" /></bezel>
	37	<bezel name="lamp7" element="lamp_dot"><bounds x="20" y="40" width="5" height="5" /></bezel>
	38	<bezel name="lamp11" element="lamp_dot"><bounds x="30" y="40" width="5" height="5" /></bezel>
	39
	40
	41	</view>
	42	</mamelayout>

trunk/src/mess/machine/victor9kb.c

r242413	r242414
11	11
12	12	/*
13	13
14		PCB Layout
	14	Keyboard PCB Layout
15	15	----------
16	16
17		A65-02307-201D
	17	Marking on PCB back: A65-02307-201D 007
18	18
19		|-----------------------------------------------------------------------|
20		|    22-008-03  22-050-3B     8021    74LS14                         CN1|
21		|                            ?MHz                                       |
22		|                                                                       |
23		|                                                                       |
24		|                                                                       |
25		|                                                                       |
26		|                                                                       |
27		|                                                                       |
28		|                                                                       |
29		|                                                                       |
30		|                                                                       |
31		|-----------------------------------------------------------------------|
	19	|------------------------------------------------------------------------------------|
	20	| 22-908-03 22-950-3B     XTAL 8021  74LS14     [804x]           [EPROM]  [???] L CN1=___
	21	|         X       X       X       X       X       X        X      X   X      X      X    |
	22	| X    X   X   X   X   X   X   X   X   X   X   X   X   X    X     X   X    X   X   X   X |
	23	| X     X   X   X   X   X   X   X   X   X   X   X   X   X    X    X   X    X   X   X   X |
	24	| X     X    X   X   X   X   X   X   X   X   X   X   X   X    X   X   X    X   X   X   X |
	25	| X    X   X  X   X   X   X   X   X   X   X   X   X       X       X   X    X   X   X   X |
	26	| X     X    marking             X                 X              X   X    X   X   X   X |
	27	|----------------------------------------------------------------------------------------|
32	28
	29
33	30	Notes:
34	31	All IC's shown.
	32	XTAL        - 3.579545Mhz Crystal, marked "48-300-010" (front of xtal) and "3.579545Mhz" (back of xtal)
	33	74LS14      - Z4 - 74LS14 Hex inverter with Schmitt-trigger inputs (0.8v hysteresis)
	34	8021        - Z3 - Intel 8021 MCU, marked: "P8021 2137 // 8227 // 20-8021-139 // (C) INTEL 77"
	35	22-908-03   - Z2 - Exar Semiconductor XR22-008-03 keyboard matrix capacitive readout latch
	36	22-950-3B   - Z1 - Exar Semiconductor XR22-050-3B keyboard matrix row driver with 4 to 12 decoder/demultiplexer
	37	CN1 or J1   - J1 - keyboard data connector (SIP, 7 pins, right angle)
	38	L           - L1 & L2 - mil-spec 22uH 10% inductors (double wide silver band(mil spec), red(2) red(2) black(x1uH) silver(10%))
35	39
36		8021        - Intel 8021 "70-8021-130?"
37		22-008-03   - Exar Semiconductor XR22-008-03 keyboard matrix capacitive readout latch
38		22-050-3B   - Exar Semiconductor XR22-050-3B keyboard matrix row driver with 4 to 12 decoder/demultiplexer
39		CN1         - keyboard data connector
	40	[804x]      - unpopulated space for a 40 pin 804x or 803x MCU
	41	[EPROM]     - unpopulated space for an EPROM, if a ROMless 803x MCU was used
	42	[???]       - unpopulated space for an unknown NDIP10 IC or DIP-switch array
	43	X           - capacitive sensor pad for one key
	44	marking     - PCB trace marking: "KTC // A65-02307-007 // PCB 201 D"
40	45
	46	74LS14 (Hex inverter with Schmitt-trigger inputs (0.8v hysteresis))
	47	------------------
	48	__   __
	49	1A 1 |* \_/  | 14 VCC
	50	/1Y 2 |       | 13 6A
	51	2A 3 |       | 12 /6Y
	52	/2Y 4 |       | 11 5A
	53	3A 5 | 74LS14| 10 /5Y
	54	/3Y 6 |       | 9  4A
	55	GND 7 |_______| 8  /4Y
	56
	57
	58	P8021 Pinout
	59	------------------
	60	_____   _____
	61	P22   1 |*    \_/     | 28  VCC
	62	P23   2 |             | 27  P21
	63	PROG   3 |             | 26  P20
	64	P00   4 |             | 25  P17
	65	P01   5 |    P8021    | 24  P16
	66	P02   6 |             | 23  P15
	67	P03   7 |             | 22  P14
	68	P04   8 |             | 21  P13
	69	P05   9 |             | 20  P12
	70	P06  10 |             | 19  P11
	71	P07  11 |             | 18  P10
	72	ALE  12 |             | 17  RESET
	73	T1  13 |             | 16  XTAL 2
	74	VSS  14 |_____________| 15  XTAL 1
	75
	76
	77	XR22-008-03 Pinout (AKA XR22-908-03)
	78	------------------
	79	_____   _____
	80	D0   1 |*    \_/     | 20  Vcc
	81	D1   2 |             | 19  _CLR
	82	D2   3 |             | 18  Q0
	83	D3   4 |             | 17  Q1
	84	HYS   5 |  22-008-03  | 16  Q2
	85	D4   6 |             | 15  Q3
	86	D5   7 |             | 14  Q4
	87	D6   8 |             | 13  Q5
	88	D7   9 |             | 12  Q6
	89	GND  10 |_____________| 11  Q7
	90
	91
	92	XR22-050-3B Pinout (AKA XR22-950-3B)
	93	------------------
	94	_____   _____
	95	Y8   1 |*    \_/     | 20  Vcc
	96	Y9   2 |             | 19  Y7
	97	Y10   3 |             | 18  Y6
	98	Y11   4 |             | 17  Y5
	99	_STB   5 |  22-050-3B  | 16  Y4
	100	A0   6 |             | 15  Y3
	101	A1   7 |             | 14  Y2
	102	A2   8 |             | 13  Y1
	103	A3   9 |             | 12  Y0
	104	GND  10 |_____________| 11  OE?
	105
	106	i8021 to elsewhere connections
	107	------------------------------
	108	8021 pin - 22-xxx pin
	109	P22  1 - 74LS14 pin 5 (3A)                            AND (804x chip pin 37, P26)
	110	P23  2 - 74LS14 pin 11 (5A)                           AND (804x chip pin 38, P27)
	111	PROG  3 -                                                  (804x chip pin 25, PROG)
	112	P00  4 - N/C
	113	P01  5 - N/C
	114	P02  6 - N/C
	115	P03  7 - N/C
	116	P04  8 - N/C
	117	P05  9 - N/C
	118	P06 10 - N/C
	119	P07 11 - N/C
	120	ALE 12 - N/C
	121	T1 13 - 74LS14 pin 2 (/1Y)                           AND (804x chip pin 39, T1)
	122	VSS 14 - GND
	123	XTAL1 15 - XTAL
	124	XTAL2 16 - XTAL
	125	RESET 17 - 10uf capacitor - VCC
	126	P10 18 - 22-908 pin 18 (Q0) AND 22-950 pin 6 (A0)     AND (804x chip pin 27, P10)
	127	P11 19 - 22-908 pin 17 (Q1) AND 22-950 pin 7 (A1)     AND (804x chip pin 28, P11)
	128	P12 20 - 22-908 pin 16 (Q2) AND 22-950 pin 8 (A2)     AND (804x chip pin 29, P12)
	129	P13 21 - 22-908 pin 15 (Q3) AND 22-950 pin 9 (A3)     AND (804x chip pin 30, P13)
	130	P14 22 - 22-908 pin 14 (Q4)                           AND (804x chip pin 31, P14)
	131	P15 23 - 22-908 pin 13 (Q5)                           AND (804x chip pin 32, P15)
	132	P16 24 - 22-908 pin 12 (Q6)                           AND (804x chip pin 33, P16)
	133	P17 25 - 22-908 pin 11 (Q7)                           AND (804x chip pin 34, P17)
	134	P20 26 - 22-908 pin 19 (/CLR) AND 22-950 pin 5 (/STB) AND (804x chip pin 35, P24)
	135	P21 27 - 74LS14 pin 9 (4A)                            AND (804x chip pin 36, P25)
	136	VCC 28 - VCC
	137
	138	74LS14 to elsewhere connections
	139	-------------------------------
	140	1A  1 - 100 Ohm resistor - J1 pin 4
	141	/1Y  2 - 8021 pin 13 (T1)
	142	2A  3 - 74LS14 pin 8
	143	/2Y  4 - 22uH 10% inductor 'L1' - J1 pin 5
	144	3A  5 - 8021 pin 1 (P22)
	145	/3Y  6 - many keyboard contact pads (!)
	146	GND  7 - GND
	147	/4Y  8 - 74LS14 pin 3
	148	4A  9 - 8021 pin 27 (P21)
	149	/5Y 10 - 74LS14 pin 13
	150	5A 11 - 8021 pin 2 (P23)
	151	/6Y 12 - 22uH 10% inductor 'L2' - J1 pin 6
	152	6A 13 - 74LS14 pin 10
	153	VCC 14 - VCC
	154
	155
	156	J1 (aka CN1) connections:
	157	-------------------------
	158	1 - VCC
	159	2 - GND
	160	3 - GND
	161	4 - 100 Ohm 5% resistor -> 74LS14 pin 1 -> inverted 74LS14 pin 2 -> inverted 8021 pin 13 (T1)
	162	5 - 22uH 10% inductor 'L1' <- 74LS14 pin 4 <- inverted 74LS14 pin 3 <- inverted 74LS14 pin 8 <- 74LS14 pin 9 <- 8021 pin 27 (P21)
	163	6 - 22uH 10% inductor 'L2' <- 74LS14 pin 12 <- inverted 74LS14 pin 13 <- inverted 74LS14 pin 10 <- 74LS14 pin 11 <- 8021 pin 2 (P23)
	164	7 - VCC
	165
	166	Pins 5,and 6 also have a .0047uF capacitor to GND (forming some sort of LC filter)
	167	There is another .0047uF capacitor to ground from the connection between 74LS14 pin 1 and the 100 Ohm 5% resistor which connects to pin 4 (forming some sort of RC filter)
	168
	169	Exar Custom connections between each other:
	170	-------------------------------------------
	171	22-950 pin 11 (OE?) - 68KOhm 5% resistor - 22-908 pin 5 (HYS)
	172
	173	Cable connecting J1/CN1 to the Victor:
	174	--------------------------------------
	175	RJ45 when looking at end of plug (not socket!)
	176	.||||||||.
	177	|87654321|
	178	|__----__|
	179	|__|
	180
	181	RJ45 pins   Wire Color   Connection
	182	1           White        J1 pin 1 (VCC)
	183	2           Yellow       J1 pin 2 (GND)
	184	3           Green        J1 pin 3 (GND)
	185	4           Orange       J1 pin 4 (?KBACK?)
	186	5           Blue         J1 pin 5 (?KBRDY?)
	187	6           Red          J1 pin 6 (?KBDATA?)
	188	7           Black        J1 pin 7 (VCC)
	189	8           shield/bare  Keyboard Frame Ground
	190
	191
	192	Key Layout (USA Variant): (the S0x markings appear on the back of the PCB)
	193	|------------------------------------------------------------------------------------|
	194	| 22-908-03 22-950-3B     XTAL 8021  74LS14     [804x]           [EPROM]  [???] L CN1=___
	195	|         01      02      03      04      05      06       07     08  09     10     11   |
	196	| 12   13  14  15  16  17  18  19  20  21  22  23  24  25   26    27  28   29  30  31 32 |
	197	| 33    34  35  36  37  38  39  40  41  42  43  44  45  46   47   48  49   50  51  52 53 |
	198	| 54    55   56  57  58  59  60  61  62  63  64  65  66  67   68  69  70   71  72  73 74 |
	199	| 75   76  77 78  79  80  81  82  83  84  85  86  87      88      89  90   91  92  93 94 |
	200	| 95    96   marking             97                98             99 100  101 102 103 104|
	201	|----------------------------------------------------------------------------------------|
	202
	203	key - Shifted(top)/Unshifted(bottom)/Alt(front) (if no slashes in description assume key has just one symbol on it)
	204	S01 - [1]
	205	S02 - [2]
	206	S03 - [3]
	207	S04 - [4]
	208	S05 - [5]
	209	S06 - [6]
	210	S07 - [7]
	211	S08 - [8]
	212	S09 - UNUSED (under the [8] key, no metal contact on key)
	213	S10 - [9]
	214	S11 - [10]
	215
	216	S12 - CLR/HOME
	217	S13 - (Degree symbol U+00B0)/(+- symbol U+00B1)/(Pi symbol U+03C0)
	218	S14 - !/1/|
	219	S15 - @/2/<
	220	S16 - #/3/>
	221	S17 - $/4/(centered closed dot U+00B7)
	222	S18 - %/5/(up arrow symbol U+2191)
	223	S19 - (cent symbol U+00A2)/6/(logical not symbol U+00AC)
	224	S20 - &/7/^
	225	S21 - * /8/`
	226	S22 - (/9/{
	227	S23 - )/0/}
	228	S24 - _/-/~
	229	S25 - +/=/\
	230	S26 - BACKSPACE
	231	S27 - INS
	232	S28 - DEL
	233	S29 - MODE CALC/= (white keypad key)
	234	S30 - % (white keypad key)
	235	S31 - (division symbol U+00F7) (white keypad key)
	236	S32 - (multiplication symbol U+00D7) (white keypad key)
	237
	238	S33 - (up arrow, SCRL, down arrow)//VTAB
	239	S34 - TAB//BACK
	240	S35 - Q
	241	S36 - W
	242	S37 - E
	243	S38 - R
	244	S39 - T
	245	S40 - Y
	246	S41 - U
	247	S42 - I
	248	S43 - O
	249	S44 - P
	250	S45 - (1/4 symbol U+00BC)/(1/2 symbol U+00BD)
	251	S46 - [/]
	252	S47 - UNUSED (under the RETURN key, no metal contact on key)
	253	S48 - ERASE/EOL
	254	S49 - REQ/CAN
	255	S50 - 7 (white keypad key)
	256	S51 - 8 (white keypad key)
	257	S52 - 9 (white keypad key)
	258	S53 - - (white keypad key)
	259
	260	S54 - (OFF,RVS,ON)//ESC
	261	S55 - LOCK//CAPS LOCK
	262	S56 - A
	263	S57 - S
	264	S58 - D
	265	S59 - F
	266	S60 - G
	267	S61 - H
	268	S62 - J
	269	S63 - K
	270	S64 - L
	271	S65 - :/;
	272	S66 - "/'
	273	S67 - UNUSED (under the RETURN key, no metal contact on key)
	274	S68 - RETURN
	275	S69 - WORD/(left arrow U+2190)/(volume up U+1F508 plus U+25B4) (i.e. 'Previous Word')
	276	S70 - WORD/(right arrow U+2192)/(volume down U+1F508 plus U+25BE) (i.e. 'Next Word')
	277	S71 - 4 (white keypad key)
	278	S72 - 5 (white keypad key)
	279	S73 - 6 (white keypad key)
	280	S74 - + (white keypad key)
	281
	282	S75 - (OFF,UNDL,ON)
	283	S76 - SHIFT (left shift)
	284	S77 - UNUSED (under the left SHIFT key, no metal contact on key)
	285	S78 - Z
	286	S79 - X
	287	S80 - C
	288	S81 - V
	289	S82 - B
	290	S83 - N
	291	S84 - M
	292	S85 - ,/, (yes, both are comma)
	293	S86 - ./. (yes, both are period/fullstop)
	294	S87 - ?// (this is the actual / key)
	295	S88 - SHIFT (right shift)
	296	S89 - (up arrow U+2191)//(brightness up U+263C plus U+25B4)
	297	S90 - (down arrow U+2193)//(brightness down U+263C plus U+25BE)
	298	S91 - 1 (white keypad key)
	299	S92 - 2 (white keypad key)
	300	S93 - 3 (white keypad key)
	301	S94 - ENTER (white keypad key)
	302
	303	S95 - RPT
	304	S96 - ALT
	305	S97 - (spacebar)
	306	S98 - PAUSE/CONT
	307	S99 - (left arrow U+2190)//(contrast up U+25D0 plus U+25B4) (U+1F313 can be used in place of U+25D0)
	308	S100 - (right arrow U+2192)//(contrast down U+25D0 plus U+25BE) ''
	309	S101 - 0 (white keypad key)
	310	S102 - 00 (white keypad key) ('double zero')
	311	S103 - . (white keypad key)
	312	S104 - UNUSED (under the ENTER (keypad) key, no metal contact on key)
	313
	314	Note that the five unused key contacts:
	315	S09, S47, S67, S77 and S104
	316	may be used on international variants of the Victor 9000/Sirius 1 Keyboard.
	317
	318	Keyboard Matrix
	319	---------------
	320	Row select
	321	|         Columns Sxxx by bit                 Columns Key by bit
	322	|         D0  D1  D2  D3  D4  D5  D6  D7      D0   D1   D2   D3   D4   D5   D6   D7
	323	V         V   V   V   V   V   V   V   V       V    V    V    V    V    V    V    V
	324	Y0        12  13  33  34  54  55  75  76      CLRH DEGR SCRL TAB  RVS  LOCK UNDL LSHFT
	325	Y1        14  15  35  36  56  57  77  78      1    2    Q    W    A    S    N/A  Z
	326	Y2        16  17  37  38  58  59  79  80      3    4    E    R    D    F    X    C
	327	Y3        18  19  39  40  60  61  81  82      5    6    T    Y    G    H    V    B
	328	Y4        20  21  41  42  62  63  83  84      7    8    U    I    J    K    N    M
	329	Y5        22  23  43  44  64  65  85  86      9    0    O    P    L    ;    ,    .
	330	Y6        24  25  45  46  66  67  87  88      -    =    1/2  []   '    N/A  ?    RSHFT
	331	Y7        26  27  47  48  68  69  89  90      BKSP INS  N/A  ERSE RETN WRDL UP   DOWN
	332	Y8        28  29  49  50  70  71  91  92      DEL  MODE REQ  k7   WRDR k4   k1   k2
	333	Y9        30  31  51  52  72  73  93  94      k%   kDIV k8   k9   k5   k6   k3   kENTR
	334	Y10       32  11  53  10  74  09  07  06      kMUL [10] k-   [9]  k+   N/A  [7]  [6]
	335	Y11       104 103 102 101 100 99  98  97      kN/A k.   k00  k0   RGHT LEFT PAUS SPACE
	336	/3Y       05  04  03  02  01  08  95  96      [5]  [4]  [3]  [2]  [1]  [8]  RPT  ALT
	337
41	338	*/
42	339
43	340	#include "victor9kb.h"
r242413	r242414
48	345	//  MACROS / CONSTANTS
49	346	//**************************************************************************
50	347
51		#define I8021_TAG       "z3"
	348	#define I8021_TAG   "z3"
52	349
	350	#define LOG       0
53	351
54	352
	353
55	354	//**************************************************************************
56	355	//  DEVICE DEFINITIONS
57	356	//**************************************************************************
58	357
59		const device_type VICTOR9K_KEYBOARD = &device_creator<victor9k_keyboard_device>;
	358	const device_type VICTOR9K_KEYBOARD = &device_creator<victor_9000_keyboard_t>;
60	359
61	360
62	361	//-------------------------------------------------
r242413	r242414
73	372	//  rom_region - device-specific ROM region
74	373	//-------------------------------------------------
75	374
76		const rom_entry *victor9k_keyboard_device::device_rom_region() const
	375	const rom_entry *victor_9000_keyboard_t::device_rom_region() const
77	376	{
78	377	return ROM_NAME( victor9k_keyboard );
79	378	}
r242413	r242414
83	382	//  ADDRESS_MAP( kb_io )
84	383	//-------------------------------------------------
85	384
86		static ADDRESS_MAP_START( victor9k_keyboard_io, AS_IO, 8, victor9k_keyboard_device )
	385	static ADDRESS_MAP_START( victor9k_keyboard_io, AS_IO, 8, victor_9000_keyboard_t )
	386	// P0 is unconnected on pcb
87	387	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_READWRITE(kb_p1_r, kb_p1_w)
88	388	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_WRITE(kb_p2_w)
89	389	AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(kb_t1_r)
r242413	r242414
105	405	//  machine configurations
106	406	//-------------------------------------------------
107	407
108		machine_config_constructor victor9k_keyboard_device::device_mconfig_additions() const
	408	machine_config_constructor victor_9000_keyboard_t::device_mconfig_additions() const
109	409	{
110	410	return MACHINE_CONFIG_NAME( victor9k_keyboard );
111	411	}
r242413	r242414
117	417
118	418	INPUT_PORTS_START( victor9k_keyboard )
119	419	PORT_START("Y0")
120		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
121		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
122		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
123		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
124		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
125		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
126		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
127		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	420	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CLR/HOME") PORT_CODE(KEYCODE_HOME) // S12
	421	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_PLUSMINUS" "UTF8_DEGREES" "UTF8_SMALL_PI) PORT_CODE(KEYCODE_TILDE) // +-, degree, pi // S13
	422	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_UP" SCRL "UTF8_DOWN) PORT_CODE(KEYCODE_SCRLOCK) // unicode arrows // S33
	423	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("TAB/BACK") PORT_CODE(KEYCODE_TAB) PORT_CHAR(9) // S34
	424	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("RVS On-Off/ESC") PORT_CODE(KEYCODE_ESC) PORT_CHAR(27) // S54
	425	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("LOCK/CAPSLOCK") PORT_CODE(KEYCODE_CAPSLOCK) // S55
	426	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNDL On-Off") PORT_CODE(KEYCODE_PRTSCR) // need better key code // S75
	427	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Left Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1) // S76
128	428
129	429	PORT_START("Y1")
130		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
131		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
132		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
133		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
134		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
135		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
136		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
137		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	430	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("1 ! |") PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') PORT_CHAR('|') // S14
	431	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("2 @ <") PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@') PORT_CHAR('<') // S15
	432	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q') // S35
	433	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W') // S36
	434	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') // S56
	435	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') // S57
	436	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNUSED S75") // unused // S75
	437	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z') // S76
138	438
139	439	PORT_START("Y2")
140		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
141		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
142		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
143		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
144		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
145		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
146		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
147		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	440	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("3 # >") PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('3') PORT_CHAR('3')// S16
	441	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("4 $ \xc2\xb7") PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$') // centered closed dot U+00B7 // S17
	442	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E') // S37
	443	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') // S38
	444	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') // S58
	445	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F') // S59
	446	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X') // S79
	447	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C') // S80
148	448
149	449	PORT_START("Y3")
150		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
151		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
152		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
153		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
154		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
155		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
156		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
157		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	450	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("5 % "UTF8_UP) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') // S18
	451	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("6 \xc2\xa2 \xc2\xac") PORT_CODE(KEYCODE_6) PORT_CHAR('6') // cent U+00A2, logic not U+00AC // S19
	452	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T') // S39
	453	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') // S40
	454	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G') // S60
	455	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') // S61
	456	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V') // S81
	457	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B') // S82
158	458
159	459	PORT_START("Y4")
160		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
161		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
162		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
163		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
164		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
165		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
166		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
167		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	460	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("7 & ^") PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&') PORT_CHAR('^') // S20
	461	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("8 * `") PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*') PORT_CHAR('`') // S21
	462	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U') // S41
	463	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') // S42
	464	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J') // S62
	465	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') // S63
	466	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N') // S83
	467	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M') // S84
168	468
169	469	PORT_START("Y5")
170		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
171		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
172		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
173		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
174		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
175		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
176		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
177		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	470	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("9 ( {") PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(') PORT_CHAR('{') // S22
	471	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("0 ) }") PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(')') PORT_CHAR('}') // S23
	472	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O') // S43
	473	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P') // S44
	474	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L') // S64
	475	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("; :") PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':') // S65
	476	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(",") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') // S85
	477	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(".") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') // S86
178	478
179	479	PORT_START("Y6")
180		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
181		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
182		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
183		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
184		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
185		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
186		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
187		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	480	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("- _ ~") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('_') PORT_CHAR('~') // S24
	481	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("= + \\") PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('+') PORT_CHAR('\\') // S25
	482	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("\xc2\xbd \xc2\xbc") PORT_CODE(KEYCODE_OPENBRACE) // unicode half fraction U+00BD / quarter fraction U+00BC // S45
	483	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("[ ]") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('[') PORT_CHAR(']') // S46
	484	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("' \"") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('\"') // S66
	485	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNUSED S67") // unused // S67
	486	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("/ ?") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') // S87
	487	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Right Shift") PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1) // S88
188	488
189	489	PORT_START("Y7")
190		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
191		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
192		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
193		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
194		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
195		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
196		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
197		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	490	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("BACKSPACE") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) // S26
	491	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("INS") PORT_CODE(KEYCODE_INSERT) // S27
	492	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNUSED S47") // unused // S47
	493	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("ERASE/EOL") PORT_CODE(KEYCODE_END) // should this be mapped to end or del? // S48
	494	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("RETURN") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13) // S68
	495	//PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Word "UTF8_LEFT"/Volume Up \xf0\x9f\x94\x88\xe2\x96\xb4") PORT_CODE(KEYCODE_PGUP) // unicode U+2190/U+1F508 + U+25B4 // S69
	496	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Word "UTF8_LEFT"/Volume Up") PORT_CODE(KEYCODE_PGUP) // unicode U+2190/U+1F508 + U+25B4 // S69
	497	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_UP"/Brightness Up \xe2\x98\xbc\xe2\x96\xb4") PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP)) // U+2191/U+263C + U+25B4 // S89
	498	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_DOWN"/Brightness Down \xe2\x98\xbc\xe2\x96\xbe") PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) // U+2193/U+263C + U+25BE // S90
198	499
199	500	PORT_START("Y8")
200		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
201		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
202		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
203		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
204		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
205		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
206		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
207		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	501	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("DEL") PORT_CODE(KEYCODE_DEL) PORT_CHAR(127) // S28
	502	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad MODE CALC/=") PORT_CODE(KEYCODE_NUMLOCK) // S29
	503	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("REQ/CAN") PORT_CODE(KEYCODE_BACKSLASH) // is this a good key for this? does sysrq make more sense? // S49
	504	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 7") PORT_CODE(KEYCODE_7_PAD) // S50
	505	//PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Word "UTF8_RIGHT"/Volume Down \xf0\x9f\x94\x88\xe2\x96\xbe") PORT_CODE(KEYCODE_PGDN) // unicode U+2192/U+1F508 + U+25B4 // S70
	506	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Word "UTF8_RIGHT"/Volume Down") PORT_CODE(KEYCODE_PGDN) // unicode U+2192/U+1F508 + U+25B4 // S70
	507	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 4") PORT_CODE(KEYCODE_4_PAD) // S71
	508	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 1") PORT_CODE(KEYCODE_1_PAD) // S91
	509	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 2") PORT_CODE(KEYCODE_2_PAD) // S92
208	510
209	511	PORT_START("Y9")
210		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
211		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
212		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
213		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
214		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
215		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
216		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
217		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	512	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad %") // find a good key for this // S30
	513	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad "UTF8_DIVIDE) PORT_CODE(KEYCODE_SLASH_PAD) // unicode division sign U+00F7 // S31
	514	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 8") PORT_CODE(KEYCODE_8_PAD) // S51
	515	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 9") PORT_CODE(KEYCODE_9_PAD) // S52
	516	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 5") PORT_CODE(KEYCODE_5_PAD) // S72
	517	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 6") PORT_CODE(KEYCODE_6_PAD) // S73
	518	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 3") PORT_CODE(KEYCODE_3_PAD) // S93
	519	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad Enter") PORT_CODE(KEYCODE_ENTER_PAD) // S94
218	520
219	521	PORT_START("YA")
220		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
221		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
222		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
223		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
224		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
225		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
226		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
227		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	522	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad "UTF8_MULTIPLY) PORT_CODE(KEYCODE_ASTERISK) // unicode multiply sign U+00D7 // S32
	523	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F10 [10]") PORT_CODE(KEYCODE_F10) // S11
	524	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad -") PORT_CODE(KEYCODE_MINUS_PAD) // S53
	525	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F9 [9]") PORT_CODE(KEYCODE_F9) // S10
	526	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad +") PORT_CODE(KEYCODE_PLUS_PAD) // S74
	527	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNUSED S09") // unused // S09
	528	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F7 [7]") PORT_CODE(KEYCODE_F7) // S07
	529	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F6 [6]") PORT_CODE(KEYCODE_F6) // S06
228	530
229	531	PORT_START("YB")
230		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
231		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
232		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
233		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
234		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
235		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
236		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
237		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	532	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("UNUSED S04") // unused // S104
	533	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad .") PORT_CODE(KEYCODE_DEL_PAD) // S103
	534	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 00") // S102
	535	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 0") PORT_CODE(KEYCODE_0_PAD) // S101
	536	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_RIGHT"/Contrast Down \xe2\x97\x90\xe2\x96\xbe") PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) // U+2190/U+25D0 + U+25BE S100
	537	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_LEFT"/Contrast Up \xe2\x97\x90\xe2\x96\xb4") PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT)) // U+2190/U+25D0 + U+25B4 S99
	538	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("PAUSE/CONT") PORT_CODE(KEYCODE_PAUSE) // S98
	539	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Spacebar") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ') // S97
238	540
239	541	PORT_START("YC")
240		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
241		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
242		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
243		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
244		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
245		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
246		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
247		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
	542	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F5 [5]") PORT_CODE(KEYCODE_F5) // S05
	543	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F4 [4]") PORT_CODE(KEYCODE_F4) // S04
	544	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F3 [3]") PORT_CODE(KEYCODE_F3) // S03
	545	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F2 [2]") PORT_CODE(KEYCODE_F2) // S02
	546	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F1 [1]") PORT_CODE(KEYCODE_F1) // S01
	547	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F8 [8]") PORT_CODE(KEYCODE_F8) // S11
	548	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("RPT") PORT_CODE(KEYCODE_LCONTROL) // S95
	549	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("ALT") PORT_CODE(KEYCODE_LALT) PORT_CODE(KEYCODE_RALT) PORT_CHAR(UCHAR_SHIFT_2) // S96
248	550	INPUT_PORTS_END
249	551
250	552
r242413	r242414
252	554	//  input_ports - device-specific input ports
253	555	//-------------------------------------------------
254	556
255		ioport_constructor victor9k_keyboard_device::device_input_ports() const
	557	ioport_constructor victor_9000_keyboard_t::device_input_ports() const
256	558	{
257	559	return INPUT_PORTS_NAME( victor9k_keyboard );
258	560	}
r242413	r242414
264	566	//**************************************************************************
265	567
266	568	//-------------------------------------------------
267		//  victor9k_keyboard_device - constructor
	569	//  victor_9000_keyboard_t - constructor
268	570	//-------------------------------------------------
269	571
270		victor9k_keyboard_device::victor9k_keyboard_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	572	victor_9000_keyboard_t::victor_9000_keyboard_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
271	573	device_t(mconfig, VICTOR9K_KEYBOARD, "Victor 9000 Keyboard", tag, owner, clock, "victor9kb", __FILE__),
272	574	m_maincpu(*this, I8021_TAG),
273	575	m_y0(*this, "Y0"),
r242413	r242414
283	585	m_ya(*this, "YA"),
284	586	m_yb(*this, "YB"),
285	587	m_yc(*this, "YC"),
286		m_kbrdy_handler(*this),
287		m_kbdata_handler(*this),
	588	m_kbrdy_cb(*this),
	589	m_kbdata_cb(*this),
288	590	m_y(0),
289		m_kbrdy(1),
290		m_kbdata(1),
	591	m_kbrdy(-1),
	592	m_kbdata(-1),
291	593	m_kback(1)
292	594	{
293	595	}
r242413	r242414
297	599	//  device_start - device-specific startup
298	600	//-------------------------------------------------
299	601
300		void victor9k_keyboard_device::device_start()
	602	void victor_9000_keyboard_t::device_start()
301	603	{
302	604	// resolve callbacks
303		m_kbrdy_handler.resolve_safe();
304		m_kbdata_handler.resolve_safe();
	605	m_kbrdy_cb.resolve_safe();
	606	m_kbdata_cb.resolve_safe();
305	607
306	608	// state saving
	609	save_item(NAME(m_p1));
307	610	save_item(NAME(m_y));
	611	save_item(NAME(m_stb));
	612	save_item(NAME(m_y12));
308	613	save_item(NAME(m_kbrdy));
309	614	save_item(NAME(m_kbdata));
310	615	save_item(NAME(m_kback));
r242413	r242414
312	617
313	618
314	619	//-------------------------------------------------
315		//  device_reset - device-specific reset
	620	//  kback_w -
316	621	//-------------------------------------------------
317	622
318		void victor9k_keyboard_device::device_reset()
	623	WRITE_LINE_MEMBER( victor_9000_keyboard_t::kback_w )
319	624	{
320		}
	625	if (LOG) logerror("KBACK %u\n", state);
321	626
322
323		//-------------------------------------------------
324		//  kback_w -
325		//-------------------------------------------------
326
327		WRITE_LINE_MEMBER( victor9k_keyboard_device::kback_w )
328		{
329		//logerror("KBACK %u\n", state);
330		m_kback = state;
	627	m_kback = !state;
331	628	}
332	629
333	630
r242413	r242414
335	632	//  kb_p1_r -
336	633	//-------------------------------------------------
337	634
338		READ8_MEMBER( victor9k_keyboard_device::kb_p1_r )
	635	READ8_MEMBER( victor_9000_keyboard_t::kb_p1_r )
339	636	{
340	637	UINT8 data = 0xff;
341	638
r242413	r242414
353	650	case 9: data &= m_y9->read(); break;
354	651	case 0xa: data &= m_ya->read(); break;
355	652	case 0xb: data &= m_yb->read(); break;
356		case 0xc: data &= m_yc->read(); break;
357	653	}
358	654
	655	if (!m_y12)
	656	{
	657	data &= m_yc->read();
	658	}
	659
359	660	return data;
360	661	}
361	662
r242413	r242414
364	665	//  kb_p1_w -
365	666	//-------------------------------------------------
366	667
367		WRITE8_MEMBER( victor9k_keyboard_device::kb_p1_w )
	668	WRITE8_MEMBER( victor_9000_keyboard_t::kb_p1_w )
368	669	{
369		if ((data & 0xf0) == 0x20)
370		{
371		m_y = data & 0x0f;
372		}
373
374		//logerror("P1 %02x\n", data);
	670	m_p1 = data;
375	671	}
376	672
377	673
r242413	r242414
379	675	//  kb_p2_w -
380	676	//-------------------------------------------------
381	677
382		WRITE8_MEMBER( victor9k_keyboard_device::kb_p2_w )
	678	WRITE8_MEMBER( victor_9000_keyboard_t::kb_p2_w )
383	679	{
384	680	/*
385	681
386	682	bit     description
387	683
388		P20     ?
	684	P20     22-908 CLR, 22-950 STB
389	685	P21     KBRDY
390		P22     ?
	686	P22     Y12
391	687	P23     KBDATA
392	688
393	689	*/
394	690
395		int kbrdy = BIT(data, 1);
396
397		if (m_kbrdy != kbrdy)
	691	// falling (?edge or level?), latch keyboard rows 0-11
	692	if (!BIT(data, 0))
398	693	{
399		m_kbrdy = kbrdy;
400		m_kbrdy_handler(m_kbrdy);
	694	m_y = m_p1 & 0x0f;
401	695	}
402	696
403		int kbdata = BIT(data, 3);
	697	// keyboard row 12
	698	m_y12 = BIT(data, 2);
404	699
405		if (m_kbdata != kbdata)
406		{
407		m_kbdata = kbdata;
408		m_kbdata_handler(m_kbdata);
409		}
	700	// keyboard ready
	701	m_kbrdy_cb(BIT(data, 1));
410	702
411		//logerror("P2 %02x\n", data);
	703	// keyboard data
	704	m_kbdata_cb(BIT(data, 3));
412	705	}
413	706
414	707
r242413	r242414
416	709	//  kb_t1_r -
417	710	//-------------------------------------------------
418	711
419		READ8_MEMBER( victor9k_keyboard_device::kb_t1_r )
	712	READ8_MEMBER( victor_9000_keyboard_t::kb_t1_r )
420	713	{
421	714	return m_kback;
422	715	}

trunk/src/mess/machine/victor9kb.h

r242413	r242414
25	25	//**************************************************************************
26	26
27	27	#define MCFG_VICTOR9K_KBRDY_HANDLER(_devcb) \
28		devcb = &victor9k_keyboard_device::set_kbrdy_handler(*device, DEVCB_##_devcb);
	28	devcb = &victor_9000_keyboard_t::set_kbrdy_cb(*device, DEVCB_##_devcb);
29	29
30	30	#define MCFG_VICTOR9K_KBDATA_HANDLER(_devcb) \
31		devcb = &victor9k_keyboard_device::set_kbdata_handler(*device, DEVCB_##_devcb);
	31	devcb = &victor_9000_keyboard_t::set_kbdata_cb(*device, DEVCB_##_devcb);
32	32
33	33
34	34	//**************************************************************************
35	35	//  TYPE DEFINITIONS
36	36	//**************************************************************************
37	37
38		// ======================> victor9k_keyboard_device
	38	// ======================> victor_9000_keyboard_t
39	39
40		class victor9k_keyboard_device :  public device_t
	40	class victor_9000_keyboard_t :  public device_t
41	41	{
42	42	public:
43	43	// construction/destruction
44		victor9k_keyboard_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	44	victor_9000_keyboard_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
45	45
46		template<class _Object> static devcb_base &set_kbrdy_handler(device_t &device, _Object object) { return downcast<victor9k_keyboard_device &>(device).m_kbrdy_handler.set_callback(object); }
47		template<class _Object> static devcb_base &set_kbdata_handler(device_t &device, _Object object) { return downcast<victor9k_keyboard_device &>(device).m_kbdata_handler.set_callback(object); }
	46	template<class _Object> static devcb_base &set_kbrdy_cb(device_t &device, _Object object) { return downcast<victor_9000_keyboard_t &>(device).m_kbrdy_cb.set_callback(object); }
	47	template<class _Object> static devcb_base &set_kbdata_cb(device_t &device, _Object object) { return downcast<victor_9000_keyboard_t &>(device).m_kbdata_cb.set_callback(object); }
48	48
49	49	// optional information overrides
50	50	virtual const rom_entry *device_rom_region() const;
r242413	r242414
62	62	protected:
63	63	// device-level overrides
64	64	virtual void device_start();
65		virtual void device_reset();
66	65
67	66	private:
68	67	required_device<cpu_device> m_maincpu;
r242413	r242414
80	79	required_ioport m_yb;
81	80	required_ioport m_yc;
82	81
83		devcb_write_line   m_kbrdy_handler;
84		devcb_write_line   m_kbdata_handler;
	82	devcb_write_line   m_kbrdy_cb;
	83	devcb_write_line   m_kbdata_cb;
85	84
	85	UINT8 m_p1;
86	86	UINT8 m_y;
	87	int m_stb;
	88	int m_y12;
87	89	int m_kbrdy;
88	90	int m_kbdata;
89	91	int m_kback;

trunk/src/mess/mess.lst

r242413	r242414
1220	1220	radionic  // Radionic
1221	1221	tandy2k
1222	1222	tandy2khd
	1223	tandy12
1223	1224
1224	1225	coco      // Color Computer
1225	1226	cocoe    // Color Computer (Extended BASIC 1.0)
r242413	r242414
1719	1720	hp9845b
1720	1721	hp9845t
1721	1722	hp9845c
	1723	hp9k320
	1724	hp9k330
1722	1725
1723	1726	// SpectraVideo
1724	1727	svi318  // SVI-318 (PAL)
r242413	r242414
2570	2573	leapster
2571	2574	leapstertv
2572	2575	excali64
2573
	2576	bitgrpha
	2577	bitgrphb

trunk/src/mess/mess.mak

r242413	r242414
1299	1299	$(MESS_DRIVERS)/hp49gp.o    \
1300	1300	$(MESS_DRIVERS)/hp9845.o    \
1301	1301	$(MESS_DRIVERS)/hp9k.o      \
	1302	$(MESS_DRIVERS)/hp9k_3xx.o   \
1302	1303
	1304
1303	1305	$(MESSOBJ)/hec2hrp.a:           \
1304	1306	$(MESS_DRIVERS)/hec2hrp.o   \
1305	1307	$(MESS_MACHINE)/hec2hrp.o   \
r242413	r242414
1771	1773	$(MESS_DRIVERS)/pasopia7.o  \
1772	1774	$(MESS_DRIVERS)/paso1600.o  \
1773	1775
1774		$(MESSOBJ)/trainer.a: \
	1776	$(MESSOBJ)/trainer.a:           \
1775	1777	$(MESS_DRIVERS)/amico2k.o   \
1776	1778	$(MESS_DRIVERS)/babbage.o   \
1777	1779	$(MESS_DRIVERS)/bob85.o     \
r242413	r242414
1797	1799	$(MESS_MACHINE)/dragon.o    \
1798	1800	$(MESS_MACHINE)/dgnalpha.o  \
1799	1801	$(MESS_VIDEO)/gime.o        \
	1802	$(MESS_DRIVERS)/tandy12.o   \
1800	1803	$(MESS_DRIVERS)/trs80.o $(MESS_MACHINE)/trs80.o $(MESS_VIDEO)/trs80.o \
1801	1804	$(MESS_DRIVERS)/trs80m2.o $(MESS_MACHINE)/trs80m2kb.o \
1802	1805	$(MESS_DRIVERS)/tandy2k.o $(MESS_MACHINE)/tandy2kb.o \
1803	1806
1804		$(MESSOBJ)/ultratec.a:        \
	1807	$(MESSOBJ)/ultratec.a:          \
1805	1808	$(MESS_DRIVERS)/minicom.o   \
1806	1809
1807	1810	$(MESSOBJ)/unisys.a:            \
r242413	r242414
1854	1857	$(MESS_DRIVERS)/bigbord2.o  \
1855	1858	$(MESS_DRIVERS)/alto2.o     \
1856	1859
1857		$(MESSOBJ)/xussrpc.a:            \
	1860	$(MESSOBJ)/xussrpc.a:           \
1858	1861	$(MESS_DRIVERS)/ec184x.o    \
1859	1862	$(MESS_DRIVERS)/iskr103x.o  \
1860	1863	$(MESS_DRIVERS)/mc1502.o    \
r242413	r242414
1865	1868	$(MESS_DRIVERS)/fb01.o      \
1866	1869
1867	1870	$(MESS_DRIVERS)/ymmu100.o: $(MESS_DRIVERS)/ymmu100.inc
1868		$(MESS_DRIVERS)/ymmu100.inc: $(MESSSRC)/drivers/ymmu100.ppm $(FILE2STR_TARGET)
	1871	$(MESS_DRIVERS)/ymmu100.inc: $(MESSSRC)/drivers/ymmu100.ppm $(SRC)/build/file2str.py
1869	1872	@echo Converting $<...
1870		@$(FILE2STR) $(MESSSRC)/drivers/ymmu100.ppm $@ ymmu100_bkg UINT8
	1873	@$(PYTHON) $(SRC)/build/file2str.py $(MESSSRC)/drivers/ymmu100.ppm $@ ymmu100_bkg UINT8
1871	1874
1872	1875	$(MESSOBJ)/zenith.a:            \
1873	1876	$(MESS_DRIVERS)/z100.o      \
r242413	r242414
1888	1891	$(MESS_DRIVERS)/beehive.o   \
1889	1892	$(MESS_DRIVERS)/binbug.o    \
1890	1893	$(MESS_DRIVERS)/besta.o     \
	1894	$(MESS_DRIVERS)/bitgraph.o  \
1891	1895	$(MESS_DRIVERS)/br8641.o    \
1892	1896	$(MESS_DRIVERS)/busicom.o $(MESS_VIDEO)/busicom.o \
1893	1897	$(MESS_DRIVERS)/chaos.o     \
r242413	r242414
2077	2081	$(MESS_DRIVERS)/babbage.o:  $(MESS_LAYOUT)/babbage.lh
2078	2082	$(MESS_DRIVERS)/bbc.o:      $(MESS_LAYOUT)/bbc.lh
2079	2083	$(MESS_DRIVERS)/beta.o:     $(MESS_LAYOUT)/beta.lh
	2084	$(MESS_DRIVERS)/bitgraph.o: $(MESS_LAYOUT)/bitgrpha.lh $(MESS_LAYOUT)/bitgrphb.lh
2080	2085	$(MESS_DRIVERS)/bob85.o:    $(MESS_LAYOUT)/bob85.lh
2081	2086	$(MESS_DRIVERS)/cc40.o:     $(MESS_LAYOUT)/cc40.lh
2082	2087	$(MAME_DRIVERS)/cdi.o:      $(MAME_LAYOUT)/cdi.lh
r242413	r242414
2162	2167	$(MESS_DRIVERS)/svision.o:  $(MESS_LAYOUT)/svision.lh
2163	2168	$(MESS_DRIVERS)/svmu.o:     $(MESS_LAYOUT)/svmu.lh
2164	2169	$(MESS_DRIVERS)/sym1.o:     $(MESS_LAYOUT)/sym1.lh
	2170	$(MESS_DRIVERS)/tandy12.o:  $(MESS_LAYOUT)/tandy12.lh
2165	2171	$(MESS_DRIVERS)/tavernie.o: $(MESS_LAYOUT)/tavernie.lh
2166	2172	$(MESS_DRIVERS)/tec1.o:     $(MESS_LAYOUT)/tec1.lh
2167	2173	$(MESS_DRIVERS)/tecnbras.o: $(MESS_LAYOUT)/tecnbras.lh

trunk/src/mess/video/apple2.c

r242413	r242414
1201	1201	switch (mon_type)
1202	1202	{
1203	1203	case 0:
1204		artifact_map_ptr = &m_hires_artifact_map[((vram_row[col+1] & 0x80) >> 7) * 16];
	1204	// verified on h/w: setting dhires w/o 80col emulates a rev. 0 Apple ][ with no orange/blue
	1205	if (m_dhires)
	1206	{
	1207	artifact_map_ptr = m_hires_artifact_map;
	1208	}
	1209	else
	1210	{
	1211	artifact_map_ptr = &m_hires_artifact_map[((vram_row[col + 1] & 0x80) >> 7) * 16];
	1212	}
1205	1213	for (b = 0; b < 7; b++)
1206	1214	{
1207	1215	v = artifact_map_ptr[((w >> (b + 7-1)) & 0x07) | (((b ^ col) & 0x01) << 3)];

trunk/src/mess/video/mikromik.c

r242413	r242414
38	38	//  ADDRESS_MAP( mm1_upd7220_map )
39	39	//-------------------------------------------------
40	40
41		static ADDRESS_MAP_START( mm1_upd7220_map, AS_0, 8, mm1_state )
	41	static ADDRESS_MAP_START( mm1_upd7220_map, AS_0, 16, mm1_state )
42	42	ADDRESS_MAP_GLOBAL_MASK(0x7fff)
43	43	AM_RANGE(0x0000, 0x7fff) AM_RAM AM_SHARE("video_ram")
44	44	ADDRESS_MAP_END
r242413	r242414
50	50
51	51	UPD7220_DISPLAY_PIXELS_MEMBER( mm1_state::hgdc_display_pixels )
52	52	{
53		UINT8 data = m_video_ram[address];
	53	UINT16 data = m_video_ram[address >> 1];
54	54
55		for (int i = 0; i < 8; i++)
	55	for (int i = 0; i < 16; i++)
56	56	{
57		if (BIT(data, 7 - i)) bitmap.pix32(y, x + i) = m_palette->pen(1);
	57	if (BIT(data, i)) bitmap.pix32(y, x + i) = m_palette->pen(1);
58	58	}
59	59	}
60	60

trunk/src/osd/sdl/input.c

r242413	r242414
757	757
758	758	osd_printf_verbose("Joystick: %s\n", devinfo->name.cstr());
759	759	osd_printf_verbose("Joystick:   ...  %d axes, %d buttons %d hats %d balls\n", SDL_JoystickNumAxes(joy), SDL_JoystickNumButtons(joy), SDL_JoystickNumHats(joy), SDL_JoystickNumBalls(joy));
760		osd_printf_verbose("Joystick:   ...  Physical id %d mapped to logical id %d\n", physical_stick, stick);
	760	osd_printf_verbose("Joystick:   ...  Physical id %d mapped to logical id %d\n", physical_stick, stick + 1);
761	761
762	762	// loop over all axes
763	763	for (axis = 0; axis < SDL_JoystickNumAxes(joy); axis++)

trunk/src/osd/sdl/man/castool.1

r242413	r242414
6	6	.\" Cesare Falco <c.falco@ubuntu.com>, February 2011
7	7	.\"
8	8	.\"
9		.TH CASTOOL 1 2014-11-19 0.156 "MESS Generic cassette manipulation tool"
	9	.TH CASTOOL 1 2014-12-15 0.157 "MESS Generic cassette manipulation tool"
10	10	.\"
11	11	.\"
12	12	.\" NAME chapter

trunk/src/osd/sdl/man/chdman.1

r242413	r242414
6	6	.\" Ashley T. Howes <debiandev@ashleyhowes.com>, February 2005
7	7	.\" updated by Cesare Falco <c.falco@ubuntu.com>, February 2007
8	8	.\"
9		.TH CHDMAN 1 2014-11-19 0.156 "MAME Compressed Hunks of Data (CHD) manager"
	9	.TH CHDMAN 1 2014-12-15 0.157 "MAME Compressed Hunks of Data (CHD) manager"
10	10	.\"
11	11	.\" NAME chapter
12	12	.SH NAME

trunk/src/osd/sdl/man/floptool.1

r242413	r242414
6	6	.\" Cesare Falco <c.falco@ubuntu.com>, April 2014
7	7	.\"
8	8	.\"
9		.TH FLOPTOOL 1 2014-11-19 0.156 "MESS Generic floppy manipulation tool"
	9	.TH FLOPTOOL 1 2014-12-15 0.157 "MESS Generic floppy manipulation tool"
10	10	.\"
11	11	.\"
12	12	.\" NAME chapter

trunk/src/osd/sdl/man/imgtool.1

r242413	r242414
6	6	.\" Cesare Falco <c.falco@ubuntu.com>, February 2011
7	7	.\"
8	8	.\"
9		.TH IMGTOOL 1 2014-11-19 0.156 "MESS media image manipulation tool"
	9	.TH IMGTOOL 1 2014-12-15 0.157 "MESS media image manipulation tool"
10	10	.\"
11	11	.\"
12	12	.\" NAME chapter

trunk/src/osd/sdl/man/jedutil.1

r242413	r242414
8	8	.\" References
9	9	.\" http://aarongiles.com/?p=159
10	10	.\"
11		.TH JEDUTIL 1 2014-11-19 0.156 "MAME JEDEC file utilities"
	11	.TH JEDUTIL 1 2014-12-15 0.157 "MAME JEDEC file utilities"
12	12	.\"
13	13	.\" NAME chapter
14	14	.SH NAME

trunk/src/osd/sdl/man/ldresample.1

r242413	r242414
3	3	.\" Second parameter, SECTION, should be 1-8, maybe w/ subsection
4	4	.\" other parameters are allowed: see man(7), man(1)
5	5	.\"
6		.TH LDRESAMPLE 1 2014-11-19 0.156 "MAME laserdisc audio manipulation tool"
	6	.TH LDRESAMPLE 1 2014-12-15 0.157 "MAME laserdisc audio manipulation tool"
7	7	.\"
8	8	.\" Please adjust this date whenever revising the manpage.
9	9	.\"

trunk/src/osd/sdl/man/ldverify.1

r242413	r242414
5	5	.\" Man page created from source and usage information by
6	6	.\" Cesare Falco <c.falco@ubuntu.com>, August 2008
7	7	.\"
8		.TH LDVERIFY 1 2014-11-19 0.156 "MAME laserdisc data checker"
	8	.TH LDVERIFY 1 2014-12-15 0.157 "MAME laserdisc data checker"
9	9	.\"
10	10	.\" NAME chapter
11	11	.SH NAME

trunk/src/osd/sdl/man/mame.6

r242413	r242414
13	13	.\" and updated by Andrew Burton <burtona@gol.com>, July 2003
14	14	.\"
15	15	.\"
16		.TH MAME 6 2014-11-19 0.156 "MAME \- The Multiple Arcade Machine Emulator"
	16	.TH MAME 6 2014-12-15 0.157 "MAME \- The Multiple Arcade Machine Emulator"
17	17	.\"
18	18	.\"
19	19	.\" NAME chapter

trunk/src/osd/sdl/man/mess.6

r242413	r242414
16	16	.\" http://www.mess.org/
17	17	.\"
18	18	.\"
19		.TH MESS 6 2014-11-19 0.156 "The Multiple Emulator Super System (MESS)"
	19	.TH MESS 6 2014-12-15 0.157 "The Multiple Emulator Super System (MESS)"
20	20	.\"
21	21	.\"
22	22	.\" NAME chapter

trunk/src/osd/sdl/man/romcmp.1

r242413	r242414
9	9	.\" References
10	10	.\" http://www.mame.net/mamefaq.html
11	11	.\"
12		.TH ROMCMP 1 2014-11-19 0.156 "MAME romset checking tool"
	12	.TH ROMCMP 1 2014-12-15 0.157 "MAME romset checking tool"
13	13	.\"
14	14	.\" NAME chapter
15	15	.SH NAME

trunk/src/osd/sdl/man/testkeys.1

r242413	r242414
5	5	.\" Man page created from source and usage information
6	6	.\" Cesare Falco <c.falco@ubuntu.com>, February 2007
7	7	.\"
8		.TH TESTKEYS 1 2014-11-19 0.156 "MAME SDL keycode scanner"
	8	.TH TESTKEYS 1 2014-12-15 0.157 "MAME SDL keycode scanner"
9	9	.\"
10	10	.\" NAME chapter
11	11	.SH NAME

trunk/src/osd/windows/drawd3d.c

r242413	r242414
250	250	if (d3d == NULL)
251	251	return;
252	252
253		if (d3d->get_shaders()->recording())
	253	if (d3d->get_shaders() != NULL && d3d->get_shaders()->recording())
254	254	d3d->get_shaders()->window_record();
255	255
256	256	// free the memory in the window
r242413	r242414
1040	1040
1041	1041	void renderer::device_delete()
1042	1042	{
1043		// free our effects
1044		m_shaders->delete_resources(false);
	1043	if (m_shaders != NULL)
	1044	{
	1045	// free our effects
	1046	m_shaders->delete_resources(false);
1045	1047
1046		// delete the HLSL interface
1047		global_free(m_shaders);
	1048	// delete the HLSL interface
	1049	global_free(m_shaders);
	1050	}
1048	1051
1049	1052	// free our base resources
1050	1053	device_delete_resources();
r242413	r242414
1070	1073
1071	1074	void renderer::device_delete_resources()
1072	1075	{
1073		m_texture_manager->delete_resources();
	1076	if (m_texture_manager != NULL)
	1077	m_texture_manager->delete_resources();
1074	1078	// free the vertex buffer
1075	1079	if (m_vertexbuf != NULL)
1076	1080	(*d3dintf->vertexbuf.release)(m_vertexbuf);

trunk/src/osd/windows/input.c

r242413	r242414
506	506	void windows_osd_interface::input_exit()
507	507	{
508	508	// acquire the lock and turn off input (this ensures everyone is done)
509		osd_lock_acquire(input_lock);
510		input_enabled = false;
511		osd_lock_release(input_lock);
	509	if (input_lock != NULL)
	510	{
	511	osd_lock_acquire(input_lock);
	512	input_enabled = false;
	513	osd_lock_release(input_lock);
512	514
513		// free the lock
514		osd_lock_free(input_lock);
	515	// free the lock
	516	osd_lock_free(input_lock);
	517	}
515	518	}
516	519
517	520

trunk/src/version.c

r242413	r242414
8	8
9	9	***************************************************************************/
10	10
	11	#define BARE_BUILD_VERSION "0.156"
	12
	13	extern const char bare_build_version[];
11	14	extern const char build_version[];
12		const char build_version[] = "0.156 (" __DATE__")";
	15	const char bare_build_version[] = BARE_BUILD_VERSION;
	16	const char build_version[] = BARE_BUILD_VERSION " (" __DATE__")";

https://github.com/mamedev/mame/commit/607739a6bbcef3a35e5d73e58205acd06952fc7a

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