trunk/src/mess/drivers/pc9801.c
| r242360 | r242361 | |
|---|
| 1376 | 1376 | UINT16 mask = m_egc.regs[4] & mem_mask, out = 0; |
| 1377 | 1377 | bool dir = !(m_egc.regs[6] & 0x1000); |
| 1378 | 1378 | int dst_off = (m_egc.regs[6] >> 4) & 0xf; |
| 1379 | | offset &= 0x3fff; |
| 1379 | offset &= 0x13fff; |
| 1380 | 1380 | |
| 1381 | 1381 | if((((m_egc.regs[2] >> 11) & 3) == 1) || ((((m_egc.regs[2] >> 11) & 3) == 2) && !BIT(m_egc.regs[2], 10))) |
| 1382 | 1382 | { |
| 1383 | 1383 | // mask off the bits past the end of the blit |
| 1384 | 1384 | if(m_egc.count < 16) |
| 1385 | | mask &= dir ? ((1 << (m_egc.count + 1)) - 1) : ~((1 << (16 - m_egc.count)) - 1); |
| 1385 | mask &= dir ? ((1 << m_egc.count) - 1) : ~((1 << (16 - m_egc.count)) - 1); |
| 1386 | 1386 | |
| 1387 | 1387 | // mask off the bits before the start |
| 1388 | 1388 | if(m_egc.first) |
| 1389 | 1389 | { |
| 1390 | 1390 | m_egc.leftover[0] = m_egc.leftover[1] = m_egc.leftover[2] = m_egc.leftover[3] = 0; |
| 1391 | | mask &= dir ? ~((1 << (16 - dst_off)) - 1) : ((1 << (dst_off + 1)) - 1); |
| 1391 | mask &= dir ? ~((1 << dst_off) - 1) : ((1 << (16 - dst_off)) - 1); |
| 1392 | 1392 | } |
| 1393 | 1393 | } |
| 1394 | 1394 | |
| r242360 | r242361 | |
|---|
| 1455 | 1455 | |
| 1456 | 1456 | UINT16 pc9801_state::egc_blit_r(UINT32 offset, UINT16 mem_mask) |
| 1457 | 1457 | { |
| 1458 | | UINT16 plane_off = offset & 0x3fff; |
| 1458 | UINT16 plane_off = offset & 0x13fff; |
| 1459 | 1459 | if((m_egc.regs[2] & 0x300) == 0x100) |
| 1460 | 1460 | { |
| 1461 | 1461 | m_egc.pat[0] = m_video_ram_2[plane_off + 0x4000]; |
| r242360 | r242361 | |
|---|
| 1488 | 1488 | { |
| 1489 | 1489 | int i; |
| 1490 | 1490 | |
| 1491 | | offset &= 0x3fff; |
| 1491 | offset &= 0x13fff; |
| 1492 | 1492 | res = 0; |
| 1493 | 1493 | for(i=0;i<4;i++) |
| 1494 | 1494 | { |
| r242360 | r242361 | |
|---|
| 1514 | 1514 | { |
| 1515 | 1515 | int i; |
| 1516 | 1516 | UINT8 *vram = (UINT8 *)m_video_ram_2.target(); |
| 1517 | | offset = (offset << 1) & 0x7fff; |
| 1517 | offset = (offset << 1) & 0x27fff; |
| 1518 | 1518 | |
| 1519 | 1519 | if(m_grcg.mode & 0x40) // RMW |
| 1520 | 1520 | { |