trunk/src/mess/drivers/mz6500.c
| r242345 | r242346 | |
|---|
| 62 | 62 | |
| 63 | 63 | READ8_MEMBER( mz6500_state::mz6500_vram_r ) |
| 64 | 64 | { |
| 65 | | return m_video_ram[offset]; |
| 65 | return m_video_ram[offset >> 1] >> ((offset & 1) ? 8 : 0); |
| 66 | 66 | } |
| 67 | 67 | |
| 68 | 68 | WRITE8_MEMBER( mz6500_state::mz6500_vram_w ) |
| 69 | 69 | { |
| 70 | | m_video_ram[offset] = data; |
| 70 | int mask = (offset & 1) ? 8 : 0; |
| 71 | offset >>= 1; |
| 72 | m_video_ram[offset] &= 0xff00 >> mask; |
| 73 | m_video_ram[offset] |= data << mask; |
| 71 | 74 | } |
| 72 | 75 | |
| 73 | 76 | static ADDRESS_MAP_START(mz6500_map, AS_PROGRAM, 16, mz6500_state) |
trunk/src/mess/drivers/qx10.c
| r242345 | r242346 | |
|---|
| 704 | 704 | else if(m_vram_bank & 2) { bank = 1; } // G |
| 705 | 705 | else if(m_vram_bank & 4) { bank = 2; } // R |
| 706 | 706 | |
| 707 | | return m_video_ram[offset + (0x20000 * bank)] | (m_video_ram[offset + (0x20000 * bank) + 1] << 8); |
| 707 | return m_video_ram[offset + (0x20000 * bank)]; |
| 708 | 708 | } |
| 709 | 709 | |
| 710 | 710 | WRITE16_MEMBER( qx10_state::vram_w ) |
| r242345 | r242346 | |
|---|
| 715 | 715 | else if(m_vram_bank & 2) { bank = 1; } // G |
| 716 | 716 | else if(m_vram_bank & 4) { bank = 2; } // R |
| 717 | 717 | |
| 718 | | if(mem_mask & 0xff) |
| 719 | | m_video_ram[offset + (0x20000 * bank)] = data; |
| 720 | | if(mem_mask & 0xff00) |
| 721 | | m_video_ram[offset + (0x20000 * bank) + 1] = data >> 8; |
| 718 | COMBINE_DATA(&m_video_ram[offset + (0x20000 * bank)]); |
| 722 | 719 | } |
| 723 | 720 | |
| 724 | 721 | static ADDRESS_MAP_START( upd7220_map, AS_0, 16, qx10_state ) |