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r33804 Wednesday 10th December, 2014 at 18:54:52 UTC by Jonathan Gevaryahu
Merge branch 'master' of https://github.com/mamedev/mame
[src/emu/bus]bus.mak
[src/emu/bus/ieee488]c2040fdc.c c2040fdc.h c8050fdc.c* c8050fdc.h*
[src/emu/machine]i6300esb.c i82875p.c i82875p.h pci.c pci.h
[src/mame/drivers]gts1.c viper.c
[src/mess/drivers]excali64.c victor9k.c
[src/mess/includes]victor9k.h
[src/mess/machine]victor9kb.c

trunk/src/emu/bus/bus.mak
r242315r242316
403403BUSOBJS += $(BUSOBJ)/ieee488/c2040.o
404404BUSOBJS += $(BUSOBJ)/ieee488/c2040fdc.o
405405BUSOBJS += $(BUSOBJ)/ieee488/c8050.o
406BUSOBJS += $(BUSOBJ)/ieee488/c8050fdc.o
406407BUSOBJS += $(BUSOBJ)/ieee488/c8280.o
407408BUSOBJS += $(BUSOBJ)/ieee488/d9060.o
408409BUSOBJS += $(BUSOBJ)/ieee488/softbox.o
trunk/src/emu/bus/ieee488/c2040fdc.c
r242315r242316
99
1010**********************************************************************/
1111
12/*
13
14    TODO:
15
16    - writing starts in the middle of a byte
17    - 8050 PLL
18
19*/
20
2112#include "c2040fdc.h"
2213
2314
r242315r242316
3526//**************************************************************************
3627
3728const device_type C2040_FDC = &device_creator<c2040_fdc_t>;
38const device_type C8050_FDC = &device_creator<c8050_fdc_t>;
3929
4030
4131//-------------------------------------------------
r242315r242316
6757//  c2040_fdc_t - constructor
6858//-------------------------------------------------
6959
70c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
71   device_t(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
72   m_write_sync(*this),
73   m_write_ready(*this),
74   m_write_error(*this),
75   m_gcr_rom(*this, "gcr"),
76   m_floppy0(NULL),
77   m_floppy1(NULL),
78   m_mtr0(1),
79   m_mtr1(1),
80   m_stp0(0),
81   m_stp1(0),
82   m_ds(0),
83   m_drv_sel(0),
84   m_mode_sel(0),
85   m_rw_sel(0),
86   m_period(attotime::from_hz(clock))
87{
88   cur_live.tm = attotime::never;
89   cur_live.state = IDLE;
90   cur_live.next_state = -1;
91   cur_live.write_position = 0;
92   cur_live.write_start_time = attotime::never;
93}
94
9560c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
9661   device_t(mconfig, C2040_FDC, "C2040 FDC", tag, owner, clock, "c2040fdc", __FILE__),
9762   m_write_sync(*this),
r242315r242316
11883   cur_live.drv_sel = m_drv_sel;
11984}
12085
121c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
122   c2040_fdc_t(mconfig, C8050_FDC, "C8050 FDC", tag, owner, clock, "c8050fdc", __FILE__) { }
12386
12487
125
12688//-------------------------------------------------
12789//  device_start - device-specific startup
12890//-------------------------------------------------
r242315r242316
635597   m_floppy0 = floppy0;
636598   m_floppy1 = floppy1;
637599}
638
639void c8050_fdc_t::live_start()
640{
641   cur_live.tm = machine().time();
642   cur_live.state = RUNNING;
643   cur_live.next_state = -1;
644
645   cur_live.shift_reg = 0;
646   cur_live.shift_reg_write = 0;
647   cur_live.cycle_counter = 0;
648   cur_live.cell_counter = 0;
649   cur_live.bit_counter = 0;
650   cur_live.ds = m_ds;
651   cur_live.drv_sel = m_drv_sel;
652   cur_live.mode_sel = m_mode_sel;
653   cur_live.rw_sel = m_rw_sel;
654   cur_live.pi = m_pi;
655
656   pll_reset(cur_live.tm, attotime::from_double(0));
657   checkpoint_live = cur_live;
658   pll_save_checkpoint();
659
660   live_run();
661}
662
663void c8050_fdc_t::pll_reset(const attotime &when, const attotime clock)
664{
665   cur_pll.reset(when);
666   cur_pll.set_clock(clock);
667}
668
669void c8050_fdc_t::pll_save_checkpoint()
670{
671   checkpoint_pll = cur_pll;
672}
673
674void c8050_fdc_t::pll_retrieve_checkpoint()
675{
676   cur_pll = checkpoint_pll;
677}
678
679void c8050_fdc_t::checkpoint()
680{
681   checkpoint_live = cur_live;
682   pll_save_checkpoint();
683}
684
685void c8050_fdc_t::rollback()
686{
687   cur_live = checkpoint_live;
688   pll_retrieve_checkpoint();
689}
690
691void c8050_fdc_t::live_run(const attotime &limit)
692{
693   if(cur_live.state == IDLE || cur_live.next_state != -1)
694      return;
695
696   for(;;) {
697      switch(cur_live.state) {
698      case RUNNING: {
699         bool syncpoint = false;
700
701         if (cur_live.tm > limit)
702            return;
703
704         int bit = get_next_bit(cur_live.tm, limit);
705         if(bit < 0)
706            return;
707
708         if (syncpoint) {
709            commit(cur_live.tm);
710
711            cur_live.tm += m_period;
712            live_delay(RUNNING_SYNCPOINT);
713            return;
714         }
715
716         cur_live.tm += m_period;
717         break;
718      }
719
720      case RUNNING_SYNCPOINT: {
721         m_write_ready(cur_live.ready);
722         m_write_sync(cur_live.sync);
723         m_write_error(cur_live.error);
724
725         cur_live.state = RUNNING;
726         checkpoint();
727         break;
728      }
729      }
730   }
731}
732
733int c8050_fdc_t::get_next_bit(attotime &tm, const attotime &limit)
734{
735   return cur_pll.get_next_bit(tm, get_floppy(), limit);
736}
737
738void c8050_fdc_t::stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp)
739{
740   if (mtr) return;
741
742   int tracks = 0;
743
744   switch (old_stp)
745   {
746   case 0: if (stp == 1) tracks++; else if (stp == 2) tracks--; break;
747   case 1: if (stp == 3) tracks++; else if (stp == 0) tracks--; break;
748   case 2: if (stp == 0) tracks++; else if (stp == 3) tracks--; break;
749   case 3: if (stp == 2) tracks++; else if (stp == 1) tracks--; break;
750   }
751
752   if (tracks == -1)
753   {
754      floppy->dir_w(1);
755      floppy->stp_w(1);
756      floppy->stp_w(0);
757   }
758   else if (tracks == 1)
759   {
760      floppy->dir_w(0);
761      floppy->stp_w(1);
762      floppy->stp_w(0);
763   }
764
765   old_stp = stp;
766}
767
768WRITE_LINE_MEMBER( c8050_fdc_t::odd_hd_w )
769{
770   if (m_odd_hd != state)
771   {
772      live_sync();
773      m_odd_hd = cur_live.odd_hd = state;
774      if (LOG) logerror("%s ODD HD %u\n", machine().time().as_string(), state);
775      m_floppy0->ss_w(!state);
776      if (m_floppy1) m_floppy1->ss_w(!state);
777      checkpoint();
778      live_run();
779   }
780}
781
782WRITE_LINE_MEMBER( c8050_fdc_t::pull_sync_w )
783{
784   // TODO
785   if (LOG) logerror("%s PULL SYNC %u\n", machine().time().as_string(), state);
786}
trunk/src/emu/bus/ieee488/c2040fdc.h
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1818#include "formats/d64_dsk.h"
1919#include "formats/d67_dsk.h"
2020#include "formats/g64_dsk.h"
21#include "formats/d80_dsk.h"
22#include "formats/d82_dsk.h"
2321#include "imagedev/floppy.h"
24#include "machine/fdc_pll.h"
2522
2623
2724
r242315r242316
5047{
5148public:
5249   // construction/destruction
53   c2040_fdc_t(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
5450   c2040_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
5551
5652   template<class _Object> static devcb_base &set_sync_wr_callback(device_t &device, _Object object) { return downcast<c2040_fdc_t &>(device).m_write_sync.set_callback(object); }
r242315r242316
6864
6965   DECLARE_READ_LINE_MEMBER( wps_r ) { return checkpoint_live.drv_sel ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); }
7066   DECLARE_READ_LINE_MEMBER( sync_r ) { return checkpoint_live.sync; }
71   DECLARE_READ_LINE_MEMBER( ready_r ) { return checkpoint_live.ready; }
72   DECLARE_READ_LINE_MEMBER( error_r ) { return checkpoint_live.error; }
7367
7468   void stp0_w(int stp);
7569   void stp1_w(int stp);
r242315r242316
147141   emu_timer *t_gen;
148142
149143   floppy_image_device* get_floppy();
150   virtual void live_start();
151   virtual void checkpoint();
152   virtual void rollback();
144
145   void live_start();
146   void checkpoint();
147   void rollback();
153148   bool write_next_bit(bool bit, const attotime &limit);
154149   void start_writing(const attotime &tm);
155150   void commit(const attotime &tm);
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157152   void live_delay(int state);
158153   void live_sync();
159154   void live_abort();
160   virtual void live_run(const attotime &limit = attotime::never);
155   void live_run(const attotime &limit = attotime::never);
161156   void get_next_edge(const attotime &when);
162   virtual int get_next_bit(attotime &tm, const attotime &limit);
157   int get_next_bit(attotime &tm, const attotime &limit);
163158};
164159
165160
166// ======================> c8050_fdc_t
167
168class c8050_fdc_t :  public c2040_fdc_t
169{
170public:
171   // construction/destruction
172   c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
173
174   DECLARE_WRITE_LINE_MEMBER( odd_hd_w );
175   DECLARE_WRITE_LINE_MEMBER( pull_sync_w );
176
177protected:
178   fdc_pll_t cur_pll, checkpoint_pll;
179
180   void stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp);
181
182   virtual void live_start();
183   virtual void checkpoint();
184   virtual void rollback();
185   void pll_reset(const attotime &when, const attotime clock);
186   void pll_save_checkpoint();
187   void pll_retrieve_checkpoint();
188   virtual void live_run(const attotime &limit = attotime::never);
189   virtual int get_next_bit(attotime &tm, const attotime &limit);
190};
191
192
193
194161// device type definition
195162extern const device_type C2040_FDC;
196extern const device_type C8050_FDC;
197163
198164
199165
trunk/src/emu/bus/ieee488/c8050fdc.c
r0r242316
1// license:BSD-3-Clause
2// copyright-holders:Curt Coder
3/**********************************************************************
4
5    Commodore 8050 floppy disk controller emulation
6
7    Copyright MESS Team.
8    Visit http://mamedev.org for licensing and usage restrictions.
9
10**********************************************************************/
11
12#include "c8050fdc.h"
13
14
15
16//**************************************************************************
17//  MACROS / CONSTANTS
18//**************************************************************************
19
20#define LOG 0
21
22
23
24//**************************************************************************
25//  DEVICE DEFINITIONS
26//**************************************************************************
27
28const device_type C8050_FDC = &device_creator<c8050_fdc_t>;
29
30
31//-------------------------------------------------
32//  ROM( c8050_fdc )
33//-------------------------------------------------
34
35ROM_START( c8050_fdc )
36   ROM_REGION( 0x800, "gcr", 0)
37   ROM_LOAD( "901467.uk6", 0x000, 0x800, CRC(a23337eb) SHA1(97df576397608455616331f8e837cb3404363fa2) )
38ROM_END
39
40
41//-------------------------------------------------
42//  rom_region - device-specific ROM region
43//-------------------------------------------------
44
45const rom_entry *c8050_fdc_t::device_rom_region() const
46{
47   return ROM_NAME( c8050_fdc );
48}
49
50
51
52//**************************************************************************
53//  LIVE DEVICE
54//**************************************************************************
55
56//-------------------------------------------------
57//  c8050_fdc_t - constructor
58//-------------------------------------------------
59
60c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
61   device_t(mconfig, C8050_FDC, "C8050 FDC", tag, owner, clock, "c8050fdc", __FILE__),
62   m_write_sync(*this),
63   m_write_ready(*this),
64   m_write_error(*this),
65   m_gcr_rom(*this, "gcr"),
66   m_floppy0(NULL),
67   m_floppy1(NULL),
68   m_mtr0(1),
69   m_mtr1(1),
70   m_stp0(0),
71   m_stp1(0),
72   m_ds(0),
73   m_drv_sel(0),
74   m_mode_sel(0),
75   m_rw_sel(0),
76   m_period(attotime::from_hz(clock))
77{
78   cur_live.tm = attotime::never;
79   cur_live.state = IDLE;
80   cur_live.next_state = -1;
81   cur_live.drv_sel = m_drv_sel;
82}
83
84
85
86//-------------------------------------------------
87//  device_start - device-specific startup
88//-------------------------------------------------
89
90void c8050_fdc_t::device_start()
91{
92   // resolve callbacks
93   m_write_sync.resolve_safe();
94   m_write_ready.resolve_safe();
95   m_write_error.resolve_safe();
96
97   // allocate timer
98   t_gen = timer_alloc(0);
99
100   // register for state saving
101   save_item(NAME(m_mtr0));
102   save_item(NAME(m_mtr1));
103   save_item(NAME(m_stp0));
104   save_item(NAME(m_stp1));
105   save_item(NAME(m_ds));
106   save_item(NAME(m_drv_sel));
107   save_item(NAME(m_mode_sel));
108   save_item(NAME(m_rw_sel));
109}
110
111
112//-------------------------------------------------
113//  device_reset - device-specific reset
114//-------------------------------------------------
115
116void c8050_fdc_t::device_reset()
117{
118   live_abort();
119}
120
121
122//-------------------------------------------------
123//  device_timer - handler timer events
124//-------------------------------------------------
125
126void c8050_fdc_t::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
127{
128   live_sync();
129   live_run();
130}
131
132floppy_image_device* c8050_fdc_t::get_floppy()
133{
134   return cur_live.drv_sel ? m_floppy1 : m_floppy0;
135}
136
137void c8050_fdc_t::stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp)
138{
139   if (mtr) return;
140
141   int tracks = 0;
142
143   switch (old_stp)
144   {
145   case 0: if (stp == 1) tracks++; else if (stp == 2) tracks--; break;
146   case 1: if (stp == 3) tracks++; else if (stp == 0) tracks--; break;
147   case 2: if (stp == 0) tracks++; else if (stp == 3) tracks--; break;
148   case 3: if (stp == 2) tracks++; else if (stp == 1) tracks--; break;
149   }
150
151   if (tracks == -1)
152   {
153      floppy->dir_w(1);
154      floppy->stp_w(1);
155      floppy->stp_w(0);
156   }
157   else if (tracks == 1)
158   {
159      floppy->dir_w(0);
160      floppy->stp_w(1);
161      floppy->stp_w(0);
162   }
163
164   old_stp = stp;
165}
166
167void c8050_fdc_t::stp0_w(int stp)
168{
169   if (m_stp0 != stp)
170   {
171      live_sync();
172      this->stp_w(m_floppy0, m_mtr0, m_stp0, stp);
173      checkpoint();
174      live_run();
175   }
176}
177
178void c8050_fdc_t::stp1_w(int stp)
179{
180   if (m_stp1 != stp)
181   {
182      live_sync();
183      if (m_floppy1) this->stp_w(m_floppy1, m_mtr1, m_stp1, stp);
184      checkpoint();
185      live_run();
186   }
187}
188
189void c8050_fdc_t::ds_w(int ds)
190{
191   if (m_ds != ds)
192   {
193      live_sync();
194      m_ds = cur_live.ds = ds;
195      checkpoint();
196      live_run();
197   }
198}
199
200void c8050_fdc_t::set_floppy(floppy_image_device *floppy0, floppy_image_device *floppy1)
201{
202   m_floppy0 = floppy0;
203   m_floppy1 = floppy1;
204}
205
206void c8050_fdc_t::live_start()
207{
208   cur_live.tm = machine().time();
209   cur_live.state = RUNNING;
210   cur_live.next_state = -1;
211
212   cur_live.shift_reg = 0;
213   cur_live.shift_reg_write = 0;
214   cur_live.cycle_counter = 0;
215   cur_live.cell_counter = 0;
216   cur_live.bit_counter = 0;
217   cur_live.ds = m_ds;
218   cur_live.drv_sel = m_drv_sel;
219   cur_live.mode_sel = m_mode_sel;
220   cur_live.rw_sel = m_rw_sel;
221   cur_live.pi = m_pi;
222
223   pll_reset(cur_live.tm, attotime::from_double(0));
224   checkpoint_live = cur_live;
225   pll_save_checkpoint();
226
227   live_run();
228}
229
230void c8050_fdc_t::pll_reset(const attotime &when, const attotime clock)
231{
232   cur_pll.reset(when);
233   cur_pll.set_clock(clock);
234}
235
236void c8050_fdc_t::pll_start_writing(const attotime &tm)
237{
238   cur_pll.start_writing(tm);
239}
240
241void c8050_fdc_t::pll_commit(floppy_image_device *floppy, const attotime &tm)
242{
243   cur_pll.commit(floppy, tm);
244}
245
246void c8050_fdc_t::pll_stop_writing(floppy_image_device *floppy, const attotime &tm)
247{
248   cur_pll.stop_writing(floppy, tm);
249}
250
251void c8050_fdc_t::pll_save_checkpoint()
252{
253   checkpoint_pll = cur_pll;
254}
255
256void c8050_fdc_t::pll_retrieve_checkpoint()
257{
258   cur_pll = checkpoint_pll;
259}
260
261int c8050_fdc_t::pll_get_next_bit(attotime &tm, floppy_image_device *floppy, const attotime &limit)
262{
263   return cur_pll.get_next_bit(tm, floppy, limit);
264}
265
266bool c8050_fdc_t::pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit)
267{
268   return cur_pll.write_next_bit_prev_cell(bit, tm, floppy, limit);
269}
270
271void c8050_fdc_t::checkpoint()
272{
273   pll_commit(get_floppy(), cur_live.tm);
274   checkpoint_live = cur_live;
275   pll_save_checkpoint();
276}
277
278void c8050_fdc_t::rollback()
279{
280   cur_live = checkpoint_live;
281   pll_retrieve_checkpoint();
282}
283
284void c8050_fdc_t::live_sync()
285{
286   if(!cur_live.tm.is_never()) {
287      if(cur_live.tm > machine().time()) {
288         rollback();
289         live_run(machine().time());
290         pll_commit(get_floppy(), cur_live.tm);
291      } else {
292         pll_commit(get_floppy(), cur_live.tm);
293         if(cur_live.next_state != -1) {
294            cur_live.state = cur_live.next_state;
295            cur_live.next_state = -1;
296         }
297         if(cur_live.state == IDLE) {
298            pll_stop_writing(get_floppy(), cur_live.tm);
299            cur_live.tm = attotime::never;
300         }
301      }
302      cur_live.next_state = -1;
303      checkpoint();
304   }
305}
306
307void c8050_fdc_t::live_abort()
308{
309   if(!cur_live.tm.is_never() && cur_live.tm > machine().time()) {
310      rollback();
311      live_run(machine().time());
312   }
313
314   pll_stop_writing(get_floppy(), cur_live.tm);
315
316   cur_live.tm = attotime::never;
317   cur_live.state = IDLE;
318   cur_live.next_state = -1;
319
320   cur_live.ready = 1;
321   cur_live.sync = 1;
322   cur_live.error = 1;
323}
324
325
326void c8050_fdc_t::live_run(const attotime &limit)
327{
328   if(cur_live.state == IDLE || cur_live.next_state != -1)
329      return;
330
331   for(;;) {
332      switch(cur_live.state) {
333      case RUNNING: {
334         bool syncpoint = false;
335
336         if (cur_live.tm > limit)
337            return;
338
339         int bit = pll_get_next_bit(cur_live.tm, get_floppy(), limit);
340         if(bit < 0)
341            return;
342
343         if (syncpoint) {
344            live_delay(RUNNING_SYNCPOINT);
345            return;
346         }
347         break;
348      }
349
350      case RUNNING_SYNCPOINT: {
351         m_write_ready(cur_live.ready);
352         m_write_sync(cur_live.sync);
353         m_write_error(cur_live.error);
354
355         cur_live.state = RUNNING;
356         checkpoint();
357         break;
358      }
359      }
360   }
361}
362
363READ8_MEMBER( c8050_fdc_t::read )
364{
365   UINT8 e = checkpoint_live.e;
366   offs_t i = checkpoint_live.i;
367
368   UINT8 data = (BIT(e, 6) << 7) | (BIT(i, 7) << 6) | (e & 0x33) | (BIT(e, 2) << 3) | (i & 0x04);
369
370   if (LOG) logerror("%s VIA reads data %02x (%03x)\n", machine().time().as_string(), data, checkpoint_live.shift_reg);
371
372   return data;
373}
374
375WRITE8_MEMBER( c8050_fdc_t::write )
376{
377   if (m_pi != data)
378   {
379      live_sync();
380      m_pi = cur_live.pi = data;
381      checkpoint();
382      if (LOG) logerror("%s PI %02x\n", machine().time().as_string(), data);
383      live_run();
384   }
385}
386
387WRITE_LINE_MEMBER( c8050_fdc_t::drv_sel_w )
388{
389   if (m_drv_sel != state)
390   {
391      live_sync();
392      m_drv_sel = cur_live.drv_sel = state;
393      checkpoint();
394      if (LOG) logerror("%s DRV SEL %u\n", machine().time().as_string(), state);
395      live_run();
396   }
397}
398
399WRITE_LINE_MEMBER( c8050_fdc_t::mode_sel_w )
400{
401   if (m_mode_sel != state)
402   {
403      live_sync();
404      m_mode_sel = cur_live.mode_sel = state;
405      checkpoint();
406      if (LOG) logerror("%s MODE SEL %u\n", machine().time().as_string(), state);
407      live_run();
408   }
409}
410
411WRITE_LINE_MEMBER( c8050_fdc_t::rw_sel_w )
412{
413   if (m_rw_sel != state)
414   {
415      live_sync();
416      m_rw_sel = cur_live.rw_sel = state;
417      checkpoint();
418      if (LOG) logerror("%s RW SEL %u\n", machine().time().as_string(), state);
419      if (m_rw_sel) {
420         pll_stop_writing(get_floppy(), machine().time());
421      } else {
422         pll_start_writing(machine().time());
423      }
424      live_run();
425   }
426}
427
428WRITE_LINE_MEMBER( c8050_fdc_t::mtr0_w )
429{
430   if (m_mtr0 != state)
431   {
432      live_sync();
433      m_mtr0 = state;
434      if (LOG) logerror("%s MTR0 %u\n", machine().time().as_string(), state);
435      m_floppy0->mon_w(state);
436      checkpoint();
437
438      if (!m_mtr0 || !m_mtr1) {
439         if(cur_live.state == IDLE) {
440            live_start();
441         }
442      } else {
443         live_abort();
444      }
445
446      live_run();
447   }
448}
449
450WRITE_LINE_MEMBER( c8050_fdc_t::mtr1_w )
451{
452   if (m_mtr1 != state)
453   {
454      live_sync();
455      m_mtr1 = state;
456      if (LOG) logerror("%s MTR1 %u\n", machine().time().as_string(), state);
457      if (m_floppy1) m_floppy1->mon_w(state);
458      checkpoint();
459
460      if (!m_mtr0 || !m_mtr1) {
461         if(cur_live.state == IDLE) {
462            live_start();
463         }
464      } else {
465         live_abort();
466      }
467
468      live_run();
469   }
470}
471
472WRITE_LINE_MEMBER( c8050_fdc_t::odd_hd_w )
473{
474   if (m_odd_hd != state)
475   {
476      live_sync();
477      m_odd_hd = cur_live.odd_hd = state;
478      if (LOG) logerror("%s ODD HD %u\n", machine().time().as_string(), state);
479      m_floppy0->ss_w(!state);
480      if (m_floppy1) m_floppy1->ss_w(!state);
481      checkpoint();
482      live_run();
483   }
484}
485
486WRITE_LINE_MEMBER( c8050_fdc_t::pull_sync_w )
487{
488   // TODO
489   if (LOG) logerror("%s PULL SYNC %u\n", machine().time().as_string(), state);
490}
trunk/src/emu/bus/ieee488/c8050fdc.h
r0r242316
1// license:BSD-3-Clause
2// copyright-holders:Curt Coder
3/**********************************************************************
4
5    Commodore 8050 floppy disk controller emulation
6
7    Copyright MESS Team.
8    Visit http://mamedev.org for licensing and usage restrictions.
9
10**********************************************************************/
11
12#pragma once
13
14#ifndef __C8050_FLOPPY__
15#define __C8050_FLOPPY__
16
17#include "emu.h"
18#include "formats/d80_dsk.h"
19#include "formats/d82_dsk.h"
20#include "imagedev/floppy.h"
21#include "machine/fdc_pll.h"
22
23
24
25//**************************************************************************
26//  INTERFACE CONFIGURATION MACROS
27//**************************************************************************
28
29#define MCFG_C8050_SYNC_CALLBACK(_write) \
30   devcb = &c8050_fdc_t::set_sync_wr_callback(*device, DEVCB_##_write);
31
32#define MCFG_C8050_READY_CALLBACK(_write) \
33   devcb = &c8050_fdc_t::set_ready_wr_callback(*device, DEVCB_##_write);
34
35#define MCFG_C8050_ERROR_CALLBACK(_write) \
36   devcb = &c8050_fdc_t::set_error_wr_callback(*device, DEVCB_##_write);
37
38
39
40//**************************************************************************
41//  TYPE DEFINITIONS
42//**************************************************************************
43
44// ======================> c8050_fdc_t
45
46class c8050_fdc_t :  public device_t
47{
48public:
49   // construction/destruction
50   c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
51
52   template<class _Object> static devcb_base &set_sync_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_sync.set_callback(object); }
53   template<class _Object> static devcb_base &set_ready_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_ready.set_callback(object); }
54   template<class _Object> static devcb_base &set_error_wr_callback(device_t &device, _Object object) { return downcast<c8050_fdc_t &>(device).m_write_error.set_callback(object); }
55
56   DECLARE_READ8_MEMBER( read );
57   DECLARE_WRITE8_MEMBER( write );
58
59   DECLARE_WRITE_LINE_MEMBER( drv_sel_w );
60   DECLARE_WRITE_LINE_MEMBER( mode_sel_w );
61   DECLARE_WRITE_LINE_MEMBER( rw_sel_w );
62   DECLARE_WRITE_LINE_MEMBER( mtr0_w );
63   DECLARE_WRITE_LINE_MEMBER( mtr1_w );
64   DECLARE_WRITE_LINE_MEMBER( odd_hd_w );
65   DECLARE_WRITE_LINE_MEMBER( pull_sync_w );
66
67   DECLARE_READ_LINE_MEMBER( wps_r ) { return checkpoint_live.drv_sel ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); }
68   DECLARE_READ_LINE_MEMBER( sync_r ) { return checkpoint_live.sync; }
69
70   void stp0_w(int stp);
71   void stp1_w(int stp);
72   void ds_w(int ds);
73
74   void set_floppy(floppy_image_device *floppy0, floppy_image_device *floppy1);
75
76protected:
77   // device-level overrides
78   virtual void device_start();
79   virtual void device_reset();
80   virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
81
82   // optional information overrides
83   virtual const rom_entry *device_rom_region() const;
84
85   void stp_w(floppy_image_device *floppy, int mtr, int &old_stp, int stp);
86
87   enum {
88      IDLE,
89      RUNNING,
90      RUNNING_SYNCPOINT
91   };
92
93   struct live_info {
94      attotime tm;
95      int state, next_state;
96      int sync;
97      int ready;
98      int error;
99      int ds;
100      int drv_sel;
101      int mode_sel;
102      int rw_sel;
103      int odd_hd;
104
105      attotime edge;
106      UINT16 shift_reg;
107      int cycle_counter;
108      int cell_counter;
109      int bit_counter;
110      UINT8 e;
111      offs_t i;
112
113      UINT8 pi;
114      UINT16 shift_reg_write;
115   };
116
117   devcb_write_line m_write_sync;
118   devcb_write_line m_write_ready;
119   devcb_write_line m_write_error;
120
121   required_memory_region m_gcr_rom;
122
123   floppy_image_device *m_floppy0;
124   floppy_image_device *m_floppy1;
125
126   int m_mtr0;
127   int m_mtr1;
128   int m_stp0;
129   int m_stp1;
130   int m_ds;
131   int m_drv_sel;
132   int m_mode_sel;
133   int m_rw_sel;
134   int m_odd_hd;
135   UINT8 m_pi;
136
137   attotime m_period;
138
139   live_info cur_live, checkpoint_live;
140   fdc_pll_t cur_pll, checkpoint_pll;
141   emu_timer *t_gen;
142
143   floppy_image_device* get_floppy();
144
145   void live_start();
146   void checkpoint();
147   void rollback();
148   void pll_reset(const attotime &when, const attotime clock);
149   void pll_start_writing(const attotime &tm);
150   void pll_commit(floppy_image_device *floppy, const attotime &tm);
151   void pll_stop_writing(floppy_image_device *floppy, const attotime &tm);
152   int pll_get_next_bit(attotime &tm, floppy_image_device *floppy, const attotime &limit);
153   bool pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit);
154   void pll_save_checkpoint();
155   void pll_retrieve_checkpoint();
156   void live_delay(int state);
157   void live_sync();
158   void live_abort();
159   void live_run(const attotime &limit = attotime::never);
160};
161
162
163// device type definition
164extern const device_type C8050_FDC;
165
166
167
168#endif
trunk/src/emu/machine/i6300esb.c
r242315r242316
121121   memset(mon_trp_rng, 0, sizeof(mon_trp_rng));
122122   mon_trp_msk = 0;
123123   nmi_sc = 0;
124   gen_sta = 0x00;
124125}
125126
126127void i6300esb_lpc_device::reset_all_mappings()
trunk/src/emu/machine/i82875p.c
r242315r242316
240240WRITE16_MEMBER(i82875p_host_device::toud_w)
241241{
242242   COMBINE_DATA(&toud);
243   logerror("%s: toud = %08x\n", tag(), 512*toud);
243   toud &= ~7;
244   logerror("%s: toud = %08x\n", tag(), toud << 16);
244245   remap_cb();
245246}
246247
r242315r242316
309310   return 0x00;
310311}
311312
313void i82875p_host_device::reset_all_mappings()
314{
315   pci_host_device::reset_all_mappings();
316
317   toud = 0x0400;
318   smram = 0x02;
319   esmramc = 0x38;
320   memset(pam, 0, sizeof(pam));
321}
322
312323void i82875p_host_device::device_reset()
313324{
314325   pci_host_device::device_reset();
315326
316327   agpm = 0x00;
317328   fpllcont = 0x00;
318   memset(pam, 0, sizeof(pam));
319   smram = 0x02;
320   esmramc = 0x38;
321329   agpctrl = 0x00000000;
322330   apsize = 0x00;
323331   attbase = 0x00000000;
324332   amtt = 0x10;
325333   lptt = 0x10;
326   toud = 0x0400;
327334   mchcfg = 0x0000;
328335   errcmd = 0x0000;
329336   smicmd = 0x0000;
r242315r242316
406413
407414   if((esmramc & 0x40) && (smram & 0x08))
408415      memory_space->install_ram      (0xfeda0000, 0xfedbffff, &ram[0x000a0000/4]);
409
410416}
411417
412418
trunk/src/emu/machine/i82875p.h
r242315r242316
2020   void set_cpu_tag(const char *tag);
2121   void set_ram_size(int ram_size);
2222
23   virtual void reset_all_mappings();
24
2325   virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
2426                     UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
2527
trunk/src/emu/machine/pci.c
r242315r242316
6363   revision = 0x00;
6464   pclass = 0xffffff;
6565   subsystem_id = 0xffffffff;
66   is_multifunction_device = false;
6667}
6768
6869void pci_device::set_ids(UINT32 _main_id, UINT8 _revision, UINT32 _pclass, UINT32 _subsystem_id)
r242315r242316
194195   return 0x00;
195196}
196197
198void pci_device::set_multifunction_device(bool enable)
199{
200   is_multifunction_device = enable;
201}
202
197203READ8_MEMBER(pci_device::header_type_r)
198204{
199   return 0x00;
205   return is_multifunction_device ? 0x80 : 0x00;
200206}
201207
202208READ8_MEMBER(pci_device::bist_r)
r242315r242316
237243   return 0x00;
238244}
239245
240void pci_device::scan_sub_devices(pci_device **devices, dynamic_array<pci_device *> &all, dynamic_array<pci_device *> &bridges, device_t *root)
241{
242}
243
244246void pci_device::set_remap_cb(mapper_cb _remap_cb)
245247{
246248   remap_cb = _remap_cb;
r242315r242316
425427
426428   for(int i=0; i<32*8; i++)
427429      if(sub_devices[i]) {
430         if((i & 7) && sub_devices[i & ~7])
431            sub_devices[i & ~7]->set_multifunction_device(true);
432
428433         all_devices.append(sub_devices[i]);
429434         if(sub_devices[i] != this) {
430435            sub_devices[i]->remap_config_cb = cf_cb;
r242315r242316
449454
450455void pci_bridge_device::reset_all_mappings()
451456{
457   pci_device::reset_all_mappings();
458
452459   for(int i=0; i != all_devices.count(); i++)
453460      if(all_devices[i] != this)
454461         all_devices[i]->reset_all_mappings();
r242315r242316
784791   memory_window_start = memory_window_end = memory_offset = 0;
785792   io_window_start = io_window_end = io_offset = 0;
786793
787   for(int i=0; i != all_devices.count(); i++)
788      if(all_devices[i] != this)
789         all_devices[i]->reset_all_mappings();
794   reset_all_mappings();
790795}
791796
792797void pci_host_device::device_reset()
trunk/src/emu/machine/pci.h
r242315r242316
3131   pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
3232
3333   void set_ids(UINT32 main_id, UINT8 revision, UINT32 pclass, UINT32 subsystem_id);
34   void set_multifunction_device(bool enable);
3435
3536   virtual void set_remap_cb(mapper_cb _remap_cb);
3637   virtual void reset_all_mappings();
r242315r242316
109110   const UINT8 *expansion_rom;
110111   UINT32 expansion_rom_size;
111112   UINT32 expansion_rom_base;
113   bool is_multifunction_device;
112114
113115   virtual void device_start();
114116   virtual void device_reset();
115117
116   static void scan_sub_devices(pci_device **devices, dynamic_array<pci_device *> &all, dynamic_array<pci_device *> &bridges, device_t *root);
117
118118   void skip_map_regs(int count);
119119   void add_map(UINT64 size, int flags, address_map_delegate &map);
120120   template <typename T> void add_map(UINT64 size, int flags, void (T::*map)(address_map &map, device_t &device), const char *name) {
trunk/src/mame/drivers/gts1.c
r242315r242316
9999    virtual void machine_reset();
100100    required_device<cpu_device> m_maincpu;
101101    UINT8 m_io[256];
102    UINT8 m_counter;
103102    UINT8 m_6351_addr;
104103};
105104
trunk/src/mame/drivers/viper.c
r242315r242316
1616G?A30    2002    Tsurugi
1717GMA41    2001    Thrill Drive 2
1818G?A45    2001    Boxing Mania
19GCB11    2001    Police 911 2 (USA) / Police 24/7 2 (World) / Keisatsukan Shinjuku 24ji 2 (Japan)
19G*B11    2001    Police 911 2 (USA) / Police 24/7 2 (World) / Keisatsukan Shinjuku 24ji 2 (Japan)
2020G?B33    2001    Mocap Golf
2121G?B41    2001    Jurassic Park 3
2222G?B4x    2002    Xtrial Racing
r242315r242316
7979      ADC0838 - National Semiconductor ADC0838 Serial I/O 8-Bit A/D Converters with Multiplexer Options (SOIC20 @ U13)
8080       DS2430 - Dallas DS2430 256-bits 1-Wire EEPROM. Has 256 bits x8 EEPROM (32 bytes), 64 bits x8 (8 bytes)
8181                one-time programmable application register and unique factory-lasered and tested 64-bit
82                registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) (TO-92 @ U37)
83                It appears the DS2430 is not protected from reading but the unique silicon serial number isn't
84                included in the 40 byte dump.
82                registration number (8-bit family code + 48-bit serial number + 8-bit CRC) (TO-92 @ U37)
83                The OTP application register on the common DS2430 and the Police 911 2 DS2430 are not programmed
84                (application register reads all 0xFF and the status register reads back 0xFF), so it's probably safe
85                to assume they're not used on any of them.
86                It appears the DS2430 is not protected from reading and the unique silicon serial number is
87                included in the 40 byte dump. In the Police 911 2 NVRAM dump the serial number is located at both 0x002A and 0x1026
88                so that means it is tied to the DS2430. If the serial number in the NVRAM and DS2430 match then they are
89                paired. The same serial number is likely present in the CF card image and a compare is done there too.
90                If they don't match the game requires an external DS2430 (i.e. dongle)
91                When the lasered ROM is read from the DS2430, it comes out from LSB to MSB (family code, LSB of
92                S/N->MSB of S/N, CRC)
93                For Police 911 2 that is 0x14 0xB2 0xB7 0x4A 0x00 0x00 0x00 0x83
94                Family code=0x14
95                S/N=0x0000004AB7B2
96                CRC=0x83
97                In a DS2430 dump, the first 32 bytes is the EEPROM and the lasered ROM is 8 bytes and starts at 0x20h
98                For Police 911 2 that is....
99                00000000h CB 9B 56 EC A0 4C 87 53 51 46 28 E7 00 00 00 74
100                00000010h 30 A9 C7 76 B9 85 A3 43 87 53 50 42 1A E7 FA CF
101                00000020h 14 B2 B7 4A 00 00 00 83
102                It may be possible to hand craft a DS2430 for a dongle-protected version of a game simply by using
103                one of the existing DS2430 dumps and adjusting the serial number found in a dump of the NVRAM to pair them
104                or adjusting the serial number in the NVRAM to match the serial number found in one of the dumped DS2430s.
85105      M48T58Y - ST Microelectronics M48T58Y Timekeeper RAM (DIP28 @ U39). When this dies (after 10 year lifespan)
86106                the game will complain with error RTC BAD then reset. The data inside the RTC can not be hand created
87107                (yet) so to revive the PCB the correct RTC data must be re-programmed to a new RTC and replaced
r242315r242316
22992319ROM_START(p9112) /* dongle-protected version */
23002320   VIPER_BIOS
23012321
2302   ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00)       /* plug-in male DIN5 dongle containing a DS2430 */
2322   ROM_REGION(0x28, "ds2430", ROMREGION_ERASE00)       /* plug-in male DIN5 dongle containing a DS2430. The sticker on the dongle says 'GCB11-UA' */
23032323   ROM_LOAD("ds2430_p9112.u3", 0x00, 0x28, CRC(d745c6ee) SHA1(065C9D0DF1703B3BBB53A07F4923FDEE3B16F80E))
23042324
23052325   ROM_REGION(0x2000, "m48t58", ROMREGION_ERASE00)     /* M48T58 Timekeeper NVRAM */
r242315r242316
25642584GAME(2001, p911kc,    p911,      viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Police 911 (ver KAC)", GAME_NOT_WORKING|GAME_NO_SOUND)
25652585GAME(2001, p911e,     p911,      viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Police 24/7 (ver EAA)", GAME_NOT_WORKING|GAME_NO_SOUND)
25662586GAME(2001, p911j,     p911,      viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Keisatsukan Shinjuku 24ji (ver JAC)", GAME_NOT_WORKING|GAME_NO_SOUND)
2567GAME(2001, p9112,     kviper,    viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Police 911 2 (ver UAD)", GAME_NOT_WORKING|GAME_NO_SOUND)
2587GAME(2001, p9112,     kviper,    viper, viper, viper_state, vipercf,  ROT90,  "Konami", "Police 911 2 (VER. UAA:B)", GAME_NOT_WORKING|GAME_NO_SOUND)
25682588GAME(2003, popn9,     kviper,    viper, viper, viper_state, vipercf,  ROT0,  "Konami", "Pop'n Music 9 (ver JAB)", GAME_NOT_WORKING|GAME_NO_SOUND)
25692589GAME(2001, sscopex,   kviper,    viper, viper, viper_state, vipercf,  ROT0,  "Konami", "Silent Scope EX (ver UAA)", GAME_NOT_WORKING|GAME_NO_SOUND)
25702590GAME(2001, sogeki,    sscopex,   viper, viper, viper_state, vipercf,  ROT0,  "Konami", "Sogeki (ver JAA)", GAME_NOT_WORKING|GAME_NO_SOUND)
trunk/src/mess/drivers/excali64.c
r242315r242316
77Skeleton driver created on 2014-12-09.
88
99Chips: Z80A, 8251, 8253, 8255, 6845
10We have Basic 1.1. Other known versions are 1.01, 2.1
1011
12Control W then Enter will switch between 40 and 80 characters per line.
13
1114ToDo:
1215- Some keys can be connected to more than one position in the matrix. Need to
1316  determine the correct positions.
1417- The position of the "Line Insert" key is unknown.
15- The video section has attributes and colour, none of this is done.
18- PCGEN command not working.
19- Colours are wrong (colour prom needs to be dumped)
1620- Disk controller
1721- Banking
1822- The schematic shows the audio counter connected to 2MHz, but this produces
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2024- Serial
2125- Parallel / Centronics
2226- Need software
27- Pasting can drop a character or two at the start of a line.
28- Clock change for crtc
2329
2430****************************************************************************/
2531
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4551      , m_palette(*this, "palette")
4652      , m_maincpu(*this, "maincpu")
4753      , m_cass(*this, "cassette")
54      , m_crtc(*this, "crtc")
4855      , m_io_keyboard(*this, "KEY")
4956   { }
5057
5158   DECLARE_DRIVER_INIT(excali64);
59   DECLARE_PALETTE_INIT(excali64);
5260   DECLARE_WRITE8_MEMBER(ppib_w);
5361   DECLARE_READ8_MEMBER(ppic_r);
5462   DECLARE_WRITE8_MEMBER(ppic_w);
r242315r242316
7179   bool m_crtc_de;
7280   required_device<cpu_device> m_maincpu;
7381   required_device<cassette_image_device> m_cass;
82   required_device<mc6845_device> m_crtc;
7483   required_ioport_array<8> m_io_keyboard;
7584};
7685
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96105
97106/* Input ports */
98107static INPUT_PORTS_START( excali64 )
99   //PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("LINEFEED") PORT_CODE(KEYCODE_ENTER_PAD) PORT_CHAR(0x0a)//H
100   //PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("REPT") PORT_CODE(KEYCODE_LALT)//0x11
101   //PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Down)") PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))//B
102   //PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Up)") PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
103   //PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Fire)") PORT_CODE(KEYCODE_INSERT) PORT_CHAR(UCHAR_MAMEKEY(INSERT))
104   //PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("\\ |")PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|') PORT_CHAR(0x1c)
105   //PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Right)") PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
106   //PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("BRK") PORT_CODE(KEYCODE_NUMLOCK) PORT_CHAR(0x03)
107   //PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("(Left)") PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
108
109108   PORT_START("KEY.0")    /* line 0 */
110   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('R') PORT_CHAR('R') PORT_CHAR(0x12)
111   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_CHAR('W') PORT_CHAR(0x17)
109   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') PORT_CHAR(0x12)
110   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W') PORT_CHAR(0x17)
112111   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
113   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('E') PORT_CHAR('E') PORT_CHAR(0x05)
112   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E') PORT_CHAR(0x05)
114113   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB) PORT_CHAR(0x09)
115114   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CAPSLOCK") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE
116   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('A') PORT_CHAR('A') PORT_CHAR(0x01)
117   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') PORT_CHAR('Q') PORT_CHAR(0x11)
115   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') PORT_CHAR(0x01)
116   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q') PORT_CHAR(0x11)
118117
119118   PORT_START("KEY.1")    /* line 1 */
120119   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F3") PORT_CODE(KEYCODE_F3)
121120   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F2") PORT_CODE(KEYCODE_F2)
122121   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F4") PORT_CODE(KEYCODE_F4)
123122   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Space") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
124   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)//=
123   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
125124   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED) // space
126125   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F1") PORT_CODE(KEYCODE_F1)
127126   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) // F1
128127
129128   PORT_START("KEY.2")    /* line 2 */
130129   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(". >") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
131   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('M') PORT_CHAR('M') PORT_CHAR(0x0d)
130   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M') PORT_CHAR(0x0d)
132131   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("/ ?") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
133132   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(", <") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
134   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('B') PORT_CHAR('B') PORT_CHAR(0x02)
133   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B') PORT_CHAR(0x02)
135134   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED) //B
136   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('N') PORT_CHAR('N') PORT_CHAR(0x0e)
135   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N') PORT_CHAR(0x0e)
137136   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) //N
138137
139138   PORT_START("KEY.3")    /* line 3 */
140139   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("' \"") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(0x27) PORT_CHAR(0x22) PORT_CHAR(0x27)
141   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('L') PORT_CHAR('L') PORT_CHAR(0x0c)
140   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L') PORT_CHAR(0x0c)
142141   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("RETURN") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(0x0d)
143142   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("; :") PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
144   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('J') PORT_CHAR('J') PORT_CHAR(0x0a)
145   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('G') PORT_CHAR('G') PORT_CHAR(0x07)
146   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('K') PORT_CHAR('K') PORT_CHAR(0x0b)
147   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('H') PORT_CHAR('H') PORT_CHAR(0x08)
143   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J') PORT_CHAR(0x0a)
144   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G') PORT_CHAR(0x07)
145   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') PORT_CHAR(0x0b)
146   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') PORT_CHAR(0x08)
148147
149148   PORT_START("KEY.4")    /* line 4 */
150149   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("4 $") PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
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158157
159158   PORT_START("KEY.5")    /* line 5 */
160159   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("[ {") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{') PORT_CHAR(0x1b)
161   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_CHAR('O') PORT_CHAR(0x0f)
160   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O') PORT_CHAR(0x0f)
162161   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("] }") PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']') PORT_CHAR('}') PORT_CHAR(0x1d)
163   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('P') PORT_CHAR('P') PORT_CHAR(0x10)
164   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('U') PORT_CHAR('U') PORT_CHAR(0x15)
165   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('T') PORT_CHAR('T') PORT_CHAR(0x14)
166   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('I') PORT_CHAR('I') PORT_CHAR(0x09)//0x12
167   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') PORT_CHAR('Y') PORT_CHAR(0x19)//0x14
162   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P') PORT_CHAR(0x10)
163   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U') PORT_CHAR(0x15)
164   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T') PORT_CHAR(0x14)
165   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') PORT_CHAR(0x09)
166   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') PORT_CHAR(0x19)
168167
169168   PORT_START("KEY.6")    /* line 6 */
170   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('F') PORT_CHAR('F') PORT_CHAR(0x06)
171   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('X') PORT_CHAR('X') PORT_CHAR(0x18)
172   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('V') PORT_CHAR('V') PORT_CHAR(0x16)
173   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('C') PORT_CHAR('C') PORT_CHAR(0x03)
174   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('D') PORT_CHAR('D') PORT_CHAR(0x04)
175   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('S') PORT_CHAR('S') PORT_CHAR(0x13)
176   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') PORT_CHAR('Z') PORT_CHAR(0x1a)
169   PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F') PORT_CHAR(0x06)
170   PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X') PORT_CHAR(0x18)
171   PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V') PORT_CHAR(0x16)
172   PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C') PORT_CHAR(0x03)
173   PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') PORT_CHAR(0x04)
174   PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') PORT_CHAR(0x13)
175   PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z') PORT_CHAR(0x1a)
177176   PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED) //Z
178177
179178   PORT_START("KEY.7")    /* line 7 */
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234233
235234/*
236235d0,1,2 : same as port50
237d7 : 2nd col
236d3 : 2nd colour set
238237*/
239238WRITE8_MEMBER( excali64_state::port70_w )
240239{
241240   m_sys_status = data;
241   m_crtc->set_unscaled_clock(BIT(data, 2) ? 2e6 : 1e6);
242242}
243243
244244WRITE8_MEMBER( excali64_state::video_w )
r242315r242316
262262   m_p_videoram = memregion("videoram")->base();
263263}
264264
265/* F4 Character Displayer */
266static const gfx_layout excali64_charlayout =
267{
268   8, 12,                  /* 8 x 12 characters */
269   256,                    /* 256 characters */
270   1,                      /* 1 bits per pixel */
271   { 0 },                  /* no bitplanes */
272   /* x offsets */
273   { 7, 6, 5, 4, 3, 2, 1, 0 },
274   /* y offsets */
275   { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8, 9*8, 10*8, 11*8 },
276   8*16                    /* every char takes 16 bytes */
277};
278
279static GFXDECODE_START( excali64 )
280   GFXDECODE_ENTRY( "chargen", 0x0000, excali64_charlayout, 0, 1 )
281GFXDECODE_END
282
283// The colour names in the comments are what's needed, the current rgb values are mostly wrong
284PALETTE_INIT_MEMBER( excali64_state, excali64 )
285{
286   // Colour Menu A
287   palette.set_pen_color(0, 0x00, 0x00, 0x00);   /*  0 Black     */
288   palette.set_pen_color(1, 0x7f, 0x00, 0x00);   /*  1 Dark Red      */
289   palette.set_pen_color(2, 0xff, 0x00, 0x00);   /*  2 Red       */
290   palette.set_pen_color(3, 0x00, 0x00, 0x00);   /*  3 Pink     */
291   palette.set_pen_color(4, 0xbf, 0xbf, 0xbf);   /*  4 Orange     */
292   palette.set_pen_color(5, 0x00, 0xff, 0xff);   /*  5 Brown     */
293   palette.set_pen_color(6, 0xff, 0xff, 0x00);   /*  6 Yellow        */
294   palette.set_pen_color(7, 0x7f, 0x7f, 0x00);   /*  7 Dark Green */
295   palette.set_pen_color(8, 0x00, 0x7f, 0x00);   /*  8 Green     */
296   palette.set_pen_color(9, 0x00, 0xff, 0x00);   /*  9 Bright Green  */
297   palette.set_pen_color(10, 0x00, 0x00, 0xff);  /* 10 Light Blue    */
298   palette.set_pen_color(11, 0x00, 0x00, 0x7f);  /* 11 Blue      */
299   palette.set_pen_color(12, 0xff, 0x00, 0xff);  /* 12 Magenta       */
300   palette.set_pen_color(13, 0x7f, 0x00, 0x7f);  /* 13 Purple        */
301   palette.set_pen_color(14, 0x80, 0x80, 0x80);  /* 14 Dark Grey      */
302   palette.set_pen_color(15, 0xff, 0xff, 0xff);  /* 15 White     */
303   // Colour Menu B
304   palette.set_pen_color(16, 0x00, 0x00, 0x00);  /*  0 Black     */
305   palette.set_pen_color(17, 0x7f, 0x00, 0x00);  /*  1 Dark Red  */
306   palette.set_pen_color(18, 0xff, 0x00, 0x00);  /*  2 Red       */
307   palette.set_pen_color(19, 0x80, 0x80, 0x80);  /*  3 Flesh     */
308   palette.set_pen_color(20, 0x00, 0x00, 0xff);  /*  4 Pink      */
309   palette.set_pen_color(21, 0xff, 0xff, 0x80);  /*  5 Yellow Brown */
310   palette.set_pen_color(22, 0x00, 0x00, 0x00);  /*  6 Dark Brown     */
311   palette.set_pen_color(23, 0x00, 0xff, 0x00);  /*  7 Dark Purple */
312   palette.set_pen_color(24, 0xff, 0x80, 0xff);  /*  8 Very Dark Green */
313   palette.set_pen_color(25, 0x00, 0xff, 0xff);  /*  9 Yellow Green */
314   palette.set_pen_color(26, 0xff, 0x40, 0x40);  /* 10 Grey Blue */
315   palette.set_pen_color(27, 0xff, 0x00, 0x00);  /* 11 Sky Blue */
316   palette.set_pen_color(28, 0x00, 0x80, 0x80);  /* 12 Very Pale Blue */
317   palette.set_pen_color(29, 0xff, 0x00, 0xff);  /* 13 Dark Grey */
318   palette.set_pen_color(30, 0x80, 0xff, 0x80);  /* 14 Light Grey */
319   palette.set_pen_color(31, 0xff, 0xff, 0xff);  /* 15 White     */
320   // Background
321   palette.set_pen_color(32, 0x00, 0x00, 0x00);  //  0 Black
322   palette.set_pen_color(33, 0xff, 0x00, 0x00);  //  1 Red
323   palette.set_pen_color(34, 0x00, 0x00, 0xff);  //  2 Blue
324   palette.set_pen_color(35, 0xff, 0x00, 0xff);  //  3 Magenta
325   palette.set_pen_color(36, 0x00, 0xff, 0x00);  //  4 Green
326   palette.set_pen_color(37, 0xff, 0xff, 0x00);  //  5 Yellow
327   palette.set_pen_color(38, 0x00, 0xff, 0xff);  //  6 Cyan
328   palette.set_pen_color(39, 0xff, 0xff, 0xff);  //  7 White
329
330}
331
265332MC6845_UPDATE_ROW( excali64_state::update_row )
266333{
267334   const rgb_t *palette = m_palette->palette()->entry_list_raw();
268   UINT8 chr,gfx;
335   UINT8 chr,gfx,col,bg,fg;
269336   UINT16 mem,x;
337   UINT8 col_base = BIT(m_sys_status, 3) ? 16 : 0;
270338   UINT32 *p = &bitmap.pix32(y);
271339
272340   for (x = 0; x < x_count; x++)
273341   {
274      UINT8 inv=0;
275      if (x == cursor_x) inv=0xff;
276      mem = (ma + x) & 0xfff;
342      mem = (ma + x) & 0x7ff;
277343      chr = m_p_videoram[mem];
278      gfx = m_p_chargen[(chr<<4) | ra] ^ inv;
344      col = m_p_videoram[mem+0x800];
345      fg = col_base + (col >> 4);
346      bg = 32 + ((col >> 1) & 7);
279347
348      if (BIT(col, 0) & BIT(chr, 7))
349         gfx = m_p_videoram[0x800 + (chr<<4) + ra]; // hires definition
350      else
351         gfx = m_p_chargen[(chr<<4) | ra]; // normal character
352     
353      gfx ^= ((x == cursor_x) ? 0xff : 0);
354
280355      /* Display a scanline of a character */
281      *p++ = palette[BIT(gfx, 0)];
282      *p++ = palette[BIT(gfx, 1)];
283      *p++ = palette[BIT(gfx, 2)];
284      *p++ = palette[BIT(gfx, 3)];
285      *p++ = palette[BIT(gfx, 4)];
286      *p++ = palette[BIT(gfx, 5)];
287      *p++ = palette[BIT(gfx, 6)];
288      *p++ = palette[BIT(gfx, 7)];
356      *p++ = palette[BIT(gfx, 0) ? fg : bg];
357      *p++ = palette[BIT(gfx, 1) ? fg : bg];
358      *p++ = palette[BIT(gfx, 2) ? fg : bg];
359      *p++ = palette[BIT(gfx, 3) ? fg : bg];
360      *p++ = palette[BIT(gfx, 4) ? fg : bg];
361      *p++ = palette[BIT(gfx, 5) ? fg : bg];
362      *p++ = palette[BIT(gfx, 6) ? fg : bg];
363      *p++ = palette[BIT(gfx, 7) ? fg : bg];
289364   }
290365}
291366
r242315r242316
328403   MCFG_SCREEN_ADD("screen", RASTER)
329404   MCFG_SCREEN_REFRESH_RATE(50)
330405   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
331   MCFG_SCREEN_SIZE(80*8, 25*10)
332   MCFG_SCREEN_VISIBLE_AREA(0, 80*8-1, 0, 25*10-1)
406   MCFG_SCREEN_SIZE(80*8, 24*12)
407   MCFG_SCREEN_VISIBLE_AREA(0, 80*8-1, 0, 24*12-1)
333408   MCFG_SCREEN_UPDATE_DEVICE("crtc", mc6845_device, screen_update)
334   MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
409   MCFG_PALETTE_ADD("palette", 40)
410   MCFG_PALETTE_INIT_OWNER(excali64_state, excali64)
411   //MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
412   MCFG_GFXDECODE_ADD("gfxdecode", "palette", excali64)
335413   MCFG_MC6845_ADD("crtc", MC6845, "screen", XTAL_16MHz / 16) // 1MHz for lowres; 2MHz for highres
336414   MCFG_MC6845_SHOW_BORDER_AREA(false)
337415   MCFG_MC6845_CHAR_WIDTH(8)
r242315r242316
346424/* ROM definition */
347425ROM_START( excali64 )
348426   ROM_REGION(0x10000, "maincpu", 0)
349   ROM_LOAD( "rom_1.bin", 0x0000, 0x4000, CRC(e129a305) SHA1(e43ec7d040c2b2e548d22fd6bbc7df8b45a26e5a) )
350   ROM_LOAD( "rom_2.bin", 0x2000, 0x2000, CRC(916d9f5a) SHA1(91c527cce963481b7bebf077e955ca89578bb553) )
427   ROM_LOAD( "rom_1.ic17", 0x0000, 0x4000, CRC(e129a305) SHA1(e43ec7d040c2b2e548d22fd6bbc7df8b45a26e5a) )
428   ROM_LOAD( "rom_2.ic24", 0x2000, 0x2000, CRC(916d9f5a) SHA1(91c527cce963481b7bebf077e955ca89578bb553) )
429   // fix a bug that causes screen to be filled with 'p'
430   ROM_FILL(0x4ee, 1, 0)
431   ROM_FILL(0x4ef, 1, 8)
432   ROM_FILL(0x4f6, 1, 0)
433   ROM_FILL(0x4f7, 1, 8)
351434
352435   ROM_REGION(0x2000, "videoram", ROMREGION_ERASE00)
353436
354437   ROM_REGION(0x1000, "chargen", 0)
355   ROM_LOAD( "genex_3.bin", 0x0000, 0x1000, CRC(b91619a9) SHA1(2ced636cb7b94ba9d329868d7ecf79963cefe9d9) )
438   ROM_LOAD( "genex_3.ic43", 0x0000, 0x1000, CRC(b91619a9) SHA1(2ced636cb7b94ba9d329868d7ecf79963cefe9d9) )
356439ROM_END
357440
358441/* Driver */
359442
360443/*    YEAR  NAME      PARENT  COMPAT   MACHINE    INPUT     CLASS             INIT        COMPANY         FULLNAME        FLAGS */
361COMP( 1984, excali64, 0,      0,       excali64,  excali64, excali64_state, excali64,  "BGR Computers", "Excalibur 64", GAME_IS_SKELETON )
444COMP( 1984, excali64, 0,      0,       excali64,  excali64, excali64_state, excali64,  "BGR Computers", "Excalibur 64", GAME_NOT_WORKING )
trunk/src/mess/drivers/victor9k.c
r242315r242316
1313
1414    TODO:
1515
16   - centronics
16    - keyboard
1717   - expansion bus
1818      - Z80 card
1919      - Winchester DMA card (Xebec S1410 + Tandon TM502/TM603SE)
2020      - RAM cards
2121      - clock cards
2222    - floppy 8048
23    - keyboard
2423    - hires graphics
2524    - brightness/contrast
2625    - MC6852
r242315r242316
4140//-------------------------------------------------
4241
4342static ADDRESS_MAP_START( victor9k_mem, AS_PROGRAM, 8, victor9k_state )
44//  AM_RANGE(0x00000, 0xdffff) AM_RAM
43   AM_RANGE(0x00000, 0x1ffff) AM_RAM
4544   AM_RANGE(0x20000, 0xdffff) AM_NOP
46   AM_RANGE(0xe0000, 0xe0001) AM_DEVREADWRITE(I8259A_TAG, pic8259_device, read, write)
47   AM_RANGE(0xe0020, 0xe0023) AM_DEVREADWRITE(I8253_TAG, pit8253_device, read, write)
48   AM_RANGE(0xe0040, 0xe0043) AM_DEVREADWRITE(UPD7201_TAG, upd7201_device, cd_ba_r, cd_ba_w)
45   AM_RANGE(0xe0000, 0xe0001) AM_MIRROR(0x7f00) AM_DEVREADWRITE(I8259A_TAG, pic8259_device, read, write)
46   AM_RANGE(0xe0020, 0xe0023) AM_MIRROR(0x7f00) AM_DEVREADWRITE(I8253_TAG, pit8253_device, read, write)
47   AM_RANGE(0xe0040, 0xe0043) AM_MIRROR(0x7f00) AM_DEVREADWRITE(UPD7201_TAG, upd7201_device, cd_ba_r, cd_ba_w)
4948   AM_RANGE(0xe8000, 0xe8000) AM_MIRROR(0x7f00) AM_DEVREADWRITE(HD46505S_TAG, mc6845_device, status_r, address_w)
5049   AM_RANGE(0xe8001, 0xe8001) AM_MIRROR(0x7f00) AM_DEVREADWRITE(HD46505S_TAG, mc6845_device, register_r, register_w)
5150   AM_RANGE(0xe8020, 0xe802f) AM_MIRROR(0x7f00) AM_DEVREADWRITE(M6522_1_TAG, via6522_device, read, write)
r242315r242316
5655   AM_RANGE(0xe80c0, 0xe80cf) AM_MIRROR(0x7f00) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs6_r, cs6_w)
5756   AM_RANGE(0xe80e0, 0xe80ef) AM_MIRROR(0x7f00) AM_DEVREADWRITE(FDC_TAG, victor_9000_fdc_t, cs7_r, cs7_w)
5857   AM_RANGE(0xf0000, 0xf0fff) AM_MIRROR(0x1000) AM_RAM AM_SHARE("video_ram")
59   AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION(I8088_TAG, 0)
58   AM_RANGE(0xf8000, 0xf9fff) AM_MIRROR(0x6000) AM_ROM AM_REGION(I8088_TAG, 0)
6059ADDRESS_MAP_END
6160
6261
r242315r242316
169168{
170169   m_ssda_irq = state;
171170
172   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
171   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
173172}
174173
175174
r242315r242316
190189
191190   */
192191
192   // centronics
193   m_centronics->write_data0(BIT(data, 0));
194   m_centronics->write_data1(BIT(data, 1));
195   m_centronics->write_data2(BIT(data, 2));
196   m_centronics->write_data3(BIT(data, 3));
197   m_centronics->write_data4(BIT(data, 4));
198   m_centronics->write_data5(BIT(data, 5));
199   m_centronics->write_data6(BIT(data, 6));
200   m_centronics->write_data7(BIT(data, 7));
201
202   // IEEE-488
193203   m_ieee488->dio_w(data);
194204}
195205
r242315r242316
211221
212222       bit     description
213223
214       PB0     DAV
215       PB1     EOI
224       PB0     DAV / DATA STROBE
225       PB1     EOI / VFU?
216226       PB2     REN
217227       PB3     ATN
218228       PB4     IFC
r242315r242316
222232
223233   */
224234
235   // centronics
236   m_centronics->write_strobe(BIT(data, 0));
237
225238   // IEEE-488
226239   m_ieee488->dav_w(BIT(data, 0));
227240   m_ieee488->eoi_w(BIT(data, 1));
r242315r242316
241254{
242255   m_via1_irq = state;
243256
244   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
257   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
245258}
246259
247260WRITE8_MEMBER( victor9k_state::via2_pa_w )
r242315r242316
304317}
305318
306319
307WRITE_LINE_MEMBER( victor9k_state::via2_irq_w )
308{
309   m_via2_irq = state;
310
311   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
312}
313
314
315320/*
316321    bit    description
317322
r242315r242316
348353{
349354   m_via3_irq = state;
350355
351   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
356   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
352357}
353358
354359
r242315r242316
359364WRITE_LINE_MEMBER( victor9k_state::kbrdy_w )
360365{
361366   //logerror("KBRDY %u\n", state);
367
362368   m_via2->write_cb1(state);
363
364   m_pic->ir6_w(state ? CLEAR_LINE : ASSERT_LINE);
365369}
366370
367371WRITE_LINE_MEMBER( victor9k_state::kbdata_w )
368372{
369373   //logerror("KBDATA %u\n", state);
374
370375   m_via2->write_cb2(state);
371376   m_via2->write_pa6(state);
372377}
r242315r242316
376381{
377382   m_fdc_irq = state;
378383
379   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_fdc_irq);
384   m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via3_irq || m_fdc_irq);
380385}
381386
382387
r242315r242316
390395   save_item(NAME(m_brt));
391396   save_item(NAME(m_cont));
392397   save_item(NAME(m_via1_irq));
393   save_item(NAME(m_via2_irq));
394398   save_item(NAME(m_via3_irq));
395399   save_item(NAME(m_fdc_irq));
396400   save_item(NAME(m_ssda_irq));
397401
398   // memory banking
399   address_space &program = m_maincpu->space(AS_PROGRAM);
400   program.install_ram(0x00000, m_ram->size() - 1, m_ram->pointer());
401
402402   // patch out SCP self test
403403   m_rom->base()[0x11ab] = 0xc3;
404404
r242315r242316
422422}
423423
424424
425
425426//**************************************************************************
426427//  MACHINE CONFIGURATION
427428//**************************************************************************
r242315r242316
446447
447448   MCFG_PALETTE_ADD_MONOCHROME_GREEN_HIGHLIGHT("palette")
448449
449   MCFG_MC6845_ADD(HD46505S_TAG, HD6845, SCREEN_TAG, 1000000) // HD6845 == HD46505S
450   MCFG_MC6845_ADD(HD46505S_TAG, HD6845, SCREEN_TAG, XTAL_30MHz/11) // HD6845 == HD46505S
450451   MCFG_MC6845_SHOW_BORDER_AREA(true)
451452   MCFG_MC6845_CHAR_WIDTH(10)
452453   MCFG_MC6845_UPDATE_ROW_CB(victor9k_state, crtc_update_row)
r242315r242316
501502   MCFG_DEVICE_ADD(M6522_2_TAG, VIA6522, XTAL_30MHz/30)
502503   MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor9k_state, via2_pa_w))
503504   MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via2_pb_w))
504   MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via2_irq_w))
505   MCFG_VIA6522_IRQ_HANDLER(DEVWRITELINE(I8259A_TAG, pic8259_device, ir6_w))
505506
506507   MCFG_DEVICE_ADD(M6522_3_TAG, VIA6522, XTAL_30MHz/30)
507508   MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via3_pb_w))
508509   MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via3_irq_w))
509510
511   MCFG_CENTRONICS_ADD(CENTRONICS_TAG, centronics_devices, "printer")
512   MCFG_CENTRONICS_BUSY_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb5))
513   MCFG_CENTRONICS_ACK_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb6))
514   MCFG_CENTRONICS_SELECT_HANDLER(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb7))
515
510516   MCFG_RS232_PORT_ADD(RS232_A_TAG, default_rs232_devices, NULL)
511517   MCFG_RS232_RXD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, rxa_w))
512518   MCFG_RS232_DCD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, dcda_w))
r242315r242316
521527   MCFG_RS232_CTS_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, ctsb_w))
522528   MCFG_RS232_DSR_HANDLER(DEVWRITELINE(M6522_2_TAG, via6522_device, write_pa5))
523529
524   MCFG_DEVICE_ADD(VICTOR9K_KEYBOARD_TAG, VICTOR9K_KEYBOARD, 0)
530   MCFG_DEVICE_ADD(KB_TAG, VICTOR9K_KEYBOARD, 0)
525531   MCFG_VICTOR9K_KBRDY_HANDLER(WRITELINE(victor9k_state, kbrdy_w))
526532   MCFG_VICTOR9K_KBDATA_HANDLER(WRITELINE(victor9k_state, kbdata_w))
527533
r242315r242316
533539   // internal ram
534540   MCFG_RAM_ADD(RAM_TAG)
535541   MCFG_RAM_DEFAULT_SIZE("128K")
536   MCFG_RAM_EXTRA_OPTIONS("256K,384K,512K,640K,768K,896K")
537542
538543   // software list
539544   MCFG_SOFTWARE_LIST_ADD("flop_list", "victor9k_flop")
trunk/src/mess/includes/victor9k.h
r242315r242316
1515#define __VICTOR9K__
1616
1717#include "bus/rs232/rs232.h"
18#include "bus/centronics/ctronics.h"
1819#include "cpu/i86/i86.h"
1920#include "formats/victor9k_dsk.h"
2021#include "imagedev/floppy.h"
r242315r242316
4748#define RS232_A_TAG     "rs232a"
4849#define RS232_B_TAG     "rs232b"
4950#define SCREEN_TAG      "screen"
50#define VICTOR9K_KEYBOARD_TAG   "victor9kb"
51#define KB_TAG         "kb"
5152#define FDC_TAG         "fdc"
5253
5354class victor9k_state : public driver_device
r242315r242316
6667      m_cvsd(*this, HC55516_TAG),
6768      m_crtc(*this, HD46505S_TAG),
6869      m_ram(*this, RAM_TAG),
69      m_kb(*this, VICTOR9K_KEYBOARD_TAG),
70      m_kb(*this, KB_TAG),
7071      m_fdc(*this, FDC_TAG),
72      m_centronics(*this, CENTRONICS_TAG),
7173      m_rs232a(*this, RS232_A_TAG),
7274      m_rs232b(*this, RS232_B_TAG),
7375      m_palette(*this, "palette"),
r242315r242316
7678      m_brt(0),
7779      m_cont(0),
7880      m_via1_irq(CLEAR_LINE),
79      m_via2_irq(CLEAR_LINE),
8081      m_via3_irq(CLEAR_LINE),
8182      m_fdc_irq(CLEAR_LINE),
8283      m_ssda_irq(CLEAR_LINE)
r242315r242316
9596   required_device<ram_device> m_ram;
9697   required_device<victor9k_keyboard_device> m_kb;
9798   required_device<victor_9000_fdc_t> m_fdc;
99   required_device<centronics_device> m_centronics;
98100   required_device<rs232_port_device> m_rs232a;
99101   required_device<rs232_port_device> m_rs232b;
100102   required_device<palette_device> m_palette;
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115117   DECLARE_WRITE8_MEMBER( via2_pb_w );
116118   DECLARE_WRITE_LINE_MEMBER( write_ria );
117119   DECLARE_WRITE_LINE_MEMBER( write_rib );
118   DECLARE_WRITE_LINE_MEMBER( via2_irq_w );
119120
120121   DECLARE_WRITE8_MEMBER( via3_pb_w );
121122   DECLARE_WRITE_LINE_MEMBER( via3_irq_w );
r242315r242316
136137
137138   /* interrupts */
138139   int m_via1_irq;
139   int m_via2_irq;
140140   int m_via3_irq;
141141   int m_fdc_irq;
142142   int m_ssda_irq;
trunk/src/mess/machine/victor9kb.c
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179179   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
180180
181181   PORT_START("Y6")
182   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
183   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
184   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
185   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
186   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
187   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
188   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
189   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
182   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q)
183   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W)
184   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E)
185   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R)
186   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T)
187   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y)
188   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U)
189   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I)
190190
191191   PORT_START("Y7")
192192   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
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288288   m_kbrdy_handler(*this),
289289   m_kbdata_handler(*this),
290290   m_y(0),
291   m_kbrdy(1),
292   m_kbdata(1),
291   m_kbrdy(-1),
292   m_kbdata(-1),
293293   m_kback(1)
294294{
295295}
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373373      m_y = data & 0x0f;
374374   }
375375
376   //logerror("P1 %02x\n", data);
376   //logerror("%s P1 %02x\n", machine().describe_context(), data);
377377}
378378
379379
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410410      m_kbdata_handler(m_kbdata);
411411   }
412412
413   //logerror("P2 %02x\n", data);
413   //logerror("%s P2 %01x\n", machine().describe_context(), data&0x0f);
414414}
415415
416416

https://github.com/mamedev/mame/commit/6082fc677279d40567370aee727a9b5293c7c648

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