Previous

199869 Revisions

Next

r33743 Monday 8th December, 2014 at 18:01:08 UTC by David Haywood
misc ARC dasm (nw)

[src/emu/cpu/arcompact]

arcompactdasm.c

trunk/src/emu/cpu/arcompact/arcompactdasm.c

r242254	r242255
24	24
25	25	/*****************************************************************************/
26	26
	27	#define DASM_OPS_16 char *output, offs_t pc, UINT16 op, const UINT8* oprom
	28	#define DASM_OPS_32 char *output, offs_t pc, UINT32 op, const UINT8* oprom
27	29
28		static const char *basic[0x20] =
29		{
30		/* opcode below are 32-bit mode */
31		/* 00 */ "Bcc",
32		/* 01 */ "BLcc/BRcc",
33		/* 02 */ "LD r+o",
34		/* 03 */ "ST r+o",
35		/* 04 */ "op a,b,c (basecase)", // basecase ops
36		/* 05 */ "op a,b,c (05 ARC ext)", // ARC processor specific extensions
37		/* 06 */ "op a,b,c (06 ARC ext)",
38		/* 07 */ "op a,b,c (07 User ext)", // User speciifc extensions
39		/* 08 */ "op a,b,c (08 User ext)",
40		/* 09 */ "op a,b,c (09 Market ext)", // Market specific extensions
41		/* 0a */ "op a,b,c (0a Market ext)",
42		/* 0b */ "op a,b,c (0b Market ext)",
43		/* opcodes below are 16-bit mode */
44		/* 0c */ "Load/Add reg-reg",
45		/* 0d */ "Add/Sub/Shft imm",
46		/* 0e */ "Mov/Cmp/Add",
47		/* 0f */ "op_S b,b,c", // single ops
48		/* 10 */ "LD_S",
49		/* 11 */ "LDB_S",
50		/* 12 */ "LDW_S",
51		/* 13 */ "LSW_S.X",
52		/* 14 */ "ST_S",
53		/* 15 */ "STB_S",
54		/* 16 */ "STW_S",
55		/* 17 */ "Shift/Sub/Bit",
56		/* 18 */ "Stack Instr",
57		/* 19 */ "GP Instr",
58		/* 1a */ "PCL Instr",
59		/* 1b */ "MOV_S",
60		/* 1c */ "ADD_S/CMP_S",
61		/* 1d */ "BRcc_S",
62		/* 1e */ "Bcc_S",
63		/* 1f */ "BL_S"
64		};
	30	int arcompact_handle18_00_dasm(DASM_OPS_16);
	31	int arcompact_handle18_01_dasm(DASM_OPS_16);
	32	int arcompact_handle18_02_dasm(DASM_OPS_16);
	33	int arcompact_handle18_03_dasm(DASM_OPS_16);
	34	int arcompact_handle18_04_dasm(DASM_OPS_16);
65	35
	36	int arcompact_handle18_05_dasm(DASM_OPS_16);
	37	int arcompact_handle18_05_00_dasm(DASM_OPS_16);
	38	int arcompact_handle18_05_01_dasm(DASM_OPS_16);
	39	int arcompact_handle18_05_02_dasm(DASM_OPS_16);
	40	int arcompact_handle18_05_03_dasm(DASM_OPS_16);
	41	int arcompact_handle18_05_04_dasm(DASM_OPS_16);
	42	int arcompact_handle18_05_05_dasm(DASM_OPS_16);
	43	int arcompact_handle18_05_06_dasm(DASM_OPS_16);
	44	int arcompact_handle18_05_07_dasm(DASM_OPS_16);
	45
	46	int arcompact_handle18_06_dasm(DASM_OPS_16);
	47	int arcompact_handle18_06_00_dasm(DASM_OPS_16);
	48	int arcompact_handle18_06_01_dasm(DASM_OPS_16);
	49	int arcompact_handle18_06_02_dasm(DASM_OPS_16);
	50	int arcompact_handle18_06_03_dasm(DASM_OPS_16);
	51	int arcompact_handle18_06_04_dasm(DASM_OPS_16);
	52	int arcompact_handle18_06_05_dasm(DASM_OPS_16);
	53	int arcompact_handle18_06_06_dasm(DASM_OPS_16);
	54	int arcompact_handle18_06_07_dasm(DASM_OPS_16);
	55	int arcompact_handle18_06_08_dasm(DASM_OPS_16);
	56	int arcompact_handle18_06_09_dasm(DASM_OPS_16);
	57	int arcompact_handle18_06_0a_dasm(DASM_OPS_16);
	58	int arcompact_handle18_06_0b_dasm(DASM_OPS_16);
	59	int arcompact_handle18_06_0c_dasm(DASM_OPS_16);
	60	int arcompact_handle18_06_0d_dasm(DASM_OPS_16);
	61	int arcompact_handle18_06_0e_dasm(DASM_OPS_16);
	62	int arcompact_handle18_06_0f_dasm(DASM_OPS_16);
	63	int arcompact_handle18_06_10_dasm(DASM_OPS_16);
	64	int arcompact_handle18_06_11_dasm(DASM_OPS_16);
	65	int arcompact_handle18_06_12_dasm(DASM_OPS_16);
	66	int arcompact_handle18_06_13_dasm(DASM_OPS_16);
	67	int arcompact_handle18_06_14_dasm(DASM_OPS_16);
	68	int arcompact_handle18_06_15_dasm(DASM_OPS_16);
	69	int arcompact_handle18_06_16_dasm(DASM_OPS_16);
	70	int arcompact_handle18_06_17_dasm(DASM_OPS_16);
	71	int arcompact_handle18_06_18_dasm(DASM_OPS_16);
	72	int arcompact_handle18_06_19_dasm(DASM_OPS_16);
	73	int arcompact_handle18_06_1a_dasm(DASM_OPS_16);
	74	int arcompact_handle18_06_1b_dasm(DASM_OPS_16);
	75	int arcompact_handle18_06_1c_dasm(DASM_OPS_16);
	76	int arcompact_handle18_06_1d_dasm(DASM_OPS_16);
	77	int arcompact_handle18_06_1e_dasm(DASM_OPS_16);
	78	int arcompact_handle18_06_1f_dasm(DASM_OPS_16);
	79
	80	int arcompact_handle18_07_dasm(DASM_OPS_16);
	81	int arcompact_handle18_07_00_dasm(DASM_OPS_16);
	82	int arcompact_handle18_07_01_dasm(DASM_OPS_16);
	83	int arcompact_handle18_07_02_dasm(DASM_OPS_16);
	84	int arcompact_handle18_07_03_dasm(DASM_OPS_16);
	85	int arcompact_handle18_07_04_dasm(DASM_OPS_16);
	86	int arcompact_handle18_07_05_dasm(DASM_OPS_16);
	87	int arcompact_handle18_07_06_dasm(DASM_OPS_16);
	88	int arcompact_handle18_07_07_dasm(DASM_OPS_16);
	89	int arcompact_handle18_07_08_dasm(DASM_OPS_16);
	90	int arcompact_handle18_07_09_dasm(DASM_OPS_16);
	91	int arcompact_handle18_07_0a_dasm(DASM_OPS_16);
	92	int arcompact_handle18_07_0b_dasm(DASM_OPS_16);
	93	int arcompact_handle18_07_0c_dasm(DASM_OPS_16);
	94	int arcompact_handle18_07_0d_dasm(DASM_OPS_16);
	95	int arcompact_handle18_07_0e_dasm(DASM_OPS_16);
	96	int arcompact_handle18_07_0f_dasm(DASM_OPS_16);
	97	int arcompact_handle18_07_10_dasm(DASM_OPS_16);
	98	int arcompact_handle18_07_11_dasm(DASM_OPS_16);
	99	int arcompact_handle18_07_12_dasm(DASM_OPS_16);
	100	int arcompact_handle18_07_13_dasm(DASM_OPS_16);
	101	int arcompact_handle18_07_14_dasm(DASM_OPS_16);
	102	int arcompact_handle18_07_15_dasm(DASM_OPS_16);
	103	int arcompact_handle18_07_16_dasm(DASM_OPS_16);
	104	int arcompact_handle18_07_17_dasm(DASM_OPS_16);
	105	int arcompact_handle18_07_18_dasm(DASM_OPS_16);
	106	int arcompact_handle18_07_19_dasm(DASM_OPS_16);
	107	int arcompact_handle18_07_1a_dasm(DASM_OPS_16);
	108	int arcompact_handle18_07_1b_dasm(DASM_OPS_16);
	109	int arcompact_handle18_07_1c_dasm(DASM_OPS_16);
	110	int arcompact_handle18_07_1d_dasm(DASM_OPS_16);
	111	int arcompact_handle18_07_1e_dasm(DASM_OPS_16);
	112	int arcompact_handle18_07_1f_dasm(DASM_OPS_16);
	113
	114
	115
66	116	// condition codes (basic ones are the same as arc
67	117	static const char *conditions[0x20] =
68	118	{
r242254	r242255
120	170	/* 0f */ "<BBIT1>"
121	171	};
122	172
123		static const char *table18[0x8] =
124		{
125		/* 00 */ "LD_S (SP)",
126		/* 01 */ "LDB_S (SP)",
127		/* 02 */ "ST_S (SP)",
128		/* 03 */ "STB_S (SP)",
129		/* 04 */ "ADD_S (SP)",
130		/* 05 */ "ADD_S/SUB_S (SP)",
131		/* 06 */ "POP_S (SP)",
132		/* 07 */ "PUSH_S (SP)",
133	173
134		};
135	174
	175
	176
136	177	static const char *table0f[0x20] =
137	178	{
138	179	/* 00 */ "SOPs", // Sub Operation (another table..) ( table0f_00 )
r242254	r242255
195	236
196	237	#define ARCOMPACT_OPERATION ((op & 0xf800) >> 11)
197	238
198		CPU_DISASSEMBLE(arcompact)
	239
	240	int arcompact_handle00_dasm(DASM_OPS_32)
199	241	{
200		int size = 2;
	242	if (op & 0x00010000)
	243	{ // Branch Unconditionally Far
	244	// 00000 ssssssssss 1  SSSSSSSSSS N R TTTT
	245	INT32 address =   (op & 0x07fe0000) >> 17;
	246	address |=        ((op & 0x0000ffc0) >> 6) << 10;
	247	address |=        ((op & 0x0000000f) >> 0) << 20;
	248	if (address & 0x800000) address = -(address&0x7fffff);
201	249
202		UINT32 op = oprom[2] | (oprom[3] << 8);
203		output = buffer;
	250	print("B %08x (%08x)",  pc + (address *2) + 2, op & ~0xffffffcf );
	251	}
	252	else
	253	{ // Branch Conditionally
	254	// 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ
	255	INT32 address =   (op & 0x07fe0000) >> 17;
	256	address |=        ((op & 0x0000ffc0) >> 6) << 10;
	257	if (address & 0x800000) address = -(address&0x7fffff);
204	258
205		UINT8 instruction = ARCOMPACT_OPERATION;
	259	UINT8 condition = op & 0x0000001f;
206	260
207		if (instruction < 0x0c)
	261	print("B(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 2, op & ~0xffffffdf );
	262	}
	263	return 4;
	264	}
	265
	266	int arcompact_handle01_dasm(DASM_OPS_32)
	267	{
	268	if (op & 0x00010000)
208	269	{
209		size = 4;
210		op <<= 16;
211		op |= oprom[0] | (oprom[1] << 8);
	270	if (op & 0x00000010)
	271	{ // Branch on Compare / Bit Test - Register-Immediate
	272	// 00001 bbb sssssss 1 S BBB UUUUUU N 1 iiii
	273	UINT8 subinstr = op & 0x0000000f;
	274	INT32 address =    (op & 0x00fe0000) >> 17;
	275	address |=        ((op & 0x00008000) >> 15) << 7;
	276	if (address & 0x80) address = -(address&0x7f);
212	277
213		switch (instruction)
	278
	279	print("%s (reg-imm) %08x (%08x)", table01_01_0x[subinstr], pc + (address *2) + 4, op & ~0xf8fe800f);
	280
	281
	282	}
	283	else
214	284	{
215		case 0x00:
216		if (op & 0x00010000)
217		{ // Branch Unconditionally Far
218		// 00000 ssssssssss 1  SSSSSSSSSS N R TTTT
219		INT32 address =   (op & 0x07fe0000) >> 17;
220		address |=        ((op & 0x0000ffc0) >> 6) << 10;
221		address |=        ((op & 0x0000000f) >> 0) << 20;
222		if (address & 0x800000) address = -(address&0x7fffff);
	285	// Branch on Compare / Bit Test - Register-Register
	286	// 00001 bbb sssssss 1 S BBB CCCCCC N 0 iiii
	287	UINT8 subinstr = op & 0x0000000f;
	288	INT32 address =    (op & 0x00fe0000) >> 17;
	289	address |=        ((op & 0x00008000) >> 15) << 7;
	290	if (address & 0x80) address = -(address&0x7f);
223	291
224		print("B %08x (%08x)",  pc + (address *2) + 2, op & ~0xffffffcf );
225		}
226		else
227		{ // Branch Conditionally
228		// 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ
229		INT32 address =   (op & 0x07fe0000) >> 17;
230		address |=        ((op & 0x0000ffc0) >> 6) << 10;
231		if (address & 0x800000) address = -(address&0x7fffff);
	292	print("%s (reg-reg) %08x (%08x)", table01_01_0x[subinstr], pc + (address *2) + 4, op & ~0xf8fe800f);
232	293
233		UINT8 condition = op & 0x0000001f;
	294	}
234	295
235		print("B(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 2, op & ~0xffffffdf );
	296	}
	297	else
	298	{
	299	if (op & 0x00020000)
	300	{ // Branch and Link Unconditionally Far
	301	// 00001 sssssssss 10  SSSSSSSSSS N R TTTT
	302	INT32 address =   (op & 0x07fc0000) >> 17;
	303	address |=        ((op & 0x0000ffc0) >> 6) << 10;
	304	address |=        ((op & 0x0000000f) >> 0) << 20;
	305	if (address & 0x800000) address = -(address&0x7fffff);
236	306
237		}
	307	print("BL %08x (%08x)",  pc + (address *2) + 2, op & ~0xffffffcf );
	308	}
	309	else
	310	{ // Branch and Link Conditionally
	311	// 00001 sssssssss 00 SSSSSSSSSS N QQQQQ
	312	INT32 address =   (op & 0x07fc0000) >> 17;
	313	address |=        ((op & 0x0000ffc0) >> 6) << 10;
	314	if (address & 0x800000) address = -(address&0x7fffff);
238	315
239		break;
	316	UINT8 condition = op & 0x0000001f;
240	317
241		case 0x01:
242		if (op & 0x00010000)
243		{
244		if (op & 0x00000010)
245		{ // Branch on Compare / Bit Test - Register-Immediate
246		// 00001 bbb sssssss 1 S BBB UUUUUU N 1 iiii
247		UINT8 subinstr = op & 0x0000000f;
248		INT32 address =    (op & 0x00fe0000) >> 17;
249		address |=        ((op & 0x00008000) >> 15) << 7;
250		if (address & 0x80) address = -(address&0x7f);
	318	print("BL(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 2, op & ~0xffffffdf );
251	319
252
253		print("%s (reg-imm) %08x (%08x)", table01_01_0x[subinstr], pc + (address *2) + 4, op & ~0xf8fe800f);
	320	}
254	321
	322	}
	323	return 4;
	324	}
255	325
256		}
257		else
258		{
259		// Branch on Compare / Bit Test - Register-Register
260		// 00001 bbb sssssss 1 S BBB CCCCCC N 0 iiii
261		UINT8 subinstr = op & 0x0000000f;
262		INT32 address =    (op & 0x00fe0000) >> 17;
263		address |=        ((op & 0x00008000) >> 15) << 7;
264		if (address & 0x80) address = -(address&0x7f);
	326	int arcompact_handle02_dasm(DASM_OPS_32)
	327	{
	328	print("LD r+o (%08x)", op );
	329	return 4;
	330	}
265	331
266		print("%s (reg-reg) %08x (%08x)", table01_01_0x[subinstr], pc + (address *2) + 4, op & ~0xf8fe800f);
	332	int arcompact_handle03_dasm(DASM_OPS_32)
	333	{
	334	print("ST r+o (%08x)", op );
	335	return 4;
	336	}
267	337
268		}
	338	int arcompact_handle04_dasm(DASM_OPS_32)
	339	{
	340	print("op a,b,c (basecase) (%08x)", op );
	341	return 4;
	342	}
269	343
270		}
271		else
272		{
273		if (op & 0x00020000)
274		{ // Branch and Link Unconditionally Far
275		// 00001 sssssssss 10  SSSSSSSSSS N R TTTT
276		INT32 address =   (op & 0x07fc0000) >> 17;
277		address |=        ((op & 0x0000ffc0) >> 6) << 10;
278		address |=        ((op & 0x0000000f) >> 0) << 20;
279		if (address & 0x800000) address = -(address&0x7fffff);
	344	int arcompact_handle05_dasm(DASM_OPS_32)
	345	{
	346	print("op a,b,c (05 ARC ext) (%08x)", op );
	347	return 4;
	348	}
280	349
281		print("BL %08x (%08x)",  pc + (address *2) + 2, op & ~0xffffffcf );
282		}
283		else
284		{ // Branch and Link Conditionally
285		// 00001 sssssssss 00 SSSSSSSSSS N QQQQQ
286		INT32 address =   (op & 0x07fc0000) >> 17;
287		address |=        ((op & 0x0000ffc0) >> 6) << 10;
288		if (address & 0x800000) address = -(address&0x7fffff);
	350	int arcompact_handle06_dasm(DASM_OPS_32)
	351	{
	352	print("op a,b,c (06 ARC ext) (%08x)", op );
	353	return 4;
	354	}
289	355
290		UINT8 condition = op & 0x0000001f;
	356	int arcompact_handle07_dasm(DASM_OPS_32)
	357	{
	358	print("op a,b,c (07 User ext) (%08x)", op );
	359	return 4;
	360	}
291	361
292		print("BL(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 2, op & ~0xffffffdf );
	362	int arcompact_handle08_dasm(DASM_OPS_32)
	363	{
	364	print("op a,b,c (08 User ext) (%08x)", op );
	365	return 4;
	366	}
293	367
294		}
	368	int arcompact_handle09_dasm(DASM_OPS_32)
	369	{
	370	print("op a,b,c (09 Market ext) (%08x)", op );
	371	return 4;
	372	}
295	373
296		}
297		break;
	374	int arcompact_handle0a_dasm(DASM_OPS_32)
	375	{
	376	print("op a,b,c (0a Market ext) (%08x)",  op );
	377	return 4;
	378	}
298	379
299		default:
300		print("%s (%08x)", basic[instruction], op & ~0xf8000000 );
301		break;
	380	int arcompact_handle0b_dasm(DASM_OPS_32)
	381	{
	382	print("op a,b,c (0b Market ext) (%08x)",  op );
	383	return 4;
	384	}
302	385
303		}
304	386
	387
	388
	389	int arcompact_handle0c_dasm(DASM_OPS_16)
	390	{
	391	print("Load/Add reg-reg (%04x)", op);
	392	return 2;
	393	}
	394
	395	int arcompact_handle0d_dasm(DASM_OPS_16)
	396	{
	397	print("Add/Sub/Shft imm (%04x)", op);
	398	return 2;
	399	}
	400
	401	int arcompact_handle0e_dasm(DASM_OPS_16)
	402	{
	403	print("Mov/Cmp/Add (%04x)", op);
	404	return 2;
	405	}
	406
	407	int arcompact_handle0f_dasm(DASM_OPS_16)
	408	{
	409	// General Register Instructions (16-bit)
	410	// 01111 bbb ccc iiiii
	411	UINT8 subinstr = (op & 0x01f) >> 0;
	412	//print("%s (%04x)", table0f[subinstr], op & ~0xf81f);
305	413
306		}
307		else
308		{
309		size = 2;
	414	switch (subinstr)
	415	{
	416
	417	default:
	418	print("%s (%04x)", table0f[subinstr], op & ~0xf81f);
	419	break;
310	420
311		switch (instruction)
	421	case 0x00:
312	422	{
313		case 0x0f:
	423	// General Operations w/ Register
	424	// 01111 bbb iii 00000
	425	UINT8 subinstr2 = (op & 0x00e0) >> 5;
	426
	427	switch (subinstr2)
314	428	{
315		// General Register Instructions (16-bit)
316		// 01111 bbb ccc iiiii
317		UINT8 subinstr = (op & 0x01f) >> 0;
318		//print("%s (%04x)", table0f[subinstr], op & ~0xf81f);
	429	default:
	430	print("%s (%04x)", table0f_00[subinstr2], op & ~0xf8ff);
	431	return 2;
319	432
320		#if 1
321		switch (subinstr)
	433	case 0x7:
322	434	{
	435	// General Operations w/o Register
	436	// 01111 iii 111 00000
	437	UINT8 subinstr3 = (op & 0x0700) >> 8;
	438
	439	print("%s (%04x)", table0f_00_07[subinstr3], op & ~0xffff);
	440
	441	return 2;
	442	}
	443	}
	444	}
	445	}
323	446
324		default:
325		print("%s (%04x)", table0f[subinstr], op & ~0xf81f);
326		break;
	447	return 2;
	448	}
327	449
328		case 0x00:
329		{
330		// General Operations w/ Register
331		// 01111 bbb iii 00000
332		UINT8 subinstr2 = (op & 0x00e0) >> 5;
	450	int arcompact_handle10_dasm(DASM_OPS_16)
	451	{
	452	print("LD_S (%04x)",  op);
	453	return 2;
	454	}
333	455
334		switch (subinstr2)
335		{
336		default:
337		print("%s (%04x)", table0f_00[subinstr2], op & ~0xf8ff);
338		break;
	456	int arcompact_handle11_dasm(DASM_OPS_16)
	457	{
	458	print("LDB_S (%04x)", op);
	459	return 2;
	460	}
339	461
340		case 0x7:
341		{
342		// General Operations w/o Register
343		// 01111 iii 111 00000
344		UINT8 subinstr3 = (op & 0x0700) >> 8;
	462	int arcompact_handle12_dasm(DASM_OPS_16)
	463	{
	464	print("LDW_S (%04x)", op);
	465	return 2;
	466	}
345	467
346		print("%s (%04x)", table0f_00_07[subinstr3], op & ~0xffff);
	468	int arcompact_handle13_dasm(DASM_OPS_16)
	469	{
	470	print("LSW_S.X (%04x)", op);
	471	return 2;
	472	}
347	473
348		break;
349		}
350		}
351		}
352		}
353		#endif
354
355		break;
	474	int arcompact_handle14_dasm(DASM_OPS_16)
	475	{
	476	print("ST_S (%04x)", op);
	477	return 2;
	478	}
356	479
357		}
	480	int arcompact_handle15_dasm(DASM_OPS_16)
	481	{
	482	print("STB_S (%04x)", op);
	483	return 2;
	484	}
358	485
	486	int arcompact_handle16_dasm(DASM_OPS_16)
	487	{
	488	print("STW_S (%04x)",  op);
	489	return 2;
	490	}
359	491
360		case 0x18:
361		{
362		// Stack Pointer Based Instructions (16-bit)
363		// 11000 bbb iii uuuuu
364		UINT8 subinstr = (op & 0x00e0) >> 5;
365		print("%s (%04x)", table18[subinstr], op & ~0xf8e0);
366		break;
	492	int arcompact_handle17_dasm(DASM_OPS_16)
	493	{
	494	print("Shift/Sub/Bit (%04x)",  op);
	495	return 2;
	496	}
367	497
368		}
	498	int arcompact_handle18_dasm(DASM_OPS_16)
	499	{
	500	int size = 2;
	501	// Stack Pointer Based Instructions (16-bit)
	502	// 11000 bbb iii uuuuu
	503	UINT8 subinstr = (op & 0x00e0) >> 5;
	504	op &= ~0x00e0;
369	505
370		default:
371		print("%s (%04x)", basic[instruction], op & ~0xf800);
372		break;
	506	switch (subinstr)
	507	{
	508	case 0x00: size = arcompact_handle18_00_dasm(output, pc, op, oprom); break; // LD_S (SP)
	509	case 0x01: size = arcompact_handle18_01_dasm(output, pc, op, oprom); break; // LDB_S (SP)
	510	case 0x02: size = arcompact_handle18_02_dasm(output, pc, op, oprom); break; // ST_S (SP)
	511	case 0x03: size = arcompact_handle18_03_dasm(output, pc, op, oprom); break; // STB_S (SP)
	512	case 0x04: size = arcompact_handle18_04_dasm(output, pc, op, oprom); break; // ADD_S (SP)
	513	case 0x05: size = arcompact_handle18_05_dasm(output, pc, op, oprom); break; // subtable 18_05
	514	case 0x06: size = arcompact_handle18_06_dasm(output, pc, op, oprom); break; // subtable 18_06
	515	case 0x07: size = arcompact_handle18_07_dasm(output, pc, op, oprom); break; // subtable 18_07
	516	}
	517
	518	return size;
	519	}
	520
	521	// op bits remaining for 0x18_xx subgroups 0x071f
	522
	523	int arcompact_handle18_00_dasm(DASM_OPS_16)
	524	{
	525	print("LD_S (SP) (%04x)",  op);
	526	return 2;
	527	}
	528
	529	int arcompact_handle18_01_dasm(DASM_OPS_16)
	530	{
	531	print("LDB_S (SP) (%04x)",  op);
	532	return 2;
	533	}
	534
	535	int arcompact_handle18_02_dasm(DASM_OPS_16)
	536	{
	537	print("ST_S (SP) (%04x)",  op);
	538	return 2;
	539	}
	540
	541	int arcompact_handle18_03_dasm(DASM_OPS_16)
	542	{
	543	print("STB_S (SP) (%04x)",  op);
	544	return 2;
	545	}
	546
	547	int arcompact_handle18_04_dasm(DASM_OPS_16)
	548	{
	549	print("ADD_S (SP) (%04x)",  op);
	550	return 2;
	551	}
	552
	553
	554
	555
	556
	557	int arcompact_handle18_05_dasm(DASM_OPS_16)
	558	{
	559	int size = 2;
	560	UINT8 subinstr2 = (op & 0x0700) >> 8;
	561	op &= ~0x001f;
	562
	563	switch (subinstr2)
	564	{
	565	case 0x00: size = arcompact_handle18_05_00_dasm(output, pc, op, oprom); break; // ADD_S (SP)
	566	case 0x01: size = arcompact_handle18_05_01_dasm(output, pc, op, oprom); break; // SUB_S (SP)
	567	case 0x02: size = arcompact_handle18_05_02_dasm(output, pc, op, oprom); break; // <illegal 0x18_05_02>
	568	case 0x03: size = arcompact_handle18_05_03_dasm(output, pc, op, oprom); break; // <illegal 0x18_05_03>
	569	case 0x04: size = arcompact_handle18_05_04_dasm(output, pc, op, oprom); break; // <illegal 0x18_05_04>
	570	case 0x05: size = arcompact_handle18_05_05_dasm(output, pc, op, oprom); break; // <illegal 0x18_05_05>
	571	case 0x06: size = arcompact_handle18_05_06_dasm(output, pc, op, oprom); break; // <illegal 0x18_05_06>
	572	case 0x07: size = arcompact_handle18_05_07_dasm(output, pc, op, oprom); break; // <illegal 0x18_05_07>
	573	}
	574
	575	return size;
	576	}
	577	// op bits remaining for 0x18_05_xx subgroups 0x001f
	578	int arcompact_handle18_05_00_dasm(DASM_OPS_16)
	579	{
	580	int u = op & 0x001f;
	581	op &= ~0x001f; // all bits now used
	582
	583	print("ADD_S %02x (SP)", u);
	584	return 2;
	585
	586	}
	587
	588	int arcompact_handle18_05_01_dasm(DASM_OPS_16)
	589	{
	590	int u = op & 0x001f;
	591	op &= ~0x001f; // all bits now used
	592
	593	print("SUB_S %02x (SP)", u);
	594	return 2;
	595	}
	596
	597
	598	int arcompact_handle18_05_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_02> (%04x)", op); return 2;}
	599	int arcompact_handle18_05_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_03> (%04x)", op); return 2;}
	600	int arcompact_handle18_05_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_04> (%04x)", op); return 2;}
	601	int arcompact_handle18_05_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_05> (%04x)", op); return 2;}
	602	int arcompact_handle18_05_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_06> (%04x)", op); return 2;}
	603	int arcompact_handle18_05_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_05_07> (%04x)", op); return 2;}
	604
	605
	606	int arcompact_handle18_06_dasm(DASM_OPS_16)
	607	{
	608	int size = 2;
	609	UINT8 subinstr2 = (op & 0x001f) >> 0;
	610	op &= ~0x001f;
	611
	612	switch (subinstr2)
	613	{
	614	case 0x00: size = arcompact_handle18_06_00_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_00>
	615	case 0x01: size = arcompact_handle18_06_01_dasm(output, pc, op, oprom); break; // POP_S b
	616	case 0x02: size = arcompact_handle18_06_02_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_02>
	617	case 0x03: size = arcompact_handle18_06_03_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_03>
	618	case 0x04: size = arcompact_handle18_06_04_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_04>
	619	case 0x05: size = arcompact_handle18_06_05_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_05>
	620	case 0x06: size = arcompact_handle18_06_06_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_06>
	621	case 0x07: size = arcompact_handle18_06_07_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_07>
	622	case 0x08: size = arcompact_handle18_06_08_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_08>
	623	case 0x09: size = arcompact_handle18_06_09_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_09>
	624	case 0x0a: size = arcompact_handle18_06_0a_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_0a>
	625	case 0x0b: size = arcompact_handle18_06_0b_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_0b>
	626	case 0x0c: size = arcompact_handle18_06_0c_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_0c>
	627	case 0x0d: size = arcompact_handle18_06_0d_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_0d>
	628	case 0x0e: size = arcompact_handle18_06_0e_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_0e>
	629	case 0x0f: size = arcompact_handle18_06_0f_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_0f>
	630	case 0x10: size = arcompact_handle18_06_10_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_10>
	631	case 0x11: size = arcompact_handle18_06_11_dasm(output, pc, op, oprom); break; // POP_S blink
	632	case 0x12: size = arcompact_handle18_06_12_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_12>
	633	case 0x13: size = arcompact_handle18_06_13_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_13>
	634	case 0x14: size = arcompact_handle18_06_14_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_14>
	635	case 0x15: size = arcompact_handle18_06_15_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_15>
	636	case 0x16: size = arcompact_handle18_06_16_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_16>
	637	case 0x17: size = arcompact_handle18_06_17_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_17>
	638	case 0x18: size = arcompact_handle18_06_18_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_18>
	639	case 0x19: size = arcompact_handle18_06_19_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_19>
	640	case 0x1a: size = arcompact_handle18_06_1a_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_1a>
	641	case 0x1b: size = arcompact_handle18_06_1b_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_1b>
	642	case 0x1c: size = arcompact_handle18_06_1c_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_1c>
	643	case 0x1d: size = arcompact_handle18_06_1d_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_1d>
	644	case 0x1e: size = arcompact_handle18_06_1e_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_1e>
	645	case 0x1f: size = arcompact_handle18_06_1f_dasm(output, pc, op, oprom); break; // <illegal 0x18_06_1f>
	646	}
	647
	648	return size;
	649	}
	650
	651
	652	// op bits remaining for 0x18_06_xx subgroups 0x0700
	653	int arcompact_handle18_06_00_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_00> (%04x)",  op); return 2;}
	654
	655	int arcompact_handle18_06_01_dasm(DASM_OPS_16)
	656	{
	657	int b = (op & 0x0700) >> 8;
	658	op &= ~0x0700; // all bits now used
	659
	660	print("POP_S [%02x]", b);
	661
	662	return 2;
	663	}
	664
	665	int arcompact_handle18_06_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_02> (%04x)", op); return 2;}
	666	int arcompact_handle18_06_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_03> (%04x)", op); return 2;}
	667	int arcompact_handle18_06_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_04> (%04x)", op); return 2;}
	668	int arcompact_handle18_06_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_05> (%04x)", op); return 2;}
	669	int arcompact_handle18_06_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_06> (%04x)", op); return 2;}
	670	int arcompact_handle18_06_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_07> (%04x)", op); return 2;}
	671	int arcompact_handle18_06_08_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_08> (%04x)", op); return 2;}
	672	int arcompact_handle18_06_09_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_09> (%04x)", op); return 2;}
	673	int arcompact_handle18_06_0a_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0a> (%04x)", op); return 2;}
	674	int arcompact_handle18_06_0b_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0b> (%04x)", op); return 2;}
	675	int arcompact_handle18_06_0c_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0c> (%04x)", op); return 2;}
	676	int arcompact_handle18_06_0d_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0d> (%04x)", op); return 2;}
	677	int arcompact_handle18_06_0e_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0e> (%04x)", op); return 2;}
	678	int arcompact_handle18_06_0f_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_0f> (%04x)", op); return 2;}
	679	int arcompact_handle18_06_10_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_10> (%04x)", op); return 2;}
	680
	681	int arcompact_handle18_06_11_dasm(DASM_OPS_16)
	682	{
	683	int res = (op & 0x0700) >> 8;
	684	op &= ~0x0700; // all bits now used
	685
	686	if (res)
	687	print("POP_S [BLINK] (Reserved Bits set %04x)", op);
	688	else
	689	print("POP_S [BLINK]");
	690
	691	return 2;
	692	}
	693
	694	int arcompact_handle18_06_12_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_12> (%04x)",  op); return 2;}
	695	int arcompact_handle18_06_13_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_13> (%04x)",  op); return 2;}
	696	int arcompact_handle18_06_14_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_14> (%04x)",  op); return 2;}
	697	int arcompact_handle18_06_15_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_15> (%04x)",  op); return 2;}
	698	int arcompact_handle18_06_16_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_16> (%04x)",  op); return 2;}
	699	int arcompact_handle18_06_17_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_17> (%04x)",  op); return 2;}
	700	int arcompact_handle18_06_18_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_18> (%04x)",  op); return 2;}
	701	int arcompact_handle18_06_19_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_19> (%04x)",  op); return 2;}
	702	int arcompact_handle18_06_1a_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1a> (%04x)",  op); return 2;}
	703	int arcompact_handle18_06_1b_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1b> (%04x)",  op); return 2;}
	704	int arcompact_handle18_06_1c_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1c> (%04x)",  op); return 2;}
	705	int arcompact_handle18_06_1d_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1d> (%04x)",  op); return 2;}
	706	int arcompact_handle18_06_1e_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1e> (%04x)",  op); return 2;}
	707	int arcompact_handle18_06_1f_dasm(DASM_OPS_16)  { print("<illegal 0x18_06_1f> (%04x)",  op); return 2;}
	708
	709
	710
	711
	712	int arcompact_handle18_07_dasm(DASM_OPS_16)
	713	{
	714	int size = 2;
	715	UINT8 subinstr2 = (op & 0x001f) >> 0;
	716	op &= ~0x001f;
	717
	718	switch (subinstr2)
	719	{
	720	case 0x00: size = arcompact_handle18_07_00_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_00>
	721	case 0x01: size = arcompact_handle18_07_01_dasm(output, pc, op, oprom); break; // PUSH_S b
	722	case 0x02: size = arcompact_handle18_07_02_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_02>
	723	case 0x03: size = arcompact_handle18_07_03_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_03>
	724	case 0x04: size = arcompact_handle18_07_04_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_04>
	725	case 0x05: size = arcompact_handle18_07_05_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_05>
	726	case 0x06: size = arcompact_handle18_07_06_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_06>
	727	case 0x07: size = arcompact_handle18_07_07_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_07>
	728	case 0x08: size = arcompact_handle18_07_08_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_08>
	729	case 0x09: size = arcompact_handle18_07_09_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_09>
	730	case 0x0a: size = arcompact_handle18_07_0a_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_0a>
	731	case 0x0b: size = arcompact_handle18_07_0b_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_0b>
	732	case 0x0c: size = arcompact_handle18_07_0c_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_0c>
	733	case 0x0d: size = arcompact_handle18_07_0d_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_0d>
	734	case 0x0e: size = arcompact_handle18_07_0e_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_0e>
	735	case 0x0f: size = arcompact_handle18_07_0f_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_0f>
	736	case 0x10: size = arcompact_handle18_07_10_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_10>
	737	case 0x11: size = arcompact_handle18_07_11_dasm(output, pc, op, oprom); break; // PUSH_S blink
	738	case 0x12: size = arcompact_handle18_07_12_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_12>
	739	case 0x13: size = arcompact_handle18_07_13_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_13>
	740	case 0x14: size = arcompact_handle18_07_14_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_14>
	741	case 0x15: size = arcompact_handle18_07_15_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_15>
	742	case 0x16: size = arcompact_handle18_07_16_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_16>
	743	case 0x17: size = arcompact_handle18_07_17_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_17>
	744	case 0x18: size = arcompact_handle18_07_18_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_18>
	745	case 0x19: size = arcompact_handle18_07_19_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_19>
	746	case 0x1a: size = arcompact_handle18_07_1a_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_1a>
	747	case 0x1b: size = arcompact_handle18_07_1b_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_1b>
	748	case 0x1c: size = arcompact_handle18_07_1c_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_1c>
	749	case 0x1d: size = arcompact_handle18_07_1d_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_1d>
	750	case 0x1e: size = arcompact_handle18_07_1e_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_1e>
	751	case 0x1f: size = arcompact_handle18_07_1f_dasm(output, pc, op, oprom); break; // <illegal 0x18_07_1f>
	752	}
	753
	754	return size;
	755	}
	756
	757
	758	// op bits remaining for 0x18_07_xx subgroups 0x0700
	759	int arcompact_handle18_07_00_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_00> (%04x)",  op); return 2;}
	760
	761	int arcompact_handle18_07_01_dasm(DASM_OPS_16)
	762	{
	763	int b = (op & 0x0700) >> 8;
	764	op &= ~0x0700; // all bits now used
	765
	766	print("PUSH_S [%02x]", b);
	767
	768	return 2;
	769	}
	770
	771	int arcompact_handle18_07_02_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_02> (%04x)", op); return 2;}
	772	int arcompact_handle18_07_03_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_03> (%04x)", op); return 2;}
	773	int arcompact_handle18_07_04_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_04> (%04x)", op); return 2;}
	774	int arcompact_handle18_07_05_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_05> (%04x)", op); return 2;}
	775	int arcompact_handle18_07_06_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_06> (%04x)", op); return 2;}
	776	int arcompact_handle18_07_07_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_07> (%04x)", op); return 2;}
	777	int arcompact_handle18_07_08_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_08> (%04x)", op); return 2;}
	778	int arcompact_handle18_07_09_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_09> (%04x)", op); return 2;}
	779	int arcompact_handle18_07_0a_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0a> (%04x)", op); return 2;}
	780	int arcompact_handle18_07_0b_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0b> (%04x)", op); return 2;}
	781	int arcompact_handle18_07_0c_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0c> (%04x)", op); return 2;}
	782	int arcompact_handle18_07_0d_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0d> (%04x)", op); return 2;}
	783	int arcompact_handle18_07_0e_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0e> (%04x)", op); return 2;}
	784	int arcompact_handle18_07_0f_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_0f> (%04x)", op); return 2;}
	785	int arcompact_handle18_07_10_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_10> (%04x)", op); return 2;}
	786
	787	int arcompact_handle18_07_11_dasm(DASM_OPS_16)
	788	{
	789	int res = (op & 0x0700) >> 8;
	790	op &= ~0x0700; // all bits now used
	791
	792	if (res)
	793	print("PUSH_S [BLINK] (Reserved Bits set %04x)", op);
	794	else
	795	print("PUSH_S [BLINK]");
	796
	797	return 2;
	798	}
	799
	800	int arcompact_handle18_07_12_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_12> (%04x)",  op); return 2;}
	801	int arcompact_handle18_07_13_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_13> (%04x)",  op); return 2;}
	802	int arcompact_handle18_07_14_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_14> (%04x)",  op); return 2;}
	803	int arcompact_handle18_07_15_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_15> (%04x)",  op); return 2;}
	804	int arcompact_handle18_07_16_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_16> (%04x)",  op); return 2;}
	805	int arcompact_handle18_07_17_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_17> (%04x)",  op); return 2;}
	806	int arcompact_handle18_07_18_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_18> (%04x)",  op); return 2;}
	807	int arcompact_handle18_07_19_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_19> (%04x)",  op); return 2;}
	808	int arcompact_handle18_07_1a_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1a> (%04x)",  op); return 2;}
	809	int arcompact_handle18_07_1b_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1b> (%04x)",  op); return 2;}
	810	int arcompact_handle18_07_1c_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1c> (%04x)",  op); return 2;}
	811	int arcompact_handle18_07_1d_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1d> (%04x)",  op); return 2;}
	812	int arcompact_handle18_07_1e_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1e> (%04x)",  op); return 2;}
	813	int arcompact_handle18_07_1f_dasm(DASM_OPS_16)  { print("<illegal 0x18_07_1f> (%04x)",  op); return 2;}
	814
	815
	816	int arcompact_handle19_dasm(DASM_OPS_16)
	817	{
	818	print("GP Instr (%04x)",  op);
	819	return 2;
	820	}
	821
	822
	823	int arcompact_handle1a_dasm(DASM_OPS_16)
	824	{
	825	print("PCL Instr (%04x)", op);
	826	return 2;
	827	}
	828
	829	int arcompact_handle1b_dasm(DASM_OPS_16)
	830	{
	831	print("MOV_S (%04x)", op);
	832	return 2;
	833	}
	834
	835	int arcompact_handle1c_dasm(DASM_OPS_16)
	836	{
	837	print("ADD_S/CMP_S (%04x)", op);
	838	return 2;
	839	}
	840
	841	int arcompact_handle1d_dasm(DASM_OPS_16)
	842	{
	843	print("BRcc_S (%04x)", op);
	844	return 2;
	845	}
	846
	847	int arcompact_handle1e_dasm(DASM_OPS_16)
	848	{
	849	print("Bcc_S (%04x)", op);
	850	return 2;
	851	}
	852
	853	int arcompact_handle1f_dasm(DASM_OPS_16)
	854	{
	855	print("BL_S (%04x)", op);
	856	return 2;
	857	}
	858
	859	CPU_DISASSEMBLE(arcompact)
	860	{
	861	int size = 2;
	862
	863	UINT32 op = oprom[2] | (oprom[3] << 8);
	864	output = buffer;
	865
	866	UINT8 instruction = ARCOMPACT_OPERATION;
	867
	868	if (instruction < 0x0c)
	869	{
	870	size = 4;
	871	op <<= 16;
	872	op |= oprom[0] | (oprom[1] << 8);
	873
	874	op &= ~0xf8000000;
	875
	876	switch (instruction) // 32-bit instructions (with optional extra dword for immediate data)
	877	{
	878	case 0x00: size = arcompact_handle00_dasm(output, pc, op, oprom);   break; // Bcc
	879	case 0x01: size = arcompact_handle01_dasm(output, pc, op, oprom);   break; // BLcc/BRcc
	880	case 0x02: size = arcompact_handle02_dasm(output, pc, op, oprom);   break; // LD r+o
	881	case 0x03: size = arcompact_handle03_dasm(output, pc, op, oprom);   break; // ST r+o
	882	case 0x04: size = arcompact_handle04_dasm(output, pc, op, oprom);   break; // op a,b,c (basecase)
	883	case 0x05: size = arcompact_handle05_dasm(output, pc, op, oprom);   break; // op a,b,c (05 ARC ext)
	884	case 0x06: size = arcompact_handle06_dasm(output, pc, op, oprom);   break; // op a,b,c (06 ARC ext)
	885	case 0x07: size = arcompact_handle07_dasm(output, pc, op, oprom);   break; // op a,b,c (07 User ext)
	886	case 0x08: size = arcompact_handle08_dasm(output, pc, op, oprom);   break; // op a,b,c (08 User ext)
	887	case 0x09: size = arcompact_handle09_dasm(output, pc, op, oprom);   break; // op a,b,c (09 Market ext)
	888	case 0x0a: size = arcompact_handle0a_dasm(output, pc, op, oprom);   break; // op a,b,c (0a Market ext)
	889	case 0x0b: size = arcompact_handle0b_dasm(output, pc, op, oprom);   break; // op a,b,c (0b Market ext)
373	890	}
374	891	}
	892	else
	893	{
	894	size = 2;
	895	op &= ~0xf800;
375	896
376	897
	898	switch (instruction) // 16-bit instructions
	899	{
	900	case 0x0c: size = arcompact_handle0c_dasm(output, pc, op, oprom);   break; // Load/Add reg-reg
	901	case 0x0d: size = arcompact_handle0d_dasm(output, pc, op, oprom);   break; // Add/Sub/Shft imm
	902	case 0x0e: size = arcompact_handle0e_dasm(output, pc, op, oprom);   break; // Mov/Cmp/Add
	903	case 0x0f: size = arcompact_handle0f_dasm(output, pc, op, oprom);   break; // op_S b,b,c (single 16-bit ops)
	904	case 0x10: size = arcompact_handle10_dasm(output, pc, op, oprom);   break; // LD_S
	905	case 0x11: size = arcompact_handle11_dasm(output, pc, op, oprom);   break; // LDB_S
	906	case 0x12: size = arcompact_handle12_dasm(output, pc, op, oprom);   break; // LDW_S
	907	case 0x13: size = arcompact_handle13_dasm(output, pc, op, oprom);   break; // LSW_S.X
	908	case 0x14: size = arcompact_handle14_dasm(output, pc, op, oprom);   break; // ST_S
	909	case 0x15: size = arcompact_handle15_dasm(output, pc, op, oprom);   break; // STB_S
	910	case 0x16: size = arcompact_handle16_dasm(output, pc, op, oprom);   break; // STW_S
	911	case 0x17: size = arcompact_handle17_dasm(output, pc, op, oprom);   break; // Shift/Sub/Bit
	912	case 0x18: size = arcompact_handle18_dasm(output, pc, op, oprom);   break; // Stack Instr
	913	case 0x19: size = arcompact_handle19_dasm(output, pc, op, oprom);   break; // GP Instr
	914	case 0x1a: size = arcompact_handle1a_dasm(output, pc, op, oprom);   break; // PCL Instr
	915	case 0x1b: size = arcompact_handle1b_dasm(output, pc, op, oprom);   break; // MOV_S
	916	case 0x1c: size = arcompact_handle1c_dasm(output, pc, op, oprom);   break; // ADD_S/CMP_S
	917	case 0x1d: size = arcompact_handle1d_dasm(output, pc, op, oprom);   break; // BRcc_S
	918	case 0x1e: size = arcompact_handle1e_dasm(output, pc, op, oprom);   break; // Bcc_S
	919	case 0x1f: size = arcompact_handle1f_dasm(output, pc, op, oprom);   break; // BL_S
	920	}
	921	}
	922
377	923	return size | DASMFLAG_SUPPORTED;
378	924	}

https://github.com/mamedev/mame/commit/4f399fb83031929a8d0d8bcf4752a2f37962ef68

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team