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r33736 Sunday 7th December, 2014 at 22:57:35 UTC by Jonathan Gevaryahu
MESS: Prose2k WIP (n/w)
[src/emu/machine]i6300esb.c i6300esb.h lpc-pit.c lpc-pit.h machine.mak pci.c pci.h
[src/mame/drivers]lindbergh.c
[src/mess/drivers]tsispch.c
[src/mess/includes]tsispch.h

trunk/src/emu/machine/i6300esb.c
r242247r242248
8383   AM_RANGE(0x00ec, 0x00ef) AM_WRITE8(                           nop_w,             0x0000ff00) // Non-existing, used for delays by the bios/os
8484ADDRESS_MAP_END
8585
86   
86
8787i6300esb_lpc_device::i6300esb_lpc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
8888   : pci_device(mconfig, I6300ESB_LPC, "i6300ESB southbridge ISA/LPC bridge", tag, owner, clock, "i6300esb_lpc", __FILE__),
89     acpi(*this, "acpi"),
90     rtc (*this, "rtc"),
91     pit (*this, "pit")
89      acpi(*this, "acpi"),
90      rtc (*this, "rtc")
9291{
9392}
9493
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750749   rtc->map_device(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
751750   if(rtc_conf & 4)
752751      rtc->map_extdevice(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
753   pit->map_device(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
754752}
trunk/src/emu/machine/i6300esb.h
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66#include "pci.h"
77#include "lpc-acpi.h"
88#include "lpc-rtc.h"
9#include "lpc-pit.h"
109
1110#define MCFG_I6300ESB_LPC_ADD(_tag) \
1211   MCFG_PCI_DEVICE_ADD(_tag, I6300ESB_LPC, 0x808625a1, 0x02, 0x060100, 0x00000000)
r242247r242248
3231private:
3332   required_device<lpc_acpi_device> acpi;
3433   required_device<lpc_rtc_device> rtc;
35   required_device<lpc_pit_device> pit;
3634
3735   DECLARE_ADDRESS_MAP(internal_io_map, 32);
3836
trunk/src/emu/machine/lpc-pit.c
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1#include "lpc-pit.h"
2
3const device_type LPC_PIT = &device_creator<lpc_pit_device>;
4
5DEVICE_ADDRESS_MAP_START(map, 32, lpc_pit_device)
6   AM_RANGE(0x40, 0x43) AM_READWRITE8(status_r, access_w,  0x00ffffff)
7   AM_RANGE(0x40, 0x43) AM_WRITE8    (          control_w, 0xff000000)
8   AM_RANGE(0x50, 0x53) AM_READWRITE8(status_r, access_w,  0x00ffffff)
9   AM_RANGE(0x50, 0x53) AM_WRITE8    (          control_w, 0xff000000)
10ADDRESS_MAP_END
11
12lpc_pit_device::lpc_pit_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
13   : lpc_device(mconfig, LPC_PIT, "LPC PIT", tag, owner, clock, "lpc_pit", __FILE__)
14{
15}
16
17void lpc_pit_device::map_device(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
18                           UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
19{
20   io_space->install_device(io_offset, io_window_end, *this, &lpc_pit_device::map);
21}
22
23void lpc_pit_device::device_start()
24{
25}
26
27void lpc_pit_device::device_reset()
28{
29}
30
31READ8_MEMBER( lpc_pit_device::status_r)
32{
33   logerror("%s: status_r %d\n", tag(), offset);
34   return 0xff;
35}
36
37WRITE8_MEMBER(lpc_pit_device::access_w)
38{
39   logerror("%s: access_w %d, %02x\n", tag(), offset, data);
40}
41
42WRITE8_MEMBER(lpc_pit_device::control_w)
43{
44   logerror("%s: control_w %02x\n", tag(), data);
45}
trunk/src/emu/machine/lpc-pit.h
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1#ifndef LPC_PIT_H
2#define LPC_PIT_H
3
4#include "lpc.h"
5
6#define MCFG_LPC_PIT_ADD(_tag) \
7   MCFG_DEVICE_ADD(_tag, LPC_PIT, 0)
8
9class lpc_pit_device : public lpc_device {
10public:
11   lpc_pit_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
12
13   virtual void map_device(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
14                     UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
15
16   DECLARE_READ8_MEMBER( status_r);
17   DECLARE_WRITE8_MEMBER(access_w);
18   DECLARE_WRITE8_MEMBER(control_w);
19
20protected:
21   void device_start();
22   void device_reset();
23
24private:
25   DECLARE_ADDRESS_MAP(map, 32);
26};
27
28extern const device_type LPC_PIT;
29
30#endif
trunk/src/emu/machine/machine.mak
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12631263MACHINEOBJS += $(MACHINEOBJ)/lpc.o
12641264MACHINEOBJS += $(MACHINEOBJ)/lpc-acpi.o
12651265MACHINEOBJS += $(MACHINEOBJ)/lpc-rtc.o
1266MACHINEOBJS += $(MACHINEOBJ)/lpc-pit.o
12671266endif
12681267
12691268#-------------------------------------------------
trunk/src/emu/machine/pci.c
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44const device_type PCI_BRIDGE = &device_creator<pci_bridge_device>;
55
66DEVICE_ADDRESS_MAP_START(config_map, 32, pci_device)
7   AM_RANGE(0x00, 0x03) AM_READ16     (vendor_r,                                 0x0000ffff)
8   AM_RANGE(0x00, 0x03) AM_READ16     (device_r,                                 0xffff0000)
9   AM_RANGE(0x04, 0x07) AM_READWRITE16(command_r,           command_w,           0x0000ffff)
10   AM_RANGE(0x04, 0x07) AM_READ16     (status_r,                                 0xffff0000)
7   AM_RANGE(0x00, 0x03) AM_READ16     (vendor_r,                          0x0000ffff)
8   AM_RANGE(0x00, 0x03) AM_READ16     (device_r,                          0xffff0000)
9   AM_RANGE(0x04, 0x07) AM_READWRITE16(command_r,         command_w,      0x0000ffff)
10   AM_RANGE(0x04, 0x07) AM_READ16     (status_r,                          0xffff0000)
1111   AM_RANGE(0x08, 0x0b) AM_READ       (class_rev_r)
12   AM_RANGE(0x0c, 0x0f) AM_READ8      (cache_line_size_r,                        0x000000ff)
13   AM_RANGE(0x0c, 0x0f) AM_READ8      (latency_timer_r,                          0x0000ff00)
14   AM_RANGE(0x0c, 0x0f) AM_READ8      (header_type_r,                            0x00ff0000)
15   AM_RANGE(0x0c, 0x0f) AM_READ8      (bist_r,                                   0xff000000)
16   AM_RANGE(0x10, 0x27) AM_READWRITE  (address_base_r,      address_base_w)
12   AM_RANGE(0x0c, 0x0f) AM_READ8      (cache_line_size_r,                 0x000000ff)
13   AM_RANGE(0x0c, 0x0f) AM_READ8      (latency_timer_r,                   0x0000ff00)
14   AM_RANGE(0x0c, 0x0f) AM_READ8      (header_type_r,                     0x00ff0000)
15   AM_RANGE(0x0c, 0x0f) AM_READ8      (bist_r,                            0xff000000)
16   AM_RANGE(0x10, 0x27) AM_READWRITE  (address_base_r,    address_base_w)
1717
18   AM_RANGE(0x2c, 0x2f) AM_READ16     (subvendor_r,                              0x0000ffff)
19   AM_RANGE(0x2c, 0x2f) AM_READ16     (subsystem_r,                              0xffff0000)
18   AM_RANGE(0x2c, 0x2f) AM_READ16     (subvendor_r,                       0x0000ffff)
19   AM_RANGE(0x2c, 0x2f) AM_READ16     (subsystem_r,                       0xffff0000)
2020   AM_RANGE(0x2c, 0x2f) AM_WRITENOP
2121
22   AM_RANGE(0x34, 0x37) AM_READ8      (capptr_r,                                 0x000000ff)
22   AM_RANGE(0x34, 0x37) AM_READ8      (capptr_r,                          0x000000ff)
2323ADDRESS_MAP_END
2424
25DEVICE_ADDRESS_MAP_START(config_map, 32, pci_bridge_device)
26   AM_RANGE(0x00, 0x03) AM_READ16     (vendor_r,                                 0x0000ffff)
27   AM_RANGE(0x00, 0x03) AM_READ16     (device_r,                                 0xffff0000)
28   AM_RANGE(0x04, 0x07) AM_READWRITE16(command_r,           command_w,           0x0000ffff)
29   AM_RANGE(0x04, 0x07) AM_READ16     (status_r,                                 0xffff0000)
30   AM_RANGE(0x08, 0x0b) AM_READ       (class_rev_r)
31   AM_RANGE(0x0c, 0x0f) AM_READ8      (cache_line_size_r,                        0x000000ff)
32   AM_RANGE(0x0c, 0x0f) AM_READ8      (latency_timer_r,                          0x0000ff00)
33   AM_RANGE(0x0c, 0x0f) AM_READ8      (header_type_r,                            0x00ff0000)
34   AM_RANGE(0x0c, 0x0f) AM_READ8      (bist_r,                                   0xff000000)
35   AM_RANGE(0x10, 0x17) AM_READWRITE  (b_address_base_r,    b_address_base_w)
36   AM_RANGE(0x18, 0x1b) AM_READWRITE8 (primary_bus_r,       primary_bus_w,       0x000000ff)
37   AM_RANGE(0x18, 0x1b) AM_READWRITE8 (secondary_bus_r,     secondary_bus_w,     0x0000ff00)
38   AM_RANGE(0x18, 0x1b) AM_READWRITE8 (subordinate_bus_r,   subordinate_bus_w,   0x00ff0000)
39   AM_RANGE(0x18, 0x1b) AM_READWRITE8 (secondary_latency_r, secondary_latency_w, 0xff000000)
40   AM_RANGE(0x1c, 0x1f) AM_READWRITE8 (iobase_r,            iobase_w,            0x000000ff)
41   AM_RANGE(0x1c, 0x1f) AM_READWRITE8 (iolimit_r,           iolimit_w,           0x0000ff00)
42   AM_RANGE(0x1c, 0x1f) AM_READWRITE16(secondary_status_r,  secondary_status_w,  0xffff0000)
43   AM_RANGE(0x20, 0x23) AM_READWRITE16(memory_base_r,       memory_base_w,       0x0000ffff)
44   AM_RANGE(0x20, 0x23) AM_READWRITE16(memory_limit_r,      memory_limit_w,      0xffff0000)
45   AM_RANGE(0x24, 0x27) AM_READWRITE16(prefetch_base_r,     prefetch_base_w,     0x0000ffff)
46   AM_RANGE(0x24, 0x27) AM_READWRITE16(prefetch_limit_r,    prefetch_limit_w,    0xffff0000)
47   AM_RANGE(0x28, 0x2b) AM_READWRITE  (prefetch_baseu_r,    prefetch_baseu_w)
48   AM_RANGE(0x2c, 0x2f) AM_READWRITE  (prefetch_limitu_r,   prefetch_limitu_w)
49   AM_RANGE(0x30, 0x33) AM_READWRITE16(iobaseu_r,           iobaseu_w,           0x0000ffff)
50   AM_RANGE(0x30, 0x33) AM_READWRITE16(iolimitu_r,          iolimitu_w,          0xffff0000)
51   AM_RANGE(0x34, 0x37) AM_READ8      (capptr_r,                                 0x000000ff)
52   AM_RANGE(0x38, 0x3b) AM_READWRITE  (expansion_base_r,    expansion_base_w)
53   AM_RANGE(0x3c, 0x3f) AM_READWRITE8 (interrupt_line_r,    interrupt_line_w,    0x000000ff)
54   AM_RANGE(0x3c, 0x3f) AM_READWRITE8 (interrupt_pin_r,     interrupt_pin_w,     0x0000ff00)
55   AM_RANGE(0x3c, 0x3f) AM_READWRITE16(bridge_control_r,    bridge_control_w,    0xffff0000)
56ADDRESS_MAP_END
57
5825pci_device::pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
5926   : device_t(mconfig, type, name, tag, owner, clock, shortname, source)
6027{
r242247r242248
394361void pci_bridge_device::device_reset()
395362{
396363   pci_device::device_reset();
397
398   bridge_control = 0x0000;
399   primary_bus = 0x00;
400   secondary_bus = 0x00;
401   subordinate_bus = 0x00;
402364   regenerate_config_mapping();
403365}
404366
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409371         all_devices[i]->reset_all_mappings();
410372}
411373
374
412375void pci_bridge_device::map_device(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
413376                           UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
414377{
r242247r242248
431394         sub_devices[i]->map_config(i, config_space);
432395}
433396
434UINT32 pci_bridge_device::do_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
435{
436   if(sub_devices[device]) {
437      UINT32 data = space(AS_PROGRAM).read_dword((device << 12) | reg, mem_mask);
438      logerror("%s: config_read %02x:%02x.%x:%02x %08x @ %08x\n", tag(), bus, device >> 3, device & 7, reg, data, mem_mask);
439      return data;
440   } else
441      return 0xffffffff;
442}
443397
444UINT32 pci_bridge_device::propagate_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
445{
446   UINT32 data = 0xffffffff;
447   for(int i=0; i != all_bridges.count(); i++)
448      data &= all_bridges[i]->config_read(bus, device, reg, mem_mask);
449   return data;
450}
451
452UINT32 pci_bridge_device::config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
453{
454   if(bus == secondary_bus)
455      return do_config_read(bus, device, reg, mem_mask);
456
457   if(bus > secondary_bus && bus <= subordinate_bus)
458      return propagate_config_read(bus, device, reg, mem_mask);
459
460   return 0xffffffff;
461}
462
463void pci_bridge_device::do_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
464{
465   if(sub_devices[device]) {
466      space(AS_PROGRAM).write_dword((device << 12) | reg, data, mem_mask);
467      logerror("%s: config_write %02x:%02x.%x:%02x %08x @ %08x\n", tag(), bus, device >> 3, device & 7, reg, data, mem_mask);
468   }
469}
470
471void pci_bridge_device::propagate_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
472{
473   for(int i=0; i != all_bridges.count(); i++)
474      all_bridges[i]->config_write(bus, device, reg, data, mem_mask);
475}
476
477void pci_bridge_device::config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
478{
479   if(bus == secondary_bus)
480      do_config_write(bus, device, reg, data, mem_mask);
481
482   else if(bus > secondary_bus && bus <= subordinate_bus)
483      propagate_config_write(bus, device, reg, data, mem_mask);
484}
485
486READ32_MEMBER (pci_bridge_device::b_address_base_r)
487{
488   logerror("%s: b_address_base_r %d\n", tag(), offset);
489   return 0xffffffff;
490}
491
492WRITE32_MEMBER(pci_bridge_device::b_address_base_w)
493{
494   logerror("%s: b_address_base_w %d, %08x\n", tag(), offset, data);
495}
496
497READ8_MEMBER  (pci_bridge_device::primary_bus_r)
498{
499   logerror("%s: primary_bus_r\n", tag());
500   return primary_bus;
501}
502
503WRITE8_MEMBER (pci_bridge_device::primary_bus_w)
504{
505   primary_bus = data;
506   logerror("%s: primary_bus_w %02x\n", tag(), data);
507}
508
509READ8_MEMBER  (pci_bridge_device::secondary_bus_r)
510{
511   logerror("%s: secondary_bus_r\n", tag());
512   return secondary_bus;
513}
514
515WRITE8_MEMBER (pci_bridge_device::secondary_bus_w)
516{
517   secondary_bus = data;
518   logerror("%s: secondary_bus_w %02x\n", tag(), data);
519}
520
521READ8_MEMBER  (pci_bridge_device::subordinate_bus_r)
522{
523   logerror("%s: subordinate_bus_r\n", tag());
524   return subordinate_bus;
525}
526
527WRITE8_MEMBER (pci_bridge_device::subordinate_bus_w)
528{
529   subordinate_bus = data;
530   logerror("%s: subordinate_bus_w %02x\n", tag(), data);
531}
532
533READ8_MEMBER  (pci_bridge_device::secondary_latency_r)
534{
535   logerror("%s: secondary_latency_r\n", tag());
536   return 0xff;
537}
538
539WRITE8_MEMBER (pci_bridge_device::secondary_latency_w)
540{
541   logerror("%s: secondary_latency_w %02x\n", tag(), data);
542}
543
544READ8_MEMBER  (pci_bridge_device::iobase_r)
545{
546   logerror("%s: iobase_r\n", tag());
547   return 0xff;
548}
549
550WRITE8_MEMBER (pci_bridge_device::iobase_w)
551{
552   logerror("%s: iobase_w %02x\n", tag(), data);
553}
554
555READ8_MEMBER  (pci_bridge_device::iolimit_r)
556{
557   logerror("%s: iolimit_r\n", tag());
558   return 0xff;
559}
560
561WRITE8_MEMBER (pci_bridge_device::iolimit_w)
562{
563   logerror("%s: iolimit_w %02x\n", tag(), data);
564}
565
566READ16_MEMBER (pci_bridge_device::secondary_status_r)
567{
568   logerror("%s: secondary_status_r\n", tag());
569   return 0xffff;
570}
571
572WRITE16_MEMBER(pci_bridge_device::secondary_status_w)
573{
574   logerror("%s: secondary_status_w %04x\n", tag(), data);
575}
576
577READ16_MEMBER (pci_bridge_device::memory_base_r)
578{
579   logerror("%s: memory_base_r\n", tag());
580   return 0xffff;
581}
582
583WRITE16_MEMBER(pci_bridge_device::memory_base_w)
584{
585   logerror("%s: memory_base_w %04x\n", tag(), data);
586}
587
588READ16_MEMBER (pci_bridge_device::memory_limit_r)
589{
590   logerror("%s: memory_limit_r\n", tag());
591   return 0xffff;
592}
593
594WRITE16_MEMBER(pci_bridge_device::memory_limit_w)
595{
596   logerror("%s: memory_limit_w %04x\n", tag(), data);
597}
598
599READ16_MEMBER (pci_bridge_device::prefetch_base_r)
600{
601   logerror("%s: prefetch_base_r\n", tag());
602   return 0xffff;
603}
604
605WRITE16_MEMBER(pci_bridge_device::prefetch_base_w)
606{
607   logerror("%s: prefetch_base_w %04x\n", tag(), data);
608}
609
610READ16_MEMBER (pci_bridge_device::prefetch_limit_r)
611{
612   logerror("%s: prefetch_limit_r\n", tag());
613   return 0xffff;
614}
615
616WRITE16_MEMBER(pci_bridge_device::prefetch_limit_w)
617{
618   logerror("%s: prefetch_limit_w %04x\n", tag(), data);
619}
620
621READ32_MEMBER (pci_bridge_device::prefetch_baseu_r)
622{
623   logerror("%s: prefetch_baseu_r\n", tag());
624   return 0xffffffff;
625}
626
627WRITE32_MEMBER(pci_bridge_device::prefetch_baseu_w)
628{
629   logerror("%s: prefetch_baseu_w %08x\n", tag(), data);
630}
631
632READ32_MEMBER (pci_bridge_device::prefetch_limitu_r)
633{
634   logerror("%s: prefetch_limitu_r\n", tag());
635   return 0xffffffff;
636}
637
638WRITE32_MEMBER(pci_bridge_device::prefetch_limitu_w)
639{
640   logerror("%s: prefetch_limitu_w %08x\n", tag(), data);
641}
642
643READ16_MEMBER (pci_bridge_device::iobaseu_r)
644{
645   logerror("%s: iobaseu_r\n", tag());
646   return 0xffff;
647}
648
649WRITE16_MEMBER(pci_bridge_device::iobaseu_w)
650{
651   logerror("%s: iobaseu_w %04x\n", tag(), data);
652}
653
654READ16_MEMBER (pci_bridge_device::iolimitu_r)
655{
656   logerror("%s: iolimitu_r\n", tag());
657   return 0xffff;
658}
659
660WRITE16_MEMBER(pci_bridge_device::iolimitu_w)
661{
662   logerror("%s: iolimitu_w %04x\n", tag(), data);
663}
664
665READ32_MEMBER (pci_bridge_device::expansion_base_r)
666{
667   logerror("%s: expansion_base_r\n", tag());
668   return 0xffffffff;
669}
670
671WRITE32_MEMBER(pci_bridge_device::expansion_base_w)
672{
673   logerror("%s: expansion_base_w %08x\n", tag(), data);
674}
675
676READ8_MEMBER  (pci_bridge_device::interrupt_line_r)
677{
678   logerror("%s: interrupt_line_r\n", tag());
679   return 0xff;
680}
681
682WRITE8_MEMBER (pci_bridge_device::interrupt_line_w)
683{
684   logerror("%s: interrupt_line_w %02x\n", tag(), data);
685}
686
687READ8_MEMBER  (pci_bridge_device::interrupt_pin_r)
688{
689   logerror("%s: interrupt_pin_r\n", tag());
690   return 0xff;
691}
692
693WRITE8_MEMBER (pci_bridge_device::interrupt_pin_w)
694{
695   logerror("%s: interrupt_pin_w %02x\n", tag(), data);
696}
697
698READ16_MEMBER (pci_bridge_device::bridge_control_r)
699{
700   logerror("%s: bridge_control_r\n", tag());
701   return bridge_control;
702}
703
704WRITE16_MEMBER(pci_bridge_device::bridge_control_w)
705{
706   COMBINE_DATA(&bridge_control);
707   logerror("%s: bridge_control_w %04x\n", tag(), bridge_control);
708}
709
710
711398agp_bridge_device::agp_bridge_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
712399   : pci_bridge_device(mconfig, type, name, tag, owner, clock, shortname, source)
713400{
r242247r242248
786473
787474READ32_MEMBER(pci_host_device::config_data_r)
788475{
789   return config_address & 0x80000000 ? root_config_read((config_address >> 16) & 0xff, (config_address >> 8) & 0xff, config_address & 0xfc, mem_mask) : 0xffffffff;
476   return config_address & 0x80000000 ? config_read((config_address >> 16) & 0xff, (config_address >> 8) & 0xff, config_address & 0xfc, mem_mask) : 0xffffffff;
790477}
791478
792479WRITE32_MEMBER(pci_host_device::config_data_w)
793480{
794481   if(config_address & 0x80000000)
795      root_config_write((config_address >> 16) & 0xff, (config_address >> 8) & 0xff, config_address & 0xfc, data, mem_mask);
482      config_write((config_address >> 16) & 0xff, (config_address >> 8) & 0xff, config_address & 0xfc, data, mem_mask);
796483}
797484
798UINT32 pci_host_device::root_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
485UINT32 pci_host_device::config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
799486{
800   if(bus == 0x00)
801      return do_config_read(bus, device, reg, mem_mask);
487   UINT32 data = 0xffffffff;
488   if(!bus) {
489      if(sub_devices[device]) {
490         data = space(AS_PROGRAM).read_dword((device << 12) | reg, mem_mask);
491         logerror("config_read %02x:%02x.%x:%02x %08x @ %08x\n", bus, device >> 3, device & 7, reg, data, mem_mask);
492      }
493   } else
494      abort();
802495
803   return propagate_config_read(bus, device, reg, mem_mask);
496   return data;
804497}
805498
806void pci_host_device::root_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
499void pci_host_device::config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
807500{
808   if(bus == 0x00)
809      do_config_write(bus, device, reg, data, mem_mask);
810
811   else
812      propagate_config_write(bus, device, reg, data, mem_mask);
501   if(!bus) {
502      if(sub_devices[device]) {
503         space(AS_PROGRAM).write_dword((device << 12) | reg, data, mem_mask);
504         logerror("config_write %02x:%02x.%x:%02x %08x @ %08x\n", bus, device >> 3, device & 7, reg, data, mem_mask);
505      }
506   } else
507      abort();
813508}
814509
815510
trunk/src/emu/machine/pci.h
r242247r242248
139139
140140   virtual DECLARE_READ8_MEMBER(header_type_r);
141141
142   virtual DECLARE_ADDRESS_MAP(config_map, 32);
143
144   DECLARE_READ32_MEMBER (b_address_base_r);
145   DECLARE_WRITE32_MEMBER(b_address_base_w);
146   DECLARE_READ8_MEMBER  (primary_bus_r);
147   DECLARE_WRITE8_MEMBER (primary_bus_w);
148   DECLARE_READ8_MEMBER  (secondary_bus_r);
149   DECLARE_WRITE8_MEMBER (secondary_bus_w);
150   DECLARE_READ8_MEMBER  (subordinate_bus_r);
151   DECLARE_WRITE8_MEMBER (subordinate_bus_w);
152   DECLARE_READ8_MEMBER  (secondary_latency_r);
153   DECLARE_WRITE8_MEMBER (secondary_latency_w);
154   DECLARE_READ8_MEMBER  (iobase_r);
155   DECLARE_WRITE8_MEMBER (iobase_w);
156   DECLARE_READ8_MEMBER  (iolimit_r);
157   DECLARE_WRITE8_MEMBER (iolimit_w);
158   DECLARE_READ16_MEMBER (secondary_status_r);
159   DECLARE_WRITE16_MEMBER(secondary_status_w);
160   DECLARE_READ16_MEMBER (memory_base_r);
161   DECLARE_WRITE16_MEMBER(memory_base_w);
162   DECLARE_READ16_MEMBER (memory_limit_r);
163   DECLARE_WRITE16_MEMBER(memory_limit_w);
164   DECLARE_READ16_MEMBER (prefetch_base_r);
165   DECLARE_WRITE16_MEMBER(prefetch_base_w);
166   DECLARE_READ16_MEMBER (prefetch_limit_r);
167   DECLARE_WRITE16_MEMBER(prefetch_limit_w);
168   DECLARE_READ32_MEMBER (prefetch_baseu_r);
169   DECLARE_WRITE32_MEMBER(prefetch_baseu_w);
170   DECLARE_READ32_MEMBER (prefetch_limitu_r);
171   DECLARE_WRITE32_MEMBER(prefetch_limitu_w);
172   DECLARE_READ16_MEMBER (iobaseu_r);
173   DECLARE_WRITE16_MEMBER(iobaseu_w);
174   DECLARE_READ16_MEMBER (iolimitu_r);
175   DECLARE_WRITE16_MEMBER(iolimitu_w);
176   DECLARE_READ32_MEMBER (expansion_base_r);
177   DECLARE_WRITE32_MEMBER(expansion_base_w);
178   DECLARE_READ8_MEMBER  (interrupt_line_r);
179   DECLARE_WRITE8_MEMBER (interrupt_line_w);
180   DECLARE_READ8_MEMBER  (interrupt_pin_r);
181   DECLARE_WRITE8_MEMBER (interrupt_pin_w);
182   DECLARE_READ16_MEMBER (bridge_control_r);
183   DECLARE_WRITE16_MEMBER(bridge_control_w);
184
185142protected:
186143   pci_device *sub_devices[32*8];
187144   dynamic_array<pci_device *> all_devices;
188   dynamic_array<pci_bridge_device *> all_bridges;
145   dynamic_array<pci_device *> all_bridges;
189146
190   UINT8 primary_bus, secondary_bus, subordinate_bus;
191   UINT16 bridge_control;
192
193147   virtual void device_start();
194148   virtual void device_reset();
195149   virtual const address_space_config *memory_space_config(address_spacenum spacenum) const;
r242247r242248
197151   virtual device_t *bus_root();
198152   virtual void regenerate_config_mapping();
199153
200   UINT32 do_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
201   UINT32 propagate_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
202   UINT32 config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
203   void do_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
204   void propagate_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
205   void config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
206
207154private:
208155   address_space_config configure_space_config;
209156};
r242247r242248
241188   DECLARE_READ32_MEMBER(config_data_r);
242189   DECLARE_WRITE32_MEMBER(config_data_w);
243190
244   UINT32 root_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
245   void root_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
191   UINT32 config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
192   void config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
246193
247194   void regenerate_mapping();
248195};
trunk/src/mame/drivers/lindbergh.c
r242247r242248
347347}
348348
349349static MACHINE_CONFIG_START(lindbergh, lindbergh_state)
350//  MCFG_CPU_ADD("maincpu", PENTIUM, 2800000000U) /* Actually Celeron D at 2,8 GHz */
350351   MCFG_CPU_ADD("maincpu", PENTIUM4, 28000000U*5) /* Actually Celeron D at 2,8 GHz */
352//  MCFG_CPU_PROGRAM_MAP(lindbergh_map)
353//  MCFG_CPU_IO_MAP(lindbergh_io)
354//  MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_1", pic8259_device, inta_cb)
351355
356//  MCFG_FRAGMENT_ADD( pcat_common )
357//  MCFG_FRAGMENT_ADD( pcvideo_vga )
358
359//  MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
360
352361   MCFG_PCI_ROOT_ADD(                ":pci")
353362   MCFG_I82875P_HOST_ADD(            ":pci:00.0",                        0x103382c0, ":maincpu", 512*1024*1024)
354363   MCFG_I82875P_AGP_ADD(             ":pci:01.0")
r242247r242248
366375   MCFG_I6300ESB_LPC_ADD(            ":pci:1f.0")
367376   MCFG_LPC_ACPI_ADD(                ":pci:1f.0:acpi")
368377   MCFG_LPC_RTC_ADD(                 ":pci:1f.0:rtc")
369   MCFG_LPC_PIT_ADD(                 ":pci:1f.0:pit")
370378   MCFG_SATA_ADD(                    ":pci:1f.2",      0x808625a3, 0x02, 0x103382c0)
371379   MCFG_SMBUS_ADD(                   ":pci:1f.3",      0x808625a4, 0x02, 0x103382c0)
372380   MCFG_AC97_ADD(                    ":pci:1f.5",      0x808625a6, 0x02, 0x103382c0)
trunk/src/mess/drivers/tsispch.c
r242247r242248
157157READ8_MEMBER( tsispch_state::dsw_r )
158158{
159159   /* the only dipswitch I'm really sure about is s4-7 which enables the test mode
160    * The switches are, for normal operation on my unit:
160    * The switches are, for normal operation on my unit (and the older unit as well):
161161    * 1  2  3   4   5   6   7   8
162162    * ON ON OFF OFF OFF OFF OFF OFF
163163    * which makes this register read 0xFC
r242247r242248
227227   upd7725->snesdsp_write(false, data);
228228}
229229
230WRITE_LINE_MEMBER( tsispch_state::dsp_to_8086_p0_w )
231{
232   fprintf(stderr, "upd772x changed p0 state to %d!\n",state);
233   //TODO: do stuff here!
234}
235
236WRITE_LINE_MEMBER( tsispch_state::dsp_to_8086_p1_w )
237{
238   fprintf(stderr, "upd772x changed p1 state to %d!\n",state);
239   //TODO: do stuff here!
240}
241
230242/*****************************************************************************
231243 Reset and Driver Init
232244*****************************************************************************/
233245void tsispch_state::machine_reset()
234246{
235   // clear fifos (TODO: memset would work better here...)
236   int i;
237   for (i=0; i<32; i++) m_infifo[i] = 0;
238   m_infifo_tail_ptr = m_infifo_head_ptr = 0;
239247   fprintf(stderr,"machine reset\n");
240248}
241249
r242247r242248
381389   MCFG_CPU_ADD("dsp", UPD7725, 8000000) /* VERIFIED clock, unknown divider; correct dsp type is UPD77P20 */
382390   MCFG_CPU_PROGRAM_MAP(dsp_prg_map)
383391   MCFG_CPU_DATA_MAP(dsp_data_map)
392   MCFG_NECDSP_OUT_P0_CB(WRITELINE(tsispch_state, dsp_to_8086_p0_w))
393   MCFG_NECDSP_OUT_P1_CB(WRITELINE(tsispch_state, dsp_to_8086_p1_w))
384394
385395   /* PIC 8259 */
386396   MCFG_PIC8259_ADD("pic8259", INPUTLINE("maincpu", 0), VCC, NULL)
r242247r242248
513523   ROMX_LOAD( "v1.1__14__speech__plus__(c)1983.am2764.14.u28", 0xfc000, 0x2000, CRC(E616BD6E) SHA1(5DFAE2C5079D89F791C9D7166F9504231A464203),ROM_SKIP(1))
514524   ROMX_LOAD( "v1.1__15__speech__plus__(c)1983.am2764.15.u51", 0xfc001, 0x2000, CRC(BEB1FA19) SHA1(72130FE45C3FD3DE7CF794936DC68ED2D4193DAF),ROM_SKIP(1))
515525
516   // TSI/Speech plus DSP firmware v?.? (no sticker, but S140025 printed on chip), unlabeled chip, but clearly a NEC UPD77P20C ceramic
517   // NOT DUMPED YET, using the 3.12 dsp firmware as a placeholder
526   // TSI/Speech plus DSP firmware v?.? (no sticker, but S140025 printed on chip), unlabeled chip, but clearly a NEC UPD7720C ceramic
527   // NOT DUMPED YET, using the 3.12 dsp firmware as a placeholder, since the dsp on the older board is MASK ROM and doesn't dump easily
518528   ROM_REGION( 0x600, "dspprgload", 0) // packed 24 bit data
519   ROM_LOAD( "s140025__dsp_prog.u29", 0x0000, 0x0600, BAD_DUMP CRC(9E46425A) SHA1(80A915D731F5B6863AEEB448261149FF15E5B786))
529   ROM_LOAD( "s140025__dsp_prog.u29", 0x0000, 0x0600, NO_DUMP)
530   ROM_LOAD( "v3.12__8-9-88__dsp_prog.u29", 0x0000, 0x0600, CRC(9E46425A) SHA1(80A915D731F5B6863AEEB448261149FF15E5B786)) // temp placeholder
520531   ROM_REGION( 0x800, "dspprg", ROMREGION_ERASEFF) // for unpacking 24 bit data into 32 bit data which cpu core can understand
521532   ROM_REGION( 0x400, "dspdata", 0)
522   ROM_LOAD( "s140025__dsp_data.u29", 0x0000, 0x0400, BAD_DUMP CRC(F4E4DD16) SHA1(6E184747DB2F26E45D0E02907105FF192E51BABA))
533   ROM_LOAD( "s140025__dsp_data.u29", 0x0000, 0x0400, NO_DUMP)
534   ROM_LOAD( "v3.12__8-9-88__dsp_data.u29", 0x0000, 0x0400, CRC(F4E4DD16) SHA1(6E184747DB2F26E45D0E02907105FF192E51BABA)) // temp placeholder
523535
524536   ROM_REGION(0x1000, "proms", 0)
525537   ROM_LOAD( "dm74s288n.u77", 0x0000, 0x0020, CRC(A88757FC) SHA1(9066D6DBC009D7A126D75B8461CA464DDF134412)) // == am27s19.u77
trunk/src/mess/includes/tsispch.h
r242247r242248
3434   required_device<i8251_device> m_uart;
3535   required_device<pic8259_device> m_pic;
3636
37   UINT8 m_infifo[32];         // input fifo
38   UINT8 m_infifo_tail_ptr;        // " tail
39   UINT8 m_infifo_head_ptr;        // " head
4037   UINT8 m_paramReg;           // status leds and resets and etc
4138
4239   virtual void machine_reset();
r242247r242248
5148   DECLARE_WRITE_LINE_MEMBER(i8251_rxrdy_int);
5249   DECLARE_WRITE_LINE_MEMBER(i8251_txempty_int);
5350   DECLARE_WRITE_LINE_MEMBER(i8251_txrdy_int);
51   DECLARE_WRITE_LINE_MEMBER(dsp_to_8086_p0_w);
52   DECLARE_WRITE_LINE_MEMBER(dsp_to_8086_p1_w);
5453};
5554
5655

https://github.com/mamedev/mame/commit/e53aaf8d896d30e713c739fbc550a09650d472d8

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