trunk/src/emu/cpu/arcompact/arcompactdasm.c
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| 133 | 133 | |
| 134 | 134 | }; |
| 135 | 135 | |
| 136 | static const char *table0f[0x20] = |
| 137 | { |
| 138 | /* 00 */ "SOPs", // Sub Operation (another table..) ( table0f_00 ) |
| 139 | /* 01 */ "0x01 <illegal>", |
| 140 | /* 02 */ "SUB_S", |
| 141 | /* 03 */ "0x03 <illegal>", |
| 142 | /* 04 */ "AND_S", |
| 143 | /* 05 */ "OR_S", |
| 144 | /* 06 */ "BIC_S", |
| 145 | /* 07 */ "XOR_S", |
| 146 | /* 08 */ "0x08 <illegal>", |
| 147 | /* 09 */ "0x09 <illegal>", |
| 148 | /* 0a */ "0x0a <illegal>", |
| 149 | /* 0b */ "TST_S", |
| 150 | /* 0c */ "MUL64_S", |
| 151 | /* 0d */ "SEXB_S", |
| 152 | /* 0e */ "SEXW_S", |
| 153 | /* 0f */ "EXTB_S", |
| 154 | /* 10 */ "EXTW_S", |
| 155 | /* 11 */ "ABS_S", |
| 156 | /* 12 */ "NOT_S", |
| 157 | /* 13 */ "NEG_S", |
| 158 | /* 14 */ "ADD1_S", |
| 159 | /* 15 */ "ADD2_S>", |
| 160 | /* 16 */ "ADD3_S", |
| 161 | /* 17 */ "0x17 <illegal>", |
| 162 | /* 18 */ "ASL_S (multiple)", |
| 163 | /* 19 */ "LSR_S (multiple)", |
| 164 | /* 1a */ "ASR_S (multiple)", |
| 165 | /* 1b */ "ASL_S (single)", |
| 166 | /* 1c */ "LSR_S (single)", |
| 167 | /* 1d */ "ASR_S (single)", |
| 168 | /* 1e */ "TRAP (not a5?)", |
| 169 | /* 1f */ "BRK_S" // 0x7fff only? |
| 170 | }; |
| 136 | 171 | |
| 172 | static const char *table0f_00[0x8] = |
| 173 | { |
| 174 | /* 00 */ "J_S", |
| 175 | /* 01 */ "J_S.D", |
| 176 | /* 02 */ "JL_S", |
| 177 | /* 03 */ "JL_S.D", |
| 178 | /* 04 */ "0x04 <illegal>", |
| 179 | /* 05 */ "0x05 <illegal>", |
| 180 | /* 06 */ "SUB_S.NE", |
| 181 | /* 07 */ "ZOPs", // Sub Operations (yet another table..) ( table0f_00_07 ) |
| 182 | }; |
| 137 | 183 | |
| 184 | static const char *table0f_00_07[0x8] = |
| 185 | { |
| 186 | /* 00 */ "NOP_S", |
| 187 | /* 01 */ "UNIMP_S", // unimplemented (not a5?) |
| 188 | /* 02 */ "0x02 <illegal>", |
| 189 | /* 03 */ "0x03 <illegal>", |
| 190 | /* 04 */ "JEQ_S [BLINK]", |
| 191 | /* 05 */ "JNE_S [BLINK]", |
| 192 | /* 06 */ "J_S [BLINK]", |
| 193 | /* 07 */ "J_S.D [BLINK]", |
| 194 | }; |
| 195 | |
| 138 | 196 | #define ARCOMPACT_OPERATION ((op & 0xf800) >> 11) |
| 139 | 197 | |
| 140 | 198 | CPU_DISASSEMBLE(arcompact) |
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| 163 | 221 | address |= ((op & 0x0000000f) >> 0) << 20; |
| 164 | 222 | if (address & 0x800000) address = -(address&0x7fffff); |
| 165 | 223 | |
| 166 | | print("B %08x (%08x)", pc + (address *2) + 4, op & ~0xffffffcf ); |
| 224 | print("B %08x (%08x)", pc + (address *2) + 2, op & ~0xffffffcf ); |
| 167 | 225 | } |
| 168 | 226 | else |
| 169 | 227 | { // Branch Conditionally |
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| 174 | 232 | |
| 175 | 233 | UINT8 condition = op & 0x0000001f; |
| 176 | 234 | |
| 177 | | print("B(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 4, op & ~0xffffffdf ); |
| 235 | print("B(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 2, op & ~0xffffffdf ); |
| 178 | 236 | |
| 179 | 237 | } |
| 180 | 238 | |
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| 220 | 278 | address |= ((op & 0x0000000f) >> 0) << 20; |
| 221 | 279 | if (address & 0x800000) address = -(address&0x7fffff); |
| 222 | 280 | |
| 223 | | print("BL %08x (%08x)", pc + (address *2) + 4, op & ~0xffffffcf ); |
| 281 | print("BL %08x (%08x)", pc + (address *2) + 2, op & ~0xffffffcf ); |
| 224 | 282 | } |
| 225 | 283 | else |
| 226 | 284 | { // Branch and Link Conditionally |
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| 231 | 289 | |
| 232 | 290 | UINT8 condition = op & 0x0000001f; |
| 233 | 291 | |
| 234 | | print("BL(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 4, op & ~0xffffffdf ); |
| 292 | print("BL(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 2, op & ~0xffffffdf ); |
| 235 | 293 | |
| 236 | 294 | } |
| 237 | 295 | |
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| 252 | 310 | |
| 253 | 311 | switch (instruction) |
| 254 | 312 | { |
| 313 | case 0x0f: |
| 314 | { |
| 315 | // General Register Instructions (16-bit) |
| 316 | // 01111 bbb ccc iiiii |
| 317 | UINT8 subinstr = (op & 0x01f) >> 0; |
| 318 | //print("%s (%04x)", table0f[subinstr], op & ~0xf81f); |
| 319 | |
| 320 | #if 1 |
| 321 | switch (subinstr) |
| 322 | { |
| 323 | |
| 324 | default: |
| 325 | print("%s (%04x)", table0f[subinstr], op & ~0xf81f); |
| 326 | break; |
| 327 | |
| 328 | case 0x00: |
| 329 | { |
| 330 | // General Operations w/ Register |
| 331 | // 01111 bbb iii 00000 |
| 332 | UINT8 subinstr2 = (op & 0x00e0) >> 5; |
| 333 | |
| 334 | switch (subinstr2) |
| 335 | { |
| 336 | default: |
| 337 | print("%s (%04x)", table0f_00[subinstr2], op & ~0xf8ff); |
| 338 | break; |
| 339 | |
| 340 | case 0x7: |
| 341 | { |
| 342 | // General Operations w/o Register |
| 343 | // 01111 iii 111 00000 |
| 344 | UINT8 subinstr3 = (op & 0x0700) >> 8; |
| 345 | |
| 346 | print("%s (%04x)", table0f_00_07[subinstr3], op & ~0xffff); |
| 347 | |
| 348 | break; |
| 349 | } |
| 350 | } |
| 351 | } |
| 352 | } |
| 353 | #endif |
| 354 | |
| 355 | break; |
| 356 | |
| 357 | } |
| 358 | |
| 359 | |
| 255 | 360 | case 0x18: |
| 256 | 361 | { |
| 257 | 362 | // Stack Pointer Based Instructions (16-bit) |