trunk/src/emu/cpu/arcompact/arcompactdasm.c
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| 100 | 100 | /* 1f */ "0x1f Reserved" |
| 101 | 101 | }; |
| 102 | 102 | |
| 103 | static const char *table01_01_0x[0x10] = |
| 104 | { |
| 105 | /* 00 */ "BREQ", |
| 106 | /* 01 */ "BRNE", |
| 107 | /* 02 */ "BRLT", |
| 108 | /* 03 */ "BRGE", |
| 109 | /* 04 */ "BRLO", |
| 110 | /* 05 */ "BRHS", |
| 111 | /* 06 */ "<reserved>", |
| 112 | /* 07 */ "<reserved>", |
| 113 | /* 08 */ "<reserved>", |
| 114 | /* 09 */ "<reserved>", |
| 115 | /* 0a */ "<reserved>", |
| 116 | /* 0b */ "<reserved>", |
| 117 | /* 0c */ "<reserved>", |
| 118 | /* 0d */ "<reserved>", |
| 119 | /* 0e */ "<BBIT0>", |
| 120 | /* 0f */ "<BBIT1>" |
| 121 | }; |
| 122 | |
| 123 | |
| 103 | 124 | #define ARCOMPACT_OPERATION ((op & 0xf800) >> 11) |
| 104 | 125 | |
| 105 | 126 | CPU_DISASSEMBLE(arcompact) |
| 106 | 127 | { |
| 107 | 128 | int size = 2; |
| 108 | 129 | |
| 109 | | UINT32 op = oprom[0] | (oprom[1] << 8); |
| 130 | UINT32 op = oprom[2] | (oprom[3] << 8); |
| 110 | 131 | output = buffer; |
| 111 | 132 | |
| 112 | 133 | UINT8 instruction = ARCOMPACT_OPERATION; |
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| 115 | 136 | { |
| 116 | 137 | size = 4; |
| 117 | 138 | op <<= 16; |
| 118 | | op |= oprom[2] | (oprom[3] << 8); |
| 139 | op |= oprom[0] | (oprom[1] << 8); |
| 119 | 140 | |
| 120 | 141 | switch (instruction) |
| 121 | 142 | { |
| 122 | 143 | case 0x00: |
| 123 | 144 | if (op & 0x00010000) |
| 124 | 145 | { // Branch Unconditionally Far |
| 125 | | // 00000 ssssssssss 1 SSSSSSSSSS N 0 TTTT |
| 126 | | UINT32 address = (op & 0x07fe0000) >> 17; |
| 146 | // 00000 ssssssssss 1 SSSSSSSSSS N R TTTT |
| 147 | INT32 address = (op & 0x07fe0000) >> 17; |
| 127 | 148 | address |= ((op & 0x0000ffc0) >> 6) << 10; |
| 128 | 149 | address |= ((op & 0x0000000f) >> 0) << 20; |
| 150 | if (address & 0x800000) address = -(address&0x7fffff); |
| 129 | 151 | |
| 130 | | print("B %08x (%08x)", address<<1, op & ~0xffffffcf ); |
| 152 | print("B %08x (%08x)", pc + (address *2) + 4, op & ~0xffffffcf ); |
| 131 | 153 | } |
| 132 | 154 | else |
| 133 | 155 | { // Branch Conditionally |
| 134 | 156 | // 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ |
| 135 | | UINT32 address = (op & 0x07fe0000) >> 17; |
| 157 | INT32 address = (op & 0x07fe0000) >> 17; |
| 136 | 158 | address |= ((op & 0x0000ffc0) >> 6) << 10; |
| 159 | if (address & 0x800000) address = -(address&0x7fffff); |
| 137 | 160 | |
| 138 | 161 | UINT8 condition = op & 0x0000001f; |
| 139 | 162 | |
| 140 | | print("B(%s) %08x (%08x)", conditions[condition], address<<1, op & ~0xffffffdf ); |
| 163 | print("B(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 4, op & ~0xffffffdf ); |
| 141 | 164 | |
| 142 | 165 | } |
| 143 | 166 | |
| 144 | 167 | break; |
| 145 | 168 | |
| 169 | case 0x01: |
| 170 | if (op & 0x00010000) |
| 171 | { |
| 172 | if (op & 0x00000010) |
| 173 | { // Branch on Compare / Bit Test - Register-Immediate |
| 174 | // 00001 bbb sssssss 1 S BBB UUUUUU N 1 iiii |
| 175 | UINT8 subinstr = op & 0x0000000f; |
| 176 | INT32 address = (op & 0x00fe0000) >> 17; |
| 177 | address |= ((op & 0x00008000) >> 15) << 7; |
| 178 | if (address & 0x80) address = -(address&0x7f); |
| 179 | |
| 180 | |
| 181 | print("%s (reg-imm) %08x (%08x)", table01_01_0x[subinstr], pc + (address *2) + 4, op & ~0xf8fe800f); |
| 182 | |
| 183 | |
| 184 | } |
| 185 | else |
| 186 | { |
| 187 | // Branch on Compare / Bit Test - Register-Register |
| 188 | // 00001 bbb sssssss 1 S BBB CCCCCC N 0 iiii |
| 189 | UINT8 subinstr = op & 0x0000000f; |
| 190 | INT32 address = (op & 0x00fe0000) >> 17; |
| 191 | address |= ((op & 0x00008000) >> 15) << 7; |
| 192 | if (address & 0x80) address = -(address&0x7f); |
| 193 | |
| 194 | print("%s (reg-reg) %08x (%08x)", table01_01_0x[subinstr], pc + (address *2) + 4, op & ~0xf8fe800f); |
| 195 | |
| 196 | } |
| 197 | |
| 198 | } |
| 199 | else |
| 200 | { |
| 201 | if (op & 0x00020000) |
| 202 | { // Branch and Link Unconditionally Far |
| 203 | // 00001 sssssssss 10 SSSSSSSSSS N R TTTT |
| 204 | INT32 address = (op & 0x07fc0000) >> 17; |
| 205 | address |= ((op & 0x0000ffc0) >> 6) << 10; |
| 206 | address |= ((op & 0x0000000f) >> 0) << 20; |
| 207 | if (address & 0x800000) address = -(address&0x7fffff); |
| 208 | |
| 209 | print("BL %08x (%08x)", pc + (address *2) + 4, op & ~0xffffffcf ); |
| 210 | } |
| 211 | else |
| 212 | { // Branch and Link Conditionally |
| 213 | // 00001 sssssssss 00 SSSSSSSSSS N QQQQQ |
| 214 | INT32 address = (op & 0x07fc0000) >> 17; |
| 215 | address |= ((op & 0x0000ffc0) >> 6) << 10; |
| 216 | if (address & 0x800000) address = -(address&0x7fffff); |
| 217 | |
| 218 | UINT8 condition = op & 0x0000001f; |
| 219 | |
| 220 | print("BL(%s) %08x (%08x)", conditions[condition], pc + (address *2) + 4, op & ~0xffffffdf ); |
| 221 | |
| 222 | } |
| 223 | |
| 224 | } |
| 225 | break; |
| 226 | |
| 146 | 227 | default: |
| 147 | 228 | print("%s (%08x)", basic[instruction], op & ~0xf8000000 ); |
| 148 | 229 | break; |