trunk/src/emu/cpu/arcompact/arcompact.c
| r242160 | r242161 | |
|---|
| 26 | 26 | |
| 27 | 27 | arcompact_device::arcompact_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
| 28 | 28 | : cpu_device(mconfig, ARCA5, "ARCtangent-A5", tag, owner, clock, "arca5", __FILE__) |
| 29 | | , m_program_config("program", ENDIANNESS_BIG, 32, 24, 0) // some docs describe these as 'middle endian'?! |
| 29 | , m_program_config("program", ENDIANNESS_LITTLE, 32, 32, 0) // some docs describe these as 'middle endian'?! |
| 30 | 30 | { |
| 31 | 31 | } |
| 32 | 32 | |
| r242160 | r242161 | |
|---|
| 49 | 49 | |
| 50 | 50 | /*****************************************************************************/ |
| 51 | 51 | |
| 52 | | UINT16 arcompact_device::READ32(UINT32 address) |
| 52 | UINT32 arcompact_device::READ32(UINT32 address) |
| 53 | 53 | { |
| 54 | 54 | return m_program->read_dword(address << 2); |
| 55 | 55 | } |
| r242160 | r242161 | |
|---|
| 59 | 59 | m_program->write_dword(address << 2, data); |
| 60 | 60 | } |
| 61 | 61 | |
| 62 | UINT16 arcompact_device::READ16(UINT32 address) |
| 63 | { |
| 64 | return m_program->read_word(address << 1); |
| 65 | } |
| 66 | |
| 67 | void arcompact_device::WRITE16(UINT32 address, UINT16 data) |
| 68 | { |
| 69 | m_program->write_word(address << 1, data); |
| 70 | } |
| 71 | |
| 72 | |
| 62 | 73 | /*****************************************************************************/ |
| 63 | 74 | |
| 64 | 75 | void arcompact_device::device_start() |
| r242160 | r242161 | |
|---|
| 80 | 91 | switch (entry.index()) |
| 81 | 92 | { |
| 82 | 93 | case 0: |
| 83 | | m_debugger_temp = m_pc << 2; |
| 94 | m_debugger_temp = m_pc << 1; |
| 84 | 95 | break; |
| 85 | 96 | |
| 86 | 97 | case STATE_GENPC: |
| 87 | | m_debugger_temp = m_pc << 2; |
| 98 | m_debugger_temp = m_pc << 1; |
| 88 | 99 | break; |
| 89 | 100 | } |
| 90 | 101 | } |
| r242160 | r242161 | |
|---|
| 94 | 105 | switch (entry.index()) |
| 95 | 106 | { |
| 96 | 107 | case 0: |
| 97 | | m_pc = (m_debugger_temp & 0xfffffffc) >> 2; |
| 108 | m_pc = (m_debugger_temp & 0xfffffffe) >> 1; |
| 98 | 109 | break; |
| 99 | 110 | } |
| 100 | 111 | } |
| r242160 | r242161 | |
|---|
| 123 | 134 | |
| 124 | 135 | //UINT32 op = READ32(m_pc); |
| 125 | 136 | |
| 137 | |
| 126 | 138 | m_pc++; |
| 127 | 139 | |
| 128 | 140 | m_icount--; |
trunk/src/emu/cpu/arcompact/arcompactdasm.c
| r242160 | r242161 | |
|---|
| 25 | 25 | /*****************************************************************************/ |
| 26 | 26 | |
| 27 | 27 | |
| 28 | static const char *basic[0x20] = |
| 29 | { |
| 30 | /* opcode below are 32-bit mode */ |
| 31 | /* 00 */ "Bcc", |
| 32 | /* 01 */ "BLcc/BRcc", |
| 33 | /* 02 */ "LD r+o", |
| 34 | /* 03 */ "ST r+o", |
| 35 | /* 04 */ "op a,b,c (basecase)", // basecase ops |
| 36 | /* 05 */ "op a,b,c (05 ARC ext)", // ARC processor specific extensions |
| 37 | /* 06 */ "op a,b,c (06 ARC ext)", |
| 38 | /* 07 */ "op a,b,c (07 User ext)", // User speciifc extensions |
| 39 | /* 08 */ "op a,b,c (08 User ext)", |
| 40 | /* 09 */ "op a,b,c (09 Market ext)", // Market specific extensions |
| 41 | /* 0a */ "op a,b,c (0a Market ext)", |
| 42 | /* 0b */ "op a,b,c (0b Market ext)", |
| 43 | /* opcodes below are 16-bit mode */ |
| 44 | /* 0c */ "Load/Add reg-reg", |
| 45 | /* 0d */ "Add/Sub/Shft imm", |
| 46 | /* 0e */ "Mov/Cmp/Add", |
| 47 | /* 0f */ "op_S b,b,c", // single ops |
| 48 | /* 10 */ "LD_S", |
| 49 | /* 11 */ "LDB_S", |
| 50 | /* 12 */ "LDW_S", |
| 51 | /* 13 */ "LSW_S.X", |
| 52 | /* 14 */ "ST_S", |
| 53 | /* 15 */ "STB_S", |
| 54 | /* 16 */ "STW_S", |
| 55 | /* 17 */ "Shift/Sub/Bit", |
| 56 | /* 18 */ "Stack Instr", |
| 57 | /* 19 */ "GP Instr", |
| 58 | /* 1a */ "PCL Instr", |
| 59 | /* 1b */ "MOV_S", |
| 60 | /* 1c */ "ADD_S/CMP_S", |
| 61 | /* 1d */ "BRcc_S", |
| 62 | /* 1e */ "Bcc_S", |
| 63 | /* 1f */ "BL_S" |
| 64 | }; |
| 28 | 65 | |
| 66 | // condition codes (basic ones are the same as arc |
| 67 | static const char *conditions[0x20] = |
| 68 | { |
| 69 | /* 00 */ "AL", // (aka RA - Always) |
| 70 | /* 01 */ "EQ", // (aka Z - Zero |
| 71 | /* 02 */ "NE", // (aka NZ - Non-Zero) |
| 72 | /* 03 */ "PL", // (aka P - Positive) |
| 73 | /* 04 */ "MI", // (aka N - Negative) |
| 74 | /* 05 */ "CS", // (aka C, LO - Carry set / Lower than) (unsigned) |
| 75 | /* 06 */ "CC", // (aka CC, NC, HS - Carry Clear / Higher or Same) (unsigned) |
| 76 | /* 07 */ "VS", // (aka V - Overflow set) |
| 77 | /* 08 */ "VC", // (aka NV - Overflow clear) |
| 78 | /* 09 */ "GT", // ( - Greater than) (signed) |
| 79 | /* 0a */ "GE", // ( - Greater than or Equal) (signed) |
| 80 | /* 0b */ "LT", // ( - Less than) (signed) |
| 81 | /* 0c */ "LE", // ( - Less than or Equal) (signed) |
| 82 | /* 0d */ "HI", // ( - Higher than) (unsigned) |
| 83 | /* 0e */ "LS", // ( - Lower or Same) (unsigned) |
| 84 | /* 0f */ "PNZ",// ( - Positive non-0 value) |
| 85 | /* 10 */ "0x10 Reserved", // possible CPU implementation specifics |
| 86 | /* 11 */ "0x11 Reserved", |
| 87 | /* 12 */ "0x12 Reserved", |
| 88 | /* 13 */ "0x13 Reserved", |
| 89 | /* 14 */ "0x14 Reserved", |
| 90 | /* 15 */ "0x15 Reserved", |
| 91 | /* 16 */ "0x16 Reserved", |
| 92 | /* 17 */ "0x17 Reserved", |
| 93 | /* 18 */ "0x18 Reserved", |
| 94 | /* 19 */ "0x19 Reserved", |
| 95 | /* 1a */ "0x1a Reserved", |
| 96 | /* 1b */ "0x1b Reserved", |
| 97 | /* 1c */ "0x1c Reserved", |
| 98 | /* 1d */ "0x1d Reserved", |
| 99 | /* 1e */ "0x1e Reserved", |
| 100 | /* 1f */ "0x1f Reserved" |
| 101 | }; |
| 102 | |
| 103 | #define ARCOMPACT_OPERATION ((op & 0xf800) >> 11) |
| 104 | |
| 29 | 105 | CPU_DISASSEMBLE(arcompact) |
| 30 | 106 | { |
| 31 | | UINT32 op = oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24); |
| 32 | | op = BIG_ENDIANIZE_INT32(op); |
| 107 | int size = 2; |
| 33 | 108 | |
| 109 | UINT32 op = oprom[0] | (oprom[1] << 8); |
| 34 | 110 | output = buffer; |
| 35 | 111 | |
| 36 | | print("<undefined>"); |
| 112 | UINT8 instruction = ARCOMPACT_OPERATION; |
| 37 | 113 | |
| 38 | | return 4 | DASMFLAG_SUPPORTED; |
| 114 | if (instruction < 0x0c) |
| 115 | { |
| 116 | size = 4; |
| 117 | op <<= 16; |
| 118 | op |= oprom[2] | (oprom[3] << 8); |
| 119 | |
| 120 | switch (instruction) |
| 121 | { |
| 122 | case 0x00: |
| 123 | if (op & 0x00010000) |
| 124 | { // Branch Unconditionally Far |
| 125 | // 00000 ssssssssss 1 SSSSSSSSSS N 0 TTTT |
| 126 | UINT32 address = (op & 0x07fe0000) >> 17; |
| 127 | address |= ((op & 0x0000ffc0) >> 6) << 10; |
| 128 | address |= ((op & 0x0000000f) >> 0) << 20; |
| 129 | |
| 130 | print("B %08x (%08x)", address<<1, op & ~0xffffffcf ); |
| 131 | } |
| 132 | else |
| 133 | { // Branch Conditionally |
| 134 | // 00000 ssssssssss 0 SSSSSSSSSS N QQQQQ |
| 135 | UINT32 address = (op & 0x07fe0000) >> 17; |
| 136 | address |= ((op & 0x0000ffc0) >> 6) << 10; |
| 137 | |
| 138 | UINT8 condition = op & 0x0000001f; |
| 139 | |
| 140 | print("B(%s) %08x (%08x)", conditions[condition], address<<1, op & ~0xffffffdf ); |
| 141 | |
| 142 | } |
| 143 | |
| 144 | break; |
| 145 | |
| 146 | default: |
| 147 | print("%s (%08x)", basic[instruction], op & ~0xf8000000 ); |
| 148 | break; |
| 149 | |
| 150 | } |
| 151 | |
| 152 | |
| 153 | } |
| 154 | else |
| 155 | { |
| 156 | size = 2; |
| 157 | print("%s (%04x)", basic[instruction], op & ~0xf800 ); |
| 158 | } |
| 159 | |
| 160 | |
| 161 | return size | DASMFLAG_SUPPORTED; |
| 39 | 162 | } |