trunk/src/emu/cpu/arc/arcdasm.c
| r242157 | r242158 | |
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| 31 | 31 | /* 02 */ "ST r+o", |
| 32 | 32 | /* 03 */ "extended", |
| 33 | 33 | /* 04 */ "B", |
| 34 | | /* 05 */ "BLcc", |
| 34 | /* 05 */ "BL", |
| 35 | 35 | /* 06 */ "LPcc", |
| 36 | 36 | /* 07 */ "Jcc JLcc", |
| 37 | 37 | /* 08 */ "ADD", |
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| 104 | 104 | "Res!", // reserved / invalid |
| 105 | 105 | }; |
| 106 | 106 | |
| 107 | static const char *regnames[0x40] = |
| 108 | { |
| 109 | /* 0x00 */ "r00", |
| 110 | /* 0x01 */ "r01", |
| 111 | /* 0x02 */ "r02", |
| 112 | /* 0x03 */ "r03", |
| 113 | /* 0x04 */ "r04", |
| 114 | /* 0x05 */ "r05", |
| 115 | /* 0x06 */ "r06", |
| 116 | /* 0x07 */ "r07", |
| 117 | /* 0x08 */ "r08", |
| 118 | /* 0x09 */ "r09", |
| 119 | /* 0x0a */ "r10", |
| 120 | /* 0x0b */ "r11", |
| 121 | /* 0x0c */ "r12", |
| 122 | /* 0x0d */ "r13", |
| 123 | /* 0x0e */ "r14", |
| 124 | /* 0x0f */ "r15", |
| 125 | |
| 126 | /* 0x10 */ "r16", |
| 127 | /* 0x11 */ "r17", |
| 128 | /* 0x12 */ "r18", |
| 129 | /* 0x13 */ "r19", |
| 130 | /* 0x14 */ "r20", |
| 131 | /* 0x15 */ "r21", |
| 132 | /* 0x16 */ "r22", |
| 133 | /* 0x17 */ "r23", |
| 134 | /* 0x18 */ "r24", |
| 135 | /* 0x19 */ "r25", |
| 136 | /* 0x1a */ "r26", |
| 137 | /* 0x1b */ "r27", |
| 138 | /* 0x1c */ "r28", |
| 139 | /* 0x1d */ "ILINK1", |
| 140 | /* 0x1e */ "ILINK2", |
| 141 | /* 0x1f */ "BLINK", |
| 142 | |
| 143 | /* 0x20 */ "r32res", // reserved for manufacturer specific extensions |
| 144 | /* 0x21 */ "r33res", |
| 145 | /* 0x22 */ "r34res", |
| 146 | /* 0x23 */ "r35res", |
| 147 | /* 0x24 */ "r36res", |
| 148 | /* 0x25 */ "r37res", |
| 149 | /* 0x26 */ "r38res", |
| 150 | /* 0x27 */ "r39res", |
| 151 | /* 0x28 */ "r40res", |
| 152 | /* 0x29 */ "r41res", |
| 153 | /* 0x2a */ "r42res", |
| 154 | /* 0x2b */ "r43res", |
| 155 | /* 0x2c */ "r44res", |
| 156 | /* 0x2d */ "r45res", |
| 157 | /* 0x2e */ "r46res", |
| 158 | /* 0x2f */ "r47res", |
| 159 | |
| 160 | /* 0x30 */ "r48res", |
| 161 | /* 0x31 */ "r49res", |
| 162 | /* 0x32 */ "r50res", |
| 163 | /* 0x33 */ "r51res", |
| 164 | /* 0x34 */ "r52res", |
| 165 | /* 0x35 */ "r53res", |
| 166 | /* 0x36 */ "r54res", |
| 167 | /* 0x37 */ "r55res", |
| 168 | /* 0x38 */ "r56res", |
| 169 | /* 0x39 */ "r57res", |
| 170 | /* 0x3a */ "r58res", |
| 171 | /* 0x3b */ "r59res", |
| 172 | /* 0x3c */ "LPCOUNT", |
| 173 | /* 0x3d */ "sImm F", |
| 174 | /* 0x3e */ "lImm", |
| 175 | /* 0x3f */ "sImm NF", |
| 176 | }; |
| 177 | |
| 107 | 178 | #define ARC_CONDITION ((op & 0x0000001f) >> 0 ) |
| 108 | 179 | |
| 109 | 180 | // used in jumps |
| 110 | | #define ARC_BRANCH_DELAY ((op & 0x00000060) >> 5 ) // aka NN |
| 181 | #define ARC_BRANCH_DELAY ((op & 0x00000060) >> 5 ) // aka N |
| 111 | 182 | #define ARC_BRANCH_ADDR ((op & 0x07ffff80) >> 7 ) // aka L |
| 112 | 183 | |
| 113 | | #define ARC_OPERATION ((op & 0xf8000000) >> 27) // aka QQQQQ |
| 184 | #define ARC_OPERATION ((op & 0xf8000000) >> 27) // aka Q |
| 114 | 185 | |
| 186 | #define ARC_REGOP_DEST ((op & 0x07e00000) >> 21 ) // aka A |
| 187 | #define ARC_REGOP_OP1 ((op & 0x001f8000) >> 15 ) // aka B |
| 188 | #define ARC_REGOP_OP2 ((op & 0x00007e00) >> 9 ) // aka C |
| 189 | #define ARC_REGOP_SHIMM ((op & 0x000001ff) >> 0 ) // aka D |
| 190 | |
| 191 | |
| 115 | 192 | CPU_DISASSEMBLE(arc) |
| 116 | 193 | { |
| 117 | 194 | UINT32 op = oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24); |
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| 123 | 200 | |
| 124 | 201 | switch (opcode) |
| 125 | 202 | { |
| 126 | | case 0x04: |
| 203 | case 0x04: // B |
| 204 | case 0x05: // BL |
| 127 | 205 | print("%s(%s)(%s) %08x", basic[opcode], conditions[ARC_CONDITION], delaytype[ARC_BRANCH_DELAY], (ARC_BRANCH_ADDR<<2)+pc+4); |
| 128 | 206 | break; |
| 129 | 207 | |
| 208 | case 0x08: // ADD |
| 209 | // todo, short / long immediate formats |
| 210 | print("%s %s , %s , %s (%08x)", basic[opcode], regnames[ARC_REGOP_DEST], regnames[ARC_REGOP_OP1], regnames[ARC_REGOP_OP2], op &~ 0xfffffe00); |
| 211 | break; |
| 212 | |
| 213 | |
| 130 | 214 | default: |
| 131 | 215 | print("%s (%08x)", basic[opcode], op &~ 0xf8000000); |
| 132 | 216 | break; |