trunk/src/emu/cpu/arc/arcdasm.c
| r242155 | r242156 | |
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| 30 | 30 | /* 01 */ "LD r+o", |
| 31 | 31 | /* 02 */ "ST r+o", |
| 32 | 32 | /* 03 */ "extended", |
| 33 | | /* 04 */ "Bcc", |
| 33 | /* 04 */ "B", |
| 34 | 34 | /* 05 */ "BLcc", |
| 35 | 35 | /* 06 */ "LPcc", |
| 36 | 36 | /* 07 */ "Jcc JLcc", |
| r242155 | r242156 | |
|---|
| 60 | 60 | /* 1f */ "MIN" |
| 61 | 61 | }; |
| 62 | 62 | |
| 63 | static const char *conditions[0x20] = |
| 64 | { |
| 65 | /* 00 */ "AL", // (aka RA - Always) |
| 66 | /* 01 */ "EQ", // (aka Z - Zero |
| 67 | /* 02 */ "NE", // (aka NZ - Non-Zero) |
| 68 | /* 03 */ "PL", // (aka P - Positive) |
| 69 | /* 04 */ "MI", // (aka N - Negative) |
| 70 | /* 05 */ "CS", // (aka C, LO - Carry set / Lower than) (unsigned) |
| 71 | /* 06 */ "CC", // (aka CC, NC, HS - Carry Clear / Higher or Same) (unsigned) |
| 72 | /* 07 */ "VS", // (aka V - Overflow set) |
| 73 | /* 08 */ "VC", // (aka NV - Overflow clear) |
| 74 | /* 09 */ "GT", // ( - Greater than) (signed) |
| 75 | /* 0a */ "GE", // ( - Greater than or Equal) (signed) |
| 76 | /* 0b */ "LT", // ( - Less than) (signed) |
| 77 | /* 0c */ "LE", // ( - Less than or Equal) (signed) |
| 78 | /* 0d */ "HI", // ( - Higher than) (unsigned) |
| 79 | /* 0e */ "LS", // ( - Lower or Same) (unsigned) |
| 80 | /* 0f */ "PNZ",// ( - Positive non-0 value) |
| 81 | /* 10 */ "0x10 Reserved", // possible CPU implementation specifics |
| 82 | /* 11 */ "0x11 Reserved", |
| 83 | /* 12 */ "0x12 Reserved", |
| 84 | /* 13 */ "0x13 Reserved", |
| 85 | /* 14 */ "0x14 Reserved", |
| 86 | /* 15 */ "0x15 Reserved", |
| 87 | /* 16 */ "0x16 Reserved", |
| 88 | /* 17 */ "0x17 Reserved", |
| 89 | /* 18 */ "0x18 Reserved", |
| 90 | /* 19 */ "0x19 Reserved", |
| 91 | /* 1a */ "0x1a Reserved", |
| 92 | /* 1b */ "0x1b Reserved", |
| 93 | /* 1c */ "0x1c Reserved", |
| 94 | /* 1d */ "0x1d Reserved", |
| 95 | /* 1e */ "0x1e Reserved", |
| 96 | /* 1f */ "0x1f Reserved" |
| 97 | }; |
| 63 | 98 | |
| 64 | | CPU_DISASSEMBLE( arc ) |
| 99 | static const char *delaytype[0x4] = |
| 65 | 100 | { |
| 101 | "ND", // NO DELAY - execute next instruction only when NOT jumping |
| 102 | "D", // always execute next instruction |
| 103 | "JD", // only execute next instruction when jumping |
| 104 | "Res!", // reserved / invalid |
| 105 | }; |
| 106 | |
| 107 | #define ARC_CONDITION ((op & 0x0000001f) >> 0 ) |
| 108 | |
| 109 | // used in jumps |
| 110 | #define ARC_BRANCH_DELAY ((op & 0x00000060) >> 5 ) // aka NN |
| 111 | #define ARC_BRANCH_ADDR ((op & 0x07ffff80) >> 7 ) // aka L |
| 112 | |
| 113 | #define ARC_OPERATION ((op & 0xf8000000) >> 27) // aka QQQQQ |
| 114 | |
| 115 | CPU_DISASSEMBLE(arc) |
| 116 | { |
| 66 | 117 | UINT32 op = oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24); |
| 67 | 118 | op = BIG_ENDIANIZE_INT32(op); |
| 68 | 119 | |
| 69 | 120 | output = buffer; |
| 70 | 121 | |
| 71 | | UINT8 opcode = (op & 0xf8000000) >> 27; |
| 122 | UINT8 opcode = ARC_OPERATION; |
| 72 | 123 | |
| 73 | | print("%s (%08x)", basic[opcode], op &~ 0xf8000000); |
| 124 | switch (opcode) |
| 125 | { |
| 126 | case 0x04: |
| 127 | print("%s(%s)(%s) %08x", basic[opcode], conditions[ARC_CONDITION], delaytype[ARC_BRANCH_DELAY], (ARC_BRANCH_ADDR<<2)+pc+4); |
| 128 | break; |
| 129 | |
| 130 | default: |
| 131 | print("%s (%08x)", basic[opcode], op &~ 0xf8000000); |
| 132 | break; |
| 133 | } |
| 74 | 134 | |
| 135 | |
| 136 | |
| 75 | 137 | return 4 | DASMFLAG_SUPPORTED; |
| 76 | 138 | } |