MAME SVN History

199869 Revisions

r33617 Monday 1st December, 2014 at 20:45:19 UTC by hap
(MESS) Rewrote TMS1xxx MCU core and added support for a couple of classic Texas Instruments handheld calculators. [hap, seanriddle]

[src/emu/cpu/tms0980]	tms0980.c tms0980.h
[src/mess]	mess.lst mess.mak
[src/mess/drivers]	comp4.c merlin.c microvsn.c simon.c stopthie.c ticalc1x.c
[src/mess/layout]	comp4.lay* merlin.lay ti1270.lay* ti30.lay* tisr16.lay* wizatron.lay*

trunk/src/emu/cpu/tms0980/tms0980.c
r242128	r242129
	1	// license:BSD-3-Clause
	2	// copyright-holders:Wilbert Pol, hap
1	3	/*
2	4
	5	TMS0980/TMS1000-family MCU cores
3	6
4		TMS0980/TMS1000-family CPU cores
5
6		The tms0980 and tms1000-family cpu cores are very similar. The tms0980 has a
7		slightly bigger addressable area and uses 9bit instructions where the tms1000
	7	The TMS0980 and TMS1000-family MCU cores are very similar. The TMS0980 has a
	8	slightly bigger addressable area and uses 9bit instructions where the TMS1000
8	9	family uses 8bit instruction. The instruction set themselves are very similar
9		though. ~~The table below shows the differences between the different models.~~
	10	though.
10	11
11		Mode \| ROM \| RAM \| R pins \| O pins \| K pins \| ids
12		---------+-----------+----------+--------+--------+--------\|----------
13		tms0970 \| 1024 * 8 \| 64 * 4 \| \| \| \| tms0972
14		tms0920* \| 511?* 9 \| 40 * 5 \| \| \| \| tmc0921
15		tms0980 \| 2048 * 9 \| 64 * 9 \| \| \| \| tmc0981
16		tms1000 \| 1024 * 8 \| 64 * 4 \| 11 \| 8 \| 4 \| tms1001
17		tms1040* \| 1024 * 8 \| 64 * 4 \| \| \| \| tms1043
18		tms1070 \| 1024 * 8 \| 64 * 4 \| 11 \| 8 \| 4 \| tms1071
19		tms1100 \| 2048 * 8 \| 128 * 4 \| 11 \| 8 \| 4 \| tms1111/tms1115
20		tms1170* \| 2048 * 8 \| 128 * 4 \| \| \| \| tmc1172
21		tms1200 \| 1024 * 8 \| 64 * 4 \| 13 \| 8 \| 4 \| tms1215
22		tms1270 \| 1024 * 8 \| 64 * 4 \| 13 \| 10 \| 4 \| tms1278
23		tms1300 \| 2048 * 8 \| 128 * 4 \| 16 \| 8 \| 4 \| tms1309
24		tms1370* \| 2048 * 8 \| 128 * 4 \| \| \| \| za0543
25		tms1400* \| 4096 * 8 \| 128 * 4 \| \| \| \|
26		tms1470* \| 4096 * 8 \| 128 * 4 \| \| \| \| tms1470
27		tms1500* \| 2048 * 13 \| 64 * 20 \| \| \| \| tmc1501
28		tms1600* \| 4096 * 8 \| 128 * 4 \| \| \| \|
29		tms1670* \| 4096 * 8 \| 128 * 4 \| \| \| \|
30		tms1700* \| 512 * 8 \| 32 * 4 \| \| \| \|
31		tms1980* \| 2048 * 9 \| 64 * 9 \| \| \| \| tmc1982
32		tms1990* \| 1024 * 8 \| 64 * 4 \| \| \| \| tmc1991
33		tp0310* \| 511?* 9 \| 40 * 5 \| \| \| \| tp0311
34		tp0320* \| 2048 * 9 \| 64 * 13 \| \| \| \| tp0321
35		tp0455* \| \| \| \| \| \| cd4501
36		tp0456* \| \| \| \| \| \| cd4555
37		tp0458* \| \| \| \| \| \| cd4812
38		tp0485* \| \| \| \| \| \| cd2901
39		tp0530* \| \| \| \| \| \| cd5402
40
41		* = not supported yet
42
43		The TMS1000 core has been tested with some example code, the other models
44		have not been tested lacking rom dumps.
45
46	12	Each instruction takes 12 cycles to execute in 2 phases: a fetch phase and an
47	13	execution phase. The execution phase takes place at the same time as the fetch
48	14	phase of the next instruction. So, during execution there are both fetch and
r242128	r242129
83	49	1. Execute BRANCH/CALL/RETN part #1
84	50
85	51
86		The CPU cores contains a set of fixed instructions and a set of
	52	The MCU cores contains a set of fixed instructions and a set of
87	53	instructions created using microinstructions. A subset of the
88	54	instruction set could be defined from the microinstructions by
89		TI customers. Currently we only support the standard instruction
90		set as defined by TI.
	55	TI customers.
91	56
92		The microinstructions are:
93		15TN - 15 to -ALU
94		ATN - ACC to -ALU
95		AUTA - ALU to ACC
96		AUTY - ALU to Y
97		C8 - CARRY8 to STATUS
98		CIN - Carry In to ALU
99		CKM - CKB to MEM
100		CKN - CKB to -ALU
101		CKP - CKB to +ALU
102		CME - Conditional Memory Enable
103		DMTP - DAM to +ALU
104		MTN - MEM to -ALU
105		MTP - MEM to +ALU
106		NATN - ~ACC to -ALU
107		NDMTP - ~DAM to +ALU
108		NE - COMP to STATUS
109		SSE - Special Status Enable
110		SSS - Special Status Sample
111		STO - ACC to MEM
112		YTP - Y to +ALU
113
114	57	cycle #0: 15TN, ATN, CIN, CKN, CKP, DMTP, MTN, MTP, NATN, NDMTP, YTP
115	58	cycle #2: C8(?), CKM, NE(?), STO
116	59	cycle #3,#4: AUTA, AUTY
117	60
118		unknown cycle: CME, SSE, SSS
119
120	61	*/
121	62
122		#include "emu.h"
	63	#include "tms0980.h"
123	64	#include "debugger.h"
124		#include "tms0980.h"
125	65
	66	// supported types:
	67	// note: dice information assumes the orientation is pictured with RAM at the bottom-left
126	68
	69	// TMS1000
	70	// - 64x4bit RAM array at the bottom-left
	71	// - 1024x8bit ROM array at the bottom-right
	72	// * FYI, the row-selector to the left of it is laid out as:
	73	// 3,4,11,12,19,20,27,28,35,36,43,44,51,52,59,60,0,7,8,15,16,23,24,31,32,39,40,47,48,55,56,63,
	74	// 2,5,10,13,18,21,26,29,34,37,42,45,50,53,58,61,1,6,9,14,17,22,25,30,33,38,41,46,49,54,57,62
	75	// - 30-term microinstructions PLA(mpla) at the top half, to the right of the midline, supporting 16 microinstructions
	76	// - 20-term output PLA(opla) at the top-left
	77	// - the ALU is between the opla and mpla
	78	const device_type TMS1000 = &device_creator<tms1000_cpu_device>; // 28-pin DIP, 11 R pins
	79	const device_type TMS1200 = &device_creator<tms1200_cpu_device>; // 40-pin DIP, 13 R pins
	80	const device_type TMS1070 = &device_creator<tms1070_cpu_device>; // same as tms1000, just supports higher voltage
127	81
128		const device_type TMS0980 = &device_creator<tms0980_cpu_device>;
129		const device_type TMS1000 = &device_creator<tms1000_cpu_device>;
130		const device_type TMS0970 = &device_creator<tms0970_cpu_device>;
131		const device_type TMS1070 = &device_creator<tms1070_cpu_device>;
132		const device_type TMS1200 = &device_creator<tms1200_cpu_device>;
133		const device_type TMS1270 = &device_creator<tms1270_cpu_device>;
134		const device_type TMS1100 = &device_creator<tms1100_cpu_device>;
135		const device_type TMS1300 = &device_creator<tms1300_cpu_device>;
	82	// TMS1100 is nearly the same as TMS1000, some different opcodes, and with double the RAM and ROM
	83	const device_type TMS1100 = &device_creator<tms1100_cpu_device>; // 28-pin DIP, 11 R pins
	84	const device_type TMS1300 = &device_creator<tms1300_cpu_device>; // 40-pin DIP, 16 R pins
136	85
	86	// TMS0980
	87	// - 64x9bit RAM array at the bottom-left (set up as 144x4)
	88	// - 2048x9bit ROM array at the bottom-left
	89	// - main instructions PLA at the top half, to the right of the midline
	90	// - 64-term microinstructions PLA between the RAM and ROM, supporting 20 microinstructions
	91	// - 16-term output PLA and segment PLA above the RAM
	92	const device_type TMS0980 = &device_creator<tms0980_cpu_device>; // 28-pin DIP, 9 R pins
137	93
138		#define MICRO_MASK 0x80000000
139		#define FIXED_INSTRUCTION 0x00000000
140	94
	95	// TMS0970 is a stripped-down version of the TMS0980, itself acting more like a TMS1000
	96	// - 64x4bit RAM array at the bottom-left
	97	// - 1024x8bit ROM array at the bottom-right
	98	// - main instructions PLA at the top half, to the right of the midline
	99	// - 32-term microinstructions PLA between the RAM and ROM, supporting 15 microinstructions
	100	// - 16-term output PLA and segment PLA above the RAM
	101	const device_type TMS0970 = &device_creator<tms0970_cpu_device>; // 28-pin DIP, 11 R pins
141	102
142		/* Standard/fixed intructions */
143		#define F_ILL 0x00000000
	103
	104
	105	static ADDRESS_MAP_START(program_11bit_9, AS_PROGRAM, 16, tms1xxx_cpu_device)
	106	AM_RANGE(0x000, 0xfff) AM_ROM
	107	ADDRESS_MAP_END
	108
	109	static ADDRESS_MAP_START(program_10bit_8, AS_PROGRAM, 8, tms1xxx_cpu_device)
	110	AM_RANGE(0x000, 0x3ff) AM_ROM
	111	ADDRESS_MAP_END
	112
	113	static ADDRESS_MAP_START(program_11bit_8, AS_PROGRAM, 8, tms1xxx_cpu_device)
	114	AM_RANGE(0x000, 0x7ff) AM_ROM
	115	ADDRESS_MAP_END
	116
	117
	118	static ADDRESS_MAP_START(data_64x4, AS_DATA, 8, tms1xxx_cpu_device)
	119	AM_RANGE(0x00, 0x3f) AM_RAM
	120	ADDRESS_MAP_END
	121
	122	static ADDRESS_MAP_START(data_128x4, AS_DATA, 8, tms1xxx_cpu_device)
	123	AM_RANGE(0x00, 0x7f) AM_RAM
	124	ADDRESS_MAP_END
	125
	126	static ADDRESS_MAP_START(data_64x9_as4, AS_DATA, 8, tms1xxx_cpu_device)
	127	AM_RANGE(0x00, 0x7f) AM_RAM
	128	AM_RANGE(0x80, 0x8f) AM_RAM AM_MIRROR(0x70) // DAM
	129	ADDRESS_MAP_END
	130
	131
	132	tms1000_cpu_device::tms1000_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	133	: tms1xxx_cpu_device(mconfig, TMS1000, "TMS1000", tag, owner, clock, 8, 11, 4, 6, 8, 2, 10, ADDRESS_MAP_NAME(program_10bit_8), 6, ADDRESS_MAP_NAME(data_64x4), "tms1000", __FILE__)
	134	{
	135	}
	136
	137	tms1000_cpu_device::tms1000_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char shortname, const char *source)
	138	: tms1xxx_cpu_device(mconfig, type, name, tag, owner, clock, o_pins, r_pins, k_pins, pc_bits, byte_bits, x_bits, prgwidth, program, datawidth, data, shortname, source)
	139	{
	140	}
	141
	142	tms1070_cpu_device::tms1070_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	143	: tms1000_cpu_device(mconfig, TMS1070, "TMS1070", tag, owner, clock, 8, 11, 4, 6, 8, 2, 10, ADDRESS_MAP_NAME(program_10bit_8), 6, ADDRESS_MAP_NAME(data_64x4), "tms1070", __FILE__)
	144	{
	145	}
	146
	147	tms1200_cpu_device::tms1200_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	148	: tms1000_cpu_device(mconfig, TMS1200, "TMS1200", tag, owner, clock, 8, 13, 4, 6, 8, 2, 10, ADDRESS_MAP_NAME(program_10bit_8), 6, ADDRESS_MAP_NAME(data_64x4), "tms1200", __FILE__)
	149	{
	150	}
	151
	152
	153	tms1100_cpu_device::tms1100_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	154	: tms1000_cpu_device(mconfig, TMS1100, "TMS1100", tag, owner, clock, 8, 11, 4, 6, 8, 3, 11, ADDRESS_MAP_NAME(program_11bit_8), 7, ADDRESS_MAP_NAME(data_128x4), "tms1100", __FILE__)
	155	{
	156	}
	157
	158	tms1100_cpu_device::tms1100_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char shortname, const char *source)
	159	: tms1000_cpu_device(mconfig, type, name, tag, owner, clock, o_pins, r_pins, k_pins, pc_bits, byte_bits, x_bits, prgwidth, program, datawidth, data, shortname, source)
	160	{
	161	}
	162
	163	tms1300_cpu_device::tms1300_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	164	: tms1100_cpu_device(mconfig, TMS1300, "TMS1200", tag, owner, clock, 8, 16, 4, 6, 8, 3, 11, ADDRESS_MAP_NAME(program_11bit_8), 7, ADDRESS_MAP_NAME(data_128x4), "tms1300", __FILE__)
	165	{
	166	}
	167
	168
	169	tms0970_cpu_device::tms0970_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	170	: tms1000_cpu_device(mconfig, TMS0970, "TMS0970", tag, owner, clock, 8, 11, 4, 6, 8, 2, 10, ADDRESS_MAP_NAME(program_10bit_8), 6, ADDRESS_MAP_NAME(data_64x4), "tms0970", __FILE__)
	171	{
	172	}
	173
	174	tms0970_cpu_device::tms0970_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char shortname, const char *source)
	175	: tms1000_cpu_device(mconfig, type, name, tag, owner, clock, o_pins, r_pins, k_pins, pc_bits, byte_bits, x_bits, prgwidth, program, datawidth, data, shortname, source)
	176	{
	177	}
	178
	179
	180	tms0980_cpu_device::tms0980_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	181	: tms0970_cpu_device(mconfig, TMS0980, "TMS0980", tag, owner, clock, 8, 9, 5, 7, 9, 4, 12, ADDRESS_MAP_NAME(program_11bit_9), 8, ADDRESS_MAP_NAME(data_64x9_as4), "tms0980", __FILE__)
	182	{
	183	}
	184
	185
	186
	187	static MACHINE_CONFIG_FRAGMENT(tms1000)
	188
	189	// microinstructions PLA, output PLA
	190	MCFG_PLA_ADD("mpla", 8, 16, 30)
	191	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	192	MCFG_PLA_ADD("opla", 5, 8, 20)
	193	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	194	MACHINE_CONFIG_END
	195
	196	machine_config_constructor tms1000_cpu_device::device_mconfig_additions() const
	197	{
	198	return MACHINE_CONFIG_NAME(tms1000);
	199	}
	200
	201
	202	static MACHINE_CONFIG_FRAGMENT(tms0970)
	203
	204	// main opcodes PLA, microinstructions PLA, output PLA, segment PLA
	205	MCFG_PLA_ADD("ipla", 8, 15, 18)
	206	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	207	MCFG_PLA_ADD("mpla", 5, 15, 32)
	208	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	209	MCFG_PLA_ADD("opla", 4, 8, 16)
	210	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	211	MCFG_PLA_ADD("spla", 3, 8, 8)
	212	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	213	MACHINE_CONFIG_END
	214
	215	machine_config_constructor tms0970_cpu_device::device_mconfig_additions() const
	216	{
	217	return MACHINE_CONFIG_NAME(tms0970);
	218	}
	219
	220
	221	static MACHINE_CONFIG_FRAGMENT(tms0980)
	222
	223	// main opcodes PLA, microinstructions PLA, output PLA, segment PLA
	224	MCFG_PLA_ADD("ipla", 9, 22, 24)
	225	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	226	MCFG_PLA_ADD("mpla", 6, 20, 64)
	227	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	228	MCFG_PLA_ADD("opla", 4, 8, 16)
	229	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	230	MCFG_PLA_ADD("spla", 3, 8, 8)
	231	MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
	232	MACHINE_CONFIG_END
	233
	234	machine_config_constructor tms0980_cpu_device::device_mconfig_additions() const
	235	{
	236	return MACHINE_CONFIG_NAME(tms0980);
	237	}
	238
	239
	240
	241	offs_t tms1000_cpu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	242	{
	243	extern CPU_DISASSEMBLE(tms1000);
	244	return CPU_DISASSEMBLE_NAME(tms1000)(this, buffer, pc, oprom, opram, options);
	245	}
	246
	247	offs_t tms1100_cpu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	248	{
	249	extern CPU_DISASSEMBLE(tms1100);
	250	return CPU_DISASSEMBLE_NAME(tms1100)(this, buffer, pc, oprom, opram, options);
	251	}
	252
	253	offs_t tms0980_cpu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	254	{
	255	extern CPU_DISASSEMBLE(tms0980);
	256	return CPU_DISASSEMBLE_NAME(tms0980)(this, buffer, pc, oprom, opram, options);
	257	}
	258
	259
	260	void tms1000_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
	261	{
	262	switch (entry.index())
	263	{
	264	case STATE_GENPC:
	265	string.printf("%03X", (m_pa << 6) \| m_pc);
	266	break;
	267	}
	268	}
	269
	270	void tms1100_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
	271	{
	272	switch (entry.index())
	273	{
	274	case STATE_GENPC:
	275	string.printf("%03X", (m_ca << 10) \| (m_pa << 6) \| m_pc);
	276	break;
	277	}
	278	}
	279
	280	void tms0980_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
	281	{
	282	switch (entry.index())
	283	{
	284	case STATE_GENPC:
	285	string.printf("%03X", ((m_pa << 7) \| m_pc) << 1);
	286	break;
	287	}
	288	}
	289
	290
	291
	292	/* Standard/fixed instructions */
144	293	#define F_BR 0x00000001
145	294	#define F_CALL 0x00000002
146	295	#define F_CLO 0x00000004
r242128	r242129
160	309	#define F_SEAC 0x00010000
161	310	#define F_SETR 0x00020000
162	311	#define F_TDO 0x00040000
	312	#define F_XDA 0x00080000
163	313
164
165	314	/* Microinstructions */
166	315	#define M_15TN 0x00000001
167	316	#define M_ATN 0x00000002
r242128	r242129
186	335	#define M_YTP 0x00100000
187	336
188	337
189		/* instructions built from microinstructions */
190		#define I_AC1AC ( MICRO_MASK \| M_CKP \| M_ATN \| M_CIN \| M_C8 \| M_AUTA )
191		#define I_A6AAC I_ACACC
192		#define I_A8AAC I_ACACC
193		#define I_A10AAC I_ACACC
194		#define I_ACACC ( MICRO_MASK \| M_CKP \| M_ATN \| M_C8 \| M_AUTA )
195		#define I_ACNAA ( MICRO_MASK \| M_CKP \| M_NATN \| M_AUTA )
196		#define I_ALEC ( MICRO_MASK \| M_CKP \| M_NATN \| M_CIN \| M_C8 )
197		#define I_ALEM ( MICRO_MASK \| M_MTP \| M_NATN \| M_CIN \| M_C8 )
198		#define I_AMAAC ( MICRO_MASK \| M_MTP \| M_ATN \| M_C8 \| M_AUTA )
199		#define I_CCLA ( MICRO_MASK \| M_AUTA \| M_SSS )
200		#define I_CLA ( MICRO_MASK \| M_AUTA )
201		#define I_CPAIZ ( MICRO_MASK \| M_NATN \| M_CIN \| M_C8 \| M_AUTA )
202		#define I_CTMDYN ( MICRO_MASK \| M_YTP \| M_15TN \| M_C8 \| M_AUTY \| M_CME )
203		#define I_DAN ( MICRO_MASK \| M_CKP \| M_ATN \| M_CIN \| M_C8 \| M_AUTA )
204		#define I_DMAN ( MICRO_MASK \| M_MTP \| M_15TN \| M_C8 \| M_AUTA )
205		#define I_DMEA ( MICRO_MASK \| M_MTP \| M_DMTP \| M_SSS \| M_AUTA )
206		#define I_NDMEA ( MICRO_MASK \| M_MTN \| M_NDMTP \| M_SSS \| M_AUTA )
207		#define I_DNAA ( MICRO_MASK \| M_DMTP \| M_NATN \| M_SSS \| M_AUTA )
208		#define I_DYN ( MICRO_MASK \| M_YTP \| M_15TN \| M_C8 \| M_AUTY )
209		#define I_IA ( MICRO_MASK \| M_ATN \| M_CIN \| M_AUTA )
210		#define I_IMAC ( MICRO_MASK \| M_MTP \| M_CIN \| M_C8 \| M_AUTA )
211		#define I_IYC ( MICRO_MASK \| M_YTP \| M_CIN \| M_C8 \| M_AUTY )
212		#define I_KNEZ ( MICRO_MASK \| M_CKP \| M_NE )
213		#define I_MNEA ( MICRO_MASK \| M_MTP \| M_ATN \| M_NE )
214		#define I_MNEZ ( MICRO_MASK \| M_MTP \| M_NE )
215		#define I_SAMAN ( MICRO_MASK \| M_MTP \| M_NATN \| M_CIN \| M_C8 \| M_AUTA )
216		#define I_SETR ( MICRO_MASK \| M_YTP \| M_15TN \| M_AUTY \| M_C8 )
217		#define I_TAM ( MICRO_MASK \| M_STO )
218		#define I_TAMACS ( MICRO_MASK \| M_STO \| M_ATN \| M_CKP \| M_AUTA \| M_SSE )
219		#define I_TAMDYN ( MICRO_MASK \| M_STO \| M_YTP \| M_15TN \| M_AUTY \| M_C8 )
220		#define I_TAMIY ( MICRO_MASK \| M_STO \| M_YTP \| M_CIN \| M_AUTY )
221		#define I_TAMIYC ( MICRO_MASK \| M_STO \| M_YTP \| M_CIN \| M_C8 \| M_AUTY )
222		#define I_TAMZA ( MICRO_MASK \| M_STO \| M_AUTA )
223		#define I_TAY ( MICRO_MASK \| M_ATN \| M_AUTY )
224		#define I_TBIT ( MICRO_MASK \| M_CKP \| M_CKN \| M_MTP \| M_NE )
225		#define I_TCY ( MICRO_MASK \| M_CKP \| M_AUTY )
226		#define I_TCMIY ( MICRO_MASK \| M_CKM \| M_YTP \| M_CIN \| M_AUTY )
227		#define I_TKA ( MICRO_MASK \| M_CKP \| M_AUTA )
228		#define I_TKM ( MICRO_MASK \| M_CKM )
229		#define I_TMA ( MICRO_MASK \| M_MTP \| M_AUTA )
230		#define I_TMY ( MICRO_MASK \| M_MTP \| M_AUTY )
231		#define I_TYA ( MICRO_MASK \| M_YTP \| M_AUTA )
232		#define I_XDA ( MICRO_MASK \| M_DMTP \| M_AUTA \| M_STO )
233		#define I_XMA ( MICRO_MASK \| M_MTP \| M_STO \| M_AUTA )
234		#define I_YMCY ( MICRO_MASK \| M_CIN \| M_YTP \| M_CKN \| M_AUTY )
235		#define I_YNEA ( MICRO_MASK \| M_YTP \| M_ATN \| M_NE )
236		#define I_YNEC ( MICRO_MASK \| M_YTP \| M_CKN \| M_NE )
237	338
	339	//-------------------------------------------------
	340	// device_start - device-specific startup
	341	//-------------------------------------------------
238	342
239		static const UINT8 tms0980_c2_value[4] = { 0, 2, 1, 3 };
240		static const UINT8 tms0980_c3_value[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
241		static const UINT8 tms0980_c4_value[16] = { 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF };
242		static const UINT8 tms0980_bit_value[4] = { 1, 4, 2, 8 };
243		static const UINT8 tms0980_nbit_value[4] = { 0xE, 0xB, 0xD, 0x7 };
244
245
246		static const UINT32 tms0980_decode[512] =
	343	enum
247	344	{
248		/* 0x000 */
249		F_COMX, I_ALEM, I_YNEA, I_XMA, I_DYN, I_IYC, I_CLA, I_DMAN,
250		I_TKA, I_MNEA, I_TKM, F_ILL, F_ILL, F_SETR, I_KNEZ, F_ILL,
251		I_DMEA, I_DNAA, I_CCLA, I_NDMEA, F_ILL, I_AMAAC, F_ILL, F_ILL,
252		I_CTMDYN, I_XDA, F_ILL, F_ILL, F_ILL, F_ILL, F_ILL, F_ILL,
253		I_TBIT, I_TBIT, I_TBIT, I_TBIT, F_ILL, F_ILL, F_ILL, F_ILL,
254		I_TAY, I_TMA, I_TMY, I_TYA, I_TAMDYN, I_TAMIYC, I_TAMZA, I_TAM,
255		I_SAMAN, I_CPAIZ, I_IMAC, I_MNEZ, F_ILL, F_ILL, F_ILL, F_ILL,
256		I_TCY, I_YNEC, I_TCMIY, I_ACACC, I_ACNAA, I_TAMACS, I_ALEC, I_YMCY,
257		/* 0x040 */
258		I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY,
259		I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY,
260		I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC,
261		I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC,
262		I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY,
263		I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY,
264		I_ACACC, I_ACACC, I_ACACC, I_ACACC, I_ACACC, I_ACACC, I_ACACC, I_ACACC,
265		I_ACACC, I_ACACC, I_ACACC, I_ACACC, I_ACACC, I_ACACC, I_ACACC, I_ACACC,
266		/* 0x080 */
267		F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP,
268		F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP,
269		F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX,
270		F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX,
271		F_SBIT, F_SBIT, F_SBIT, F_SBIT, F_RBIT, F_RBIT, F_RBIT, F_RBIT,
272		F_ILL, F_ILL, F_ILL, F_ILL, F_ILL, F_ILL, F_ILL, F_ILL,
273		F_TDO, F_SAL, F_COMX8, F_SBL, F_REAC, F_SEAC, F_OFF, F_ILL,
274		F_ILL, F_ILL, F_ILL, F_ILL, F_ILL, F_ILL, F_ILL, F_RETN,
275		/* 0x0c0 */
276		I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA,
277		I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA, I_ACNAA,
278		I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS,
279		I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS, I_TAMACS,
280		I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC,
281		I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC,
282		I_YMCY, I_YMCY, I_YMCY, I_YMCY, I_YMCY, I_YMCY, I_YMCY, I_YMCY,
283		I_YMCY, I_YMCY, I_YMCY, I_YMCY, I_YMCY, I_YMCY, I_YMCY, I_YMCY,
284		/* 0x100 */
285		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
286		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
287		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
288		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
289		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
290		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
291		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
292		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
293		/* 0x140 */
294		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
295		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
296		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
297		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
298		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
299		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
300		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
301		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
302		/* 0x180 */
303		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
304		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
305		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
306		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
307		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
308		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
309		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
310		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
311		/* 0x1c0 */
312		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
313		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
314		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
315		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
316		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
317		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
318		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
319		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL
	345	TMS0980_PC=1, TMS0980_SR, TMS0980_PA, TMS0980_PB,
	346	TMS0980_A, TMS0980_X, TMS0980_Y, TMS0980_STATUS
320	347	};
321	348
322
323		static const UINT32 tms1000_default_decode[256] =
	349	void tms1xxx_cpu_device::device_start()
324	350	{
325		/* 0x00 */
326		F_COMX, I_A8AAC, I_YNEA, I_TAM, I_TAMZA, I_A10AAC, I_A6AAC, I_DAN,
327		I_TKA, I_KNEZ, F_TDO, F_CLO, F_RSTR, F_SETR, I_IA, F_RETN,
328		F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP,
329		F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP,
330		/* 0x20 */
331		I_TAMIY, I_TMA, I_TMY, I_TYA, I_TAY, I_AMAAC, I_MNEZ, I_SAMAN,
332		I_IMAC, I_ALEM, I_DMAN, I_IYC, I_DYN, I_CPAIZ, I_XMA, I_CLA,
333		F_SBIT, F_SBIT, F_SBIT, F_SBIT, F_RBIT, F_RBIT, F_RBIT, F_RBIT,
334		I_TBIT, I_TBIT, I_TBIT, I_TBIT, F_LDX, F_LDX, F_LDX, F_LDX,
335		/* 0x40 */
336		I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY,
337		I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY,
338		I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC,
339		I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC,
340		/* 0x60 */
341		I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY,
342		I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY,
343		I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC,
344		I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC, I_ALEC,
345		/* 0x80 */
346		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
347		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
348		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
349		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
350		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
351		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
352		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
353		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
354		/* 0xC0 */
355		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
356		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
357		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
358		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
359		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
360		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
361		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
362		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
363		};
	351	m_program = &space(AS_PROGRAM);
	352	m_data = &space(AS_DATA);
364	353
	354	m_read_k.resolve_safe(0);
	355	m_write_o.resolve_safe();
	356	m_write_r.resolve_safe();
	357	m_power_off.resolve_safe();
365	358
366		static const UINT32 tms1100_default_decode[256] =
367		{
368		/* 0x00 */
369		I_MNEA, I_ALEM, I_YNEA, I_XMA, I_DYN, I_IYC, I_AMAAC, I_DMAN,
370		I_TKA, F_COMX, F_TDO, F_COMC, F_RSTR, F_SETR, I_KNEZ, F_RETN,
371		F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP,
372		F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP, F_LDP,
373		/* 0x20 */
374		I_TAY, I_TMA, I_TMY, I_TYA, I_TAMDYN, I_TAMIYC, I_TAMZA, I_TAM,
375		F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX, F_LDX,
376		F_SBIT, F_SBIT, F_SBIT, F_SBIT, F_RBIT, F_RBIT, F_RBIT, F_RBIT,
377		I_TBIT, I_TBIT, I_TBIT, I_TBIT, I_SAMAN, I_CPAIZ, I_IMAC, I_MNEZ,
378		/* 0x40 */
379		I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY,
380		I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY, I_TCY,
381		I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC,
382		I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC, I_YNEC,
383		/* 0x60 */
384		I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY,
385		I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY, I_TCMIY,
386		I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC,
387		I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC, I_AC1AC, I_CLA,
388		/* 0x80 */
389		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
390		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
391		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
392		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
393		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
394		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
395		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
396		F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR, F_BR,
397		/* 0xC0 */
398		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
399		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
400		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
401		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
402		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
403		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
404		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
405		F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL, F_CALL,
406		};
	359	m_o_mask = (1 << m_o_pins) - 1;
	360	m_r_mask = (1 << m_r_pins) - 1;
	361	m_k_mask = (1 << m_k_pins) - 1;
	362	m_pc_mask = (1 << m_pc_bits) - 1;
	363	m_x_mask = (1 << m_x_bits) - 1;
	364
	365	// zerofill
	366	m_pc = 0;
	367	m_sr = 0;
	368	m_pa = 0;
	369	m_pb = 0;
	370	m_a = 0;
	371	m_x = 0;
	372	m_y = 0;
	373	m_ca = 0;
	374	m_cb = 0;
	375	m_cs = 0;
	376	m_r = 0;
	377	m_o = 0;
	378	m_cki_bus = 0;
	379	m_c4 = 0;
	380	m_p = 0;
	381	m_n = 0;
	382	m_adder_out = 0;
	383	m_carry_in = 0;
	384	m_carry_out = 0;
	385	m_status = 0;
	386	m_status_latch = 0;
	387	m_eac = 0;
	388	m_clatch = 0;
	389	m_add = 0;
	390	m_bl = 0;
407	391
	392	m_ram_in = 0;
	393	m_dam_in = 0;
	394	m_ram_out = 0;
	395	m_ram_address = 0;
	396	m_rom_address = 0;
	397	m_opcode = 0;
	398	m_fixed = 0;
	399	m_micro = 0;
	400	m_subcycle = 0;
408	401
409		static ADDRESS_MAP_START(program_11bit_9, AS_PROGRAM, 16, tms1xxx_cpu_device)
410		AM_RANGE( 0x000, 0xfff ) AM_ROM
411		ADDRESS_MAP_END
	402	// register for savestates
	403	save_item(NAME(m_pc));
	404	save_item(NAME(m_sr));
	405	save_item(NAME(m_pa));
	406	save_item(NAME(m_pb));
	407	save_item(NAME(m_a));
	408	save_item(NAME(m_x));
	409	save_item(NAME(m_y));
	410	save_item(NAME(m_ca));
	411	save_item(NAME(m_cb));
	412	save_item(NAME(m_cs));
	413	save_item(NAME(m_r));
	414	save_item(NAME(m_o));
	415	save_item(NAME(m_cki_bus));
	416	save_item(NAME(m_c4));
	417	save_item(NAME(m_p));
	418	save_item(NAME(m_n));
	419	save_item(NAME(m_adder_out));
	420	save_item(NAME(m_carry_in));
	421	save_item(NAME(m_carry_out));
	422	save_item(NAME(m_status));
	423	save_item(NAME(m_status_latch));
	424	save_item(NAME(m_eac));
	425	save_item(NAME(m_clatch));
	426	save_item(NAME(m_add));
	427	save_item(NAME(m_bl));
412	428
	429	save_item(NAME(m_ram_in));
	430	save_item(NAME(m_dam_in));
	431	save_item(NAME(m_ram_out));
	432	save_item(NAME(m_ram_address));
	433	save_item(NAME(m_rom_address));
	434	save_item(NAME(m_opcode));
	435	save_item(NAME(m_fixed));
	436	save_item(NAME(m_micro));
	437	save_item(NAME(m_subcycle));
413	438
414		static ADDRESS_MAP_START(program_10bit_8, AS_PROGRAM, 8, tms1xxx_cpu_device)
415		AM_RANGE( 0x000, 0x3ff ) AM_ROM
416		ADDRESS_MAP_END
	439	// register state for debugger
	440	state_add(TMS0980_PC, "PC", m_pc ).callimport().callexport().formatstr("%02X");
	441	state_add(TMS0980_SR, "SR", m_sr ).callimport().callexport().formatstr("%01X");
	442	state_add(TMS0980_PA, "PA", m_pa ).callimport().callexport().formatstr("%01X");
	443	state_add(TMS0980_PB, "PB", m_pb ).callimport().callexport().formatstr("%01X");
	444	state_add(TMS0980_A, "A", m_a ).callimport().callexport().formatstr("%01X");
	445	state_add(TMS0980_X, "X", m_x ).callimport().callexport().formatstr("%01X");
	446	state_add(TMS0980_Y, "Y", m_y ).callimport().callexport().formatstr("%01X");
	447	state_add(TMS0980_STATUS, "STATUS", m_status).callimport().callexport().formatstr("%01X");
417	448
	449	state_add(STATE_GENPC, "curpc", m_pc).callimport().callexport().formatstr("%8s").noshow();
	450	state_add(STATE_GENFLAGS, "GENFLAGS", m_sr).callimport().callexport().formatstr("%8s").noshow();
418	451
419		static ADDRESS_MAP_START(program_11bit_8, AS_PROGRAM, 8, tms1xxx_cpu_device)
420		AM_RANGE( 0x000, 0x7ff ) AM_ROM
421		ADDRESS_MAP_END
	452	m_icountptr = &m_icount;
	453	}
422	454
423	455
424		static ADDRESS_MAP_START(data_64x4, AS_DATA, 8, tms1xxx_cpu_device)
425		AM_RANGE( 0x00, 0x3f ) AM_RAM
426		ADDRESS_MAP_END
427	456
	457	//-------------------------------------------------
	458	// device_reset - device-specific reset
	459	//-------------------------------------------------
428	460
429		static ADDRESS_MAP_START(data_128x4, AS_DATA, 8, tms1xxx_cpu_device)
430		AM_RANGE( 0x00, 0x7f ) AM_RAM
431		ADDRESS_MAP_END
	461	void tms1xxx_cpu_device::device_reset()
	462	{
	463	m_pa = 0xf;
	464	m_pb = 0xf;
	465	m_pc = 0;
	466	m_ca = 0;
	467	m_cb = 0;
	468	m_cs = 0;
432	469
	470	m_eac = 0;
	471	m_bl = 0;
	472	m_add = 0;
433	473
434		static ADDRESS_MAP_START(data_64x9_as4, AS_DATA, 8, tms1xxx_cpu_device)
435		AM_RANGE( 0x00, 0x8f ) AM_RAM
436		AM_RANGE( 0x90, 0xff ) AM_NOP
437		ADDRESS_MAP_END
	474	m_opcode = 0;
	475	m_micro = 0;
	476	m_fixed = 0;
438	477
	478	m_subcycle = 0;
439	479
440		void tms1xxx_cpu_device::device_start()
	480	// clear outputs
	481	m_r = 0;
	482	m_write_r(0, m_r & m_r_mask, 0xffff);
	483	write_o_output(0);
	484	m_write_r(0, m_r & m_r_mask, 0xffff);
	485	}
	486
	487
	488	void tms1000_cpu_device::device_reset()
441	489	{
442		m_program = &space( AS_PROGRAM );
443		m_data = &space( AS_DATA );
	490	// common reset
	491	tms1xxx_cpu_device::device_reset();
	492
	493	// pre-decode instructionset
	494	m_fixed_decode.resize_and_clear(0x100);
	495	m_micro_decode.resize_and_clear(0x100);
	496
	497	for (int op = 0; op < 0x100; op++)
	498	{
	499	// _____ _____ ______ _____ ______ _____ _____ _____ _____
	500	const UINT32 md[16] = { M_STSL, M_AUTY, M_AUTA, M_CIN, M_C8, M_NE, M_CKN, M_15TN, M_MTN, M_NATN, M_ATN, M_MTP, M_YTP, M_CKP, M_CKM, M_STO };
	501	UINT16 mask = m_mpla->read(op);
	502	mask ^= 0x3fc8; // invert active-negative
	503
	504	for (int bit = 0; bit < 16; bit++)
	505	if (mask & (1 << bit))
	506	m_micro_decode[op] \|= md[bit];
	507	}
444	508
445		m_read_k.resolve_safe(0xff);
446		m_write_o.resolve_safe();
447		m_write_r.resolve_safe();
	509	// the fixed instruction set is not programmable
	510	m_fixed_decode[0x00] = F_COMX;
	511	m_fixed_decode[0x0a] = F_TDO;
	512	m_fixed_decode[0x0b] = F_CLO;
	513	m_fixed_decode[0x0c] = F_RSTR;
	514	m_fixed_decode[0x0d] = F_SETR;
	515	m_fixed_decode[0x0f] = F_RETN;
	516
	517	for (int i = 0x10; i < 0x20; i++) m_fixed_decode[i] = F_LDP;
	518	for (int i = 0x30; i < 0x34; i++) m_fixed_decode[i] = F_SBIT;
	519	for (int i = 0x34; i < 0x38; i++) m_fixed_decode[i] = F_RBIT;
	520	for (int i = 0x3c; i < 0x40; i++) m_fixed_decode[i] = F_LDX;
448	521
449		save_item( NAME(m_prev_pc) );
450		save_item( NAME(m_prev_pa) );
451		save_item( NAME(m_pc) );
452		save_item( NAME(m_pa) );
453		save_item( NAME(m_sr) );
454		save_item( NAME(m_pb) );
455		save_item( NAME(m_a) );
456		save_item( NAME(m_x) );
457		save_item( NAME(m_y) );
458		save_item( NAME(m_dam) );
459		save_item( NAME(m_ca) );
460		save_item( NAME(m_cb) );
461		save_item( NAME(m_cs) );
462		save_item( NAME(m_r) );
463		save_item( NAME(m_o) );
464		save_item( NAME(m_cki_bus) );
465		save_item( NAME(m_p) );
466		save_item( NAME(m_n) );
467		save_item( NAME(m_adder_result) );
468		save_item( NAME(m_carry_in) );
469		save_item( NAME(m_status) );
470		save_item( NAME(m_status_latch) );
471		save_item( NAME(m_special_status) );
472		save_item( NAME(m_call_latch) );
473		save_item( NAME(m_add_latch) );
474		save_item( NAME(m_branch_latch) );
475		save_item( NAME(m_subcycle) );
476		save_item( NAME(m_ram_address) );
477		save_item( NAME(m_ram_data) );
478		save_item( NAME(m_rom_address) );
479		save_item( NAME(m_opcode) );
480		save_item( NAME(m_decode) );
	522	for (int i = 0x80; i < 0xc0; i++) m_fixed_decode[i] = F_BR;
	523	for (int i = 0xc0; i < 0x100; i++) m_fixed_decode[i] = F_CALL;
	524	}
481	525
482		// Register state for debugger
483		state_add( TMS0980_PC, "PC", m_pc ).callimport().callexport().formatstr("%02X");
484		state_add( TMS0980_SR, "SR", m_sr ).callimport().callexport().formatstr("%01X");
485		state_add( TMS0980_PA, "PA", m_pa ).callimport().callexport().formatstr("%01X");
486		state_add( TMS0980_PB, "PB", m_pb ).callimport().callexport().formatstr("%01X");
487		state_add( TMS0980_A, "A", m_a ).callimport().callexport().formatstr("%01X");
488		state_add( TMS0980_X, "X", m_x ).callimport().callexport().formatstr("%01X");
489		state_add( TMS0980_Y, "Y", m_y ).callimport().callexport().formatstr("%01X");
490		state_add( TMS0980_STATUS, "STATUS", m_status ).callimport().callexport().formatstr("%01X");
	526	void tms1100_cpu_device::device_reset()
	527	{
	528	tms1000_cpu_device::device_reset();
	529
	530	// small differences in 00-3f area
	531	m_fixed_decode[0x00] = 0;
	532	m_fixed_decode[0x09] = F_COMX8; // !
	533	m_fixed_decode[0x0b] = F_COMC;
491	534
492		state_add(STATE_GENPC, "curpc", m_pc).callimport().callexport().formatstr("%8s").noshow();
493		state_add(STATE_GENFLAGS, "GENFLAGS", m_sr).callimport().callexport().formatstr("%8s").noshow();
	535	for (int i = 0x28; i < 0x30; i++) m_fixed_decode[i] = F_LDX;
	536	for (int i = 0x3c; i < 0x40; i++) m_fixed_decode[i] = 0;
	537	}
494	538
495		m_icountptr = &m_icount;
	539
	540	void tms0970_cpu_device::device_reset()
	541	{
	542	// common reset
	543	tms1xxx_cpu_device::device_reset();
	544
	545	// pre-decode instructionset
	546	m_fixed_decode.resize_and_clear(0x100);
	547	m_micro_decode.resize_and_clear(0x100);
	548
	549	for (int op = 0; op < 0x100; op++)
	550	{
	551	// upper half of the opcodes is always branch/call
	552	if (op & 0x80)
	553	m_fixed_decode[op] = (op & 0x40) ? F_CALL: F_BR;
	554
	555	// 5 output bits select a microinstruction index
	556	UINT32 imask = m_ipla->read(op);
	557	UINT8 msel = imask & 0x1f;
	558
	559	// but if (from bottom to top) term 1 is active and output bit 5 is 0, R2,R4-R7 directly select a microinstruction index
	560	if (imask & 0x40 && (imask & 0x20) == 0)
	561	msel = (op & 0xf) \| (op >> 1 & 0x10);
	562
	563	msel = BITSWAP8(msel,7,6,5,0,1,2,3,4); // lines are reversed
	564	UINT32 mmask = m_mpla->read(msel);
	565	mmask ^= 0x09fe; // invert active-negative
	566
	567	// _____ _____ _____ _____ ______ _____ ______ _____ _____
	568	const UINT32 md[15] = { M_CKM, M_CKP, M_YTP, M_MTP, M_ATN, M_NATN, M_MTN, M_15TN, M_CKN, M_NE, M_C8, M_CIN, M_AUTA, M_AUTY, M_STO };
	569
	570	for (int bit = 0; bit < 15; bit++)
	571	if (mmask & (1 << bit))
	572	m_micro_decode[op] \|= md[bit];
	573
	574	// the other ipla terms each select a fixed instruction
	575	const UINT32 id[8] = { F_LDP, F_TDO, F_COMX, F_LDX, F_SBIT, F_RBIT, F_SETR, F_RETN };
	576
	577	for (int bit = 0; bit < 8; bit++)
	578	if (imask & (0x80 << bit))
	579	m_fixed_decode[op] \|= id[bit];
	580	}
496	581	}
497	582
498	583
499		~~void~~ tms~~1xxx~~_cpu_device::device_reset()
	584	UINT32 tms0980_cpu_device::decode_micro(UINT8 sel)
500	585	{
501		m_pa = 0xF;
502		m_pb = 0xF;
503		m_pc = 0;
504		m_dam = 0;
505		m_ca = 0;
506		m_cb = 0;
507		m_cs = 0;
508		m_subcycle = 0;
509		m_status = 1;
510		m_status_latch = 0;
511		m_call_latch = 0;
512		m_add_latch = 0;
513		m_branch_latch = 0;
514		m_r = 0;
515		m_o = 0;
516		m_ram_address = 0;
517		m_decode = F_ILL;
518		m_opcode = 0;
	586	UINT32 decode = 0;
	587
	588	sel = BITSWAP8(sel,7,6,0,1,2,3,4,5); // lines are reversed
	589	UINT32 mask = m_mpla->read(sel);
	590	mask ^= 0x43fc3; // invert active-negative
	591
	592	// _______ ______ _____ _____ _____ _____ ______ _____ ______ _____ _____
	593	const UINT32 md[20] = { M_NDMTP, M_DMTP, M_AUTY, M_AUTA, M_CKM, M_SSE, M_CKP, M_YTP, M_MTP, M_ATN, M_NATN, M_MTN, M_15TN, M_CKN, M_NE, M_C8, M_SSS, M_CME, M_CIN, M_STO };
	594
	595	for (int bit = 0; bit < 20; bit++)
	596	if (mask & (1 << bit))
	597	decode \|= md[bit];
	598
	599	return decode;
519	600	}
520	601
	602	void tms0980_cpu_device::device_reset()
	603	{
	604	// common reset
	605	tms1xxx_cpu_device::device_reset();
	606
	607	// pre-decode instructionset
	608	m_fixed_decode.resize_and_clear(0x200);
	609	m_micro_decode.resize_and_clear(0x200);
521	610
522		/*
523		The program counter is implemented using PRNG logic and gets incremented as follows:
	611	for (int op = 0; op < 0x200; op++)
	612	{
	613	// upper half of the opcodes is always branch/call
	614	if (op & 0x100)
	615	m_fixed_decode[op] = (op & 0x80) ? F_CALL: F_BR;
	616
	617	UINT32 imask = m_ipla->read(op);
524	618
525		00, 01, 03, 07, 0F, 1F, 3F, 3E,
526		3D, 3B, 37, 2F, 1E, 3C, 39, 33
527		27, 0E, 1D, 3A, 35, 2B, 16, 2C,
528		18, 30, 21, 02, 05, 0B, 17, 2E,
529		1C, 38, 31, 23, 06, 0D, 1B, 36,
530		2D, 1A, 34, 29, 12, 24, 08, 11,
531		22, 04, 09, 13, 26, 0C, 19, 32,
532		25, 0A, 15, 2A, 14, 28, 10, 20
	619	// 6 output bits select a microinstruction index
	620	m_micro_decode[op] = decode_micro(imask & 0x3f);
	621
	622	// the other ipla terms each select a fixed instruction
	623	const UINT32 id[15] = { F_LDP, F_SBL, F_OFF, F_RBIT, F_SAL, F_XDA, F_REAC, F_SETR, F_RETN, F_SBIT, F_TDO, F_COMX8, F_COMX, F_LDX, F_SEAC };
	624
	625	for (int bit = 0; bit < 15; bit++)
	626	if (imask & (0x80 << bit))
	627	m_fixed_decode[op] \|= id[bit];
	628	}
	629
	630	// like on TMS0970, one of the terms directly select a microinstruction index (via R4-R8),
	631	// but it can't be pre-determined when it's active
	632	m_micro_direct.resize_and_clear(0x40);
533	633
534		There is also a strange address (AD) to location (LOC) mapping performed by the
535		tms1000 family.
	634	for (int op = 0; op < 0x40; op++)
	635	m_micro_direct[op] = decode_micro(op);
	636	}
536	637
537		From tms1000 family pdf:
538		AD LOC
539		000 000000 003 000011
540		001 000001 004 000100
541		003 000011 00C 001100
542		007 000111 01C 011100
543		00F 001111 03C 111100
544		01F 011111 03F 111111
545		03F 111111 03E 111110
546		03E 111110 039 111001
547		03D 111101 036 110110
548		03B 111011 02E 101110
549		037 110111 01E 011110
550		02F 101111 03D 111101
551		01E 011110 038 111000
552		03C 111100 031 110001
553		039 111001 026 100110
554		033 110011 00E 001110
555		027 100111 01D 011101
556		00E 001110 03B 111011
557		01D 011101 037 110111
558		03A 111010 029 101001
559		035 110101 016 010110
560		02B 101011 02D 101101
561		016 010110 018 011000
562		02C 101100 032 110010
563		018 011000 020 100000
564		030 110000 001 000001
565		021 100001 005 000101
566		002 000010 00B 001011
567		005 000101 014 010100
568		00B 001011 02C 101100
569		017 010111 01F 011111
570		02E 101110 03A 111010
571		01C 011100 030 110000
572		038 111000 021 100001
573		031 110001 006 000110
574		023 100011 00D 001101
575		006 000110 01B 011011
576		00D 001101 034 110100
577		01B 011011 02F 101111
578		036 110110 019 011001
579		02D 101101 035 110101
580		01A 011010 028 101000
581		034 110100 011 010001
582		029 101001 025 100101
583		012 010010 008 001000
584		024 100100 012 010010
585		008 001000 023 100011
586		011 010001 007 000111
587		022 100010 00A 001010
588		004 000100 013 010011
589		009 001001 024 100100
590		013 010011 00F 001111
591		026 100110 01A 011010
592		00C 001100 033 110011
593		019 011001 027 100111
594		032 110010 009 001001
595		025 100101 015 010101
596		00A 001010 02B 101011
597		015 010101 017 010111
598		02A 101010 02A 101010
599		014 010100 010 010000
600		028 101000 022 100010
601		010 010000 000 000000
602		020 100000 002 000010
603	638
604		The following formula seems to be used to decode a program counter
605		into a rom address:
606		location{5:2} = pc{3:0}
607		location{1:0} = ( pc{5:4} == 00 && pc{0} == 0 ) => 11
608		( pc{5:4} == 00 && pc{0} == 1 ) => 00
609		( pc{5:4} == 01 && pc{0} == 0 ) => 00
610		( pc{5:4} == 01 && pc{0} == 1 ) => 11
611		( pc{5:4} == 10 && pc{0} == 0 ) => 10
612		( pc{5:4} == 10 && pc{0} == 1 ) => 01
613		( pc{5:4} == 11 && pc{0} == 0 ) => 01
614		( pc{5:4} == 11 && pc{0} == 1 ) => 10
615	639
616		*/
617		static const UINT8 tms1000_next_pc[64] =
	640
	641
	642	void tms1xxx_cpu_device::next_pc()
618	643	{
619		0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,
620		0x20, 0x22, 0x24, 0x26, 0x28, 0x2A, 0x2C, 0x2E, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3A, 0x3C, 0x3F,
621		0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1A, 0x1C, 0x1E,
622		0x21, 0x23, 0x25, 0x27, 0x29, 0x2B, 0x2D, 0x2F, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3B, 0x3D, 0x3E,
623		};
	644	// The program counter is a LFSR. To put it simply, the feedback bit is a XOR of the two highest bits,
	645	// but it makes an exception when all low bits are set (eg. in TMS1000 case, when PC is 0x1f or 0x3f).
	646	int high = 1 << (m_pc_bits - 1);
	647	int fb = (m_pc << 1 & high) == (m_pc & high);
624	648
625		/* emulator for the program counter increment on the tms0980/tmc0980 mcu;
626		see patent 4064554 figure 19 (on page 13) for an explanation of feedback:
	649	if (m_pc == (m_pc_mask >> 1))
	650	fb = 1;
	651	else if (m_pc == m_pc_mask)
	652	fb = 0;
	653
	654	m_pc = (m_pc << 1 \| fb) & m_pc_mask;
	655	}
627	656
628		nand324 = NAND of PC0 through pc4, i.e. output is true if ((pc&0x1f) != 0x1f)
629		nand323 = NAND of pc5, pc6 and nand324
630		i.e. output is true, if ((pc&0x1f)==0x1f) \|\| pc5 is 0 \|\| pc 6 is 0
631		or321 = OR of pc5 and pc6, i.e. output is true if ((pc&0x60) != 0)
632		nand322 = NAND of pc0 through pc5 plus /pc6,
633		i.e. output is true if (pc != 0x3f)
634		nand325 = nand of nand323, or321 and nand322
635		This one is complex:
636		/ or321 means if pc&0x60 is zero, output MUST be true
637		\ nand323 means if (pc&0x60=0x60) && (pc&0x1f != 0x1f), output MUST be true
638		nand322 means if pc = 0x3f, output MUST be true
639		hence, nand325 is if pc = 0x7f, false. if pc = 0x3f, true. if pc&0x60 is zero OR pc&0x60 is 0x60, true. otherwise, false.
	657	void tms1xxx_cpu_device::read_opcode()
	658	{
	659	debugger_instruction_hook(this, m_rom_address);
	660	m_opcode = m_program->read_byte(m_rom_address);
	661	m_c4 = BITSWAP8(m_opcode,7,6,5,4,0,1,2,3) & 0xf; // opcode operand is bitswapped for most opcodes
640	662
641		tms0980_next_pc below implements an identical function to this in a somewhat more elegant way.
642		*/
643		void tms1xxx_cpu_device::next_pc()
	663	m_fixed = m_fixed_decode[m_opcode];
	664	m_micro = m_micro_decode[m_opcode];
	665
	666	next_pc();
	667	}
	668
	669	void tms0980_cpu_device::read_opcode()
644	670	{
645		if ( m_byte_size > 8 )
646		{
647		UINT8 xorval = ( m_pc & 0x3F ) == 0x3F ? 1 : 0;
648		UINT8 new_bit = ( ( m_pc ^ ( m_pc << 1 ) ) & 0x40 ) ? xorval : 1 - xorval;
	671	debugger_instruction_hook(this, m_rom_address << 1);
	672	m_opcode = m_program->read_word(m_rom_address << 1) & 0x1ff;
	673	m_c4 = BITSWAP8(m_opcode,7,6,5,4,0,1,2,3) & 0xf; // opcode operand is bitswapped for most opcodes
	674
	675	m_fixed = m_fixed_decode[m_opcode];
	676
	677	// if ipla term 0 is active, R4-R8 directly select a microinstruction index when R0 or R0^BL is 0
	678	int r0 = m_opcode >> 8 & 1;
	679	if (m_ipla->read(m_opcode) & 0x40 && !((r0 & m_bl) ^ r0))
	680	m_micro = m_micro_direct[m_opcode & 0x3f];
	681	else
	682	m_micro = m_micro_decode[m_opcode];
649	683
650		m_pc = ((m_pc << 1) \| new_bit) & ((1 << m_pc_size) - 1);
651		}
652		else
653		{
654		m_pc = tms1000_next_pc[ m_pc & 0x3f ];
655		}
	684	next_pc();
656	685	}
657	686
658	687
659		~~stat~~ic ~~cons~~t ~~UINT8 t~~ms1~~000~~_pc_decode~~[64]~~ =
	688	void tms1xxx_cpu_device::write_o_output(UINT8 data)
660	689	{
661		0x03, 0x04, 0x0B, 0x0C, 0x13, 0x14, 0x1B, 0x1C,
662		0x23, 0x24, 0x2B, 0x2C, 0x33, 0x34, 0x3B, 0x3C,
663		0x00, 0x07, 0x08, 0x0F, 0x10, 0x17, 0x18, 0x1F,
664		0x20, 0x27, 0x28, 0x2F, 0x30, 0x37, 0x38, 0x3F,
665		0x02, 0x05, 0x0A, 0x0D, 0x12, 0x15, 0x1A, 0x1D,
666		0x22, 0x25, 0x2A, 0x2D, 0x32, 0x35, 0x3A, 0x3D,
667		0x01, 0x06, 0x09, 0x0E, 0x11, 0x16, 0x19, 0x1E,
668		0x21, 0x26, 0x29, 0x2E, 0x31, 0x36, 0x39, 0x3E
669		};
	690	// a hardcoded table is supported if the output pla is unknown
	691	m_o = (c_output_pla == NULL) ? m_opla->read(data) : c_output_pla[data];
	692
	693	if ((m_o & 0xff00) == 0xff00)
	694	logerror("unknown output pla mapping for index %02X\n", data);
	695
	696	m_write_o(0, m_o & m_o_mask, 0xffff);
	697	}
670	698
	699	void tms0970_cpu_device::write_o_output(UINT8 data)
	700	{
	701	m_o = m_spla->read(data);
	702	m_write_o(0, m_o & m_o_mask, 0xffff);
	703	}
671	704
672		~~void~~ tms1xxx_cpu_device::set_cki_bus()
	705	UINT8 tms1xxx_cpu_device::read_k_input()
673	706	{
674		switch( m_opcode & 0x1F8 )
675		{
676		case 0x008:
677		m_cki_bus = m_read_k( 0, 0xff );
678		break;
679		case 0x020: case 0x028:
680		m_cki_bus = 0;
681		break;
682		case 0x030: case 0x038:
683		m_cki_bus = tms0980_nbit_value[ m_opcode & 0x03 ];
684		break;
685		case 0x000:
686		case 0x040: case 0x048:
687		case 0x050: case 0x058:
688		case 0x060: case 0x068:
689		case 0x070: case 0x078:
690		case 0x080: case 0x088:
691		case 0x090: case 0x098:
692		case 0x0c0: case 0x0c8:
693		case 0x0d0: case 0x0d8:
694		case 0x0e0: case 0x0e8:
695		case 0x0f0: case 0x0f8:
696		m_cki_bus = tms0980_c4_value[ m_opcode & 0x0F ];
697		break;
698		default:
699		m_cki_bus = 0x0F;
700		break;
701		}
	707	// K1,2,4,8,3 (KC test pin is not emulated)
	708	UINT8 k = m_read_k(0, 0xff) & m_k_mask;
	709	UINT8 k3 = (k & 0x10) ? 3: 0; // the K3 line that is on some chips, is simply K1\|K2
	710	return (k & 0xf) \| k3;
702	711	}
703	712
704	713
705		void tms1xxx_cpu_device::e~~xecu~~te_run()
	714	void tms1xxx_cpu_device::set_cki_bus()
706	715	{
707		do
	716	switch (m_opcode & 0xf8)
708	717	{
709		m_icount--;
710		switch( m_subcycle )
711		{
712		case 0:
713		/* fetch: rom address 0 */
714		/* execute: read ram, alu input, execute br/call, k input valid */
715		set_cki_bus();
716		m_ram_data = m_data->read_byte( m_ram_address );
717		m_status = 1;
718		m_p = 0;
719		m_n = 0;
720		m_carry_in = 0;
	718	// 00001XXX: K-inputs
	719	case 0x08:
	720	m_cki_bus = read_k_input();
721	721	break;
722		case 1:
723		/* fetch: rom address 1 */
724		m_rom_address = ( m_ca << ( m_pc_size + 4 ) ) \| ( m_pa << m_pc_size ) \| m_pc;
725		/* execute: k input valid */
726		if ( m_decode & MICRO_MASK )
727		{
728		/* Check N inputs */
729		if ( m_decode & ( M_15TN \| M_ATN \| M_CKN \| M_MTN \| M_NATN ) )
730		{
731		m_n = 0;
732		if ( m_decode & M_15TN )
733		{
734		m_n \|= 0x0F;
735		}
736		if ( m_decode & M_ATN )
737		{
738		m_n \|= m_a;
739		}
740		if ( m_decode & M_CKN )
741		{
742		m_n \|= m_cki_bus;
743		}
744		if ( m_decode & M_MTN )
745		{
746		m_n \|= m_ram_data;
747		}
748		if ( m_decode & M_NATN )
749		{
750		m_n \|= ( ( ~m_a ) & 0x0F );
751		}
752		}
753	722
	723	// 0011XXXX: select bit
	724	case 0x30: case 0x38:
	725	m_cki_bus = 1 << (m_c4 >> 2) ^ 0xf;
	726	break;
	727
	728	// 01XXXXXX: constant
	729	case 0x00: // R2,3,4 are NANDed with eachother, and then ORed with R1, making 00000XXX valid too
	730	case 0x40: case 0x48: case 0x50: case 0x58: case 0x60: case 0x68: case 0x70: case 0x78:
	731	m_cki_bus = m_c4;
	732	break;
754	733
755		/* Check P inputs */
756		if ( m_decode & ( M_CKP \| M_DMTP \| M_MTP \| M_NDMTP \| M_YTP ) )
757		{
758		m_p = 0;
759		if ( m_decode & M_CKP )
760		{
761		m_p \|= m_cki_bus;
762		}
763		if ( m_decode & M_DMTP )
764		{
765		m_p \|= m_dam;
766		}
767		if ( m_decode & M_MTP )
768		{
769		m_p \|= m_ram_data;
770		}
771		if ( m_decode & M_NDMTP )
772		{
773		m_p \|= ( ( ~m_dam ) & 0x0F );
774		}
775		if ( m_decode & M_YTP )
776		{
777		m_p \|= m_y;
778		}
779		}
	734	default:
	735	m_cki_bus = 0;
	736	break;
	737	}
	738	}
780	739
781		/* Carry In input */
782		if ( m_decode & M_CIN )
783		{
784		m_carry_in = 1;
785		}
786		}
	740	void tms0980_cpu_device::set_cki_bus()
	741	{
	742	switch (m_opcode & 0x1f8)
	743	{
	744	// 000001XXX: K-inputs
	745	case 0x008:
	746	m_cki_bus = read_k_input();
787	747	break;
788		case 2:
789		/* fetch: nothing */
790		/* execute: write ram */
791		/* perform adder logic */
792		m_adder_result = m_p + m_n + m_carry_in;
793		if ( m_decode & MICRO_MASK )
794		{
795		if ( m_decode & M_NE )
796		{
797		if ( m_n == m_p )
798		{
799		m_status = 0;
800		}
801		}
802		if ( m_decode & M_C8 )
803		{
804		m_status = m_adder_result >> 4;
805		}
806		if ( m_decode & M_STO )
807		{
808		m_data->write_byte( m_ram_address, m_a );
809		}
810		if ( m_decode & M_CKM )
811		{
812		m_data->write_byte( m_ram_address, m_cki_bus );
813		}
814		}
815		else
816		{
817		if ( m_decode & F_SBIT )
818		{
819		m_data->write_byte( m_ram_address, m_ram_data \| tms0980_bit_value[ m_opcode & 0x03 ] );
820		}
821		if ( m_decode & F_RBIT )
822		{
823		m_data->write_byte( m_ram_address, m_ram_data & tms0980_nbit_value[ m_opcode & 0x03 ] );
824		}
825		if ( m_decode & F_SETR )
826		{
827		m_r = m_r \| ( 1 << m_y );
828		m_write_r( 0, m_r & m_r_mask, 0xffff );
829		}
830		if ( m_decode & F_RSTR )
831		{
832		m_r = m_r & ( ~( 1 << m_y ) );
833		m_write_r( 0, m_r & m_r_mask, 0xffff );
834		}
835		if ( m_decode & F_TDO )
836		{
837		/* Calculate O-outputs based on status latch, A, and the output PLA configuration */
838		m_o = c_output_pla[ ( m_status_latch << 4 ) \| m_a ];
839		if ( ( c_output_pla[ ( m_status_latch << 4 ) \| m_a ] & 0xFF00 ) == 0xFF00 )
840		{
841		logerror("unknown output pla mapping for status latch = %d and a = %X\n", m_status_latch, m_a);
842		}
843	748
844		m_write_o( 0, m_o & m_o_mask, 0xffff );
845		}
846		if ( m_decode & F_CLO )
847		{
848		m_o = 0;
849		m_write_o( 0, m_o & m_o_mask, 0xffff );
850		}
851		if ( m_decode & F_LDX )
852		{
853		switch( m_x_bits )
854		{
855		case 2:
856		m_x = tms0980_c2_value[ m_opcode & 0x03 ];
857		break;
858		case 3:
859		m_x = tms0980_c3_value[ m_opcode & 0x07 ];
860		break;
861		case 4:
862		m_x = tms0980_c4_value[ m_opcode & 0x0f ];
863		break;
864		}
865		}
866		if ( m_decode & F_COMX )
867		{
868		switch ( m_x_bits )
869		{
870		case 2:
871		m_x = m_x ^ 0x03;
872		break;
873		case 3:
874		m_x = m_x ^ 0x07;
875		break;
876		case 4:
877		m_x = m_x ^ 0x0f;
878		break;
879		}
880		}
881		if ( m_decode & F_COMC )
882		{
883		m_cb = m_cb ^ 0x01;
884		}
885		if ( m_decode & F_LDP )
886		{
887		m_pb = tms0980_c4_value[ m_opcode & 0x0F ];
888		}
889		if ( m_decode & F_REAC )
890		{
891		m_special_status = 0;
892		}
893		if ( m_decode & F_SEAC )
894		{
895		m_special_status = 1;
896		}
897		if ( m_decode == F_SAL )
898		{
899		m_add_latch = 1;
900		}
901		if ( m_decode == F_SBL )
902		{
903		m_branch_latch = 1;
904		}
905		}
	749	// 0X0100XXX: select bit
	750	case 0x020: case 0x0a0:
	751	m_cki_bus = 1 << (m_c4 >> 2) ^ 0xf;
906	752	break;
907		case 3:
908		/* fetch: fetch, update pc, ram address */
909		/* execute: register store */
	753
	754	// 0X1XXXXXX: constant
	755	case 0x040: case 0x048: case 0x050: case 0x058: case 0x060: case 0x068: case 0x070: case 0x078:
	756	case 0x0c0: case 0x0c8: case 0x0d0: case 0x0d8: case 0x0e0: case 0x0e8: case 0x0f0: case 0x0f8:
	757	m_cki_bus = m_c4;
910	758	break;
911		case 4:
912		/* execute: register store */
913		if ( m_decode & MICRO_MASK )
914		{
915		if ( m_decode & M_AUTA )
916		{
917		m_a = m_adder_result & 0x0F;
918		}
919		if ( m_decode & M_AUTY )
920		{
921		m_y = m_adder_result & 0x0F;
922		}
923		if ( m_decode & M_STSL )
924		{
925		m_status_latch = m_status;
926		}
927		}
928		/* fetch: fetch, update pc, ram address */
929		if ( m_byte_size > 8 )
930		{
931		debugger_instruction_hook( this, m_rom_address << 1 );
932		m_opcode = m_program->read_word( m_rom_address << 1 ) & 0x1FF;
933		}
934		else
935		{
936		debugger_instruction_hook( this, m_rom_address );
937		m_opcode = m_program->read_byte( m_rom_address );
938		}
939		next_pc();
940	759
941		/* ram address */
942		m_ram_address = ( m_x << 4 ) \| m_y;
	760	default:
	761	m_cki_bus = 0;
943	762	break;
944		case 5:
945		/* fetch: instruction decode */
946		m_decode = m_decode_table[ m_opcode ];
947		/* execute: execute br/call */
948		if ( m_status )
949		{
950		if ( m_decode == F_BR )
951		{
952		m_ca = m_cb;
953		if ( m_call_latch == 0 )
954		{
955		m_pa = m_pb;
956		}
957		m_pc = m_opcode & ( ( 1 << m_pc_size ) - 1 );
958		}
959		if ( m_decode == F_CALL )
960		{
961		UINT8 t = m_pa;
962		if ( m_call_latch == 0 )
963		{
964		m_sr = m_pc;
965		m_call_latch = 1;
966		m_pa = m_pb;
967		m_cs = m_ca;
968		}
969		m_ca = m_cb;
970		m_pb = t;
971		m_pc = m_opcode & ( ( 1 << m_pc_size ) - 1 );
972		}
973		}
974		if ( m_decode == F_RETN )
975		{
976		if ( m_call_latch == 1 )
977		{
978		m_pc = m_sr;
979		m_call_latch = 0;
980		m_ca = m_cs;
981		}
982		m_add_latch = 0;
983		m_pa = m_pb;
984		} else {
985		m_branch_latch = 0;
986		}
987		break;
988		}
989		m_subcycle = ( m_subcycle + 1 ) % 6;
990		} while( m_icount > 0 );
	763	}
991	764	}
992	765
993	766
994		void tms0980_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
	767	// fixed opcode set
	768
	769	// TMS1000/common:
	770
	771	void tms1xxx_cpu_device::op_sbit()
995	772	{
996		switch( entry.index() )
997		{
998		case STATE_GENPC:
999		string.printf( "%03X", ( ( m_pa << 7 ) \| m_pc ) << 1 );
1000		break;
1001		}
	773	// SBIT: set memory bit
	774	if (m_ram_out == -1)
	775	m_ram_out = m_ram_in;
	776	m_ram_out \|= (m_cki_bus ^ 0xf);
1002	777	}
1003	778
	779	void tms1xxx_cpu_device::op_rbit()
	780	{
	781	// RBIT: reset memory bit
	782	if (m_ram_out == -1)
	783	m_ram_out = m_ram_in;
	784	m_ram_out &= m_cki_bus;
	785	}
1004	786
1005		void tms1~~000~~_cpu_device::~~state_string_exp~~o~~rt(const device~~_s~~tat~~e~~_en~~tr~~y &entry, astring &string~~)
	787	void tms1xxx_cpu_device::op_setr()
1006	788	{
1007		switch( entry.index() )
1008		{
1009		case STATE_GENPC:
1010		string.printf( "%03X", ( m_pa << 6 ) \| tms1000_pc_decode[ m_pc ] );
1011		break;
1012		}
	789	// SETR: set one R-output line
	790	m_r = m_r \| (1 << m_y);
	791	m_write_r(0, m_r & m_r_mask, 0xffff);
1013	792	}
1014	793
	794	void tms1xxx_cpu_device::op_rstr()
	795	{
	796	// RSTR: reset one R-output line
	797	m_r = m_r & ~(1 << m_y);
	798	m_write_r(0, m_r & m_r_mask, 0xffff);
	799	}
1015	800
1016		void tms1~~100~~_cpu_device::~~state~~_st~~ring_exp~~ort(~~const device_state_entry &entry, astring &string~~)
	801	void tms1xxx_cpu_device::op_tdo()
1017	802	{
1018		switch( entry.index() )
1019		{
1020		case STATE_GENPC:
1021		string.printf( "%03X", ( m_ca << 10 ) \| ( m_pa << 6 ) \| m_pc );
1022		break;
1023		}
	803	// TDO: transfer accumulator and status latch to O-output
	804	write_o_output(m_status_latch << 4 \| m_a);
1024	805	}
1025	806
	807	void tms1xxx_cpu_device::op_clo()
	808	{
	809	// CLO: clear O-output
	810	write_o_output(0);
	811	}
1026	812
1027		tms0980_cpu_device::tms0980_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1028		: tms1xxx_cpu_device( mconfig, TMS0980, "TMS0980", tag, owner, clock, tms0980_decode, 0x00ff, 0x07ff, 7, 9, 4
1029		, 12, ADDRESS_MAP_NAME( program_11bit_9 ), 8, ADDRESS_MAP_NAME( data_64x9_as4 ), "tms0980", __FILE__)
	813	void tms1xxx_cpu_device::op_ldx()
1030	814	{
	815	// LDX: load X register with (x_bits) constant
	816	m_x = m_c4 >> (4-m_x_bits);
1031	817	}
1032	818
	819	void tms1xxx_cpu_device::op_comx()
	820	{
	821	// COMX: complement X register
	822	m_x ^= m_x_mask;
	823	}
1033	824
1034		o~~ffs_t~~ tms~~0980~~_cpu_device::~~disasm_disassemble(char buffer,~~ o~~ffs_t~~ pc~~, c~~o~~nst UINT8 opro~~m~~, const UINT~~8 *opram, UINT32 options)
	825	void tms1xxx_cpu_device::op_comx8()
1035	826	{
1036		extern CPU_DISASSEMBLE( tms0980 );
1037		return CPU_DISASSEMBLE_NAME(tms0980)(this, buffer, pc, oprom, opram, options);
	827	// COMX8: complement MSB of X register
	828	// note: on TMS1100, the mnemonic is simply called "COMX"
	829	m_x ^= 1 << (m_x_bits-1);
1038	830	}
1039	831
1040
1041		tms1000_cpu_device::tms1000_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1042		: tms1xxx_cpu_device( mconfig, TMS1000, "TMS1000", tag, owner, clock, tms1000_default_decode, 0x00ff, 0x07ff, 6, 8, 2
1043		, 10, ADDRESS_MAP_NAME( program_10bit_8 ), 6, ADDRESS_MAP_NAME( data_64x4 ), "tms1000", __FILE__)
	832	void tms1xxx_cpu_device::op_ldp()
1044	833	{
	834	// LDP: load page buffer with constant
	835	m_pb = m_c4;
1045	836	}
1046	837
1047	838
1048		tms1000_cpu_device::tms1000_cpu_device(const machine_config &mconfig, device_type type, const charname, const char tag, device_t owner, UINT32 clock, UINT16 o_mask, UINT16 r_mask, const char shortname, const char *source)
1049		: tms1xxx_cpu_device( mconfig, type, name, tag, owner, clock, tms1000_default_decode, o_mask, r_mask, 6, 8, 2
1050		, 10, ADDRESS_MAP_NAME( program_10bit_8 ), 6, ADDRESS_MAP_NAME( data_64x4 ), shortname, source )
	839	// TMS1100-specific
	840
	841	void tms1100_cpu_device::op_setr()
1051	842	{
	843	// SETR: same, but X register MSB must be clear
	844	if (~m_x & (1 << (m_x_bits-1)))
	845	tms1xxx_cpu_device::op_setr();
1052	846	}
1053	847
	848	void tms1100_cpu_device::op_rstr()
	849	{
	850	// RSTR: same, but X register MSB must be clear
	851	if (~m_x & (1 << (m_x_bits-1)))
	852	tms1xxx_cpu_device::op_rstr();
	853	}
1054	854
1055		o~~ffs_t~~ tms1~~000~~_cpu_device::~~disasm_disassemble(char buffer,~~ o~~ffs_t~~ pc~~, c~~o~~nst UINT8 opro~~m, c~~onst UINT8 *opram, UINT32 options~~)
	855	void tms1xxx_cpu_device::op_comc()
1056	856	{
1057		extern CPU_DISASSEMBLE( tms1000 );
1058		return CPU_DISASSEMBLE_NAME(tms1000)(this, buffer, pc, oprom, opram, options);
	857	// COMC: complement chapter buffer
	858	m_cb ^= 1;
1059	859	}
1060	860
1061	861
1062		tms0970_cpu_device::tms0970_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1063		: tms1000_cpu_device( mconfig, TMS0970, "TMS0970", tag, owner, clock, 0x00ff, 0x07ff, "tms0970", __FILE__)
	862	// TMS09x0-specific
	863	void tms0970_cpu_device::op_setr()
1064	864	{
	865	// SETR: set output register
	866	// DDIG line is a coincidence between the selected output pla row(s) and segment pla row(s)
	867	int ddig = (m_opla->read(m_a) & m_o) ? 0 : 1;
	868	m_r = (m_r & ~(1 << m_y)) \| (ddig << m_y);
1065	869	}
1066	870
1067		tms1070_cpu_device::tms1070_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1068		: tms1000_cpu_device( mconfig, TMS1070, "TMS1070", tag, owner, clock, 0x00ff, 0x07ff, "tms1070", __FILE__)
	871	void tms0970_cpu_device::op_tdo()
1069	872	{
	873	// TDO: transfer digits to output
	874	write_o_output(m_a & 0x7);
	875	m_write_r(0, m_r & m_r_mask, 0xffff);
1070	876	}
1071	877
1072	878
1073		tms1200_cpu_device::tms1200_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1074		: tms1000_cpu_device( mconfig, TMS1200, "TMS1200", tag, owner, clock, 0x00ff, 0x1fff, "tms1200", __FILE__)
	879	// TMS0980-specific
	880	void tms0980_cpu_device::op_comx()
1075	881	{
	882	// COMX: complement X register, but not the MSB
	883	m_x ^= (m_x_mask >> 1);
1076	884	}
1077	885
	886	void tms1xxx_cpu_device::op_xda()
	887	{
	888	// XDA: exchange DAM and A
	889	// note: setting A to DAM is done with DMTP and AUTA during this instruction
	890	m_ram_address \|= (0x10 << (m_x_bits-1));
	891	}
1078	892
1079		tms1270_cpu_device::tms1270_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1080		: tms1000_cpu_device( mconfig, TMS1270, "TMS1270", tag, owner, clock, 0x03ff, 0x1fff, "tms1270", __FILE__)
	893	void tms1xxx_cpu_device::op_off()
1081	894	{
	895	// OFF: request power off
	896	logerror("%s: power-off request\n", tag());
	897	m_power_off(1);
1082	898	}
1083	899
	900	void tms1xxx_cpu_device::op_seac()
	901	{
	902	// SEAC: set end around carry
	903	m_eac = 1;
	904	}
1084	905
1085		tms1100_cpu_device::tms1100_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1086		: tms1xxx_cpu_device( mconfig, TMS1100, "TMS1100", tag, owner, clock, tms1100_default_decode, 0x00ff, 0x07ff, 6, 8, 3
1087		, 11, ADDRESS_MAP_NAME( program_11bit_8 ), 7, ADDRESS_MAP_NAME( data_128x4 ), "tms1100", __FILE__ )
	906	void tms1xxx_cpu_device::op_reac()
1088	907	{
	908	// REAC: reset end around carry
	909	m_eac = 0;
1089	910	}
1090	911
	912	void tms1xxx_cpu_device::op_sal()
	913	{
	914	// SAL: set add latch (reset is done with RETN)
	915	m_add = 1;
	916	}
1091	917
1092		tms1100_cpu_device::tms1100_cpu_device(const machine_config &mconfig, device_type type, const charname, const char tag, device_t owner, UINT32 clock, UINT16 o_mask, UINT16 r_mask, const char shortname, const char *source)
1093		: tms1xxx_cpu_device( mconfig, type, name, tag, owner, clock, tms1100_default_decode, o_mask, r_mask, 6, 8, 3
1094		, 11, ADDRESS_MAP_NAME( program_11bit_8 ), 7, ADDRESS_MAP_NAME( data_128x4 ), shortname, source )
	918	void tms1xxx_cpu_device::op_sbl()
1095	919	{
	920	// SBL: set branch latch (reset is done with RETN)
	921	m_bl = 1;
1096	922	}
1097	923
1098	924
1099		o~~ffs_t~~ tms1~~100~~_cpu_device::~~disasm_disass~~e~~mbl~~e(c~~har b~~uffe~~r, o~~ffs_~~t pc, c~~o~~nst UINT8 o~~p~~rom,~~ co~~nst UINT8 *opram, UINT32 options~~)
	925	void tms1xxx_cpu_device::execute_fixed_opcode()
1100	926	{
1101		extern CPU_DISASSEMBLE( tms1100 );
1102		return CPU_DISASSEMBLE_NAME(tms1100)(this, buffer, pc, oprom, opram, options);
	927	switch (m_fixed)
	928	{
	929	case F_SBIT: op_sbit(); break;
	930	case F_RBIT: op_rbit(); break;
	931	case F_SETR: op_setr(); break;
	932	case F_RSTR: op_rstr(); break;
	933	case F_TDO: op_tdo(); break;
	934	case F_CLO: op_clo(); break;
	935	case F_LDX: op_ldx(); break;
	936	case F_COMX: op_comx(); break;
	937	case F_COMX8:op_comx8();break;
	938	case F_LDP: op_ldp(); break;
	939	case F_COMC: op_comc(); break;
	940	case F_OFF: op_off(); break;
	941	case F_SEAC: op_seac(); break;
	942	case F_REAC: op_reac(); break;
	943	case F_SAL: op_sal(); break;
	944	case F_SBL: op_sbl(); break;
	945	case F_XDA: op_xda(); break;
	946
	947	default:
	948	// BR, CALL, RETN are handled in execute_run
	949	if (m_fixed & ~(F_BR \| F_CALL \| F_RETN))
	950	fatalerror("%s unsupported fixed opcode %03X %04X!\n", tag(), m_opcode, m_fixed);
	951	break;
	952	}
1103	953	}
1104	954
1105	955
1106		tms1300_cpu_device::tms1300_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
1107		: tms1100_cpu_device( mconfig, TMS1300, "TMS1300", tag, owner, clock, 0x00ff, 0xffff, "tms1300", __FILE__ )
	956
	957	void tms1xxx_cpu_device::execute_run()
1108	958	{
	959	do
	960	{
	961	m_icount--;
	962	switch (m_subcycle)
	963	{
	964	case 0:
	965	// fetch: rom address 1/2
	966
	967	// execute: br/call 2/2
	968	// note: add(latch) and bl(branch latch) are specific to 0980 series,
	969	// c(chapter) bits are specific to 1100 series
	970	if (m_status)
	971	{
	972	UINT8 new_pc = m_opcode & m_pc_mask;
	973
	974	// BR: conditional branch
	975	if (m_fixed & F_BR)
	976	{
	977	if (m_clatch == 0)
	978	m_pa = m_pb;
	979	m_ca = m_cb;
	980	m_pc = new_pc;
	981	}
	982
	983	// CALL: conditional call
	984	if (m_fixed & F_CALL)
	985	{
	986	UINT8 prev_pa = m_pa;
	987	if (m_clatch == 0)
	988	{
	989	m_sr = m_pc;
	990	m_clatch = 1;
	991	m_pa = m_pb;
	992	m_cs = m_ca;
	993	}
	994	m_ca = m_cb;
	995	m_pb = prev_pa;
	996	m_pc = new_pc;
	997	}
	998	}
	999
	1000	// RETN: return from subroutine
	1001	if (m_fixed & F_RETN)
	1002	{
	1003	if (m_clatch == 1)
	1004	{
	1005	m_pc = m_sr;
	1006	m_clatch = 0;
	1007	m_ca = m_cs;
	1008	}
	1009	m_add = 0;
	1010	m_bl = 0;
	1011	m_pa = m_pb;
	1012	}
	1013
	1014	// execute: k input valid, read ram, clear alu inputs
	1015	set_cki_bus();
	1016	m_ram_in = m_data->read_byte(m_ram_address) & 0xf;
	1017	m_dam_in = m_data->read_byte(m_ram_address \| (0x10 << (m_x_bits-1))) & 0xf;
	1018	m_ram_out = -1;
	1019	m_status = 1;
	1020	m_p = 0;
	1021	m_n = 0;
	1022	m_carry_in = 0;
	1023
	1024	break;
	1025
	1026	case 1:
	1027	// fetch: rom address 2/2
	1028	m_rom_address = (m_ca << (m_pc_bits+4)) \| (m_pa << m_pc_bits) \| m_pc;
	1029
	1030	// execute: update alu inputs
	1031	// N inputs
	1032	if (m_micro & M_15TN) m_n \|= 0xf;
	1033	if (m_micro & M_ATN) m_n \|= m_a;
	1034	if (m_micro & M_NATN) m_n \|= (~m_a & 0xf);
	1035	if (m_micro & M_CKN) m_n \|= m_cki_bus;
	1036	if (m_micro & M_MTN) m_n \|= m_ram_in;
	1037
	1038	// P inputs
	1039	if (m_micro & M_CKP) m_p \|= m_cki_bus;
	1040	if (m_micro & M_MTP) m_p \|= m_ram_in;
	1041	if (m_micro & M_YTP) m_p \|= m_y;
	1042	if (m_micro & M_DMTP) m_p \|= m_dam_in;
	1043	if (m_micro & M_NDMTP) m_p \|= (~m_dam_in & 0xf);
	1044
	1045	// carry input
	1046	if (m_micro & M_CIN) m_carry_in \|= 1;
	1047	if (m_micro & M_SSS) m_carry_in \|= m_eac;
	1048
	1049	break;
	1050
	1051	case 2:
	1052	{
	1053	// fetch: nothing
	1054
	1055	// execute: perform alu logic
	1056	// note: officially, only 1 alu operation is allowed per opcode
	1057	m_adder_out = m_p + m_n + m_carry_in;
	1058	int carry_out = m_adder_out >> 4 & 1;
	1059
	1060	if (m_micro & M_C8) m_status &= carry_out;
	1061	if (m_micro & M_NE) m_status &= (m_n != m_p); // COMP
	1062
	1063	if (m_micro & M_CKM) m_ram_out = m_cki_bus;
	1064
	1065	// special status circuit
	1066	if (m_micro & M_SSE)
	1067	{
	1068	m_eac = m_carry_out;
	1069	if (m_add)
	1070	m_eac \|= carry_out;
	1071	}
	1072	m_carry_out = carry_out;
	1073
	1074	if (m_micro & M_STO \|\| (m_micro & M_CME && m_eac == m_add))
	1075	m_ram_out = m_a;
	1076
	1077	// handle the fixed opcodes here
	1078	execute_fixed_opcode();
	1079
	1080	// execute: write ram
	1081	if (m_ram_out != -1)
	1082	m_data->write_byte(m_ram_address, m_ram_out);
	1083
	1084	break;
	1085	}
	1086
	1087	case 3:
	1088	// fetch: update pc, ram address 1/2
	1089	// execute: register store 1/2
	1090	break;
	1091
	1092	case 4:
	1093	// execute: register store 2/2
	1094	if (m_micro & M_AUTA) m_a = m_adder_out & 0xf;
	1095	if (m_micro & M_AUTY) m_y = m_adder_out & 0xf;
	1096	if (m_micro & M_STSL) m_status_latch = m_status;
	1097
	1098	// fetch: update pc, ram address 2/2
	1099	read_opcode();
	1100	m_ram_address = m_x << 4 \| m_y;
	1101	break;
	1102
	1103	case 5:
	1104	// fetch: instruction decode (handled above, before next_pc)
	1105	// execute: br/call 1/2
	1106	break;
	1107	}
	1108	m_subcycle = (m_subcycle + 1) % 6;
	1109	} while (m_icount > 0);
1109	1110	}

trunk/src/emu/cpu/tms0980/tms0980.h
r242128	r242129
	1	// license:BSD-3-Clause
	2	// copyright-holders:Wilbert Pol, hap
	3	/*
	4
	5	TMS0980/TMS1000-family MCU cores
	6
	7	*/
1	8	#ifndef _TMS0980_H_
2	9	#define _TMS0980_H_
3	10
	11	#include "emu.h"
	12	#include "machine/pla.h"
4	13
5		/* Registers */
6		enum {
7		TMS0980_PC=1, TMS0980_SR, TMS0980_PA, TMS0980_PB,
8		TMS0980_A, TMS0980_X, TMS0980_Y, TMS0980_STATUS
9		};
10	14
11
12	15	#define MCFG_TMS1XXX_OUTPUT_PLA(_pla) \
13	16	tms1xxx_cpu_device::set_output_pla(*device, _pla);
14	17
15		#define MCFG_TMS1XXX_READ_K(_devcb) \
16		tms1xxx_cpu_device::set_read_k(*device, DEVCB_##_devcb);
	18	#define MCFG_TMS1XXX_READ_K_CB(_devcb) \
	19	tms1xxx_cpu_device::set_read_k_callback(*device, DEVCB_##_devcb);
17	20
18		#define MCFG_TMS1XXX_WRITE_O(_devcb) \
19		tms1xxx_cpu_device::set_write_o(*device, DEVCB_##_devcb);
	21	#define MCFG_TMS1XXX_WRITE_O_CB(_devcb) \
	22	tms1xxx_cpu_device::set_write_o_callback(*device, DEVCB_##_devcb);
20	23
21		#define MCFG_TMS1XXX_WRITE_R(_devcb) \
22		tms1xxx_cpu_device::set_write_r(*device, DEVCB_##_devcb);
	24	#define MCFG_TMS1XXX_WRITE_R_CB(_devcb) \
	25	tms1xxx_cpu_device::set_write_r_callback(*device, DEVCB_##_devcb);
23	26
	27	#define MCFG_TMS1XXX_POWER_OFF_CB(_devcb) \
	28	tms1xxx_cpu_device::set_power_off_callback(*device, DEVCB_##_devcb);
24	29
	30
25	31	class tms1xxx_cpu_device : public cpu_device
26	32	{
27	33	public:
28	34	// construction/destruction
29		tms1xxx_cpu_device( const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock
30		, const UINT32* decode_table, UINT16 o_mask, UINT16 r_mask, UINT8 pc_size, UINT8 byte_size, UINT8 x_bits
31		, int program_addrbus_width, address_map_constructor program, int data_addrbus_width, address_map_constructor data, const char shortname, const char source)
32		: cpu_device( mconfig, type, name, tag, owner, clock, shortname, source)
33		, m_program_config("program", ENDIANNESS_BIG, byte_size > 8 ? 16 : 8, program_addrbus_width, 0, program )
34		, m_data_config("data", ENDIANNESS_BIG, 8, data_addrbus_width, 0, data )
35		, m_pc(0)
36		, m_pa(0)
37		, m_sr(0)
38		, m_pb(0)
39		, m_a(0)
40		, m_x(0)
41		, m_y(0)
42		, m_status(0)
43		, m_o_mask( o_mask )
44		, m_r_mask( r_mask )
45		, m_pc_size( pc_size )
46		, m_byte_size( byte_size )
47		, m_x_bits( x_bits )
48		, m_decode_table( decode_table )
49		, c_output_pla( NULL )
50		, m_read_k( *this )
51		, m_write_o( *this )
52		, m_write_r( *this )
	35	tms1xxx_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock
	36	, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits
	37	, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char shortname, const char source)
	38	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
	39	, m_program_config("program", ENDIANNESS_BIG, byte_bits > 8 ? 16 : 8, prgwidth, 0, program)
	40	, m_data_config("data", ENDIANNESS_BIG, 8, datawidth, 0, data)
	41	, m_mpla(*this, "mpla")
	42	, m_ipla(*this, "ipla")
	43	, m_opla(*this, "opla")
	44	, m_spla(*this, "spla")
	45	, m_o_pins(o_pins)
	46	, m_r_pins(r_pins)
	47	, m_k_pins(k_pins)
	48	, m_pc_bits(pc_bits)
	49	, m_byte_bits(byte_bits)
	50	, m_x_bits(x_bits)
	51	, c_output_pla(NULL)
	52	, m_read_k(*this)
	53	, m_write_o(*this)
	54	, m_write_r(*this)
	55	, m_power_off(*this)
53	56	{ }
54	57
55	58	// static configuration helpers
56		template<class _Object> static devcb_base &set_read_k(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_read_k.set_callback(object); }
57		template<class _Object> static devcb_base &set_write_o(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_write_o.set_callback(object); }
58		template<class _Object> static devcb_base &set_write_r(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_write_r.set_callback(object); }
	59	template<class _Object> static devcb_base &set_read_k_callback(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_read_k.set_callback(object); }
	60	template<class _Object> static devcb_base &set_write_o_callback(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_write_o.set_callback(object); }
	61	template<class _Object> static devcb_base &set_write_r_callback(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_write_r.set_callback(object); }
	62	template<class _Object> static devcb_base &set_power_off_callback(device_t &device, _Object object) { return downcast<tms1xxx_cpu_device &>(device).m_power_off.set_callback(object); }
59	63	static void set_output_pla(device_t &device, const UINT16 *output_pla) { downcast<tms1xxx_cpu_device &>(device).c_output_pla = output_pla; }
60	64
61	65	protected:
r242128	r242129
65	69
66	70	// device_execute_interface overrides
67	71	virtual UINT32 execute_min_cycles() const { return 1; }
68		virtual UINT32 execute_max_cycles() const { return 6; }
	72	virtual UINT32 execute_max_cycles() const { return 1; }
69	73	virtual UINT32 execute_input_lines() const { return 1; }
70	74	virtual void execute_run();
71	75
72	76	// device_memory_interface overrides
73		virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA ) ? &m_data_config : NULL ); }
	77	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return(spacenum == AS_PROGRAM) ? &m_program_config :((spacenum == AS_DATA) ? &m_data_config : NULL); }
74	78
75	79	// device_disasm_interface overrides
76	80	virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
77	81	virtual UINT32 disasm_max_opcode_bytes() const { return 1; }
78	82
79	83	void next_pc();
80		void set_cki_bus();
	84	void execute_fixed_opcode();
	85
	86	virtual void write_o_output(UINT8 data);
	87	virtual UINT8 read_k_input();
	88	virtual void set_cki_bus();
	89	virtual void read_opcode();
81	90
	91	virtual void op_sbit();
	92	virtual void op_rbit();
	93	virtual void op_setr();
	94	virtual void op_rstr();
	95	virtual void op_tdo();
	96	virtual void op_clo();
	97	virtual void op_ldx();
	98	virtual void op_comx();
	99	virtual void op_comx8();
	100	virtual void op_ldp();
	101
	102	virtual void op_comc();
	103	virtual void op_xda();
	104	virtual void op_off();
	105	virtual void op_seac();
	106	virtual void op_reac();
	107	virtual void op_sal();
	108	virtual void op_sbl();
	109
82	110	address_space_config m_program_config;
83	111	address_space_config m_data_config;
84	112
85		UINT8 m_prev_pc; /* previous program counter */
86		UINT8 m_prev_pa; /* previous page address register */
87		UINT8 m_pc; /* program counter is a 7 bit register on tms0980, 6 bit register on tms1000/1070/1200/1270/1100/1300 */
88		UINT8 m_pa; /* page address register is a 4 bit register */
89		UINT8 m_sr; /* subroutine return register is a 7 bit register */
90		UINT8 m_pb; /* page buffer register is a 4 bit register */
91		UINT8 m_a; /* Accumulator is a 4 bit register (?) */
92		UINT8 m_x; /* X-register is a 2, 3, or 4 bit register */
93		UINT8 m_y; /* Y-register is a 4 bit register */
94		UINT8 m_dam; /* DAM register is a 4 bit register */
95		UINT8 m_ca; /* Chapter address bit */
96		UINT8 m_cb; /* Chapter buffer bit */
97		UINT8 m_cs; /* Chapter subroutine bit */
	113	optional_device<pla_device> m_mpla;
	114	optional_device<pla_device> m_ipla;
	115	optional_device<pla_device> m_opla;
	116	optional_device<pla_device> m_spla;
	117
	118	UINT8 m_pc; // 6 or 7-bit program counter
	119	UINT8 m_sr; // 6 or 7-bit subroutine return register
	120	UINT8 m_pa; // 4-bit page address register
	121	UINT8 m_pb; // 4-bit page buffer register
	122	UINT8 m_a; // 4-bit accumulator
	123	UINT8 m_x; // 2,3,or 4-bit RAM X register
	124	UINT8 m_y; // 4-bit RAM Y register
	125	UINT8 m_ca; // chapter address bit
	126	UINT8 m_cb; // chapter buffer bit
	127	UINT8 m_cs; // chapter subroutine bit
98	128	UINT16 m_r;
99		UINT8 m_o;
100		UINT8 m_cki_bus; /* CKI bus */
101		UINT8 m_p; /* adder p-input */
102		UINT8 m_n; /* adder n-input */
103		UINT8 m_adder_result; /* adder result */
104		UINT8 m_carry_in; /* carry in */
	129	UINT16 m_o;
	130	UINT8 m_cki_bus;
	131	UINT8 m_c4;
	132	UINT8 m_p; // 4-bit adder p(lus)-input
	133	UINT8 m_n; // 4-bit adder n(egative)-input
	134	UINT8 m_adder_out; // adder result
	135	UINT8 m_carry_in; // adder carry-in bit
	136	UINT8 m_carry_out; // adder carry-out bit
105	137	UINT8 m_status;
106	138	UINT8 m_status_latch;
107		UINT8 m_special_status;
108		UINT8 m_call_latch;
109		UINT8 m_add_latch;
110		UINT8 m_branch_latch;
111		int m_subcycle;
	139	UINT8 m_eac; // end around carry bit
	140	UINT8 m_clatch; // call latch bit
	141	UINT8 m_add; // add latch bit
	142	UINT8 m_bl; // branch latch bit
	143
	144	UINT8 m_ram_in;
	145	UINT8 m_dam_in;
	146	int m_ram_out; // signed!
112	147	UINT8 m_ram_address;
113		UINT16 m_ram_data;
114	148	UINT16 m_rom_address;
115	149	UINT16 m_opcode;
116		UINT32 m_decode;
	150	UINT32 m_fixed;
	151	UINT32 m_micro;
	152	int m_subcycle;
117	153	int m_icount;
118		UINT16 m_o_mask; /* mask to determine the number of O outputs */
119		UINT16 m_r_mask; /* mask to determine the number of R outputs */
120		UINT8 m_pc_size; /* how bits in the PC register */
121		UINT8 m_byte_size; /* 8 or 9 bit bytes */
122		UINT8 m_x_bits; /* determine the number of bits in the X register */
123		const UINT32 *m_decode_table;
	154
	155	UINT8 m_o_pins; // how many O pins
	156	UINT8 m_r_pins; // how many R pins
	157	UINT8 m_k_pins; // how many K pins
	158	UINT8 m_pc_bits; // how many program counter bits
	159	UINT8 m_byte_bits; // how many bits per 'byte'
	160	UINT8 m_x_bits; // how many X register bits
	161
124	162	address_space *m_program;
125	163	address_space *m_data;
126	164
r242128	r242129
128	166	devcb_read8 m_read_k;
129	167	devcb_write16 m_write_o;
130	168	devcb_write16 m_write_r;
	169	devcb_write_line m_power_off;
	170
	171	UINT32 m_o_mask;
	172	UINT32 m_r_mask;
	173	UINT32 m_k_mask;
	174	UINT32 m_pc_mask;
	175	UINT32 m_x_mask;
131	176
	177	// lookup tables
	178	dynamic_array<UINT32> m_fixed_decode;
	179	dynamic_array<UINT32> m_micro_decode;
	180	dynamic_array<UINT32> m_micro_direct;
132	181	};
133	182
134	183
135		class tms0980_cpu_device : public tms1xxx_cpu_device
136		{
137		public:
138		tms0980_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
139	184
140		protected:
141		// device_state_interface overrides
142		void state_string_export(const device_state_entry &entry, astring &string);
143
144		// device_disasm_interface overrides
145		virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
146		virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
147		virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
148		};
149
150
151	185	class tms1000_cpu_device : public tms1xxx_cpu_device
152	186	{
153	187	public:
154	188	tms1000_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
155		tms1000_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT16 o_mask, UINT16 r_mask, const char shortname, const char *source);
	189	tms1000_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char shortname, const char *source);
156	190
157	191	protected:
158		// device_state_interface overrides
	192	// overrides
	193	virtual void device_reset();
	194	virtual machine_config_constructor device_mconfig_additions() const;
	195
159	196	void state_string_export(const device_state_entry &entry, astring &string);
160	197
161	198	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
162	199	};
163	200
164
165		class tms0970_cpu_device : public tms1000_cpu_device
166		{
167		public:
168		tms0970_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
169		};
170
171
172	201	class tms1070_cpu_device : public tms1000_cpu_device
173	202	{
174	203	public:
r242128	r242129
183	212	};
184	213
185	214
186		class tms1270_cpu_device : public tms1000_cpu_device
	215	class tms1100_cpu_device : public tms1000_cpu_device
187	216	{
188	217	public:
189		tms1270_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	218	tms1100_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	219	tms1100_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char shortname, const char *source);
	220
	221	protected:
	222	// overrides
	223	virtual void device_reset();
	224
	225	void state_string_export(const device_state_entry &entry, astring &string);
	226
	227	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	228
	229	virtual void op_setr();
	230	virtual void op_rstr();
190	231	};
191	232
	233	class tms1300_cpu_device : public tms1100_cpu_device
	234	{
	235	public:
	236	tms1300_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	237	};
192	238
193		class tms1100_cpu_device : public tms1xxx_cpu_device
	239
	240	class tms0970_cpu_device : public tms1000_cpu_device
194	241	{
195	242	public:
196		tms1100_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
197		tms1100_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT16 o_mask, UINT16 r_mask, const char shortname, const char *source);
	243	tms0970_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	244	tms0970_cpu_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char shortname, const char *source);
198	245
199	246	protected:
200		// device_state_interface overrides
201		void state_string_export(const device_state_entry &entry, astring &string);
	247	// overrides
	248	virtual void device_reset();
	249	virtual machine_config_constructor device_mconfig_additions() const;
202	250
203		virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	251	virtual void write_o_output(UINT8 data);
	252
	253	virtual void op_setr();
	254	virtual void op_tdo();
204	255	};
205	256
206	257
207		class tms1300_cpu_device : public tms1100_cpu_device
	258	class tms0980_cpu_device : public tms0970_cpu_device
208	259	{
209	260	public:
210		tms1300_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	261	tms0980_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	262
	263	protected:
	264	// overrides
	265	virtual void device_reset();
	266
	267	void state_string_export(const device_state_entry &entry, astring &string);
	268	virtual machine_config_constructor device_mconfig_additions() const;
	269
	270	virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
	271	virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
	272	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	273
	274	virtual void set_cki_bus();
	275	virtual void read_opcode();
	276
	277	virtual void op_comx();
	278	private:
	279	UINT32 decode_micro(UINT8 sel);
211	280	};
212	281
213	282
214		/* 9-bit family */
215		extern const device_type TMS0980;
216	283
217		/* 8-bit family */
218	284	extern const device_type TMS1000;
219		extern const device_type TMS0970;
220	285	extern const device_type TMS1070;
221	286	extern const device_type TMS1200;
222		extern const device_type TMS1270;
223	287	extern const device_type TMS1100;
224	288	extern const device_type TMS1300;
	289	extern const device_type TMS0970;
	290	extern const device_type TMS0980;
225	291
226	292
227	293	#endif /* _TMS0980_H_ */

trunk/src/mess/drivers/comp4.c
r242128	r242129
4	4
5	5	Milton Bradley Comp IV
6	6	* TMC0904NL CP0904A (die labeled 4A0970D-04A)
7
	7
8	8	This is a handheld Mastermind game; a code-breaking game where the player
9	9	needs to find out the correct sequence of colours (numbers in our case).
10	10	It is known as Logic 5 in Europe, and as Pythaligoras in Japan.
11
	11
12	12	Press the R key to start, followed by a set of unique numbers and E.
13	13	Refer to the official manual for more information.
14	14
15	15
16		TODO:
17		- write_r doesn't look right, maybe something missing in cpu emulation
18		- layout
19
20	16	***************************************************************************/
21	17
22	18	#include "emu.h"
23	19	#include "cpu/tms0980/tms0980.h"
24	20
	21	#include "comp4.lh"
	22
	23
25	24	// master clock is cpu internal, the value below is an approximation
26	25	#define MASTER_CLOCK (250000)
27	26
r242128	r242129
38	37	required_device<cpu_device> m_maincpu;
39	38	required_ioport_array<3> m_button_matrix;
40	39
	40	UINT16 m_leds_state;
	41	UINT8 m_leds_decay[0x10];
41	42	UINT16 m_r;
42	43	UINT16 m_o;
43	44
r242128	r242129
45	46	DECLARE_WRITE16_MEMBER(write_o);
46	47	DECLARE_WRITE16_MEMBER(write_r);
47	48
	49	TIMER_DEVICE_CALLBACK_MEMBER(leds_decay_tick);
	50	void leds_update();
	51
48	52	virtual void machine_start();
49	53	};
50	54
51	55
52	56	/***************************************************************************
53	57
	58	LEDs
	59
	60	***************************************************************************/
	61
	62	// The device strobes the outputs very fast, it is unnoticeable to the user.
	63	// To prevent flickering here, we need to simulate a decay.
	64
	65	// decay time, in steps of 10ms
	66	#define LEDS_DECAY_TIME 2
	67
	68	void comp4_state::leds_update()
	69	{
	70	for (int i = 0; i < 0x10; i++)
	71	{
	72	// turn on powered leds
	73	if (m_leds_state >> i & 1)
	74	m_leds_decay[i] = LEDS_DECAY_TIME;
	75
	76	// send to output
	77	output_set_lamp_value(i, (m_leds_decay[i] != 0) ? 1 : 0);
	78	}
	79	}
	80
	81	TIMER_DEVICE_CALLBACK_MEMBER(comp4_state::leds_decay_tick)
	82	{
	83	// slowly turn off unpowered leds
	84	for (int i = 0; i < 0x10; i++)
	85	if (!(m_leds_state >> i & 1) && m_leds_decay[i])
	86	m_leds_decay[i]--;
	87
	88	leds_update();
	89	}
	90
	91
	92
	93	/***************************************************************************
	94
54	95	I/O
55	96
56	97	***************************************************************************/
r242128	r242129
63	104	for (int i = 0; i < 3; i++)
64	105	if (m_o & (1 << (i + 1)))
65	106	k \|= m_button_matrix[i]->read();
66
	107
67	108	return k;
68	109	}
69	110
70	111	WRITE16_MEMBER(comp4_state::write_r)
71	112	{
72		// R..: LEDs
	113	// LEDs:
	114	// R4 R9
	115	// R10! R8
	116	// R2 R7
	117	// R1 R6
	118	// R0 R5
73	119	m_r = data;
	120
	121	m_leds_state = m_r;
	122	leds_update();
74	123	}
75	124
76	125	WRITE16_MEMBER(comp4_state::write_o)
77	126	{
78		// O0?: LEDs (common)
	127	// O0: LEDs common (always writes 1)
79	128	// O1-O3: input mux
80	129	// other bits: N/C
81	130	m_o = data;
r242128	r242129
90	139	***************************************************************************/
91	140
92	141	static INPUT_PORTS_START( comp4 )
93		PORT_START("IN.0")
94		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_R) PORT_CODE(KEYCODE_DEL_PAD) PORT_NAME("R")
95		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_4) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("4")
96		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_1) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("1")
97		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_7) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("7")
	142	PORT_START("IN.0") // O1
	143	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CODE(KEYCODE_DEL) PORT_CODE(KEYCODE_DEL_PAD) PORT_NAME("R")
	144	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("1")
	145	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("4")
	146	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("7")
98	147
99		PORT_START("IN.1")
100		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_0) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("0")
101		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_5) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("5")
102		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_2) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("2")
103		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_8) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("8")
	148	PORT_START("IN.1") // O2
	149	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("0")
	150	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("2")
	151	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("5")
	152	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("8")
104	153
105		PORT_START("IN.2")
106		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_E) PORT_CODE(KEYCODE_ENTER_PAD) PORT_NAME("E")
107		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_6) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
108		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_3) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
109		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_9) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
	154	PORT_START("IN.2") // O3
	155	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CODE(KEYCODE_ENTER) PORT_CODE(KEYCODE_ENTER_PAD) PORT_NAME("E")
	156	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
	157	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
	158	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
110	159	INPUT_PORTS_END
111	160
112	161
r242128	r242129
119	168
120	169	void comp4_state::machine_start()
121	170	{
	171	m_leds_state = 0;
	172	memset(m_leds_decay, 0, sizeof(m_leds_decay));
122	173	m_r = 0;
123	174	m_o = 0;
124
	175
125	176	save_item(NAME(m_r));
126	177	save_item(NAME(m_o));
127	178	}
128	179
129	180
130		static const UINT16 comp4_output_pla[0x20] =
131		{
132		// many unused bits, only O0 is actually used as external out
133		0xda, 0x96, 0x9b, 0x97, 0x98, 0x94, 0x99, 0x95,
134		0x9a, 0xa0, 0x94, 0x02, 0x35, 0x4a, 0x41, 0x00,
135		0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00,
136		0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00
137		};
138
139
140	181	static MACHINE_CONFIG_START( comp4, comp4_state )
141	182
142	183	/* basic machine hardware */
143	184	MCFG_CPU_ADD("maincpu", TMS0970, MASTER_CLOCK)
144		MCFG_TMS1XXX_OUTPUT_PLA(comp4_output_pla)
145		MCFG_TMS1XXX_READ_K(READ8(comp4_state, read_k))
146		MCFG_TMS1XXX_WRITE_O(WRITE16(comp4_state, write_o))
147		MCFG_TMS1XXX_WRITE_R(WRITE16(comp4_state, write_r))
	185	MCFG_TMS1XXX_READ_K_CB(READ8(comp4_state, read_k))
	186	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(comp4_state, write_o))
	187	MCFG_TMS1XXX_WRITE_R_CB(WRITE16(comp4_state, write_r))
	188
	189	MCFG_TIMER_DRIVER_ADD_PERIODIC("leds_decay", comp4_state, leds_decay_tick, attotime::from_msec(10))
148	190
	191	MCFG_DEFAULT_LAYOUT(layout_comp4)
	192
149	193	/* no video! */
150	194
151	195	/* no sound! */
r242128	r242129
161	205
162	206	ROM_START( comp4 )
163	207	ROM_REGION( 0x0400, "maincpu", 0 )
164		ROM_LOAD( "cp0904a", 0x0000, 0x0400, CRC(c502c8a1) SHA1(f82ff1a85c4849621d32344964d8b2233fc978d0) )
	208	ROM_LOAD( "tmc0904nl_cp0904a", 0x0000, 0x0400, CRC(6233ee1b) SHA1(738e109b38c97804b4ec52bed80b00a8634ad453) )
	209
	210	ROM_REGION( 782, "maincpu:ipla", 0 )
	211	ROM_LOAD( "tms0970_default_ipla.pla", 0, 782, CRC(e038fc44) SHA1(dfc280f6d0a5828d1bb14fcd59ac29caf2c2d981) )
	212	ROM_REGION( 860, "maincpu:mpla", 0 )
	213	ROM_LOAD( "tms0970_comp4_mpla.pla", 0, 860, CRC(ee9d7d9e) SHA1(25484e18f6a07f7cdb21a07220e2f2a82fadfe7b) )
	214	ROM_REGION( 352, "maincpu:opla", 0 )
	215	ROM_LOAD( "tms0970_comp4_opla.pla", 0, 352, CRC(a0f887d1) SHA1(3c666663d484d5bed81e1014f8715aab8a3d489f) )
	216	ROM_REGION( 157, "maincpu:spla", 0 )
	217	ROM_LOAD( "tms0970_comp4_spla.pla", 0, 157, CRC(e5bddd90) SHA1(4b1c6512c70e5bcd23c2dbf0c88cd8aa2c632a10) )
165	218	ROM_END
166	219
167	220
168		CONS( 1977, comp4, 0, 0, comp4, comp4, driver_device, 0, "Milton Bradley", "Comp IV", GAME_~~NOT_WORKING \| GAME_~~SUPPORTS_SAVE \| GAME_NO_SOUND_HW )
	221	CONS( 1977, comp4, 0, 0, comp4, comp4, driver_device, 0, "Milton Bradley", "Comp IV", GAME_SUPPORTS_SAVE \| GAME_NO_SOUND_HW )

trunk/src/mess/drivers/merlin.c
r242128	r242129
	1	// license:BSD-3-Clause
	2	// copyright-holders:Wilbert Pol, hap
1	3	/***************************************************************************
2	4
3	5	Parker Bros Merlin handheld computer game
r242128	r242129
2	4	* TMS1100NLL MP3404A-N2 (has internal ROM)
3
	5
4	6	To start a game, press NEW GAME, followed by a number:
r242128	r242129
10	12	4: Blackjack 13
11	13	5: Magic Square
12	14	6: Mindbender
13
	15
14	16	Refer to the official manual for more information on the games.
15
16
	17
	18
17	19	Other handhelds assumed to be on similar hardware:
18	20	- Dr. Smith - by Tomy, released in Japan (basically a white version of Merlin,
19	21	let's assume for now that the ROM contents is identical)
20	22	- Master Merlin
21
	23
22	24	Another sequel, called Split Second, looks like different hardware.
23	25
24	26
r242128	r242129
45	47	merlin_state(const machine_config &mconfig, device_type type, const char *tag)
46	48	: driver_device(mconfig, type, tag),
47	49	m_maincpu(*this, "maincpu"),
48		m_button_matrix(*this, "O"),
	50	m_button_matrix(*this, "IN"),
49	51	m_speaker(*this, "speaker")
50	52	{ }
51	53
r242128	r242129
70	72
71	73	***************************************************************************/
72	74
73		/* The keypad is a 4*4 matrix, connected like so:
74
75		+----+ +----+ +----+ +----+
76		O0 o---\| R0 \|--\| R1 \|--\| R2 \|--\| R3 \|
77		+----+ +----+ +----+ +----+
78		\| \| \| \|
79		+----+ +----+ +----+ +----+
80		O1 o---\| R4 \|--\| R5 \|--\| R6 \|--\| R7 \|
81		+----+ +----+ +----+ +----+
82		\| \| \| \|
83		+----+ +----+ +----+ +----+
84		O2 o---\| R8 \|--\| R9 \|--\|R10 \|--\| SG \|
85		+----+ +----+ +----+ +----+
86		\| \| \| \|
87		\| +----+ +----+ +----+
88		O3 o------+----\| CT \|--\| NG \|--\| HM \|
89		\| +----+ +----+ +----+
90		\| \| \| \|
91		o o o o
92		K1 K2 K8 K4
93
94		SG = same game, CT = comp turn, NG = new game, HM = hit me */
95
96	75	READ8_MEMBER(merlin_state::read_k)
97	76	{
98	77	UINT8 k = 0;
99
	78
100	79	// read selected button rows
101	80	for (int i = 0; i < 4; i++)
102	81	if (m_o & (1 << i))
r242128	r242129
143	122	***************************************************************************/
144	123
145	124	static INPUT_PORTS_START( merlin )
146		PORT_START("O.0")
147		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_0) PORT_CODE(KEYCODE_SLASH_PAD) PORT_NAME("Button 0")
148		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_1) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("Button 1")
149		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_3) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("Button 3")
150		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_2) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("Button 2")
	125	PORT_START("IN.0") // O0
	126	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_BUTTON1) PORT_CODE(KEYCODE_0) PORT_CODE(KEYCODE_SLASH_PAD) PORT_NAME("Button 0")
	127	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_BUTTON2) PORT_CODE(KEYCODE_1) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("Button 1")
	128	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_BUTTON4) PORT_CODE(KEYCODE_3) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("Button 3")
	129	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_BUTTON3) PORT_CODE(KEYCODE_2) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("Button 2")
151	130
152		PORT_START("O.1")
153		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_4) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("Button 4")
154		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_5) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("Button 5")
155		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_7) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("Button 7")
156		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_6) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("Button 6")
	131	PORT_START("IN.1") // O1
	132	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_BUTTON5) PORT_CODE(KEYCODE_4) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("Button 4")
	133	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_BUTTON6) PORT_CODE(KEYCODE_5) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("Button 5")
	134	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_BUTTON8) PORT_CODE(KEYCODE_7) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("Button 7")
	135	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_BUTTON7) PORT_CODE(KEYCODE_6) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("Button 6")
157	136
158		PORT_START("O.2")
159		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_8) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("Button 8")
160		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_9) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("Button 9")
161		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_S) PORT_NAME("Same Game")
162		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_MINUS) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("Button 10")
	137	PORT_START("IN.2") // O2
	138	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_BUTTON9) PORT_CODE(KEYCODE_8) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("Button 8")
	139	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_BUTTON10) PORT_CODE(KEYCODE_9) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("Button 9")
	140	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_BUTTON12) PORT_CODE(KEYCODE_S) PORT_NAME("Same Game")
	141	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_BUTTON11) PORT_CODE(KEYCODE_MINUS) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("Button 10")
163	142
164		PORT_START("O.3")
	143	PORT_START("IN.3") // O3
165	144	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNUSED)
166		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_C) PORT_NAME("Comp Turn")
167		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_H) PORT_NAME("Hit Me")
168		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_CODE(KEYCODE_N) PORT_NAME("New Game")
	145	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_BUTTON13) PORT_CODE(KEYCODE_C) PORT_NAME("Comp Turn")
	146	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_BUTTON15) PORT_CODE(KEYCODE_H) PORT_NAME("Hit Me")
	147	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_BUTTON14) PORT_CODE(KEYCODE_N) PORT_CODE(KEYCODE_ENTER) PORT_CODE(KEYCODE_ENTER_PAD) PORT_NAME("New Game")
169	148	INPUT_PORTS_END
170	149
171	150
r242128	r242129
200	179	/* basic machine hardware */
201	180	MCFG_CPU_ADD("maincpu", TMS1100, MERLIN_RC_CLOCK)
202	181	MCFG_TMS1XXX_OUTPUT_PLA(merlin_output_pla)
203		MCFG_TMS1XXX_READ_K(READ8( merlin_state, read_k))
204		MCFG_TMS1XXX_WRITE_O(WRITE16( merlin_state, write_o))
205		MCFG_TMS1XXX_WRITE_R(WRITE16( merlin_state, write_r))
	182	MCFG_TMS1XXX_READ_K_CB(READ8( merlin_state, read_k))
	183	MCFG_TMS1XXX_WRITE_O_CB(WRITE16( merlin_state, write_o))
	184	MCFG_TMS1XXX_WRITE_R_CB(WRITE16( merlin_state, write_r))
206	185
207	186	MCFG_DEFAULT_LAYOUT(layout_merlin)
208	187
r242128	r242129
230	209	// 0x5E to 0x1E to make 'Music Machine' working.
231	210	// The hashes below are from the manually changed dump
232	211	ROM_LOAD( "mp3404", 0x0000, 0x800, BAD_DUMP CRC(7515a75d) SHA1(76ca3605d3fde1df62f79b9bb1f534c2a2ae0229) )
	212
	213	ROM_REGION( 867, "maincpu:mpla", 0 )
	214	ROM_LOAD( "tms1100_default_mpla.pla", 0, 867, BAD_DUMP CRC(62445fc9) SHA1(d6297f2a4bc7a870b76cc498d19dbb0ce7d69fec) ) // not verified
	215	ROM_REGION( 365, "maincpu:opla", 0 )
	216	ROM_LOAD( "tms1100_merlin_opla.pla", 0, 365, NO_DUMP )
233	217	ROM_END
234	218
235	219

trunk/src/mess/drivers/microvsn.c
r242128	r242129
655	655	MCFG_CPU_IO_MAP( microvision_8021_io )
656	656	MCFG_CPU_ADD("maincpu2", TMS1100, 500000) // most games seem to be running at approximately this speed
657	657	MCFG_TMS1XXX_OUTPUT_PLA( microvision_output_pla_0 )
658		MCFG_TMS1XXX_READ_K( READ8( microvision_state, tms1100_read_k ) )
659		MCFG_TMS1XXX_WRITE_O( WRITE16( microvision_state, tms1100_write_o ) )
660		MCFG_TMS1XXX_WRITE_R( WRITE16( microvision_state, tms1100_write_r ) )
	658	MCFG_TMS1XXX_READ_K_CB( READ8( microvision_state, tms1100_read_k ) )
	659	MCFG_TMS1XXX_WRITE_O_CB( WRITE16( microvision_state, tms1100_write_o ) )
	660	MCFG_TMS1XXX_WRITE_R_CB( WRITE16( microvision_state, tms1100_write_r ) )
661	661
662	662	MCFG_SCREEN_ADD("screen", LCD)
663	663	MCFG_SCREEN_REFRESH_RATE(60)
r242128	r242129
695	695	ROM_START( microvsn )
696	696	ROM_REGION( 0x800, "maincpu1", ROMREGION_ERASE00 )
697	697	ROM_REGION( 0x800, "maincpu2", ROMREGION_ERASE00 )
	698	ROM_REGION( 867, "maincpu2:mpla", ROMREGION_ERASE00 )
	699	ROM_REGION( 365, "maincpu2:opla", ROMREGION_ERASE00 )
698	700	ROM_END
699	701
700	702

trunk/src/mess/drivers/simon.c
r242128	r242129
3	3	/***************************************************************************
4	4
5	5	Milton Bradley Simon
6
	6
7	7	Revision A hardware:
8	8	* TMS1000 (has internal ROM), DS75494 lamp driver
9
	9
10	10	Newer revisions have a smaller 16-pin MB4850 chip instead of the TMS1000.
11	11	This one has been decapped too, but we couldn't find an internal ROM.
12	12	It is possibly a cost-reduced custom ASIC specifically for Simon.
13
	13
14	14	Other games assumed to be on similar hardware:
15	15	- Pocket Simon, but there's a chance it only exists with MB4850 chip
16	16	- Super Simon (TMS1100)
r242128	r242129
61	61	READ8_MEMBER(simon_state::read_k)
62	62	{
63	63	UINT8 k = 0;
64
	64
65	65	// read selected button rows
66	66	for (int i = 0; i < 4; i++)
67	67	{
68		st~~atic~~ int r[4] = { 0, 1, 2, 9 };
	68	const int r[4] = { 0, 1, 2, 9 };
69	69	if (m_r & (1 << r[i]))
70	70	k \|= m_button_matrix[i]->read();
71	71	}
r242128	r242129
82	82	// R7 -> 75494 IN2 -> blue lamp
83	83	for (int i = 0; i < 4; i++)
84	84	output_set_lamp_value(i, data >> (4 + i) & 1);
85
	85
86	86	// R8 -> 75494 IN0 -> speaker
87	87	m_speaker->level_w(data >> 8 & 1);
88	88
r242128	r242129
106	106	***************************************************************************/
107	107
108	108	static INPUT_PORTS_START( simon )
109		PORT_START("IN.0")
	109	PORT_START("IN.0") // R0
110	110	PORT_CONFNAME( 0x07, 0x02, "Game Select")
111	111	PORT_CONFSETTING( 0x02, "1" )
112	112	PORT_CONFSETTING( 0x01, "2" )
113	113	PORT_CONFSETTING( 0x04, "3" )
114	114	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
115	115
116		PORT_START("IN.1")
	116	PORT_START("IN.1") // R1
117	117	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON5 ) PORT_NAME("Green Button")
118	118	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON6 ) PORT_NAME("Red Button")
119	119	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON7 ) PORT_NAME("Yellow Button")
120	120	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON8 ) PORT_NAME("Blue Button")
121	121
122		PORT_START("IN.2")
	122	PORT_START("IN.2") // R2
123	123	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START ) PORT_NAME("Start")
124	124	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("Last")
125	125	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("Longest")
126	126	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
127	127
128		PORT_START("IN.3")
	128	PORT_START("IN.3") // R9
129	129	PORT_CONFNAME( 0x0f, 0x01, "Skill Level")
130	130	PORT_CONFSETTING( 0x02, "1" )
131	131	PORT_CONFSETTING( 0x04, "2" )
r242128	r242129
148	148	}
149	149
150	150
151		static const UINT16 simon_output_pla[0x20] =
152		{
153		/* The output PLA just maps 1 2 4 8 and SL to O0-O4 */
154		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
155		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
156		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
157		0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
158		};
159
160
161	151	static MACHINE_CONFIG_START( simon, simon_state )
162	152
163	153	/* basic machine hardware */
164	154	MCFG_CPU_ADD("maincpu", TMS1000, SIMON_RC_CLOCK)
165		MCFG_TMS1XXX_OUTPUT_PLA(simon_output_pla)
166		MCFG_TMS1XXX_READ_K(READ8(simon_state, read_k))
167		MCFG_TMS1XXX_WRITE_O(WRITE16(simon_state, write_o))
168		MCFG_TMS1XXX_WRITE_R(WRITE16(simon_state, write_r))
	155	MCFG_TMS1XXX_READ_K_CB(READ8(simon_state, read_k))
	156	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(simon_state, write_o))
	157	MCFG_TMS1XXX_WRITE_R_CB(WRITE16(simon_state, write_r))
169	158
170	159	MCFG_DEFAULT_LAYOUT(layout_simon)
171	160
r242128	r242129
188	177	ROM_START( simon )
189	178	ROM_REGION( 0x0400, "maincpu", 0 )
190	179	ROM_LOAD( "tms1000.u1", 0x0000, 0x0400, CRC(9961719d) SHA1(35dddb018a8a2b31f377ab49c1f0cb76951b81c0) )
	180
	181	ROM_REGION( 867, "maincpu:mpla", 0 )
	182	ROM_LOAD( "tms1000_simon_mpla.pla", 0, 867, CRC(52f7c1f1) SHA1(dbc2634dcb98eac173ad0209df487cad413d08a5) )
	183	ROM_REGION( 365, "maincpu:opla", 0 )
	184	ROM_LOAD( "tms1000_simon_opla.pla", 0, 365, CRC(2943c71b) SHA1(bd5bb55c57e7ba27e49c645937ec1d4e67506601) )
191	185	ROM_END
192	186
193	187

trunk/src/mess/drivers/stopthie.c
r242128	r242129
51	51	}
52	52
53	53
54		static const UINT16 stopthie_output_pla[0x20] =
55		{
56		/* O output PLA configuration currently unknown */
57		0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
58		0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
59		0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
60		0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
61		};
62	54
63	55
	56
64	57	static MACHINE_CONFIG_START( stopthie, stopthie_state )
65	58
66	59	/* basic machine hardware */
67	60	MCFG_CPU_ADD( "maincpu", TMS0980, 500000 ) /* Clock is wrong */
68		MCFG_TMS1XXX_OUTPUT_PLA( stopthie_output_pla )
69		MCFG_TMS1XXX_READ_K( READ8( stopthie_state, stopthie_read_k ) )
70		MCFG_TMS1XXX_WRITE_O( WRITE16( stopthie_state, stopthie_write_o ) )
71		MCFG_TMS1XXX_WRITE_R( WRITE16( stopthie_state, stopthie_write_r ) )
	61	MCFG_TMS1XXX_READ_K_CB( READ8( stopthie_state, stopthie_read_k ) )
	62	MCFG_TMS1XXX_WRITE_O_CB( WRITE16( stopthie_state, stopthie_write_o ) )
	63	MCFG_TMS1XXX_WRITE_R_CB( WRITE16( stopthie_state, stopthie_write_r ) )
72	64
73	65	MCFG_DEFAULT_LAYOUT(layout_stopthie)
74	66	MACHINE_CONFIG_END
r242128	r242129
76	68	ROM_START( stopthie )
77	69	ROM_REGION( 0x1000, "maincpu", 0 )
78	70	ROM_LOAD16_WORD( "stopthie.bin", 0x0000, 0x1000, CRC(03691115) SHA1(bdcd212aa50bb1c26cb2d0ee97e5cfc04841c108) )
	71
	72	ROM_REGION( 1246, "maincpu:ipla", 0 )
	73	ROM_REGION( 1982, "maincpu:mpla", 0 )
	74	ROM_REGION( 352, "maincpu:opla", 0 )
	75	ROM_REGION( 157, "maincpu:spla", 0 )
79	76	ROM_END
80	77
81	78	/***************************************************************************

trunk/src/mess/drivers/ticalc1x.c
r242128	r242129
2	2	// copyright-holders:hap
3	3	/***************************************************************************
4	4
5		Texas Instruments TMS1xxx/0970/0980 handheld calculators
	5	Texas Instruments TMS1xxx/0970/0980 handheld calculators (mostly single-chip)
	6
	7	Refer to their official manuals on how to use them.
6	8
7		Texas Instruments WIZ-A-TRON
8		* TMC0907NL DP0907BS (die labeled 0970F-07B)
	9
	10	TODO:
	11	- ON/OFF button callbacks, and support OFF callback from the 0980
	12	- CPU clocks are unknown
9	13
10		Other handhelds assumed to be on similar hardware:
11		- Math Magic
12		- Little Professor
13	14
14
15		TODO:
16		- the rom goes in an infinite loop very soon, cpu missing emulation?
17
18	15	***************************************************************************/
19	16
20	17	#include "emu.h"
21	18	#include "cpu/tms0980/tms0980.h"
22	19
23		// master clock is cpu internal, the value below is an approximation
24		#define MASTER_CLOCK (250000)
	20	#include "ti1270.lh"
	21	#include "ti30.lh"
	22	#include "tisr16.lh"
	23	#include "wizatron.lh"
25	24
26	25
27	26	class ticalc1x_state : public driver_device
r242128	r242129
34	33	{ }
35	34
36	35	required_device<cpu_device> m_maincpu;
37		~~requ~~i~~red~~_ioport_array<4> m_button_matrix;
	36	optional_ioport_array<11> m_button_matrix; // up to 11 rows
38	37
39	38	UINT16 m_r;
40	39	UINT16 m_o;
41	40
42		DECLARE_READ8_MEMBER(read_k);
43		DECLARE_WRITE16_MEMBER(write_o);
44		DECLARE_WRITE16_MEMBER(write_r);
	41	UINT16 m_leds_state[0x10];
	42	UINT16 m_leds_cache[0x10];
	43	UINT8 m_leds_decay[0x100];
45	44
	45	DECLARE_READ8_MEMBER(tisr16_read_k);
	46	DECLARE_WRITE16_MEMBER(tisr16_write_o);
	47	DECLARE_WRITE16_MEMBER(tisr16_write_r);
	48	void tisr16_leds_update();
	49
	50	DECLARE_READ8_MEMBER(ti1270_read_k);
	51	DECLARE_WRITE16_MEMBER(ti1270_write_o);
	52	DECLARE_WRITE16_MEMBER(ti1270_write_r);
	53
	54	DECLARE_READ8_MEMBER(wizatron_read_k);
	55	DECLARE_WRITE16_MEMBER(wizatron_write_o);
	56	DECLARE_WRITE16_MEMBER(wizatron_write_r);
	57
	58	DECLARE_READ8_MEMBER(ti30_read_k);
	59	DECLARE_WRITE16_MEMBER(ti30_write_o);
	60	DECLARE_WRITE16_MEMBER(ti30_write_r);
	61
	62	TIMER_DEVICE_CALLBACK_MEMBER(leds_decay_tick);
	63	void leds_update();
	64
46	65	virtual void machine_start();
47	66	};
48	67
49	68
	69
50	70	/***************************************************************************
51	71
	72	LEDs
	73
	74	***************************************************************************/
	75
	76	// Devices with TMS09x0 strobe the outputs very fast, it is unnoticeable to the user.
	77	// To prevent flickering here, we need to simulate a decay.
	78
	79	// decay time, in steps of 10ms
	80	#define LEDS_DECAY_TIME 4
	81
	82	void ticalc1x_state::leds_update()
	83	{
	84	UINT16 active_state[0x10];
	85
	86	for (int i = 0; i < 0x10; i++)
	87	{
	88	active_state[i] = 0;
	89
	90	for (int j = 0; j < 0x10; j++)
	91	{
	92	int di = j << 4 \| i;
	93
	94	// turn on powered leds
	95	if (m_leds_state[i] >> j & 1)
	96	m_leds_decay[di] = LEDS_DECAY_TIME;
	97
	98	// determine active state
	99	int ds = (m_leds_decay[di] != 0) ? 1 : 0;
	100	active_state[i] \|= (ds << j);
	101	}
	102	}
	103
	104	// on difference, send to output
	105	for (int i = 0; i < 0x10; i++)
	106	if (m_leds_cache[i] != active_state[i])
	107	output_set_digit_value(i, active_state[i]);
	108
	109	memcpy(m_leds_cache, active_state, sizeof(m_leds_cache));
	110	}
	111
	112	TIMER_DEVICE_CALLBACK_MEMBER(ticalc1x_state::leds_decay_tick)
	113	{
	114	// slowly turn off unpowered leds
	115	for (int i = 0; i < 0x100; i++)
	116	if (!(m_leds_state[i & 0xf] >> (i>>4) & 1) && m_leds_decay[i])
	117	m_leds_decay[i]--;
	118
	119	leds_update();
	120	}
	121
	122
	123
	124	/***************************************************************************
	125
52	126	I/O
53	127
54	128	***************************************************************************/
55	129
56		READ8_MEMBER(ticalc1x_state::read_k)
	130	// TMS1000 - SR-16
	131
	132	void ticalc1x_state::tisr16_leds_update()
57	133	{
	134	// update leds state
	135	for (int i = 0; i < 11; i++)
	136	if (m_r >> i & 1)
	137	m_leds_state[i] = m_o;
	138
	139	// exponent sign
	140	m_leds_state[11] = (m_leds_state[0] \| m_leds_state[1]) ? 0x40 : 0;
	141
	142	// send to output
	143	for (int i = 0; i < 12; i++)
	144	output_set_digit_value(i, m_leds_state[i]);
	145	}
	146
	147	READ8_MEMBER(ticalc1x_state::tisr16_read_k)
	148	{
58	149	UINT8 k = 0;
59	150
60	151	// read selected button rows
	152	for (int i = 0; i < 11; i++)
	153	if (m_r & (1 << i))
	154	k \|= m_button_matrix[i]->read();
	155
	156	return k;
	157	}
	158
	159	WRITE16_MEMBER(ticalc1x_state::tisr16_write_r)
	160	{
	161	// R0-R10: input mux
	162	// R0-R10: select digit (right-to-left)
	163	m_r = data;
	164
	165	tisr16_leds_update();
	166	}
	167
	168	WRITE16_MEMBER(ticalc1x_state::tisr16_write_o)
	169	{
	170	// O0-O7: digit segments
	171	m_o = data;
	172
	173	tisr16_leds_update();
	174	}
	175
	176
	177	// TMS0970 - TI-1270
	178
	179	READ8_MEMBER(ticalc1x_state::ti1270_read_k)
	180	{
	181	UINT8 k = 0;
	182
	183	// read selected button rows
	184	for (int i = 0; i < 7; i++)
	185	if (m_o & (1 << (i + 1)))
	186	k \|= m_button_matrix[i]->read();
	187
	188	return k;
	189	}
	190
	191	WRITE16_MEMBER(ticalc1x_state::ti1270_write_r)
	192	{
	193	// R0-R7: select digit (right-to-left)
	194	for (int i = 0; i < 8; i++)
	195	m_leds_state[i] = (data >> i & 1) ? m_o : 0;
	196
	197	leds_update();
	198	}
	199
	200	WRITE16_MEMBER(ticalc1x_state::ti1270_write_o)
	201	{
	202	// O1-O5,O7: input mux
	203	// O0-O7: digit segments
	204	m_o = data;
	205	}
	206
	207
	208	// TMS0970 - WIZ-A-TRON (educational toy)
	209
	210	READ8_MEMBER(ticalc1x_state::wizatron_read_k)
	211	{
	212	UINT8 k = 0;
	213
	214	// read selected button rows
61	215	for (int i = 0; i < 4; i++)
62	216	if (m_o & (1 << (i + 1)))
63	217	k \|= m_button_matrix[i]->read();
r242128	r242129
65	219	return k;
66	220	}
67	221
68		WRITE16_MEMBER(ticalc1x_state::write_r)
	222	WRITE16_MEMBER(ticalc1x_state::wizatron_write_r)
69	223	{
70		// R..: select digit
71		m_r = data;
	224	// R0-R8: select digit (right-to-left)
	225	for (int i = 0; i < 9; i++)
	226	m_leds_state[i] = (data >> i & 1) ? m_o : 0;
	227
	228	// 3rd digit has more segments, for math symbols
	229	// let's assume it's a 14-seg led
	230	m_leds_state[6] = BITSWAP16(m_leds_state[6],15,14,2,1,6,4,3,0,5,5,11,10,9,13,12,8);
	231
	232	// 6th digit only has A and G for =
	233	m_leds_state[3] &= 0x41;
	234
	235	leds_update();
72	236	}
73	237
74		WRITE16_MEMBER(ticalc1x_state::write_o)
	238	WRITE16_MEMBER(ticalc1x_state::wizatron_write_o)
75	239	{
	240	// O1-O4: input mux
76	241	// O0-O6: digit segments A-G
77		// O1-O4: input mux
	242	// O7: N/C
	243	m_o = data & 0x7f;
	244	}
	245
	246
	247	// TMS0980 - TI-30, TI Programmer, TI Business Analyst-I
	248
	249	READ8_MEMBER(ticalc1x_state::ti30_read_k)
	250	{
	251	// the top row is always on
	252	UINT8 k = m_button_matrix[8]->read();
	253
	254	// read selected button rows
	255	for (int i = 0; i < 8; i++)
	256	if (m_o & (1 << i))
	257	k \|= m_button_matrix[i]->read();
	258
	259	return k;
	260	}
	261
	262	WRITE16_MEMBER(ticalc1x_state::ti30_write_r)
	263	{
	264	// R0-R8: select digit
	265	UINT8 o = BITSWAP8(m_o,7,5,2,1,4,0,6,3);
	266	for (int i = 0; i < 9; i++)
	267	m_leds_state[i] = (data >> i & 1) ? o : 0;
	268
	269	// 1st digit only has segments B,F,G,DP
	270	m_leds_state[0] &= 0xe2;
	271
	272	leds_update();
	273	}
	274
	275	WRITE16_MEMBER(ticalc1x_state::ti30_write_o)
	276	{
	277	// O1-O5,O7: input mux
	278	// O0-O7: digit segments
78	279	m_o = data;
79	280	}
80	281
r242128	r242129
86	287
87	288	***************************************************************************/
88	289
	290	static INPUT_PORTS_START( tisr16 )
	291	PORT_START("IN.0") // R0
	292	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	293	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS_PAD) PORT_NAME("-")
	294	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_NAME("RCL")
	295	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("0")
	296
	297	PORT_START("IN.1") // R1
	298	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	299	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_PLUS_PAD) PORT_NAME("+")
	300	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_NAME("CE")
	301	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("1")
	302
	303	PORT_START("IN.2") // R2
	304	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	305	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ASTERISK) PORT_NAME(UTF8_MULTIPLY)
	306	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_NAME("+/-")
	307	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("2")
	308
	309	PORT_START("IN.3") // R3
	310	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	311	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH_PAD) PORT_NAME(UTF8_DIVIDE)
	312	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_NAME(".")
	313	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
	314
	315	PORT_START("IN.4") // R4
	316	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	317	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ENTER_PAD) PORT_NAME("=")
	318	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_NAME("EE")
	319	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("4")
	320
	321	PORT_START("IN.5") // R5
	322	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	323	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_NAME(UTF8_CAPITAL_SIGMA)
	324	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_NAME("STO")
	325	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("5")
	326
	327	PORT_START("IN.6") // R6
	328	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	329	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_NAME("1/x")
	330	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_NAME("y"UTF8_POW_X)
	331	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
	332
	333	PORT_START("IN.7") // R7
	334	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	335	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_NAME("x"UTF8_POW_2)
	336	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
	337	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("7")
	338
	339	PORT_START("IN.8") // R8
	340	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	341	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_NAME("10"UTF8_POW_X)
	342	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_NAME("e"UTF8_POW_X)
	343	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("8")
	344
	345	PORT_START("IN.9") // R9
	346	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_UNUSED )
	347	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_NAME(UTF8_SQUAREROOT"x")
	348	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED )
	349	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
	350
	351	PORT_START("IN.10") // R10
	352	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_DEL_PAD) PORT_NAME("C")
	353	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_NAME("log")
	354	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_NAME("ln(x)")
	355	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
	356	INPUT_PORTS_END
	357
	358
	359	static INPUT_PORTS_START( ti1270 )
	360	PORT_START("IN.0") // O1
	361	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_NAME("CE/C")
	362	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_NAME("0")
	363	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_NAME(".")
	364	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_NAME("=")
	365
	366	PORT_START("IN.1") // O2
	367	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_NAME("1")
	368	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_NAME("2")
	369	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_NAME("3")
	370	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_NAME("+")
	371
	372	PORT_START("IN.2") // O3
	373	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_NAME("4")
	374	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_NAME("5")
	375	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_NAME("6")
	376	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_NAME("-")
	377
	378	PORT_START("IN.3") // O4
	379	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_NAME("7")
	380	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_NAME("8")
	381	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_NAME("9")
	382	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_NAME(UTF8_MULTIPLY)
	383
	384	PORT_START("IN.4") // O5
	385	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_NAME("STO")
	386	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_NAME("RCL")
	387	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_NAME(UTF8_SMALL_PI)
	388	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_NAME(UTF8_DIVIDE)
	389
	390	PORT_START("IN.5") // O6
	391	PORT_BIT( 0x0f, IP_ACTIVE_HIGH, IPT_UNUSED )
	392
	393	PORT_START("IN.6") // O7
	394	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_NAME("1/x")
	395	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_NAME("x"UTF8_POW_2)
	396	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_NAME(UTF8_SQUAREROOT"x")
	397	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_NAME("+/-")
	398	INPUT_PORTS_END
	399
	400
89	401	static INPUT_PORTS_START( wizatron )
90		PORT_START("IN.0")
91		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 )
92		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON2 )
93		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON3 )
94		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON4 )
	402	PORT_START("IN.0") // O1
	403	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_DEL_PAD) PORT_NAME("CLEAR")
	404	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("0")
	405	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ENTER_PAD) PORT_NAME("=")
	406	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_PLUS_PAD) PORT_NAME("+")
95	407
96		PORT_START("IN.1")
97		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER )
98		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER )
99		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER )
100		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER )
	408	PORT_START("IN.1") // O2
	409	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("1")
	410	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("2")
	411	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
	412	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS_PAD) PORT_NAME("-")
101	413
102		PORT_START("IN.2")
103		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER )
104		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER )
105		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER )
106		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER )
	414	PORT_START("IN.2") // O3
	415	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("4")
	416	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("5")
	417	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
	418	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ASTERISK) PORT_NAME(UTF8_MULTIPLY)
107	419
108		PORT_START("IN.3")
109		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER )
110		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER )
111		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER )
112		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER )
	420	PORT_START("IN.3") // O4
	421	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("7")
	422	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("8")
	423	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
	424	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH_PAD) PORT_NAME(UTF8_DIVIDE)
113	425	INPUT_PORTS_END
114	426
115	427
	428	static INPUT_PORTS_START( ti30 )
	429	PORT_START("IN.0") // O0
	430	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_NAME("y"UTF8_POW_X)
	431	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_NAME("K")
	432	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_NAME("log")
	433	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_NAME("EE"UTF8_DOWN)
	434	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("ln(x)")
116	435
	436	PORT_START("IN.1") // O1
	437	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_NAME(UTF8_MULTIPLY)
	438	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_NAME("STO")
	439	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_NAME("8")
	440	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_NAME("7")
	441	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
	442
	443	PORT_START("IN.2") // O2
	444	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_NAME("-")
	445	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_NAME("RCL")
	446	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_NAME("5")
	447	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_NAME("4")
	448	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
	449
	450	PORT_START("IN.3") // O3
	451	PORT_BIT( 0x1f, IP_ACTIVE_HIGH, IPT_UNUSED )
	452
	453	PORT_START("IN.4") // O4
	454	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_NAME(UTF8_DIVIDE)
	455	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_NAME(UTF8_SMALL_PI)
	456	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_NAME("(")
	457	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_NAME("%")
	458	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME(")")
	459
	460	PORT_START("IN.5") // O5
	461	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_NAME("+")
	462	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_NAME("SUM")
	463	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_NAME("2")
	464	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_NAME("1")
	465	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
	466
	467	PORT_START("IN.6") // O6
	468	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_NAME("DRG")
	469	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_NAME("INV")
	470	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_NAME("cos")
	471	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_NAME("sin")
	472	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("tan")
	473
	474	PORT_START("IN.7") // O7
	475	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_NAME("=")
	476	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_NAME("EXC")
	477	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_NAME(".")
	478	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_NAME("0")
	479	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("+/-")
	480
	481	// note: even though power buttons are on the matrix, they are not CPU-controlled
	482	PORT_START("IN.8") // Vss!
	483	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_NAME("ON/C")
	484	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_NAME("1/x")
	485	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_NAME(UTF8_SQUAREROOT"x")
	486	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_NAME("x"UTF8_POW_2)
	487	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("OFF")
	488	INPUT_PORTS_END
	489
	490
	491	static INPUT_PORTS_START( tiprog )
	492	PORT_START("IN.0") // O0
	493	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_NAME("K")
	494	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_NAME("SHF")
	495	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_NAME("E")
	496	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_NAME("d")
	497	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("F")
	498
	499	PORT_START("IN.1") // O1
	500	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_NAME(UTF8_MULTIPLY)
	501	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_NAME("OR")
	502	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_NAME("8")
	503	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_NAME("7")
	504	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
	505
	506	PORT_START("IN.2") // O2
	507	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_NAME("-")
	508	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_NAME("AND")
	509	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_NAME("5")
	510	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_NAME("4")
	511	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
	512
	513	PORT_START("IN.3") // O3
	514	PORT_BIT( 0x1f, IP_ACTIVE_HIGH, IPT_UNUSED )
	515
	516	PORT_START("IN.4") // O4
	517	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_NAME(UTF8_DIVIDE)
	518	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_NAME("1'sC")
	519	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_NAME("b")
	520	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_NAME("A")
	521	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("C")
	522
	523	PORT_START("IN.5") // O5
	524	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_NAME("+")
	525	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_NAME("XOR")
	526	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_NAME("2")
	527	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_NAME("1")
	528	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
	529
	530	PORT_START("IN.6") // O6
	531	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_NAME(")")
	532	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_NAME("STO")
	533	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_NAME("SUM")
	534	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_NAME("RCL")
	535	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("(")
	536
	537	PORT_START("IN.7") // O7
	538	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_NAME("=")
	539	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_NAME("CE")
	540	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_NAME(".")
	541	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_NAME("0")
	542	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("+/-")
	543
	544	// note: even though power buttons are on the matrix, they are not CPU-controlled
	545	PORT_START("IN.8") // Vss!
	546	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_NAME("C/ON")
	547	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_NAME("DEC")
	548	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_NAME("OCT")
	549	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_NAME("HEX")
	550	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("OFF")
	551	INPUT_PORTS_END
	552
	553
	554	static INPUT_PORTS_START( tibusan1 )
	555	// PORT_NAME lists functions under [2nd] as secondaries.
	556	PORT_START("IN.0") // O0
	557	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_NAME("y"UTF8_POW_X" "UTF8_POW_X""UTF8_SQUAREROOT"y") // 2nd one implies xth root of y
	558	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_NAME("% "UTF8_CAPITAL_DELTA"%")
	559	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_NAME("SEL")
	560	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_NAME("CST")
	561	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("MAR")
	562
	563	PORT_START("IN.1") // O1
	564	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_NAME(UTF8_MULTIPLY)
	565	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_NAME("STO m")
	566	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_NAME("8")
	567	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_NAME("7")
	568	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9")
	569
	570	PORT_START("IN.2") // O2
	571	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_NAME("-")
	572	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_NAME("RCL b")
	573	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_NAME("5")
	574	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_NAME("4")
	575	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("6")
	576
	577	PORT_START("IN.3") // O3
	578	PORT_BIT( 0x1f, IP_ACTIVE_HIGH, IPT_UNUSED )
	579
	580	PORT_START("IN.4") // O4
	581	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_NAME(UTF8_DIVIDE)
	582	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_NAME(UTF8_CAPITAL_SIGMA"+ "UTF8_CAPITAL_SIGMA"-")
	583	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_NAME("( AN-CI\"")
	584	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_NAME("x<>y L.R.")
	585	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME(") 1/x")
	586
	587	PORT_START("IN.5") // O5
	588	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_NAME("+")
	589	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_NAME("SUM x"UTF8_PRIME)
	590	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_NAME("2")
	591	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_NAME("1")
	592	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("3")
	593
	594	PORT_START("IN.6") // O6
	595	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_NAME("FV")
	596	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_NAME("N")
	597	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_NAME("PMT")
	598	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_NAME("%i")
	599	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("PV")
	600
	601	PORT_START("IN.7") // O7
	602	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_NAME("=")
	603	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_NAME("EXC x"UTF8_PRIME)
	604	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_NAME(".")
	605	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_NAME("0")
	606	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("+/-")
	607
	608	// note: even though power buttons are on the matrix, they are not CPU-controlled
	609	PORT_START("IN.8") // Vss!
	610	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_NAME("ON/C")
	611	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_NAME("2nd")
	612	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_NAME("x"UTF8_POW_2" "UTF8_SQUAREROOT"x")
	613	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_NAME("ln(x) e"UTF8_POW_X)
	614	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("OFF")
	615	INPUT_PORTS_END
	616
	617
	618
117	619	/***************************************************************************
118	620
119		Machine Config
	621	Machine Config(s)
120	622
121	623	***************************************************************************/
122	624
123	625	void ticalc1x_state::machine_start()
124	626	{
	627	memset(m_leds_state, 0, sizeof(m_leds_state));
	628	memset(m_leds_cache, 0, sizeof(m_leds_cache));
	629	memset(m_leds_decay, 0, sizeof(m_leds_decay));
125	630	m_r = 0;
126	631	m_o = 0;
127	632
r242128	r242129
130	635	}
131	636
132	637
133		static const UINT16 wizatron_output_pla[0x20] =
134		{
135		// 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, +, -, X, /, r
136		0x7e, 0x30, 0x6d, 0x79, 0x33, 0x5b, 0x5f, 0x70,
137		0x7f, 0x7b, 0x26, 0x02, 0x35, 0x4a, 0x05, 0x00,
138		0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00,
139		0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00, 0xff00
140		};
	638	static MACHINE_CONFIG_START( tisr16, ticalc1x_state )
141	639
	640	/* basic machine hardware */
	641	MCFG_CPU_ADD("maincpu", TMS1000, 250000)
	642	MCFG_TMS1XXX_READ_K_CB(READ8(ticalc1x_state, tisr16_read_k))
	643	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(ticalc1x_state, tisr16_write_o))
	644	MCFG_TMS1XXX_WRITE_R_CB(WRITE16(ticalc1x_state, tisr16_write_r))
142	645
143		static MACHINE_CONFIG_START( wizatron, ticalc1x_state )
	646	MCFG_DEFAULT_LAYOUT(layout_tisr16)
	647	MACHINE_CONFIG_END
144	648
	649
	650	static MACHINE_CONFIG_START( t9base, ticalc1x_state )
	651
145	652	/* basic machine hardware */
146		MCFG_CPU_ADD("maincpu", TMS0970, MASTER_CLOCK)
147		MCFG_TMS1XXX_OUTPUT_PLA(wizatron_output_pla)
148		MCFG_TMS1XXX_READ_K(READ8(ticalc1x_state, read_k))
149		MCFG_TMS1XXX_WRITE_O(WRITE16(ticalc1x_state, write_o))
150		MCFG_TMS1XXX_WRITE_R(WRITE16(ticalc1x_state, write_r))
	653	MCFG_TIMER_DRIVER_ADD_PERIODIC("leds_decay", ticalc1x_state, leds_decay_tick, attotime::from_msec(10))
151	654
152	655	/* no video! */
153	656
154	657	/* no sound! */
155	658	MACHINE_CONFIG_END
156	659
	660	static MACHINE_CONFIG_DERIVED( ti1270, t9base )
157	661
	662	/* basic machine hardware */
	663	MCFG_CPU_ADD("maincpu", TMS0970, 250000)
	664	MCFG_TMS1XXX_READ_K_CB(READ8(ticalc1x_state, ti1270_read_k))
	665	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(ticalc1x_state, ti1270_write_o))
	666	MCFG_TMS1XXX_WRITE_R_CB(WRITE16(ticalc1x_state, ti1270_write_r))
158	667
	668	MCFG_DEFAULT_LAYOUT(layout_ti1270)
	669	MACHINE_CONFIG_END
	670
	671	static MACHINE_CONFIG_DERIVED( wizatron, t9base )
	672
	673	/* basic machine hardware */
	674	MCFG_CPU_ADD("maincpu", TMS0970, 250000)
	675	MCFG_TMS1XXX_READ_K_CB(READ8(ticalc1x_state, wizatron_read_k))
	676	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(ticalc1x_state, wizatron_write_o))
	677	MCFG_TMS1XXX_WRITE_R_CB(WRITE16(ticalc1x_state, wizatron_write_r))
	678
	679	MCFG_DEFAULT_LAYOUT(layout_wizatron)
	680	MACHINE_CONFIG_END
	681
	682
	683	static MACHINE_CONFIG_DERIVED( ti30, t9base )
	684
	685	/* basic machine hardware */
	686	MCFG_CPU_ADD("maincpu", TMS0980, 250000)
	687	MCFG_TMS1XXX_READ_K_CB(READ8(ticalc1x_state, ti30_read_k))
	688	MCFG_TMS1XXX_WRITE_O_CB(WRITE16(ticalc1x_state, ti30_write_o))
	689	MCFG_TMS1XXX_WRITE_R_CB(WRITE16(ticalc1x_state, ti30_write_r))
	690
	691	MCFG_DEFAULT_LAYOUT(layout_ti30)
	692	MACHINE_CONFIG_END
	693
	694
	695
159	696	/***************************************************************************
160	697
161	698	Game driver(s)
162	699
163	700	***************************************************************************/
164	701
	702	ROM_START( tisr16 )
	703	ROM_REGION( 0x0400, "maincpu", 0 )
	704	ROM_LOAD( "tms1001nl", 0x0000, 0x0400, CRC(b7ce3c1d) SHA1(95cdb0c6be31043f4fe06314ed41c0ca1337bc46) )
	705
	706	ROM_REGION( 867, "maincpu:mpla", 0 )
	707	ROM_LOAD( "tms1000_sr16_mpla.pla", 0, 867, CRC(5b35019c) SHA1(730d3b9041ed76d57fbedd73b009477fe432b386) )
	708	ROM_REGION( 365, "maincpu:opla", 0 )
	709	ROM_LOAD( "tms1000_sr16_opla.pla", 0, 365, CRC(29b08739) SHA1(d55f01e40a2d493d45ea422f12e63b01bcde08fb) )
	710	ROM_END
	711
	712	ROM_START( ti1270 )
	713	ROM_REGION( 0x0400, "maincpu", 0 )
	714	ROM_LOAD( "tms0974nl", 0x0000, 0x0400, CRC(48e09b4b) SHA1(17f27167164df223f9f06082ece4c3fc3900eda3) )
	715
	716	ROM_REGION( 782, "maincpu:ipla", 0 )
	717	ROM_LOAD( "tms0970_ti1270_ipla.pla", 0, 782, CRC(05306ef8) SHA1(60a0a3c49ce330bce0c27f15f81d61461d0432ce) )
	718	ROM_REGION( 860, "maincpu:mpla", 0 )
	719	ROM_LOAD( "tms0970_ti1270_mpla.pla", 0, 860, CRC(6ff5d51d) SHA1(59d3e5de290ba57694068ddba78d21a0c1edf427) )
	720	ROM_REGION( 352, "maincpu:opla", 0 )
	721	ROM_LOAD( "tms0970_ti1270_opla.pla", 0, 352, CRC(f39bf0a4) SHA1(160341490043eb369720d5f487cf0f59f458a93e) )
	722	ROM_REGION( 157, "maincpu:spla", 0 )
	723	ROM_LOAD( "tms0970_ti1270_spla.pla", 0, 157, CRC(56c37a4f) SHA1(18ecc20d2666e89673739056483aed5a261ae927) )
	724	ROM_END
	725
165	726	ROM_START( wizatron )
166	727	ROM_REGION( 0x0400, "maincpu", 0 )
167	728	ROM_LOAD( "dp0907bs", 0x0000, 0x0400, CRC(5a6af094) SHA1(b1f27e1f13f4db3b052dd50fb08dbf9c4d8db26e) )
	729
	730	ROM_REGION( 782, "maincpu:ipla", 0 )
	731	ROM_LOAD( "tms0970_wizatron_ipla.pla", 0, 782, CRC(05306ef8) SHA1(60a0a3c49ce330bce0c27f15f81d61461d0432ce) )
	732	ROM_REGION( 860, "maincpu:mpla", 0 )
	733	ROM_LOAD( "tms0970_wizatron_mpla.pla", 0, 860, CRC(7f50ab2e) SHA1(bff3be9af0e322986f6e545b567c97d70e135c93) )
	734	ROM_REGION( 352, "maincpu:opla", 0 )
	735	ROM_LOAD( "tms0970_wizatron_opla.pla", 0, 352, CRC(745a3900) SHA1(031b55a0cf783c8a88eec4289d4373eb8538f374) )
	736	ROM_REGION( 157, "maincpu:spla", 0 )
	737	ROM_LOAD( "tms0970_wizatron_spla.pla", 0, 157, CRC(56c37a4f) SHA1(18ecc20d2666e89673739056483aed5a261ae927) )
168	738	ROM_END
169	739
	740	ROM_START( ti30 )
	741	ROM_REGION( 0x1000, "maincpu", 0 )
	742	ROM_LOAD16_WORD( "tmc0981nl", 0x0000, 0x1000, CRC(41298a14) SHA1(06f654c70add4044a612d3a38b0c2831c188fd0c) )
170	743
171		CONS( 1977, wizatron, 0, 0, wizatron, wizatron, driver_device, 0, "Texas Instruments", "Wiz-A-Tron", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE \| GAME_NO_SOUND_HW )
	744	ROM_REGION( 1246, "maincpu:ipla", 0 )
	745	ROM_LOAD( "tms0980_default_ipla.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
	746	ROM_REGION( 1982, "maincpu:mpla", 0 )
	747	ROM_LOAD( "tms0980_default_mpla.pla", 0, 1982, CRC(3709014f) SHA1(d28ee59ded7f3b9dc3f0594a32a98391b6e9c961) )
	748	ROM_REGION( 352, "maincpu:opla", 0 )
	749	ROM_LOAD( "tms0980_ti30_opla.pla", 0, 352, CRC(38788410) SHA1(cb3d1a61190b887cd2e6d9c60b4fdb9b901f7eed) )
	750	ROM_REGION( 157, "maincpu:spla", 0 )
	751	ROM_LOAD( "tms0980_ti30_spla.pla", 0, 157, CRC(399aa481) SHA1(72c56c58fde3fbb657d69647a9543b5f8fc74279) )
	752	ROM_END
	753
	754	ROM_START( tibusan1 )
	755	ROM_REGION( 0x1000, "maincpu", 0 )
	756	ROM_LOAD16_WORD( "tmc0982nl", 0x0000, 0x1000, CRC(6954560a) SHA1(6c153a0c9239a811e3514a43d809964c06f8f88e) )
	757
	758	ROM_REGION( 1246, "maincpu:ipla", 0 )
	759	ROM_LOAD( "tms0980_default_ipla.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
	760	ROM_REGION( 1982, "maincpu:mpla", 0 )
	761	ROM_LOAD( "tms0980_default_mpla.pla", 0, 1982, CRC(3709014f) SHA1(d28ee59ded7f3b9dc3f0594a32a98391b6e9c961) )
	762	ROM_REGION( 352, "maincpu:opla", 0 )
	763	ROM_LOAD( "tms0980_tibusan1_opla.pla", 0, 352, CRC(38788410) SHA1(cb3d1a61190b887cd2e6d9c60b4fdb9b901f7eed) )
	764	ROM_REGION( 157, "maincpu:spla", 0 )
	765	ROM_LOAD( "tms0980_tibusan1_spla.pla", 0, 157, CRC(399aa481) SHA1(72c56c58fde3fbb657d69647a9543b5f8fc74279) )
	766	ROM_END
	767
	768	ROM_START( tiprog )
	769	ROM_REGION( 0x1000, "maincpu", 0 )
	770	ROM_LOAD16_WORD( "za0675nl", 0x0000, 0x1000, CRC(82355854) SHA1(03fab373bce04df8ea3fe25352525e8539213626) )
	771
	772	ROM_REGION( 1246, "maincpu:ipla", 0 )
	773	ROM_LOAD( "tms0980_default_ipla.pla", 0, 1246, CRC(42db9a38) SHA1(2d127d98028ec8ec6ea10c179c25e447b14ba4d0) )
	774	ROM_REGION( 1982, "maincpu:mpla", 0 )
	775	ROM_LOAD( "tms0980_tiprog_mpla.pla", 0, 1982, CRC(57043284) SHA1(0fa06d5865830ecdb3d870271cb92ac917bed3ca) )
	776	ROM_REGION( 352, "maincpu:opla", 0 )
	777	ROM_LOAD( "tms0980_tiprog_opla.pla", 0, 352, BAD_DUMP CRC(2a63956f) SHA1(26a62ca2b5973d8564e580e12230292f6d2888d9) ) // corrected by hand
	778	ROM_REGION( 157, "maincpu:spla", 0 )
	779	ROM_LOAD( "tms0980_tiprog_spla.pla", 0, 157, CRC(399aa481) SHA1(72c56c58fde3fbb657d69647a9543b5f8fc74279) )
	780	ROM_END
	781
	782
	783
	784	COMP( 1974, tisr16, 0, 0, tisr16, tisr16, driver_device, 0, "Texas Instruments", "SR-16 (Texas Instruments)", GAME_SUPPORTS_SAVE \| GAME_NO_SOUND_HW )
	785
	786	COMP( 1976, ti1270, 0, 0, ti1270, ti1270, driver_device, 0, "Texas Instruments", "TI-1270", GAME_SUPPORTS_SAVE \| GAME_NO_SOUND_HW )
	787	COMP( 1977, wizatron, 0, 0, wizatron, wizatron, driver_device, 0, "Texas Instruments", "Wiz-A-Tron", GAME_SUPPORTS_SAVE \| GAME_NO_SOUND_HW )
	788
	789	COMP( 1976, ti30, 0, 0, ti30, ti30, driver_device, 0, "Texas Instruments", "TI-30", GAME_SUPPORTS_SAVE \| GAME_NO_SOUND_HW )
	790	COMP( 1977, tiprog, 0, 0, ti30, tiprog, driver_device, 0, "Texas Instruments", "TI Programmer", GAME_SUPPORTS_SAVE \| GAME_NO_SOUND_HW )
	791	COMP( 1979, tibusan1, 0, 0, ti30, tibusan1, driver_device, 0, "Texas Instruments", "TI Business Analyst-I", GAME_SUPPORTS_SAVE \| GAME_NO_SOUND_HW )

trunk/src/mess/layout/comp4.lay
r0	r242129
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3
	4	<element name="lamp_disk_red" defstate="0">
	5	<disk state="1"><color red="1.0" green="0.3" blue="0.2" /></disk>
	6	<disk state="0"><color red="0.2" green="0.05" blue="0.03" /></disk>
	7	</element>
	8
	9	<view name="Internal Layout">
	10	<bounds left="0" right="180" top="0" bottom="100" />
	11
	12	<bezel name="lamp4" element="lamp_disk_red">
	13	<bounds x="10" y="50" width="5" height="5" />
	14	</bezel>
	15	<bezel name="lamp10" element="lamp_disk_red">
	16	<bounds x="10" y="60" width="5" height="5" />
	17	</bezel>
	18	<bezel name="lamp2" element="lamp_disk_red">
	19	<bounds x="10" y="70" width="5" height="5" />
	20	</bezel>
	21	<bezel name="lamp1" element="lamp_disk_red">
	22	<bounds x="10" y="80" width="5" height="5" />
	23	</bezel>
	24	<bezel name="lamp0" element="lamp_disk_red">
	25	<bounds x="10" y="90" width="5" height="5" />
	26	</bezel>
	27
	28	<bezel name="lamp9" element="lamp_disk_red">
	29	<bounds x="30" y="50" width="5" height="5" />
	30	</bezel>
	31	<bezel name="lamp8" element="lamp_disk_red">
	32	<bounds x="30" y="60" width="5" height="5" />
	33	</bezel>
	34	<bezel name="lamp7" element="lamp_disk_red">
	35	<bounds x="30" y="70" width="5" height="5" />
	36	</bezel>
	37	<bezel name="lamp6" element="lamp_disk_red">
	38	<bounds x="30" y="80" width="5" height="5" />
	39	</bezel>
	40	<bezel name="lamp5" element="lamp_disk_red">
	41	<bounds x="30" y="90" width="5" height="5" />
	42	</bezel>
	43
	44	</view>
	45	</mamelayout>

trunk/src/mess/layout/merlin.lay
r242128	r242129
256	256	<bezel name="lamp0" element="led">
257	257	<bounds x="34" y="20" width="20" height="20" />
258	258	</bezel>
259		<bezel element="button" inputtag="O.0" inputmask="0x01">
	259	<bezel element="button" inputtag="IN.0" inputmask="0x01">
260	260	<bounds x="34" y="20" width="20" height="20" />
261	261	<color alpha="0.2" />
262	262	</bezel>
r242128	r242129
267	267	<bezel name="lamp1" element="led">
268	268	<bounds x="10" y="44" width="20" height="20" />
269	269	</bezel>
270		<bezel element="button" inputtag="O.0" inputmask="0x02">
	270	<bezel element="button" inputtag="IN.0" inputmask="0x02">
271	271	<bounds x="10" y="44" width="20" height="20" />
272	272	<color alpha="0.2" />
273	273	</bezel>
r242128	r242129
277	277	<bezel name="lamp2" element="led">
278	278	<bounds x="34" y="44" width="20" height="20" />
279	279	</bezel>
280		<bezel element="button" inputtag="O.0" inputmask="0x08">
	280	<bezel element="button" inputtag="IN.0" inputmask="0x08">
281	281	<bounds x="34" y="44" width="20" height="20" />
282	282	<color alpha="0.2" />
283	283	</bezel>
r242128	r242129
287	287	<bezel name="lamp3" element="led">
288	288	<bounds x="58" y="44" width="20" height="20" />
289	289	</bezel>
290		<bezel element="button" inputtag="O.0" inputmask="0x04">
	290	<bezel element="button" inputtag="IN.0" inputmask="0x04">
291	291	<bounds x="58" y="44" width="20" height="20" />
292	292	<color alpha="0.2" />
293	293	</bezel>
r242128	r242129
298	298	<bezel name="lamp4" element="led">
299	299	<bounds x="10" y="68" width="20" height="20" />
300	300	</bezel>
301		<bezel element="button" inputtag="O.1" inputmask="0x01">
	301	<bezel element="button" inputtag="IN.1" inputmask="0x01">
302	302	<bounds x="10" y="68" width="20" height="20" />
303	303	<color alpha="0.2" />
304	304	</bezel>
r242128	r242129
308	308	<bezel name="lamp5" element="led">
309	309	<bounds x="34" y="68" width="20" height="20" />
310	310	</bezel>
311		<bezel element="button" inputtag="O.1" inputmask="0x02">
	311	<bezel element="button" inputtag="IN.1" inputmask="0x02">
312	312	<bounds x="34" y="68" width="20" height="20" />
313	313	<color alpha="0.2" />
314	314	</bezel>
r242128	r242129
318	318	<bezel name="lamp6" element="led">
319	319	<bounds x="58" y="68" width="20" height="20" />
320	320	</bezel>
321		<bezel element="button" inputtag="O.1" inputmask="0x08">
	321	<bezel element="button" inputtag="IN.1" inputmask="0x08">
322	322	<bounds x="58" y="68" width="20" height="20" />
323	323	<color alpha="0.2" />
324	324	</bezel>
r242128	r242129
329	329	<bezel name="lamp7" element="led">
330	330	<bounds x="10" y="92" width="20" height="20" />
331	331	</bezel>
332		<bezel element="button" inputtag="O.1" inputmask="0x04">
	332	<bezel element="button" inputtag="IN.1" inputmask="0x04">
333	333	<bounds x="10" y="92" width="20" height="20" />
334	334	<color alpha="0.2" />
335	335	</bezel>
r242128	r242129
339	339	<bezel name="lamp8" element="led">
340	340	<bounds x="34" y="92" width="20" height="20" />
341	341	</bezel>
342		<bezel element="button" inputtag="O.2" inputmask="0x01">
	342	<bezel element="button" inputtag="IN.2" inputmask="0x01">
343	343	<bounds x="34" y="92" width="20" height="20" />
344	344	<color alpha="0.2" />
345	345	</bezel>
r242128	r242129
349	349	<bezel name="lamp9" element="led">
350	350	<bounds x="58" y="92" width="20" height="20" />
351	351	</bezel>
352		<bezel element="button" inputtag="O.2" inputmask="0x02">
	352	<bezel element="button" inputtag="IN.2" inputmask="0x02">
353	353	<bounds x="58" y="92" width="20" height="20" />
354	354	<color alpha="0.2" />
355	355	</bezel>
r242128	r242129
360	360	<bezel name="lamp10" element="led">
361	361	<bounds x="34" y="116" width="20" height="20" />
362	362	</bezel>
363		<bezel element="button" inputtag="O.2" inputmask="0x08">
	363	<bezel element="button" inputtag="IN.2" inputmask="0x08">
364	364	<bounds x="34" y="116" width="20" height="20" />
365	365	<color alpha="0.2" />
366	366	</bezel>
r242128	r242129
371	371	<bezel element="panel_newgame">
372	372	<bounds x="21" y="156" width="20" height="20" />
373	373	</bezel>
374		<bezel element="button" inputtag="O.3" inputmask="0x08">
	374	<bezel element="button" inputtag="IN.3" inputmask="0x08">
375	375	<bounds x="21" y="156" width="20" height="20" />
376	376	<color alpha="0.2" />
377	377	</bezel>
r242128	r242129
379	379	<bezel element="panel_samegame">
380	380	<bounds x="47" y="156" width="20" height="20" />
381	381	</bezel>
382		<bezel element="button" inputtag="O.2" inputmask="0x04">
	382	<bezel element="button" inputtag="IN.2" inputmask="0x04">
383	383	<bounds x="47" y="156" width="20" height="20" />
384	384	<color alpha="0.2" />
385	385	</bezel>
r242128	r242129
387	387	<bezel element="panel_hitme">
388	388	<bounds x="21" y="182" width="20" height="20" />
389	389	</bezel>
390		<bezel element="button" inputtag="O.3" inputmask="0x04">
	390	<bezel element="button" inputtag="IN.3" inputmask="0x04">
391	391	<bounds x="21" y="182" width="20" height="20" />
392	392	<color alpha="0.2" />
393	393	</bezel>
r242128	r242129
395	395	<bezel element="panel_compturn">
396	396	<bounds x="47" y="182" width="20" height="20" />
397	397	</bezel>
398		<bezel element="button" inputtag="O.3" inputmask="0x02">
	398	<bezel element="button" inputtag="IN.3" inputmask="0x02">
399	399	<bounds x="47" y="182" width="20" height="20" />
400	400	<color alpha="0.2" />
401	401	</bezel>

trunk/src/mess/layout/ti1270.lay
r0	r242129
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3
	4	<!-- note: the digits were very small, wide space between them, and not the same style as (MAME's-)default -->
	5
	6	<element name="digit" defstate="0">
	7	<led7seg><color red="1.0" green="0.15" blue="0.08" /></led7seg>
	8	</element>
	9
	10	<view name="Internal Layout">
	11	<bounds left="0" right="120" top="0" bottom="15" />
	12
	13	<bezel name="digit7" element="digit">
	14	<bounds x="0" y="0" width="10" height="15" />
	15	</bezel>
	16	<bezel name="digit6" element="digit">
	17	<bounds x="15" y="0" width="10" height="15" />
	18	</bezel>
	19	<bezel name="digit5" element="digit">
	20	<bounds x="30" y="0" width="10" height="15" />
	21	</bezel>
	22	<bezel name="digit4" element="digit">
	23	<bounds x="45" y="0" width="10" height="15" />
	24	</bezel>
	25	<bezel name="digit3" element="digit">
	26	<bounds x="60" y="0" width="10" height="15" />
	27	</bezel>
	28	<bezel name="digit2" element="digit">
	29	<bounds x="75" y="0" width="10" height="15" />
	30	</bezel>
	31	<bezel name="digit1" element="digit">
	32	<bounds x="90" y="0" width="10" height="15" />
	33	</bezel>
	34	<bezel name="digit0" element="digit">
	35	<bounds x="105" y="0" width="10" height="15" />
	36	</bezel>
	37
	38	</view>
	39	</mamelayout>

trunk/src/mess/layout/ti30.lay
r0	r242129
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3
	4	<!-- note: the digits were very small, wide space between them, and not the same style as (MAME's-)default -->
	5
	6	<element name="digit" defstate="0">
	7	<led7seg><color red="1.0" green="0.15" blue="0.08" /></led7seg>
	8	</element>
	9
	10	<view name="Internal Layout">
	11	<bounds left="0" right="135" top="0" bottom="15" />
	12
	13	<bezel name="digit0" element="digit">
	14	<bounds x="0" y="0" width="10" height="15" />
	15	</bezel>
	16	<bezel name="digit1" element="digit">
	17	<bounds x="15" y="0" width="10" height="15" />
	18	</bezel>
	19	<bezel name="digit2" element="digit">
	20	<bounds x="30" y="0" width="10" height="15" />
	21	</bezel>
	22	<bezel name="digit3" element="digit">
	23	<bounds x="45" y="0" width="10" height="15" />
	24	</bezel>
	25	<bezel name="digit4" element="digit">
	26	<bounds x="60" y="0" width="10" height="15" />
	27	</bezel>
	28	<bezel name="digit5" element="digit">
	29	<bounds x="75" y="0" width="10" height="15" />
	30	</bezel>
	31	<bezel name="digit6" element="digit">
	32	<bounds x="90" y="0" width="10" height="15" />
	33	</bezel>
	34	<bezel name="digit7" element="digit">
	35	<bounds x="105" y="0" width="10" height="15" />
	36	</bezel>
	37	<bezel name="digit8" element="digit">
	38	<bounds x="120" y="0" width="10" height="15" />
	39	</bezel>
	40
	41	</view>
	42	</mamelayout>

trunk/src/mess/layout/tisr16.lay
r0	r242129
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3
	4	<!-- note: the digits were very small, wide space between them, and not the same style as (MAME's-)default -->
	5
	6	<element name="digit" defstate="0">
	7	<led7seg><color red="1.0" green="0.15" blue="0.08" /></led7seg>
	8	</element>
	9
	10	<view name="Internal Layout">
	11	<bounds left="0" right="180" top="0" bottom="15" />
	12
	13	<bezel name="digit10" element="digit">
	14	<bounds x="0" y="0" width="10" height="15" />
	15	</bezel>
	16	<bezel name="digit9" element="digit">
	17	<bounds x="15" y="0" width="10" height="15" />
	18	</bezel>
	19	<bezel name="digit8" element="digit">
	20	<bounds x="30" y="0" width="10" height="15" />
	21	</bezel>
	22	<bezel name="digit7" element="digit">
	23	<bounds x="45" y="0" width="10" height="15" />
	24	</bezel>
	25	<bezel name="digit6" element="digit">
	26	<bounds x="60" y="0" width="10" height="15" />
	27	</bezel>
	28	<bezel name="digit5" element="digit">
	29	<bounds x="75" y="0" width="10" height="15" />
	30	</bezel>
	31	<bezel name="digit4" element="digit">
	32	<bounds x="90" y="0" width="10" height="15" />
	33	</bezel>
	34	<bezel name="digit3" element="digit">
	35	<bounds x="105" y="0" width="10" height="15" />
	36	</bezel>
	37	<bezel name="digit2" element="digit">
	38	<bounds x="120" y="0" width="10" height="15" />
	39	</bezel>
	40	<bezel name="digit11" element="digit">
	41	<bounds x="135" y="0" width="10" height="15" />
	42	</bezel>
	43	<bezel name="digit1" element="digit">
	44	<bounds x="150" y="0" width="10" height="15" />
	45	</bezel>
	46	<bezel name="digit0" element="digit">
	47	<bounds x="165" y="0" width="10" height="15" />
	48	</bezel>
	49
	50	</view>
	51	</mamelayout>

trunk/src/mess/layout/wizatron.lay
r0	r242129
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3
	4	<!-- note: the digits were very small, wide space between them, and not the same style as (MAME's-)default -->
	5	<!-- note 2: yes, the PLUS sign is supposed to be lopsided like that -->
	6	<!-- note 3: yes, the EQUALS sign is supposed to be that high up, but newer releases improved this -->
	7
	8	<element name="static_black">
	9	<rect><color red="0.0" green="0.0" blue="0.0" /></rect>
	10	</element>
	11
	12	<element name="digit" defstate="0">
	13	<led7seg><color red="1.0" green="0.3" blue="0.2" /></led7seg>
	14	</element>
	15	<element name="digit14" defstate="0">
	16	<led14seg><color red="1.0" green="0.3" blue="0.2" /></led14seg>
	17	</element>
	18
	19
	20	<view name="Internal Layout">
	21	<bounds left="0" right="135" top="0" bottom="15" />
	22
	23	<bezel name="digit8" element="digit">
	24	<bounds x="0" y="0" width="10" height="15" />
	25	</bezel>
	26	<bezel name="digit7" element="digit">
	27	<bounds x="15" y="0" width="10" height="15" />
	28	</bezel>
	29	<bezel name="digit6" element="digit14">
	30	<bounds x="30" y="0" width="10" height="15" />
	31	</bezel>
	32	<bezel name="digit5" element="digit">
	33	<bounds x="45" y="0" width="10" height="15" />
	34	</bezel>
	35	<bezel name="digit4" element="digit">
	36	<bounds x="60" y="0" width="10" height="15" />
	37	</bezel>
	38	<bezel name="digit3" element="digit">
	39	<bounds x="75" y="0" width="10" height="15" />
	40	</bezel>
	41	<bezel name="digit2" element="digit">
	42	<bounds x="90" y="0" width="10" height="15" />
	43	</bezel>
	44	<bezel name="digit1" element="digit">
	45	<bounds x="105" y="0" width="10" height="15" />
	46	</bezel>
	47	<bezel name="digit0" element="digit">
	48	<bounds x="120" y="0" width="10" height="15" />
	49	</bezel>
	50
	51	<!-- mask out DIVIDE sign -->
	52
	53	<bezel element="static_black">
	54	<bounds x="34.5" y="1.80" width="1.8" height="2.00" />
	55	</bezel>
	56	<bezel element="static_black">
	57	<bounds x="34.3" y="5.1" width="1.75" height="1.3" />
	58	</bezel>
	59
	60	<bezel element="static_black">
	61	<bounds x="33.75" y="11.25" width="1.8" height="2.00" />
	62	</bezel>
	63	<bezel element="static_black">
	64	<bounds x="33.95" y="8.65" width="1.75" height="1.3" />
	65	</bezel>
	66
	67	</view>
	68	</mamelayout>

trunk/src/mess/mess.lst
r242128	r242129
1063	1063	avigo_it // 1997 Avigo (Italian)
1064	1064
1065	1065	// Texas Instruments Calculators
	1066	tisr16 // 1974 SR-16
	1067	ti1270
	1068	ti30 // 1976 TI-30
	1069	tiprog
	1070	tibusan1
	1071	wizatron
1066	1072	ti73 // 1990 TI-73
1067	1073	ti74 // 1985 TI-74
1068	1074	ti95 // 1986 TI-95
1069	1075	ti81 // 1990 TI-81 (Z80 2 MHz)
1070		ti81v2 // 1990 TI-81 (Z80 2 MHz)
	1076	ti81v2 // 1990 TI-81 (Z80 2 MHz)
1071	1077	ti85 // 1992 TI-85 (Z80 6 MHz)
1072	1078	ti82 // 1993 TI-82 (Z80 6 MHz)
1073	1079	ti83 // 1996 TI-83 (Z80 6 MHz)
1074	1080	ti86 // 1997 TI-86 (Z80 6 MHz)
1075		ti83p // 1999 TI-83 Plus (Z80 6 MHz)
	1081	ti83p // 1999 TI-83 Plus (Z80 6 MHz)
1076	1082	ti83pse // 2001 TI-83 Plus Silver Edition
1077		ti84p // 2004 TI-84 Plus
	1083	ti84p // 2004 TI-84 Plus
1078	1084	ti84pse // 2004 TI-84 Plus Silver Edition
1079	1085	//ti84cse // 2013 TI-84 Plus C Silver Edition (color screen)
1080	1086	ti89 // 1998 TI-89
1081	1087	ti92 // 1995 TI-92
1082		ti92p // 1999 TI-92 Plus
	1088	ti92p // 1999 TI-92 Plus
1083	1089	v200 // 2002 Voyage 200 PLT
1084		ti89t // 2004 TI-89 Titanium
1085		wizatron
	1090	ti89t // 2004 TI-89 Titanium
1086	1091	evmbug
1087	1092
1088	1093	// Exelvision (founded by former TI employees)

trunk/src/mess/mess.mak
r242128	r242129
2074	2074	$(MESS_DRIVERS)/chessmst.o: $(MESS_LAYOUT)/chessmst.lh
2075	2075	$(MESS_DRIVERS)/chesstrv.o: $(MESS_LAYOUT)/chesstrv.lh \
2076	2076	$(MESS_LAYOUT)/borisdpl.lh
	2077	$(MESS_DRIVERS)/comp4.o: $(MESS_LAYOUT)/comp4.lh
2077	2078	$(MESS_DRIVERS)/cp1.o: $(MESS_LAYOUT)/cp1.lh
2078	2079	$(MESS_DRIVERS)/cvicny.o: $(MESS_LAYOUT)/cvicny.lh
2079	2080	$(MESS_DRIVERS)/coco3.o: $(MESS_LAYOUT)/coco3.lh
r242128	r242129
2154	2155	$(MESS_DRIVERS)/tecnbras.o: $(MESS_LAYOUT)/tecnbras.lh
2155	2156	$(MESS_DRIVERS)/ti74.o: $(MESS_LAYOUT)/ti74.lh \
2156	2157	$(MESS_LAYOUT)/ti95.lh
	2158	$(MESS_DRIVERS)/ticalc1x.o: $(MESS_LAYOUT)/ti1270.lh \
	2159	$(MESS_LAYOUT)/ti30.lh \
	2160	$(MESS_LAYOUT)/tisr16.lh \
	2161	$(MESS_LAYOUT)/wizatron.lh
2157	2162	$(MESS_DRIVERS)/tk80.o: $(MESS_LAYOUT)/tk80.lh
2158	2163	$(MESS_DRIVERS)/tm990189.o: $(MESS_LAYOUT)/tm990189.lh \
2159	2164	$(MESS_LAYOUT)/tm990189v.lh

https://github.com/mamedev/mame/commit/c1eaec3cee27803f88d4520b9284f29391612394

199869 Revisions