trunk/src/mess/drivers/ngen.c
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| 15 | 15 | #include "machine/pic8259.h" |
| 16 | 16 | #include "machine/pit8253.h" |
| 17 | 17 | #include "machine/z80dart.h" |
| 18 | #include "bus/rs232/rs232.h" |
| 18 | 19 | |
| 19 | 20 | class ngen_state : public driver_device |
| 20 | 21 | { |
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| 74 | 75 | |
| 75 | 76 | WRITE_LINE_MEMBER(ngen_state::pit_out2_w) |
| 76 | 77 | { |
| 77 | | logerror("PIT Timer 2 state %i\n",state); |
| 78 | m_iouart->rxca_w(state); |
| 79 | m_iouart->rxcb_w(state); |
| 80 | m_iouart->txca_w(state); |
| 81 | m_iouart->txcb_w(state); |
| 78 | 82 | } |
| 79 | 83 | |
| 80 | 84 | WRITE16_MEMBER(ngen_state::cpu_peripheral_cb) |
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| 113 | 117 | { |
| 114 | 118 | switch(offset) |
| 115 | 119 | { |
| 120 | case 0x110: |
| 121 | if(mem_mask & 0x00ff) |
| 122 | m_pit->write(space,0,data & 0x0ff); |
| 123 | break; |
| 124 | case 0x111: |
| 125 | if(mem_mask & 0x00ff) |
| 126 | m_pit->write(space,1,data & 0x0ff); |
| 127 | break; |
| 128 | case 0x112: |
| 129 | if(mem_mask & 0x00ff) |
| 130 | m_pit->write(space,2,data & 0x0ff); |
| 131 | break; |
| 132 | case 0x113: |
| 133 | if(mem_mask & 0x00ff) |
| 134 | m_pit->write(space,3,data & 0x0ff); |
| 135 | break; |
| 116 | 136 | case 0x141: |
| 117 | 137 | // bit 1 enables speaker? |
| 118 | 138 | COMBINE_DATA(&m_periph141); |
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| 126 | 146 | m_crtc->register_w(space,0,data & 0xff); |
| 127 | 147 | break; |
| 128 | 148 | case 0x146: |
| 129 | | if(mem_mask & 0x00ff) |
| 130 | | m_iouart->ba_cd_w(space,0,data & 0xff); |
| 131 | 149 | logerror("Video write offset 0x146 data %04x mask %04x\n",data,mem_mask); |
| 132 | 150 | break; |
| 133 | 151 | case 0x147: |
| 134 | | if(mem_mask & 0x00ff) |
| 135 | | m_iouart->ba_cd_w(space,1,data & 0xff); |
| 136 | | logerror("Video write offset 0x147 data %04x mask %04x\n",data,mem_mask); |
| 152 | //logerror("Video write offset 0x147 data %04x mask %04x\n",data,mem_mask); |
| 137 | 153 | break; |
| 138 | 154 | default: |
| 139 | 155 | logerror("(PC=%06x) Unknown 80186 peripheral write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask); |
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| 145 | 161 | UINT16 ret = 0xffff; |
| 146 | 162 | switch(offset) |
| 147 | 163 | { |
| 164 | case 0x110: |
| 165 | if(mem_mask & 0x00ff) |
| 166 | ret = m_pit->read(space,0); |
| 167 | break; |
| 168 | case 0x111: |
| 169 | if(mem_mask & 0x00ff) |
| 170 | ret = m_pit->read(space,1); |
| 171 | break; |
| 172 | case 0x112: |
| 173 | if(mem_mask & 0x00ff) |
| 174 | ret = m_pit->read(space,2); |
| 175 | break; |
| 176 | case 0x113: |
| 177 | if(mem_mask & 0x00ff) |
| 178 | ret = m_pit->read(space,3); |
| 179 | break; |
| 148 | 180 | case 0x141: |
| 149 | 181 | ret = m_periph141; |
| 150 | 182 | break; |
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| 246 | 278 | MCFG_PIC8259_ADD( "pic", INPUTLINE("maincpu", 0), VCC, NULL ) |
| 247 | 279 | |
| 248 | 280 | MCFG_DEVICE_ADD("pit", PIT8254, 0) |
| 249 | | MCFG_PIT8253_CLK0(4772720/4) // correct? |
| 281 | MCFG_PIT8253_CLK0(XTAL_14_7456MHz/8) // correct? |
| 250 | 282 | MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out0_w)) |
| 251 | | MCFG_PIT8253_CLK0(4772720/4) |
| 252 | | MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out1_w)) |
| 253 | | MCFG_PIT8253_CLK0(4772720/4) |
| 254 | | MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out2_w)) |
| 283 | MCFG_PIT8253_CLK1(XTAL_14_7456MHz/8) |
| 284 | MCFG_PIT8253_OUT1_HANDLER(WRITELINE(ngen_state, pit_out1_w)) |
| 285 | MCFG_PIT8253_CLK2(XTAL_14_7456MHz/8) |
| 286 | MCFG_PIT8253_OUT2_HANDLER(WRITELINE(ngen_state, pit_out2_w)) |
| 255 | 287 | |
| 256 | 288 | MCFG_DEVICE_ADD("dmac", AM9517A, XTAL_14_7456MHz / 3) // NEC D8237A, divisor unknown |
| 257 | 289 | |
| 258 | 290 | // I/O board |
| 259 | | MCFG_UPD7201_ADD("iouart",XTAL_14_7456MHz / 3, 0,0,0,0) // no clock visible on I/O board, guessing for now |
| 291 | MCFG_UPD7201_ADD("iouart",0, 0,0,0,0) // clocked by PIT channel 2? |
| 292 | MCFG_Z80DART_OUT_TXDA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_txd)) |
| 293 | MCFG_Z80DART_OUT_TXDB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_txd)) |
| 294 | MCFG_Z80DART_OUT_DTRA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_dtr)) |
| 295 | MCFG_Z80DART_OUT_DTRB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_dtr)) |
| 296 | MCFG_Z80DART_OUT_RTSA_CB(DEVWRITELINE("rs232_a", rs232_port_device, write_rts)) |
| 297 | MCFG_Z80DART_OUT_RTSB_CB(DEVWRITELINE("rs232_b", rs232_port_device, write_rts)) |
| 260 | 298 | |
| 299 | MCFG_RS232_PORT_ADD("rs232_a", default_rs232_devices, NULL) |
| 300 | MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_device, rxa_w)) |
| 301 | MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_device, ctsa_w)) |
| 302 | MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcda_w)) |
| 303 | MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, ria_w)) |
| 304 | |
| 305 | MCFG_RS232_PORT_ADD("rs232_b", default_rs232_devices, NULL) |
| 306 | MCFG_RS232_RXD_HANDLER(DEVWRITELINE("iouart", upd7201_device, rxb_w)) |
| 307 | MCFG_RS232_CTS_HANDLER(DEVWRITELINE("iouart", upd7201_device, ctsb_w)) |
| 308 | MCFG_RS232_DCD_HANDLER(DEVWRITELINE("iouart", upd7201_device, dcdb_w)) |
| 309 | MCFG_RS232_RI_HANDLER(DEVWRITELINE("iouart", upd7201_device, rib_w)) |
| 310 | |
| 311 | |
| 261 | 312 | // video board |
| 262 | 313 | MCFG_SCREEN_ADD("screen", RASTER) |
| 263 | 314 | MCFG_SCREEN_SIZE(720,348) |