trunk/src/mess/drivers/ngen.c
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| 14 | 14 | #include "machine/am9517a.h" |
| 15 | 15 | #include "machine/pic8259.h" |
| 16 | 16 | #include "machine/pit8253.h" |
| 17 | #include "machine/z80dart.h" |
| 17 | 18 | |
| 18 | 19 | class ngen_state : public driver_device |
| 19 | 20 | { |
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| 23 | 24 | m_maincpu(*this,"maincpu"), |
| 24 | 25 | m_crtc(*this,"crtc"), |
| 25 | 26 | m_viduart(*this,"videouart"), |
| 27 | m_iouart(*this,"iouart"), |
| 26 | 28 | m_dmac(*this,"dmac"), |
| 27 | 29 | m_pic(*this,"pic"), |
| 28 | | m_pit(*this,"pit") |
| 30 | m_pit(*this,"pit"), |
| 31 | m_vram(*this,"vram"), |
| 32 | m_fontram(*this,"fontram") |
| 29 | 33 | {} |
| 30 | 34 | |
| 31 | 35 | DECLARE_WRITE_LINE_MEMBER(pit_out0_w); |
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| 43 | 47 | required_device<cpu_device> m_maincpu; |
| 44 | 48 | required_device<mc6845_device> m_crtc; |
| 45 | 49 | required_device<i8251_device> m_viduart; |
| 50 | required_device<upd7201_device> m_iouart; |
| 46 | 51 | required_device<am9517a_device> m_dmac; |
| 47 | 52 | required_device<pic8259_device> m_pic; |
| 48 | 53 | required_device<pit8254_device> m_pit; |
| 54 | required_shared_ptr<UINT16> m_vram; |
| 55 | required_shared_ptr<UINT16> m_fontram; |
| 49 | 56 | |
| 50 | 57 | UINT16 m_peripheral; |
| 51 | 58 | UINT16 m_upper; |
| 52 | 59 | UINT16 m_middle; |
| 53 | 60 | UINT16 m_port00; |
| 61 | UINT16 m_periph141; |
| 54 | 62 | }; |
| 55 | 63 | |
| 56 | 64 | WRITE_LINE_MEMBER(ngen_state::pit_out0_w) |
| 57 | 65 | { |
| 58 | | m_pic->ir0_w(state); |
| 66 | //m_pic->ir0_w(state); |
| 67 | logerror("80186 Timer 1 state %i\n",state); |
| 59 | 68 | } |
| 60 | 69 | |
| 61 | 70 | WRITE_LINE_MEMBER(ngen_state::pit_out1_w) |
| 62 | 71 | { |
| 72 | logerror("PIT Timer 1 state %i\n",state); |
| 63 | 73 | } |
| 64 | 74 | |
| 65 | 75 | WRITE_LINE_MEMBER(ngen_state::pit_out2_w) |
| 66 | 76 | { |
| 77 | logerror("PIT Timer 2 state %i\n",state); |
| 67 | 78 | } |
| 68 | 79 | |
| 69 | 80 | WRITE16_MEMBER(ngen_state::cpu_peripheral_cb) |
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| 97 | 108 | } |
| 98 | 109 | |
| 99 | 110 | // 80186 peripheral space |
| 111 | // Largely guesswork at this stage |
| 100 | 112 | WRITE16_MEMBER(ngen_state::peripheral_w) |
| 101 | 113 | { |
| 102 | 114 | switch(offset) |
| 103 | 115 | { |
| 116 | case 0x141: |
| 117 | // bit 1 enables speaker? |
| 118 | COMBINE_DATA(&m_periph141); |
| 119 | break; |
| 104 | 120 | case 0x144: |
| 105 | 121 | if(mem_mask & 0x00ff) |
| 106 | 122 | m_crtc->address_w(space,0,data & 0xff); |
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| 111 | 127 | break; |
| 112 | 128 | case 0x146: |
| 113 | 129 | if(mem_mask & 0x00ff) |
| 114 | | m_pic->write(space,0,data & 0xff); |
| 130 | m_iouart->ba_cd_w(space,0,data & 0xff); |
| 131 | logerror("Video write offset 0x146 data %04x mask %04x\n",data,mem_mask); |
| 115 | 132 | break; |
| 116 | 133 | case 0x147: |
| 117 | 134 | if(mem_mask & 0x00ff) |
| 118 | | m_pic->write(space,1,data & 0xff); |
| 135 | m_iouart->ba_cd_w(space,1,data & 0xff); |
| 136 | logerror("Video write offset 0x147 data %04x mask %04x\n",data,mem_mask); |
| 119 | 137 | break; |
| 138 | default: |
| 139 | logerror("(PC=%06x) Unknown 80186 peripheral write offset %04x data %04x mask %04x\n",m_maincpu->device_t::safe_pc(),offset,data,mem_mask); |
| 120 | 140 | } |
| 121 | | logerror("Peripheral write offset %04x data %04x mask %04x\n",offset,data,mem_mask); |
| 122 | 141 | } |
| 123 | 142 | |
| 124 | 143 | READ16_MEMBER(ngen_state::peripheral_r) |
| 125 | 144 | { |
| 126 | | UINT16 ret = 0xff; |
| 145 | UINT16 ret = 0xffff; |
| 127 | 146 | switch(offset) |
| 128 | 147 | { |
| 148 | case 0x141: |
| 149 | ret = m_periph141; |
| 150 | break; |
| 129 | 151 | case 0x144: |
| 130 | 152 | if(mem_mask & 0x00ff) |
| 131 | 153 | ret = m_crtc->status_r(space,0); |
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| 136 | 158 | break; |
| 137 | 159 | case 0x146: |
| 138 | 160 | if(mem_mask & 0x00ff) |
| 139 | | ret = m_pic->read(space,0); |
| 161 | ret = m_iouart->ba_cd_r(space,0); |
| 140 | 162 | break; |
| 141 | | case 0x147: |
| 163 | case 0x147: // definitely video related, likely UART sending data to the video board |
| 142 | 164 | if(mem_mask & 0x00ff) |
| 143 | | ret = m_pic->read(space,1); |
| 165 | ret = m_iouart->ba_cd_r(space,1); |
| 166 | // expects bit 0 to be set (Video ready signal?) |
| 167 | ret |= 1; |
| 144 | 168 | break; |
| 169 | default: |
| 170 | logerror("(PC=%06x) Unknown 80186 peripheral read offset %04x mask %04x returning %04x\n",m_maincpu->device_t::safe_pc(),offset,mem_mask,ret); |
| 145 | 171 | } |
| 146 | | logerror("Peripheral read offset %04x mask %04x\n",offset,mem_mask); |
| 147 | 172 | return ret; |
| 148 | 173 | } |
| 149 | 174 | |
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| 165 | 190 | |
| 166 | 191 | MC6845_UPDATE_ROW( ngen_state::crtc_update_row ) |
| 167 | 192 | { |
| 193 | UINT16 addr = ma; |
| 194 | |
| 195 | for(int x=0;x<bitmap.width();x+=9) |
| 196 | { |
| 197 | UINT8 ch = m_vram[addr++]; |
| 198 | for(int z=0;z<9;z++) |
| 199 | { |
| 200 | if(BIT(m_fontram[ch*16+ra],8-z)) |
| 201 | bitmap.pix32(y,x+z) = rgb_t(0,0xff,0); |
| 202 | else |
| 203 | bitmap.pix32(y,x+z) = rgb_t(0,0,0); |
| 204 | } |
| 205 | } |
| 168 | 206 | } |
| 169 | 207 | |
| 170 | 208 | static ADDRESS_MAP_START( ngen_mem, AS_PROGRAM, 16, ngen_state ) |
| 171 | | AM_RANGE(0x00000, 0xfdfff) AM_RAM |
| 209 | AM_RANGE(0x00000, 0xf7fff) AM_RAM |
| 210 | AM_RANGE(0xf8000, 0xf9fff) AM_RAM AM_SHARE("vram") |
| 211 | AM_RANGE(0xfa000, 0xfbfff) AM_RAM AM_SHARE("fontram") |
| 172 | 212 | AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("bios",0) |
| 173 | 213 | ADDRESS_MAP_END |
| 174 | 214 | |
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| 215 | 255 | |
| 216 | 256 | MCFG_DEVICE_ADD("dmac", AM9517A, XTAL_14_7456MHz / 3) // NEC D8237A, divisor unknown |
| 217 | 257 | |
| 258 | // I/O board |
| 259 | MCFG_UPD7201_ADD("iouart",XTAL_14_7456MHz / 3, 0,0,0,0) // no clock visible on I/O board, guessing for now |
| 260 | |
| 218 | 261 | // video board |
| 219 | 262 | MCFG_SCREEN_ADD("screen", RASTER) |
| 220 | 263 | MCFG_SCREEN_SIZE(720,348) |