Previous 199869 Revisions Next

r33364 Wednesday 12th November, 2014 at 23:17:35 UTC by Barry Rodewald
New skeleton drivers added: Convergent NGEN CP-001, B28/38, 386i [Al Kossow, Barry Rodewald]
[src/mess]mess.lst mess.mak
[src/mess/drivers]ngen.c*

trunk/src/mess/drivers/ngen.c
r0r241876
1/*
2
3   Convergent NGen series
4
5   10-11-14 - Skeleton driver
6
7*/
8
9#include "emu.h"
10#include "cpu/i86/i186.h"
11#include "cpu/i386/i386.h"
12#include "video/mc6845.h"
13#include "machine/i8251.h"
14#include "machine/am9517a.h"
15#include "machine/pic8259.h"
16#include "machine/pit8253.h"
17
18class ngen_state : public driver_device
19{
20public:
21   ngen_state(const machine_config &mconfig, device_type type, const char *tag)
22      : driver_device(mconfig, type, tag),
23      m_maincpu(*this,"maincpu"),
24      m_crtc(*this,"crtc"),
25      m_viduart(*this,"videouart"),
26      m_dmac(*this,"dmac"),
27      m_pic(*this,"pic"),
28      m_pit(*this,"pit")
29   {}
30
31   DECLARE_WRITE_LINE_MEMBER(pit_out0_w);
32   DECLARE_WRITE_LINE_MEMBER(pit_out1_w);
33   DECLARE_WRITE_LINE_MEMBER(pit_out2_w);
34   DECLARE_WRITE16_MEMBER(cpu_peripheral_cb);
35   DECLARE_WRITE16_MEMBER(peripheral_w);
36   DECLARE_READ16_MEMBER(peripheral_r);
37   DECLARE_WRITE16_MEMBER(port00_w);
38   DECLARE_READ16_MEMBER(port00_r);
39   MC6845_UPDATE_ROW(crtc_update_row);
40
41protected:
42private:
43   required_device<cpu_device> m_maincpu;
44   required_device<mc6845_device> m_crtc;
45   required_device<i8251_device> m_viduart;
46   required_device<am9517a_device> m_dmac;
47   required_device<pic8259_device> m_pic;
48   required_device<pit8254_device> m_pit;
49
50   UINT16 m_peripheral;
51   UINT16 m_upper;
52   UINT16 m_middle;
53   UINT16 m_port00;
54};
55
56WRITE_LINE_MEMBER(ngen_state::pit_out0_w)
57{
58   m_pic->ir0_w(state);
59}
60
61WRITE_LINE_MEMBER(ngen_state::pit_out1_w)
62{
63}
64
65WRITE_LINE_MEMBER(ngen_state::pit_out2_w)
66{
67}
68
69WRITE16_MEMBER(ngen_state::cpu_peripheral_cb)
70{
71   UINT32 addr;
72
73   switch(offset)
74   {
75   case 0:  // upper memory
76      m_upper = data;
77      break;
78   case 2:  // peripheral
79      m_peripheral = data;
80      addr = (m_peripheral & 0xffc0) << 4;
81      if(m_middle & 0x0040)
82      {
83         m_maincpu->device_t::memory().space(AS_PROGRAM).install_readwrite_handler(addr, addr + 0x3ff, read16_delegate(FUNC(ngen_state::peripheral_r), this), write16_delegate(FUNC(ngen_state::peripheral_w), this));
84         logerror("Mapped peripherals to memory 0x%08x\n",addr);
85      }
86      else
87      {
88         addr &= 0xffff;
89         m_maincpu->device_t::memory().space(AS_IO).install_readwrite_handler(addr, addr + 0x3ff, read16_delegate(FUNC(ngen_state::peripheral_r), this), write16_delegate(FUNC(ngen_state::peripheral_w), this));
90         logerror("Mapped peripherals to I/O 0x%04x\n",addr);
91      }
92      break;   
93   case 4:
94      m_middle = data;
95      break;
96   }
97}
98
99// 80186 peripheral space
100WRITE16_MEMBER(ngen_state::peripheral_w)
101{
102   switch(offset)
103   {
104   case 0x147:
105      if(mem_mask & 0xff00)
106         m_pic->write(space,0,(data >> 8) & 0xff);
107      if(mem_mask & 0x00ff)
108         m_pic->write(space,1,data & 0xff);
109      break;
110   }
111   logerror("Peripheral write offset %04x data %04x mask %04x\n",offset,data,mem_mask);
112}
113
114READ16_MEMBER(ngen_state::peripheral_r)
115{
116   UINT16 ret = 0xff;
117   switch(offset)
118   {
119   case 0x146:
120      if(mem_mask & 0x00ff)
121         ret = m_pic->read(space,0);
122      break;
123   case 0x147:
124      if(mem_mask & 0x00ff)
125         ret = m_pic->read(space,1);
126      break;
127   }
128   logerror("Peripheral read offset %04x mask %04x\n",offset,mem_mask);
129   return ret;
130}
131
132// A sequencial number is written to this port, and keeps on going until an NMI is triggered.
133// Maybe this is a RAM test of some kind, and this would be a bank switch register?
134// Even though the system supports 1MB at the most, which would fit in the CPU's whole address space...
135WRITE16_MEMBER(ngen_state::port00_w)
136{
137   m_port00 = data;
138   if(data > 0)
139      m_maincpu->set_input_line(INPUT_LINE_NMI,PULSE_LINE);
140   logerror("SYS: Port 0 write %04x\n",data);
141}
142
143READ16_MEMBER(ngen_state::port00_r)
144{
145   return m_port00;
146}
147
148MC6845_UPDATE_ROW( ngen_state::crtc_update_row )
149{
150}
151
152static ADDRESS_MAP_START( ngen_mem, AS_PROGRAM, 16, ngen_state )
153   AM_RANGE(0x00000, 0xfdfff) AM_RAM
154   AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("bios",0)
155ADDRESS_MAP_END
156
157static ADDRESS_MAP_START( ngen_io, AS_IO, 16, ngen_state )
158   AM_RANGE(0x0000, 0x0001) AM_READWRITE(port00_r,port00_w)
159ADDRESS_MAP_END
160
161static ADDRESS_MAP_START( ngen386_mem, AS_PROGRAM, 32, ngen_state )
162   AM_RANGE(0x00000000, 0x000fdfff) AM_RAM
163   AM_RANGE(0x000fe000, 0x000fffff) AM_ROM AM_REGION("bios",0)
164   AM_RANGE(0xffffe000, 0xffffffff) AM_ROM AM_REGION("bios",0)
165ADDRESS_MAP_END
166
167static ADDRESS_MAP_START( ngen386i_mem, AS_PROGRAM, 32, ngen_state )
168   AM_RANGE(0x00000000, 0x000fbfff) AM_RAM
169   AM_RANGE(0x000fc000, 0x000fffff) AM_ROM AM_REGION("bios",0)
170   AM_RANGE(0xffffc000, 0xffffffff) AM_ROM AM_REGION("bios",0)
171ADDRESS_MAP_END
172
173static ADDRESS_MAP_START( ngen386_io, AS_IO, 32, ngen_state )
174   AM_RANGE(0xfd0c, 0xfd0f) AM_DEVREADWRITE8("pic",pic8259_device,read,write,0xffffffff)
175ADDRESS_MAP_END
176
177static INPUT_PORTS_START( ngen )
178INPUT_PORTS_END
179
180static MACHINE_CONFIG_START( ngen, ngen_state )
181   // basic machine hardware
182   MCFG_CPU_ADD("maincpu", I80186, XTAL_16MHz / 2)
183   MCFG_CPU_PROGRAM_MAP(ngen_mem)
184   MCFG_CPU_IO_MAP(ngen_io)
185   MCFG_80186_CHIP_SELECT_CB(WRITE16(ngen_state, cpu_peripheral_cb))
186   MCFG_80186_TMROUT1_HANDLER(WRITELINE(ngen_state, pit_out0_w))
187
188   MCFG_PIC8259_ADD( "pic", INPUTLINE("maincpu", 0), VCC, NULL )
189
190   MCFG_DEVICE_ADD("pit", PIT8254, 0)
191   MCFG_PIT8253_CLK0(4772720/4)  // correct?
192   MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out0_w))
193   MCFG_PIT8253_CLK0(4772720/4)
194   MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out1_w))
195   MCFG_PIT8253_CLK0(4772720/4)
196   MCFG_PIT8253_OUT0_HANDLER(WRITELINE(ngen_state, pit_out2_w))
197
198   MCFG_DEVICE_ADD("dmac", AM9517A, XTAL_14_7456MHz / 3)  // NEC D8237A, divisor unknown
199
200   // video board
201   MCFG_SCREEN_ADD("screen", RASTER)
202   MCFG_SCREEN_SIZE(720,348)
203   MCFG_SCREEN_REFRESH_RATE(60)
204   MCFG_SCREEN_UPDATE_DEVICE("crtc",mc6845_device, screen_update)
205
206   MCFG_MC6845_ADD("crtc", MC6845, NULL, 19980000 / 16)  // divisor unknown
207   MCFG_MC6845_SHOW_BORDER_AREA(false)
208   MCFG_MC6845_CHAR_WIDTH(9)
209   MCFG_MC6845_UPDATE_ROW_CB(ngen_state, crtc_update_row)
210
211   MCFG_DEVICE_ADD("videouart", I8251, 19980000 / 16)  // divisor unknown
212
213MACHINE_CONFIG_END
214
215static MACHINE_CONFIG_DERIVED( ngen386, ngen )
216   MCFG_CPU_REPLACE("maincpu", I386, XTAL_50MHz / 2)
217   MCFG_CPU_PROGRAM_MAP(ngen386_mem)
218   MCFG_CPU_IO_MAP(ngen386_io)
219MACHINE_CONFIG_END
220
221static MACHINE_CONFIG_DERIVED( 386i, ngen386 )
222   MCFG_CPU_MODIFY("maincpu")
223   MCFG_CPU_PROGRAM_MAP(ngen386i_mem)
224MACHINE_CONFIG_END
225
226ROM_START( ngen )
227   ROM_REGION( 0x2000, "bios", 0)
228   ROM_LOAD16_BYTE( "72-00414_80186_cpu.bin",  0x000000, 0x001000, CRC(e1387a03) SHA1(ddca4eba67fbf8b731a8009c14f6b40edcbc3279) )
229   ROM_LOAD16_BYTE( "72-00415_80186_cpu.bin",  0x000001, 0x001000, CRC(a6dde7d9) SHA1(b4d15c1bce31460ab5b92ff43a68c15ac5485816) )
230ROM_END
231
232// not sure just how similar these systems are to the 80186 model, but are here at the moment to document the dumps
233ROM_START( ngenb38 )
234   ROM_REGION( 0x2000, "bios", 0)
235   ROM_LOAD16_BYTE( "72-168_fpc_386_cpu.bin",  0x000000, 0x001000, CRC(250a3b68) SHA1(49c070514bac264fa4892f284f7d2c852ae6605d) )
236   ROM_LOAD16_BYTE( "72-167_fpc_386_cpu.bin",  0x000001, 0x001000, CRC(4010cc4e) SHA1(74a3024d605569056484d08b63f19fbf8eaf31c6) )
237ROM_END
238
239ROM_START( 386i )
240   ROM_REGION( 0x4000, "bios", 0)
241   ROM_LOAD16_BYTE( "72-1561o_386i_cpu.bin",  0x000000, 0x002000, CRC(b5efd768) SHA1(8b250d47d9c6eb82e1afaeb2244d8c4134ecbc47) )
242   ROM_LOAD16_BYTE( "72-1562e_386i_cpu.bin",  0x000001, 0x002000, CRC(002d0d3a) SHA1(31de8592999377db9251acbeff348390a2d2602a) )
243
244   ROM_REGION( 0x2000, "video", 0)
245   ROM_LOAD( "72-1630_gc-104_vga.bin",  0x000000, 0x002000, CRC(4e4d8ebe) SHA1(50c96ccb4d0bd1beb2d1aee0d18b2c462d25fc8f) )
246ROM_END
247
248
249COMP( 1983, ngen,    0,      0,      ngen,           ngen, driver_device, 0,      "Convergent Technologies",  "NGEN CP-001", GAME_IS_SKELETON | GAME_NOT_WORKING | GAME_NO_SOUND )
250COMP( 1991, ngenb38, ngen,   0,      ngen386,        ngen, driver_device, 0,      "Financial Products Corp.", "B28/38",      GAME_IS_SKELETON | GAME_NOT_WORKING | GAME_NO_SOUND )
251COMP( 1990, 386i,    ngen,   0,      386i,           ngen, driver_device, 0,      "Convergent Technologies",  "386i",        GAME_IS_SKELETON | GAME_NOT_WORKING | GAME_NO_SOUND )
trunk/src/mess/mess.lst
r241875r241876
21332133fanucspgm   // 1983
21342134fanucs15    // 1990
21352135
2136// Convergent
2137ngen        // 1983
2138ngenb38     // 1991
2139386i        // 199?
2140
21362141//********** Misc **********************************************************
21372142
21382143ssem // Manchester Small-Scale Experimental Machine, "Baby"
trunk/src/mess/mess.mak
r241875r241876
19411941   $(MESS_DRIVERS)/mx2178.o    \
19421942   $(MESS_DRIVERS)/mycom.o     \
19431943   $(MESS_DRIVERS)/myvision.o  \
1944   $(MESS_DRIVERS)/ngen.o      \
19441945   $(MESS_DRIVERS)/octopus.o   \
19451946   $(MESS_DRIVERS)/onyx.o      \
19461947   $(MESS_DRIVERS)/okean240.o  \

https://github.com/mamedev/mame/commit/94db9be215c01368cf2cc5a54aefa84815c20b23

Previous 199869 Revisions Next

© 1997-2024 The MAME Team