trunk/src/emu/machine/i6300esb.c
| r241853 | r241854 | |
| 20 | 20 | void i6300esb_watchdog_device::device_reset() |
| 21 | 21 | { |
| 22 | 22 | pci_device::device_reset(); |
| 23 | command = 0x000f; |
| 24 | command_mask = 0x0140; |
| 25 | status = 0x0280; |
| 23 | 26 | } |
| 24 | 27 | |
| 25 | 28 | |
| 26 | 29 | DEVICE_ADDRESS_MAP_START(config_map, 32, i6300esb_lpc_device) |
| 27 | | AM_RANGE(0x58, 0x5b) AM_READWRITE (gpio_base_r, gpio_base_w) |
| 28 | | AM_RANGE(0x5c, 0x5f) AM_READWRITE8 (gpio_cntl_r, gpio_cntl_w, 0x000000ff) |
| 29 | | AM_RANGE(0xe4, 0xe7) AM_READWRITE16(gen1_dec_r, gen1_dec_w, 0x0000ffff) |
| 30 | | AM_RANGE(0xe4, 0xe7) AM_READWRITE16(lpc_en_r, lpc_en_w, 0xffff0000) |
| 31 | | AM_RANGE(0xe8, 0xeb) AM_READWRITE (fwh_sel1_r, fwh_sel1_w) |
| 32 | | AM_RANGE(0xfc, 0xff) AM_READWRITE (unk_fc_r, unk_fc_w) |
| 30 | AM_RANGE(0x40, 0x43) AM_READWRITE (pmbase_r, pmbase_w) |
| 31 | AM_RANGE(0x44, 0x47) AM_READWRITE8 (acpi_cntl_r, acpi_cntl_w, 0x000000ff) |
| 32 | AM_RANGE(0x4c, 0x4f) AM_READWRITE16(bios_cntl_r, bios_cntl_w, 0xffff0000) |
| 33 | AM_RANGE(0x54, 0x57) AM_READWRITE8 (tco_cntl_r, tco_cntl_w, 0x000000ff) |
| 34 | AM_RANGE(0x58, 0x5b) AM_READWRITE (gpio_base_r, gpio_base_w) |
| 35 | AM_RANGE(0x5c, 0x5f) AM_READWRITE8 (gpio_cntl_r, gpio_cntl_w, 0x000000ff) |
| 36 | AM_RANGE(0x60, 0x63) AM_READWRITE8 (pirq_rout_r, pirq_rout_w, 0xffffffff) |
| 37 | AM_RANGE(0x64, 0x67) AM_READWRITE8 (serirq_cntl_r, serirq_cntl_w, 0x000000ff) |
| 38 | AM_RANGE(0x68, 0x6b) AM_READWRITE8 (pirq2_rout_r, pirq2_rout_w, 0xffffffff) |
| 39 | AM_RANGE(0x88, 0x8b) AM_READWRITE8 (d31_err_cfg_r, d31_err_cfg_w, 0x000000ff) |
| 40 | AM_RANGE(0x88, 0x8b) AM_READWRITE8 (d31_err_sts_r, d31_err_sts_w, 0x00ff0000) |
| 41 | AM_RANGE(0x90, 0x93) AM_READWRITE16(pci_dma_cfg_r, pci_dma_cfg_w, 0x0000ffff) |
| 42 | AM_RANGE(0xd0, 0xd3) AM_READWRITE (gen_cntl_r, gen_cntl_w) |
| 43 | AM_RANGE(0xd4, 0xd7) AM_READWRITE8 (gen_sta_r, gen_sta_w, 0x000000ff) |
| 44 | AM_RANGE(0xd4, 0xd7) AM_READWRITE8 (back_cntl_r, back_cntl_w, 0x0000ff00) |
| 45 | AM_RANGE(0xd8, 0xdb) AM_READWRITE8 (rtc_conf_r, rtc_conf_w, 0x000000ff) |
| 46 | AM_RANGE(0xe0, 0xe3) AM_READWRITE8 (lpc_if_com_range_r, lpc_if_com_range_w, 0x000000ff) |
| 47 | AM_RANGE(0xe0, 0xe3) AM_READWRITE8 (lpc_if_fdd_lpt_range_r, lpc_if_fdd_lpt_range_w, 0x0000ff00) |
| 48 | AM_RANGE(0xe0, 0xe3) AM_READWRITE8 (lpc_if_sound_range_r, lpc_if_sound_range_w, 0x00ff0000) |
| 49 | AM_RANGE(0xe0, 0xe3) AM_READWRITE8 (fwh_dec_en1_r, fwh_dec_en1_w, 0xff000000) |
| 50 | AM_RANGE(0xe4, 0xe7) AM_READWRITE16(gen1_dec_r, gen1_dec_w, 0x0000ffff) |
| 51 | AM_RANGE(0xe4, 0xe7) AM_READWRITE16(lpc_en_r, lpc_en_w, 0xffff0000) |
| 52 | AM_RANGE(0xe8, 0xeb) AM_READWRITE (fwh_sel1_r, fwh_sel1_w) |
| 53 | AM_RANGE(0xec, 0xef) AM_READWRITE16(gen2_dec_r, gen2_dec_w, 0x0000ffff) |
| 54 | AM_RANGE(0xec, 0xef) AM_READWRITE16(fwh_sel2_r, fwh_sel2_w, 0xffff0000) |
| 55 | AM_RANGE(0xf0, 0xf3) AM_READWRITE8 (fwh_dec_en2_r, fwh_dec_en2_w, 0x000000ff) |
| 56 | AM_RANGE(0xf0, 0xf3) AM_READWRITE16(func_dis_r, func_dis_w, 0xffff0000) |
| 57 | AM_RANGE(0xf4, 0xf7) AM_READWRITE (etr1_r, etr1_w) |
| 58 | AM_RANGE(0xf8, 0xfb) AM_READ (mfid_r) |
| 59 | AM_RANGE(0xfc, 0xff) AM_READWRITE (unk_fc_r, unk_fc_w) |
| 33 | 60 | |
| 34 | 61 | AM_INHERIT_FROM(pci_device::config_map) |
| 35 | 62 | ADDRESS_MAP_END |
| r241853 | r241854 | |
| 58 | 85 | void i6300esb_lpc_device::device_reset() |
| 59 | 86 | { |
| 60 | 87 | pci_device::device_reset(); |
| 88 | tco_cntl = 0x00; |
| 89 | serirq_cntl = 0x10; |
| 90 | memset(pirq_rout, 0x80, sizeof(pirq_rout)); |
| 91 | d31_err_cfg = 0x00; |
| 92 | d31_err_sts = 0x00; |
| 93 | pci_dma_cfg = 0x0000; |
| 94 | rtc_conf = 0x00; |
| 95 | func_dis = 0x0080; |
| 96 | etr1 = 0x00000000; |
| 61 | 97 | siu_config_port = 0; |
| 62 | 98 | siu_config_state = 0; |
| 63 | 99 | } |
| 64 | 100 | |
| 65 | 101 | void i6300esb_lpc_device::reset_all_mappings() |
| 66 | 102 | { |
| 103 | pci_device::reset_all_mappings(); |
| 104 | |
| 105 | pmbase = 0; |
| 106 | acpi_cntl = 0; |
| 67 | 107 | gpio_base = 0; |
| 68 | 108 | gpio_cntl = 0x00; |
| 109 | back_cntl = 0x0f; |
| 69 | 110 | lpc_if_com_range = 0x00; |
| 70 | 111 | lpc_if_fdd_lpt_range = 0x00; |
| 71 | 112 | lpc_if_sound_range = 0x00; |
| 72 | 113 | fwh_dec_en1 = 0xff; |
| 114 | fwh_dec_en2 = 0x0f; |
| 73 | 115 | gen1_dec = 0x0000; |
| 74 | 116 | lpc_en = 0x0000; |
| 75 | 117 | fwh_sel1 = 0x00112233; |
| 118 | gen_cntl = 0x00000080; |
| 76 | 119 | } |
| 77 | 120 | |
| 121 | READ32_MEMBER (i6300esb_lpc_device::pmbase_r) |
| 122 | { |
| 123 | return pmbase | 1; |
| 124 | } |
| 125 | |
| 126 | WRITE32_MEMBER(i6300esb_lpc_device::pmbase_w) |
| 127 | { |
| 128 | COMBINE_DATA(&pmbase); |
| 129 | pmbase &= 0x0000ff80; |
| 130 | logerror("%s: pmbase = %08x\n", tag(), pmbase); |
| 131 | remap_cb(); |
| 132 | } |
| 133 | |
| 134 | READ8_MEMBER (i6300esb_lpc_device::acpi_cntl_r) |
| 135 | { |
| 136 | return acpi_cntl; |
| 137 | } |
| 138 | |
| 139 | WRITE8_MEMBER(i6300esb_lpc_device::acpi_cntl_w) |
| 140 | { |
| 141 | acpi_cntl = data; |
| 142 | logerror("%s: acpi_cntl = %08x\n", tag(), acpi_cntl); |
| 143 | remap_cb(); |
| 144 | } |
| 145 | |
| 146 | READ16_MEMBER (i6300esb_lpc_device::bios_cntl_r) |
| 147 | { |
| 148 | return pmbase | 1; |
| 149 | } |
| 150 | |
| 151 | WRITE16_MEMBER(i6300esb_lpc_device::bios_cntl_w) |
| 152 | { |
| 153 | COMBINE_DATA(&bios_cntl); |
| 154 | logerror("%s: bios_cntl = %08x\n", tag(), bios_cntl); |
| 155 | remap_cb(); |
| 156 | } |
| 157 | |
| 158 | READ8_MEMBER (i6300esb_lpc_device::tco_cntl_r) |
| 159 | { |
| 160 | return tco_cntl; |
| 161 | } |
| 162 | |
| 163 | WRITE8_MEMBER (i6300esb_lpc_device::tco_cntl_w) |
| 164 | { |
| 165 | tco_cntl = data; |
| 166 | logerror("%s: tco_cntl = %02x\n", tag(), tco_cntl); |
| 167 | } |
| 168 | |
| 78 | 169 | READ32_MEMBER (i6300esb_lpc_device::gpio_base_r) |
| 79 | 170 | { |
| 80 | 171 | return gpio_base | 1; |
| r241853 | r241854 | |
| 95 | 186 | |
| 96 | 187 | WRITE8_MEMBER (i6300esb_lpc_device::gpio_cntl_w) |
| 97 | 188 | { |
| 98 | | COMBINE_DATA(&gpio_cntl); |
| 189 | gpio_cntl = data; |
| 99 | 190 | logerror("%s: gpio_cntl = %02x\n", tag(), gpio_cntl); |
| 100 | 191 | remap_cb(); |
| 101 | 192 | } |
| 102 | 193 | |
| 194 | READ8_MEMBER (i6300esb_lpc_device::pirq_rout_r) |
| 195 | { |
| 196 | return pirq_rout[offset]; |
| 197 | } |
| 198 | |
| 199 | WRITE8_MEMBER (i6300esb_lpc_device::pirq_rout_w) |
| 200 | { |
| 201 | pirq_rout[offset] = data; |
| 202 | logerror("%s: pirq_rout[%d] = %02x\n", tag(), offset, pirq_rout[offset]); |
| 203 | } |
| 204 | |
| 205 | READ8_MEMBER (i6300esb_lpc_device::serirq_cntl_r) |
| 206 | { |
| 207 | return serirq_cntl; |
| 208 | } |
| 209 | |
| 210 | WRITE8_MEMBER (i6300esb_lpc_device::serirq_cntl_w) |
| 211 | { |
| 212 | serirq_cntl = data; |
| 213 | logerror("%s: serirq_cntl = %02x\n", tag(), serirq_cntl); |
| 214 | } |
| 215 | |
| 216 | READ8_MEMBER (i6300esb_lpc_device::pirq2_rout_r) |
| 217 | { |
| 218 | return pirq_rout_r(space, offset+4); |
| 219 | } |
| 220 | |
| 221 | WRITE8_MEMBER (i6300esb_lpc_device::pirq2_rout_w) |
| 222 | { |
| 223 | pirq_rout_w(space, offset+4, data); |
| 224 | } |
| 225 | |
| 226 | READ8_MEMBER (i6300esb_lpc_device::d31_err_cfg_r) |
| 227 | { |
| 228 | return d31_err_cfg; |
| 229 | } |
| 230 | |
| 231 | WRITE8_MEMBER (i6300esb_lpc_device::d31_err_cfg_w) |
| 232 | { |
| 233 | d31_err_cfg = data; |
| 234 | logerror("%s: d31_err_cfg = %02x\n", tag(), d31_err_cfg); |
| 235 | } |
| 236 | |
| 237 | READ8_MEMBER (i6300esb_lpc_device::d31_err_sts_r) |
| 238 | { |
| 239 | return d31_err_sts; |
| 240 | } |
| 241 | |
| 242 | WRITE8_MEMBER (i6300esb_lpc_device::d31_err_sts_w) |
| 243 | { |
| 244 | d31_err_sts &= ~data; |
| 245 | logerror("%s: d31_err_sts = %02x\n", tag(), d31_err_sts); |
| 246 | } |
| 247 | |
| 248 | READ16_MEMBER (i6300esb_lpc_device::pci_dma_cfg_r) |
| 249 | { |
| 250 | return pci_dma_cfg; |
| 251 | } |
| 252 | |
| 253 | WRITE16_MEMBER(i6300esb_lpc_device::pci_dma_cfg_w) |
| 254 | { |
| 255 | COMBINE_DATA(&pci_dma_cfg); |
| 256 | logerror("%s: pci_dma_cfg = %04x\n", tag(), pci_dma_cfg); |
| 257 | } |
| 258 | |
| 259 | READ32_MEMBER (i6300esb_lpc_device::gen_cntl_r) |
| 260 | { |
| 261 | return gen_cntl; |
| 262 | } |
| 263 | |
| 264 | WRITE32_MEMBER(i6300esb_lpc_device::gen_cntl_w) |
| 265 | { |
| 266 | COMBINE_DATA(&gen_cntl); |
| 267 | logerror("%s: gen_cntl = %08x\n", tag(), gen_cntl); |
| 268 | } |
| 269 | |
| 270 | READ8_MEMBER (i6300esb_lpc_device::gen_sta_r) |
| 271 | { |
| 272 | return gen_sta; |
| 273 | } |
| 274 | |
| 275 | WRITE8_MEMBER (i6300esb_lpc_device::gen_sta_w) |
| 276 | { |
| 277 | gen_sta = data; |
| 278 | logerror("%s: gen_sta = %02x\n", tag(), gen_sta); |
| 279 | } |
| 280 | |
| 281 | READ8_MEMBER (i6300esb_lpc_device::back_cntl_r) |
| 282 | { |
| 283 | return back_cntl; |
| 284 | } |
| 285 | |
| 286 | WRITE8_MEMBER (i6300esb_lpc_device::back_cntl_w) |
| 287 | { |
| 288 | back_cntl = data; |
| 289 | logerror("%s: back_cntl = %02x\n", tag(), back_cntl); |
| 290 | remap_cb(); |
| 291 | } |
| 292 | |
| 293 | READ8_MEMBER (i6300esb_lpc_device::rtc_conf_r) |
| 294 | { |
| 295 | return rtc_conf; |
| 296 | } |
| 297 | |
| 298 | WRITE8_MEMBER (i6300esb_lpc_device::rtc_conf_w) |
| 299 | { |
| 300 | rtc_conf = data; |
| 301 | logerror("%s: rtc_conf = %02x\n", tag(), rtc_conf); |
| 302 | } |
| 303 | |
| 103 | 304 | READ8_MEMBER (i6300esb_lpc_device::lpc_if_com_range_r) |
| 104 | 305 | { |
| 105 | 306 | return lpc_if_com_range; |
| r241853 | r241854 | |
| 107 | 308 | |
| 108 | 309 | WRITE8_MEMBER (i6300esb_lpc_device::lpc_if_com_range_w) |
| 109 | 310 | { |
| 110 | | COMBINE_DATA(&lpc_if_com_range); |
| 111 | | logerror("%s: lpc_if_com_range = %02x\n", tag(), lpc_if_com_range); |
| 311 | lpc_if_com_range = data; |
| 312 | logerror("%s: lpc_if_com_range = %02x\n", tag(), lpc_if_com_range); |
| 112 | 313 | remap_cb(); |
| 113 | 314 | } |
| 114 | 315 | |
| r241853 | r241854 | |
| 184 | 385 | remap_cb(); |
| 185 | 386 | } |
| 186 | 387 | |
| 388 | READ16_MEMBER (i6300esb_lpc_device::gen2_dec_r) |
| 389 | { |
| 390 | return gen2_dec; |
| 391 | } |
| 392 | |
| 393 | WRITE16_MEMBER(i6300esb_lpc_device::gen2_dec_w) |
| 394 | { |
| 395 | COMBINE_DATA(&gen2_dec); |
| 396 | logerror("%s: gen2_dec = %04x\n", tag(), gen2_dec); |
| 397 | remap_cb(); |
| 398 | } |
| 399 | |
| 400 | READ16_MEMBER (i6300esb_lpc_device::fwh_sel2_r) |
| 401 | { |
| 402 | return fwh_sel2; |
| 403 | } |
| 404 | |
| 405 | WRITE16_MEMBER(i6300esb_lpc_device::fwh_sel2_w) |
| 406 | { |
| 407 | COMBINE_DATA(&fwh_sel2); |
| 408 | logerror("%s: fwh_sel2 = %04x\n", tag(), fwh_sel2); |
| 409 | remap_cb(); |
| 410 | } |
| 411 | |
| 412 | READ8_MEMBER (i6300esb_lpc_device::fwh_dec_en2_r) |
| 413 | { |
| 414 | return fwh_dec_en2; |
| 415 | } |
| 416 | |
| 417 | WRITE8_MEMBER (i6300esb_lpc_device::fwh_dec_en2_w) |
| 418 | { |
| 419 | fwh_dec_en2 = data; |
| 420 | logerror("%s: fwh_dec_en2 = %02x\n", tag(), fwh_dec_en2); |
| 421 | remap_cb(); |
| 422 | } |
| 423 | |
| 424 | READ16_MEMBER (i6300esb_lpc_device::func_dis_r) |
| 425 | { |
| 426 | return func_dis; |
| 427 | } |
| 428 | |
| 429 | WRITE16_MEMBER(i6300esb_lpc_device::func_dis_w) |
| 430 | { |
| 431 | COMBINE_DATA(&func_dis); |
| 432 | logerror("%s: func_dis = %04x\n", tag(), func_dis); |
| 433 | } |
| 434 | |
| 435 | READ32_MEMBER (i6300esb_lpc_device::etr1_r) |
| 436 | { |
| 437 | return etr1; |
| 438 | } |
| 439 | |
| 440 | WRITE32_MEMBER(i6300esb_lpc_device::etr1_w) |
| 441 | { |
| 442 | logerror("%s: etr1 = %08x\n", tag(), data); |
| 443 | } |
| 444 | |
| 445 | READ32_MEMBER (i6300esb_lpc_device::mfid_r) |
| 446 | { |
| 447 | return 0xf66; |
| 448 | } |
| 449 | |
| 187 | 450 | READ32_MEMBER (i6300esb_lpc_device::unk_fc_r) |
| 188 | 451 | { |
| 189 | 452 | logerror("%s: read undocumented config reg fc\n", tag()); |
| r241853 | r241854 | |
| 289 | 552 | } |
| 290 | 553 | |
| 291 | 554 | io_space->install_device(0, 0xffff, *this, &i6300esb_lpc_device::internal_io_map); |
| 555 | |
| 556 | if(acpi_cntl & 0x10) |
| 557 | logerror("%s: Warning: acpi range enabled at %04x-%04x\n", tag(), pmbase, pmbase+127); |
| 558 | if(gpio_cntl & 0x10) |
| 559 | logerror("%s: Warning: gpio range enabled at %04x-%04x\n", tag(), gpio_base, gpio_base+63); |
| 292 | 560 | } |
| 293 | 561 | |
trunk/src/emu/machine/i6300esb.h
| r241853 | r241854 | |
| 29 | 29 | private: |
| 30 | 30 | DECLARE_ADDRESS_MAP(internal_io_map, 32); |
| 31 | 31 | |
| 32 | | UINT32 gpio_base, fwh_sel1; |
| 33 | | UINT16 gen1_dec, lpc_en; |
| 34 | | UINT8 gpio_cntl, lpc_if_com_range, lpc_if_fdd_lpt_range, lpc_if_sound_range, fwh_dec_en1, siu_config_port; |
| 32 | UINT32 pmbase, gpio_base, fwh_sel1, gen_cntl, etr1; |
| 33 | UINT16 bios_cntl, pci_dma_cfg, gen1_dec, lpc_en, gen2_dec, fwh_sel2, func_dis; |
| 34 | UINT8 pirq_rout[8]; |
| 35 | UINT8 acpi_cntl, tco_cntl, gpio_cntl, serirq_cntl, d31_err_cfg, d31_err_sts, gen_sta, back_cntl, rtc_conf; |
| 36 | UINT8 lpc_if_com_range, lpc_if_fdd_lpt_range, lpc_if_sound_range, fwh_dec_en1, fwh_dec_en2, siu_config_port; |
| 35 | 37 | int siu_config_state; |
| 36 | 38 | |
| 37 | 39 | DECLARE_WRITE8_MEMBER (nop_w); |
| 38 | 40 | |
| 39 | 41 | // configuration space registers |
| 42 | DECLARE_READ32_MEMBER (pmbase_r); // 40 |
| 43 | DECLARE_WRITE32_MEMBER(pmbase_w); |
| 44 | DECLARE_READ8_MEMBER (acpi_cntl_r); // 44 |
| 45 | DECLARE_WRITE8_MEMBER (acpi_cntl_w); |
| 46 | DECLARE_READ16_MEMBER (bios_cntl_r); // 4e |
| 47 | DECLARE_WRITE16_MEMBER(bios_cntl_w); |
| 48 | DECLARE_READ8_MEMBER (tco_cntl_r); // 54 |
| 49 | DECLARE_WRITE8_MEMBER (tco_cntl_w); |
| 40 | 50 | DECLARE_READ32_MEMBER (gpio_base_r); // 58 |
| 41 | 51 | DECLARE_WRITE32_MEMBER(gpio_base_w); |
| 42 | 52 | DECLARE_READ8_MEMBER (gpio_cntl_r); // 5c |
| 43 | 53 | DECLARE_WRITE8_MEMBER (gpio_cntl_w); |
| 44 | | |
| 54 | DECLARE_READ8_MEMBER (pirq_rout_r); // 60-63 |
| 55 | DECLARE_WRITE8_MEMBER (pirq_rout_w); |
| 56 | DECLARE_READ8_MEMBER (serirq_cntl_r); // 64 |
| 57 | DECLARE_WRITE8_MEMBER (serirq_cntl_w); |
| 58 | DECLARE_READ8_MEMBER (pirq2_rout_r); // 68-6b |
| 59 | DECLARE_WRITE8_MEMBER (pirq2_rout_w); |
| 60 | DECLARE_READ8_MEMBER (d31_err_cfg_r); // 88 |
| 61 | DECLARE_WRITE8_MEMBER (d31_err_cfg_w); |
| 62 | DECLARE_READ8_MEMBER (d31_err_sts_r); // 8a |
| 63 | DECLARE_WRITE8_MEMBER (d31_err_sts_w); |
| 64 | DECLARE_READ16_MEMBER (pci_dma_cfg_r); // 90 |
| 65 | DECLARE_WRITE16_MEMBER(pci_dma_cfg_w); |
| 66 | DECLARE_READ32_MEMBER (gen_cntl_r); // d0 |
| 67 | DECLARE_WRITE32_MEMBER(gen_cntl_w); |
| 68 | DECLARE_READ8_MEMBER (gen_sta_r); // d4 |
| 69 | DECLARE_WRITE8_MEMBER (gen_sta_w); |
| 70 | DECLARE_READ8_MEMBER (back_cntl_r); // d5 |
| 71 | DECLARE_WRITE8_MEMBER (back_cntl_w); |
| 72 | DECLARE_READ8_MEMBER (rtc_conf_r); // d8 |
| 73 | DECLARE_WRITE8_MEMBER (rtc_conf_w); |
| 45 | 74 | DECLARE_READ8_MEMBER (lpc_if_com_range_r); // e0 |
| 46 | 75 | DECLARE_WRITE8_MEMBER (lpc_if_com_range_w); |
| 47 | 76 | DECLARE_READ8_MEMBER (lpc_if_fdd_lpt_range_r); // e1 |
| r241853 | r241854 | |
| 56 | 85 | DECLARE_WRITE16_MEMBER(lpc_en_w); |
| 57 | 86 | DECLARE_READ32_MEMBER (fwh_sel1_r); // e8 |
| 58 | 87 | DECLARE_WRITE32_MEMBER(fwh_sel1_w); |
| 59 | | |
| 88 | DECLARE_READ16_MEMBER (gen2_dec_r); // ec |
| 89 | DECLARE_WRITE16_MEMBER(gen2_dec_w); |
| 90 | DECLARE_READ16_MEMBER (fwh_sel2_r); // ee |
| 91 | DECLARE_WRITE16_MEMBER(fwh_sel2_w); |
| 92 | DECLARE_READ8_MEMBER (fwh_dec_en2_r); // f0 |
| 93 | DECLARE_WRITE8_MEMBER (fwh_dec_en2_w); |
| 94 | DECLARE_READ16_MEMBER (func_dis_r); // f2 |
| 95 | DECLARE_WRITE16_MEMBER(func_dis_w); |
| 96 | DECLARE_READ32_MEMBER (etr1_r); // f4 |
| 97 | DECLARE_WRITE32_MEMBER(etr1_w); |
| 98 | DECLARE_READ32_MEMBER (mfid_r); // f8 |
| 60 | 99 | DECLARE_READ32_MEMBER (unk_fc_r); // fc |
| 61 | 100 | DECLARE_WRITE32_MEMBER(unk_fc_w); |
| 62 | 101 | |
trunk/src/emu/machine/pci.c
| r241853 | r241854 | |
| 4 | 4 | const device_type PCI_BRIDGE = &device_creator<pci_bridge_device>; |
| 5 | 5 | |
| 6 | 6 | DEVICE_ADDRESS_MAP_START(config_map, 32, pci_device) |
| 7 | | AM_RANGE(0x00, 0x03) AM_READ16(vendor_r, 0x0000ffff) |
| 8 | | AM_RANGE(0x00, 0x03) AM_READ16(device_r, 0xffff0000) |
| 7 | AM_RANGE(0x00, 0x03) AM_READ16 (vendor_r, 0x0000ffff) |
| 8 | AM_RANGE(0x00, 0x03) AM_READ16 (device_r, 0xffff0000) |
| 9 | AM_RANGE(0x04, 0x07) AM_READWRITE16(command_r, command_w, 0x0000ffff) |
| 10 | AM_RANGE(0x04, 0x07) AM_READ16 (status_r, 0xffff0000) |
| 9 | 11 | |
| 10 | | AM_RANGE(0x08, 0x0b) AM_READ (class_rev_r) |
| 11 | | AM_RANGE(0x0c, 0x0f) AM_READ8 (cache_line_size_r, 0x000000ff) |
| 12 | | AM_RANGE(0x0c, 0x0f) AM_READ8 (latency_timer_r, 0x0000ff00) |
| 13 | | AM_RANGE(0x0c, 0x0f) AM_READ8 (header_type_r, 0x00ff0000) |
| 14 | | AM_RANGE(0x0c, 0x0f) AM_READ8 (bist_r, 0xff000000) |
| 12 | AM_RANGE(0x08, 0x0b) AM_READ (class_rev_r) |
| 13 | AM_RANGE(0x0c, 0x0f) AM_READ8 (cache_line_size_r, 0x000000ff) |
| 14 | AM_RANGE(0x0c, 0x0f) AM_READ8 (latency_timer_r, 0x0000ff00) |
| 15 | AM_RANGE(0x0c, 0x0f) AM_READ8 (header_type_r, 0x00ff0000) |
| 16 | AM_RANGE(0x0c, 0x0f) AM_READ8 (bist_r, 0xff000000) |
| 15 | 17 | |
| 16 | | AM_RANGE(0x2c, 0x2f) AM_READ16(subvendor_r, 0x0000ffff) |
| 17 | | AM_RANGE(0x2c, 0x2f) AM_READ16(subsystem_r, 0xffff0000) |
| 18 | AM_RANGE(0x2c, 0x2f) AM_READ16 (subvendor_r, 0x0000ffff) |
| 19 | AM_RANGE(0x2c, 0x2f) AM_READ16 (subsystem_r, 0xffff0000) |
| 18 | 20 | |
| 19 | | AM_RANGE(0x34, 0x37) AM_READ8 (capptr_r, 0x000000ff) |
| 21 | AM_RANGE(0x34, 0x37) AM_READ8 (capptr_r, 0x000000ff) |
| 20 | 22 | ADDRESS_MAP_END |
| 21 | 23 | |
| 22 | 24 | pci_device::pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) |
| r241853 | r241854 | |
| 38 | 40 | |
| 39 | 41 | void pci_device::device_start() |
| 40 | 42 | { |
| 43 | command = 0x0080; |
| 44 | command_mask = 0x01bf; |
| 45 | status = 0x0000; |
| 41 | 46 | } |
| 42 | 47 | |
| 43 | 48 | void pci_device::device_reset() |
| r241853 | r241854 | |
| 54 | 59 | return main_id; |
| 55 | 60 | } |
| 56 | 61 | |
| 62 | READ16_MEMBER(pci_device::command_r) |
| 63 | { |
| 64 | return command; |
| 65 | } |
| 66 | |
| 67 | WRITE16_MEMBER(pci_device::command_w) |
| 68 | { |
| 69 | mem_mask &= command_mask; |
| 70 | COMBINE_DATA(&command); |
| 71 | logerror("%s: command = %04x\n", tag(), command); |
| 72 | } |
| 73 | |
| 74 | READ16_MEMBER(pci_device::status_r) |
| 75 | { |
| 76 | return status; |
| 77 | } |
| 78 | |
| 57 | 79 | READ32_MEMBER(pci_device::class_rev_r) |
| 58 | 80 | { |
| 59 | 81 | return (pclass << 8) | revision; |