trunk/src/mame/video/tc0100scn.c
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| 1 | 1 | /* |
| 2 | 2 | Taito TC0100SCN |
| 3 | 3 | --------- |
| 4 | | Tilemap generator. The front tilemap fetches gfx data from RAM, |
| 5 | | the others use ROMs as usual. |
| 4 | Tilemap generator. Manages two background tilemaps with 8x8 tiles fetched |
| 5 | from ROM, and one foreground text tilemap with tiles fetched from RAM. |
| 6 | Both background layers support rowscroll and one of them additionally |
| 7 | supports columnscroll. The three tilemaps are mixed internally (the text |
| 8 | tilemap is always on top, the other two are selectable) and output as |
| 9 | 15 bits of pixel data. |
| 10 | The TC0100SCN uses 0x10000 bytes of RAM, plus an optional 0x4000 bytes to |
| 11 | allow wider tilemaps (mainly used by multiscreen games). It can address |
| 12 | up to 0x200000 bytes of ROM (0x10000 tiles), 16 bits at a time. |
| 6 | 13 | |
| 7 | | Standard memory layout (three 64x64 tilemaps with 8x8 tiles) |
| 14 | Inputs and outputs (based on Operation Thunderbolt schematics): |
| 15 | - CPU address bus (VA1-VA17) |
| 16 | - CPU data bus (D0-D15) |
| 17 | - CPU control lines (CS, UDS, LDS, R/W, DTACK) |
| 18 | - RAM address bus (SA0-SA14) |
| 19 | - RAM data bus (SD0-SD15) |
| 20 | - RAM control lines (WEH, WEL, SCE0, SCE1) |
| 21 | (SCE0 is connected to CS of two 32Kx8 SRAMs. SCE1 is unconnected. |
| 22 | SCE1 is probably for the optional RAM, which isn't present on |
| 23 | Operation Thunderbolt) |
| 24 | - ROM address bus (AD0-AD19) |
| 25 | - ROM data bus (RD0-RD15) |
| 26 | - Pixel output (SC0-SC14) |
| 27 | - Clocks and video sync (HSYNC, HBLANK, VSYNC, VBLANK) |
| 8 | 28 | |
| 29 | Standard memory layout (three 64x64 tilemaps) |
| 30 | |
| 9 | 31 | 0000-3fff BG0 |
| 10 | 32 | 4000-5fff FG0 |
| 11 | 33 | 6000-6fff gfx data for FG0 |
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| 14 | 36 | c000-c3ff BG0 rowscroll (second half unused*) |
| 15 | 37 | c400-c7ff BG1 rowscroll (second half unused*) |
| 16 | 38 | c800-dfff unused (probably) |
| 17 | | e000-e0ff BG0 colscroll [see info below] |
| 39 | e000-e0ff BG1 colscroll [see info below] |
| 18 | 40 | e100-ffff unused (probably) |
| 19 | 41 | |
| 20 | 42 | Double width tilemaps memory layout (two 128x64 tilemaps, one 128x32 tilemap) |
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| 23 | 45 | 08000-0ffff BG1 (128x64) |
| 24 | 46 | 10000-103ff BG0 rowscroll (second half unused*) |
| 25 | 47 | 10400-107ff BG1 rowscroll (second half unused*) |
| 26 | | 10800-108ff BG0 colscroll [evidenced by Warriorb inits from $1634] |
| 48 | 10800-108ff BG1 colscroll [evidenced by Warriorb inits from $1634] |
| 27 | 49 | 10900-10fff unused (probably) |
| 28 | 50 | 11000-11fff gfx data for FG0 |
| 29 | 51 | 12000-13fff FG0 (128x32) |
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| 107 | 129 | columns [rows, as the game is rotated] scroll across with the ship. |
| 108 | 130 | $84fc0 and neighbouring routines poke col scroll area. |
| 109 | 131 | |
| 132 | TC0620SCC |
| 133 | --------- |
| 134 | The TC0620SCC seems to be similar to the TC0100SCN except that the ROM tiles |
| 135 | are 6bpp instead of 4bpp. It probably has a 24-bit bus to the ROMs instead |
| 136 | of 16-bit, but nothing else is known about it (such as whether it supports |
| 137 | the wide tilemap mode) |
| 138 | |
| 110 | 139 | */ |
| 111 | 140 | |
| 112 | 141 | #include "emu.h" |
trunk/src/mame/video/tc0480scp.c
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| 1 | 1 | /* |
| 2 | 2 | Taito TC0480SCP |
| 3 | 3 | --------- |
| 4 | | Tilemap generator, has four zoomable tilemaps with 16x16 tiles. |
| 5 | | It also has a front tilemap with 8x8 tiles which fetches gfx data |
| 6 | | from RAM. |
| 4 | Tilemap generator. Manages four background tilemaps with 16x16 tiles fetched |
| 5 | from ROM, and one foreground text tilemap with 8x8 tiles fetched from RAM. |
| 6 | All four background tilemaps support zooming and rowscroll, and two of them |
| 7 | additionally support per-row zooming and column scroll. The five tilemaps |
| 8 | are mixed internally (the text tilemap is always on top, the order of the |
| 9 | other four is selectable) and output as 16 bits of pixel data. |
| 10 | The TC0480SCP uses 0x10000 bytes of RAM. It seems to be able to address |
| 11 | up to 0x800000 bytes of ROM (0x10000 tiles) as it has 21 address lines and |
| 12 | 32 data lines, but no known game uses more than 0x400000 bytes. |
| 7 | 13 | |
| 8 | | BG2 and 3 are "special" layers which have row zoom and source |
| 9 | | columnscroll. The selectable layer priority order is a function |
| 10 | | of the need to have the "special" layers in particular priority |
| 11 | | positions. |
| 14 | Inputs and outputs (based on Gunbuster schematics): |
| 15 | - CPU address bus (VA1-VA17) |
| 16 | - CPU data bus (VD0-VD15) |
| 17 | - CPU control lines (CS, UDS, LDS, R/W, DTACK) |
| 18 | - RAM address bus (RA0-RA14) |
| 19 | - RAM data bus (RAD0-RAD15) |
| 20 | - RAM control lines (RWAH, RWAL, RAOE) |
| 21 | - ROM address bus (CH0-CH20) |
| 22 | - ROM data bus (RD0-RD31) |
| 23 | - Pixel output (SD0-SD15) |
| 24 | - Clocks and video sync (HSYNC, HBLANK, VSYNC, VBLANK) |
| 12 | 25 | |
| 13 | 26 | Standard memory layout (four 32x32 bg tilemaps, one 64x64 fg tilemap) |
| 14 | 27 | |