trunk/src/emu/cpu/i386/i386.c
| r241819 | r241820 | |
| 3148 | 3148 | |
| 3149 | 3149 | zero_state(); |
| 3150 | 3150 | |
| 3151 | | save_item(NAME( m_reg.d)); |
| 3151 | save_item(NAME(m_reg.d)); |
| 3152 | 3152 | save_item(NAME(m_sreg[ES].selector)); |
| 3153 | 3153 | save_item(NAME(m_sreg[ES].base)); |
| 3154 | 3154 | save_item(NAME(m_sreg[ES].limit)); |
| r241819 | r241820 | |
| 3190 | 3190 | save_item(NAME(m_AF)); |
| 3191 | 3191 | save_item(NAME(m_IF)); |
| 3192 | 3192 | save_item(NAME(m_TF)); |
| 3193 | | save_item(NAME( m_cr)); |
| 3194 | | save_item(NAME( m_dr)); |
| 3195 | | save_item(NAME( m_tr)); |
| 3193 | save_item(NAME(m_cr)); |
| 3194 | save_item(NAME(m_dr)); |
| 3195 | save_item(NAME(m_tr)); |
| 3196 | 3196 | save_item(NAME(m_idtr.base)); |
| 3197 | 3197 | save_item(NAME(m_idtr.limit)); |
| 3198 | 3198 | save_item(NAME(m_gdtr.base)); |
| r241819 | r241820 | |
| 3512 | 3512 | m_ext = 0; |
| 3513 | 3513 | m_halted = 0; |
| 3514 | 3514 | m_operand_size = 0; |
| 3515 | m_xmm_operand_size = 0; |
| 3515 | 3516 | m_address_size = 0; |
| 3516 | 3517 | m_operand_prefix = 0; |
| 3517 | 3518 | m_address_prefix = 0; |
| r241819 | r241820 | |
| 3765 | 3766 | { |
| 3766 | 3767 | i386_check_irq_line(); |
| 3767 | 3768 | m_operand_size = m_sreg[CS].d; |
| 3769 | m_xmm_operand_size = 0; |
| 3768 | 3770 | m_address_size = m_sreg[CS].d; |
| 3769 | 3771 | m_operand_prefix = 0; |
| 3770 | 3772 | m_address_prefix = 0; |
trunk/src/emu/cpu/i386/i386.h
| r241819 | r241820 | |
| 187 | 187 | int m_halted; |
| 188 | 188 | |
| 189 | 189 | int m_operand_size; |
| 190 | int m_xmm_operand_size; |
| 190 | 191 | int m_address_size; |
| 191 | 192 | int m_operand_prefix; |
| 192 | 193 | int m_address_prefix; |
| r241819 | r241820 | |
| 331 | 332 | void pentium_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr); |
| 332 | 333 | UINT64 p6_msr_read(UINT32 offset,UINT8 *valid_msr); |
| 333 | 334 | void p6_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr); |
| 335 | UINT64 piv_msr_read(UINT32 offset,UINT8 *valid_msr); |
| 336 | void piv_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr); |
| 334 | 337 | inline UINT64 MSR_READ(UINT32 offset,UINT8 *valid_msr); |
| 335 | 338 | inline void MSR_WRITE(UINT32 offset, UINT64 data, UINT8 *valid_msr); |
| 336 | 339 | UINT32 i386_load_protected_mode_segment(I386_SREG *seg, UINT64 *desc ); |
trunk/src/emu/cpu/i386/i386priv.h
| r241819 | r241820 | |
| 1328 | 1328 | } |
| 1329 | 1329 | } |
| 1330 | 1330 | |
| 1331 | |
| 1332 | // PIV (Pentium 4+) |
| 1333 | UINT64 i386_device::piv_msr_read(UINT32 offset,UINT8 *valid_msr) |
| 1334 | { |
| 1335 | switch(offset) |
| 1336 | { |
| 1337 | default: |
| 1338 | logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,m_pc-2); |
| 1339 | *valid_msr = 1; |
| 1340 | return 0; |
| 1341 | } |
| 1342 | return -1; |
| 1343 | } |
| 1344 | |
| 1345 | void i386_device::piv_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr) |
| 1346 | { |
| 1347 | switch(offset) |
| 1348 | { |
| 1349 | default: |
| 1350 | logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(UINT32)(data >> 32),(UINT32)data,m_pc-2); |
| 1351 | *valid_msr = 1; |
| 1352 | break; |
| 1353 | } |
| 1354 | } |
| 1355 | |
| 1331 | 1356 | UINT64 i386_device::MSR_READ(UINT32 offset,UINT8 *valid_msr) |
| 1332 | 1357 | { |
| 1333 | 1358 | UINT64 res; |
| r241819 | r241820 | |
| 1343 | 1368 | case 6: // Pentium Pro, Pentium II, Pentium III |
| 1344 | 1369 | res = p6_msr_read(offset,valid_msr); |
| 1345 | 1370 | break; |
| 1371 | case 15: // Pentium 4+ |
| 1372 | res = piv_msr_read(offset,valid_msr); |
| 1373 | break; |
| 1346 | 1374 | default: |
| 1347 | 1375 | res = 0; |
| 1348 | 1376 | break; |
| r241819 | r241820 | |
| 1364 | 1392 | case 6: // Pentium Pro, Pentium II, Pentium III |
| 1365 | 1393 | p6_msr_write(offset,data,valid_msr); |
| 1366 | 1394 | break; |
| 1395 | case 15: // Pentium 4+ |
| 1396 | piv_msr_write(offset,data,valid_msr); |
| 1397 | break; |
| 1367 | 1398 | } |
| 1368 | 1399 | } |
| 1369 | 1400 | |
trunk/src/emu/cpu/i386/pentops.inc
| r241819 | r241820 | |
| 1269 | 1269 | switch ( (modm & 0x38) >> 3 ) |
| 1270 | 1270 | { |
| 1271 | 1271 | case 2: // psrlq |
| 1272 | | MMX(modm & 7).q=MMX(modm & 7).q >> imm8; |
| 1272 | if (m_xmm_operand_size) |
| 1273 | { |
| 1274 | XMM(modm & 7).q[0] = imm8 > 63 ? 0 : XMM(modm & 7).q[0] >> imm8; |
| 1275 | XMM(modm & 7).q[1] = imm8 > 63 ? 0 : XMM(modm & 7).q[1] >> imm8; |
| 1276 | } |
| 1277 | else |
| 1278 | MMX(modm & 7).q = imm8 > 63 ? 0 : MMX(modm & 7).q >> imm8; |
| 1273 | 1279 | break; |
| 1280 | case 3: // psrldq |
| 1281 | if (imm8 >= 16) |
| 1282 | { |
| 1283 | XMM(modm & 7).q[0] = 0; |
| 1284 | XMM(modm & 7).q[1] = 0; |
| 1285 | } |
| 1286 | else if(imm8 >= 8) |
| 1287 | { |
| 1288 | imm8 = (imm8 & 7) << 3; |
| 1289 | XMM(modm & 7).q[0] = XMM(modm & 7).q[1] >> imm8; |
| 1290 | XMM(modm & 7).q[1] = 0; |
| 1291 | } |
| 1292 | else if(imm8) |
| 1293 | { |
| 1294 | imm8 = imm8 << 3; |
| 1295 | XMM(modm & 7).q[1] = (XMM(modm & 7).q[0] << (64 - imm8)) | (XMM(modm & 7).q[1] >> imm8); |
| 1296 | XMM(modm & 7).q[0] = XMM(modm & 7).q[0] >> imm8; |
| 1297 | } |
| 1298 | break; |
| 1274 | 1299 | case 6: // psllq |
| 1275 | | MMX(modm & 7).q=MMX(modm & 7).q << imm8; |
| 1300 | if (m_xmm_operand_size) |
| 1301 | { |
| 1302 | XMM(modm & 7).q[0] = imm8 > 63 ? 0 : XMM(modm & 7).q[0] << imm8; |
| 1303 | XMM(modm & 7).q[1] = imm8 > 63 ? 0 : XMM(modm & 7).q[1] << imm8; |
| 1304 | } |
| 1305 | else |
| 1306 | MMX(modm & 7).q = imm8 > 63 ? 0 : MMX(modm & 7).q << imm8; |
| 1276 | 1307 | break; |
| 1308 | case 7: // pslldq |
| 1309 | if (imm8 >= 16) |
| 1310 | { |
| 1311 | XMM(modm & 7).q[0] = 0; |
| 1312 | XMM(modm & 7).q[1] = 0; |
| 1313 | } |
| 1314 | else if(imm8 >= 8) |
| 1315 | { |
| 1316 | imm8 = (imm8 & 7) << 3; |
| 1317 | XMM(modm & 7).q[1] = XMM(modm & 7).q[0] << imm8; |
| 1318 | XMM(modm & 7).q[0] = 0; |
| 1319 | } |
| 1320 | else if(imm8) |
| 1321 | { |
| 1322 | imm8 = imm8 << 3; |
| 1323 | XMM(modm & 7).q[0] = (XMM(modm & 7).q[1] << (64 - imm8)) | (XMM(modm & 7).q[0] >> imm8); |
| 1324 | XMM(modm & 7).q[1] = XMM(modm & 7).q[1] << imm8; |
| 1325 | } |
| 1326 | break; |
| 1277 | 1327 | default: |
| 1278 | 1328 | report_invalid_modrm("mmx_group0f73", modm); |
| 1279 | 1329 | } |