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r33282 Saturday 8th November, 2014 at 16:50:49 UTC by Carl
(mess) pc9801: bit more (nw)

[src/mess/drivers]

pc9801.c

trunk/src/mess/drivers/pc9801.c

r241793	r241794
560	560	DECLARE_WRITE8_MEMBER(pc9801_fdc_2hd_w);
561	561	DECLARE_READ8_MEMBER(pc9801_fdc_2dd_r);
562	562	DECLARE_WRITE8_MEMBER(pc9801_fdc_2dd_w);
563		DECLARE_READ8_MEMBER(pc9801_tvram_r);
564		DECLARE_WRITE8_MEMBER(pc9801_tvram_w);
565		DECLARE_READ8_MEMBER(pc9801_gvram_r);
566		DECLARE_WRITE8_MEMBER(pc9801_gvram_w);
	563	DECLARE_READ8_MEMBER(tvram_r);
	564	DECLARE_WRITE8_MEMBER(tvram_w);
	565	DECLARE_READ8_MEMBER(gvram_r);
	566	DECLARE_WRITE8_MEMBER(gvram_w);
567	567	DECLARE_WRITE8_MEMBER(pc9801rs_mouse_freq_w);
568		inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank,int vrambank);
569		inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank) { return m_pc9801rs_grcg_r(offset, vbank, m_vram_bank); }
570		inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,int vrambank,UINT8 data);
571		inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data) { m_pc9801rs_grcg_w(offset, vbank, m_vram_bank, data); }
572	568	DECLARE_CUSTOM_INPUT_MEMBER(system_type_r);
573	569	DECLARE_READ8_MEMBER(grcg_gvram_r);
574	570	DECLARE_WRITE8_MEMBER(grcg_gvram_w);
r241793	r241794
594	590	DECLARE_READ8_MEMBER(pc9801rs_knjram_r);
595	591	DECLARE_WRITE8_MEMBER(pc9801rs_knjram_w);
596	592	DECLARE_WRITE8_MEMBER(pc9801rs_bank_w);
597		DECLARE_READ8_MEMBER(pc9801rs_f0_r);
598		DECLARE_WRITE8_MEMBER(pc9801rs_f0_w);
599		DECLARE_READ8_MEMBER(pc9801rs_memory_r);
600		DECLARE_WRITE8_MEMBER(pc9801rs_memory_w);
	593	DECLARE_READ8_MEMBER(a20_ctrl_r);
	594	DECLARE_WRITE8_MEMBER(a20_ctrl_w);
601	595	DECLARE_READ8_MEMBER(pc9810rs_fdc_ctrl_r);
602	596	DECLARE_WRITE8_MEMBER(pc9810rs_fdc_ctrl_w);
603	597	DECLARE_READ8_MEMBER(pc9801rs_2hd_r);
r241793	r241794
674	668	DECLARE_PALETTE_INIT(pc9801);
675	669	INTERRUPT_GEN_MEMBER(pc9801_vrtc_irq);
676	670	DECLARE_READ8_MEMBER(get_slave_ack);
677		DECLARE_WRITE_LINE_MEMBER(pc9801_dma_hrq_changed);
678		DECLARE_WRITE_LINE_MEMBER(pc9801_tc_w);
679		DECLARE_READ8_MEMBER(pc9801_dma_read_byte);
680		DECLARE_WRITE8_MEMBER(pc9801_dma_write_byte);
681		DECLARE_WRITE_LINE_MEMBER(pc9801_dack0_w);
682		DECLARE_WRITE_LINE_MEMBER(pc9801_dack1_w);
683		DECLARE_WRITE_LINE_MEMBER(pc9801_dack2_w);
684		DECLARE_WRITE_LINE_MEMBER(pc9801_dack3_w);
	671	DECLARE_WRITE_LINE_MEMBER(dma_hrq_changed);
	672	DECLARE_WRITE_LINE_MEMBER(tc_w);
	673	DECLARE_READ8_MEMBER(dma_read_byte);
	674	DECLARE_WRITE8_MEMBER(dma_write_byte);
	675	DECLARE_WRITE_LINE_MEMBER(dack0_w);
	676	DECLARE_WRITE_LINE_MEMBER(dack1_w);
	677	DECLARE_WRITE_LINE_MEMBER(dack2_w);
	678	DECLARE_WRITE_LINE_MEMBER(dack3_w);
685	679	DECLARE_WRITE8_MEMBER(ppi_sys_portc_w);
686	680
687	681	DECLARE_WRITE_LINE_MEMBER(fdc_2dd_irq);
r241793	r241794
701	695	}m_mouse;
702	696	TIMER_DEVICE_CALLBACK_MEMBER( mouse_irq_cb );
703	697
704		inline UINT32 m_calc_grcg_addr(int i,UINT32 offset,int vrambank);
705
706	698	DECLARE_DRIVER_INIT(pc9801_kanji);
707	699	inline void set_dma_channel(int channel, int state);
708	700	virtual void device_reset_after_children();
r241793	r241794
984	976
985	977	WRITE8_MEMBER(pc9801_state::pc9801_video_ff_w)
986	978	{
987		if((offset & 1) == 0)
988		{
989		/*
990		TODO: this is my best bet so far. Register 4 is annoying, the pattern seems to be:
991		Write to video FF register Graphic -> 00
992		Write to video FF register 200 lines -> 0x
993		Write to video FF register 200 lines -> 00
	979	/*
	980	TODO: this is my best bet so far. Register 4 is annoying, the pattern seems to be:
	981	Write to video FF register Graphic -> 00
	982	Write to video FF register 200 lines -> 0x
	983	Write to video FF register 200 lines -> 00
994	984
995		where x is the current mode.
996		*/
997		switch((data & 0x0e) >> 1)
998		{
999		case 1:
1000		m_gfx_ff = 1;
1001		if(data & 1)
1002		logerror("Graphic f/f actually enabled!\n");
1003		break;
1004		case 4:
1005		if(m_gfx_ff)
1006		{
1007		m_video_ff[(data & 0x0e) >> 1] = data &1;
1008		m_gfx_ff = 0;
1009		}
	985	where x is the current mode.
	986	*/
	987	switch((data & 0x0e) >> 1)
	988	{
	989	case 1:
	990	m_gfx_ff = 1;
	991	if(data & 1)
	992	logerror("Graphic f/f actually enabled!\n");
1010	993	break;
1011		default: m_video_ff[(data & 0x0e) >> 1] = data & 1; break;
1012		}
	994	case 4:
	995	if(m_gfx_ff)
	996	{
	997	m_video_ff[(data & 0x0e) >> 1] = data &1;
	998	m_gfx_ff = 0;
	999	}
	1000	break;
	1001	default: m_video_ff[(data & 0x0e) >> 1] = data & 1; break;
	1002	}
1013	1003
1014		if(0)
	1004	if(0)
	1005	{
	1006	static const char *const video_ff_regnames[] =
1015	1007	{
1016		static const char *const video_ff_regnames[] =
1017		{
1018		"Attribute Select", // 0
1019		"Graphic",          // 1
1020		"Column",           // 2
1021		"Font Select",      // 3
1022		"200 lines",        // 4
1023		"KAC?",             // 5
1024		"Memory Switch",    // 6
1025		"Display ON"        // 7
1026		};
	1008	"Attribute Select", // 0
	1009	"Graphic",          // 1
	1010	"Column",           // 2
	1011	"Font Select",      // 3
	1012	"200 lines",        // 4
	1013	"KAC?",             // 5
	1014	"Memory Switch",    // 6
	1015	"Display ON"        // 7
	1016	};
1027	1017
1028		logerror("Write to video FF register %s -> %02x\n",video_ff_regnames[(data & 0x0e) >> 1],data & 1);
1029		}
	1018	logerror("Write to video FF register %s -> %02x\n",video_ff_regnames[(data & 0x0e) >> 1],data & 1);
1030	1019	}
1031		else // odd
1032		{
1033		//logerror("Write to undefined port [%02x] <- %02x\n",offset+0x68,data);
1034		}
1035	1020	}
1036	1021
1037	1022
r241793	r241794
1294	1279
1295	1280
1296	1281	/* TODO: banking? */
1297		READ8_MEMBER(pc9801_state::pc9801_tvram_r)
	1282	READ8_MEMBER(pc9801_state::tvram_r)
1298	1283	{
1299	1284	UINT8 res;
1300	1285
1301	1286	if((offset & 0x2000) && offset & 1)
1302	1287	return 0xff;
1303	1288
1304		//res = upd7220_vram_r(machine().device("upd7220_chr"),offset);
1305	1289	res = m_tvram[offset];
1306	1290
1307	1291	return res;
1308	1292	}
1309	1293
1310		WRITE8_MEMBER(pc9801_state::pc9801_tvram_w)
	1294	WRITE8_MEMBER(pc9801_state::tvram_w)
1311	1295	{
1312	1296	if(offset < (0x3fe2) || m_video_ff[MEMSW_REG])
1313	1297	m_tvram[offset] = data;
r241793	r241794
1316	1300	}
1317	1301
1318	1302	/* +0x8000 is trusted (bank 0 is actually used by 16 colors mode) */
1319		READ8_MEMBER(pc9801_state::pc9801_gvram_r)
	1303	READ8_MEMBER(pc9801_state::gvram_r)
1320	1304	{
1321	1305	return m_video_ram_2[offset+0x08000+m_vram_bank*0x20000];
1322	1306	}
1323	1307
1324		WRITE8_MEMBER(pc9801_state::pc9801_gvram_w)
	1308	WRITE8_MEMBER(pc9801_state::gvram_w)
1325	1309	{
1326	1310	m_video_ram_2[offset+0x08000+m_vram_bank*0x20000] = data;
1327	1311	}
1328	1312
1329		inline UINT32 pc9801_state::m_calc_grcg_addr(int i,UINT32 offset,int vrambank)
	1313	READ8_MEMBER(pc9801_state::upd7220_grcg_r)
1330	1314	{
1331		return (offset) + (((i+1)*0x8000) & 0x1ffff) + (vrambank*0x20000);
1332		}
1333
1334		inline UINT8 pc9801_state::m_pc9801rs_grcg_r(UINT32 offset,int vbank,int vrambank)
1335		{
1336	1315	UINT8 res = 0;
1337	1316
1338	1317	if(!(m_grcg.mode & 0x80))
1339		res = m_video_ram_2[offset+vbank*0x8000+vrambank*0x20000];
	1318	res = m_video_ram_2[offset];
1340	1319	else if(!(m_grcg.mode & 0x40))
1341	1320	{
1342	1321	int i;
1343	1322
	1323	offset &= ~(3 << 15);
1344	1324	res = 0;
1345	1325	for(i=0;i<4;i++)
1346	1326	{
1347	1327	if((m_grcg.mode & (1 << i)) == 0)
1348		res |= (m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] ^ m_grcg.tile[i]);
	1328	res |= m_video_ram_2[offset | (((i + 1) & 3) * 0x8000)] ^ m_grcg.tile[i];
1349	1329	}
1350	1330
1351	1331	res ^= 0xff;
r241793	r241794
1354	1334	return res;
1355	1335	}
1356	1336
1357		inline void pc9801_state::m_pc9801rs_grcg_w(UINT32 offset,int vbank,int vrambank,UINT8 data)
	1337	WRITE8_MEMBER(pc9801_state::upd7220_grcg_w)
1358	1338	{
1359	1339	if((m_grcg.mode & 0x80) == 0)
1360		m_video_ram_2[offset+vbank*0x8000+vrambank*0x20000] = data;
	1340	m_video_ram_2[offset] = data;
1361	1341	else
1362	1342	{
1363	1343	int i;
	1344	offset &= ~(3 << 15);
1364	1345
1365	1346	if(m_grcg.mode & 0x40) // RMW
1366	1347	{
r241793	r241794
1368	1349	{
1369	1350	if((m_grcg.mode & (1 << i)) == 0)
1370	1351	{
1371		m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] &= ~data;
1372		m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] |= m_grcg.tile[i] & data;
	1352	m_video_ram_2[offset | (((i + 1) & 3) * 0x8000)] &= ~data;
	1353	m_video_ram_2[offset | (((i + 1) & 3) * 0x8000)] |= m_grcg.tile[i] & data;
1373	1354	}
1374	1355	}
1375	1356	}
r241793	r241794
1379	1360	{
1380	1361	if((m_grcg.mode & (1 << i)) == 0)
1381	1362	{
1382		m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] = m_grcg.tile[i];
	1363	m_video_ram_2[offset | (((i + 1) & 3) * 0x8000)] = m_grcg.tile[i];
1383	1364	}
1384	1365	}
1385	1366	}
1386	1367	}
1387	1368	}
1388	1369
1389		READ8_MEMBER(pc9801_state::upd7220_grcg_r)
1390		{
1391		return m_pc9801rs_grcg_r(offset & 0x7fff, (offset >> 15) & 3, offset >> 17);
1392		}
1393
1394		WRITE8_MEMBER(pc9801_state::upd7220_grcg_w)
1395		{
1396		m_pc9801rs_grcg_w(offset & 0x7fff, (offset >> 15) & 3, offset >> 17, data);
1397		}
1398
1399	1370	READ8_MEMBER(pc9801_state::ide_hack_r)
1400	1371	{
1401	1372	address_space &ram = m_maincpu->space(AS_PROGRAM);
r241793	r241794
1520	1491
1521	1492	static ADDRESS_MAP_START( pc9801_map, AS_PROGRAM, 16, pc9801_state )
1522	1493	AM_RANGE(0x00000, 0x9ffff) AM_RAM //work RAM
1523		AM_RANGE(0xa0000, 0xa3fff) AM_READWRITE8(pc9801_tvram_r,pc9801_tvram_w,0xffff) //TVRAM
1524		AM_RANGE(0xa8000, 0xbffff) AM_READWRITE8(pc9801_gvram_r,pc9801_gvram_w,0xffff) //bitmap VRAM
	1494	AM_RANGE(0xa0000, 0xa3fff) AM_READWRITE8(tvram_r,tvram_w,0xffff) //TVRAM
	1495	AM_RANGE(0xa8000, 0xbffff) AM_READWRITE8(gvram_r,gvram_w,0xffff) //bitmap VRAM
1525	1496	AM_RANGE(0xcc000, 0xcdfff) AM_ROM AM_REGION("sound_bios",0) //sound BIOS
1526	1497	AM_RANGE(0xd6000, 0xd6fff) AM_ROM AM_REGION("fdc_bios_2dd",0) //floppy BIOS 2dd
1527	1498	AM_RANGE(0xd7000, 0xd7fff) AM_ROM AM_REGION("fdc_bios_2hd",0) //floppy BIOS 2hd
r241793	r241794
1541	1512	AM_RANGE(0x0050, 0x0053) AM_WRITE8(nmi_ctrl_w,0x00ff) // NMI FF / i8255 floppy port (2d?)
1542	1513	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("upd7220_chr", upd7220_device, read, write, 0x00ff) //upd7220 character ports / <undefined>
1543	1514	AM_RANGE(0x0064, 0x0065) AM_WRITE8(vrtc_mask_w,0x00ff)
1544		AM_RANGE(0x0068, 0x0069) AM_WRITE8(pc9801_video_ff_w,0xffff) //mode FF / <undefined>
	1515	AM_RANGE(0x0068, 0x0069) AM_WRITE8(pc9801_video_ff_w,0x00ff) //mode FF / <undefined>
1545	1516	//  AM_RANGE(0x006c, 0x006f) border color / <undefined>
1546	1517	AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00)
1547	1518	AM_RANGE(0x0070, 0x007b) AM_READWRITE8(txt_scrl_r,txt_scrl_w,0x00ff) //display registers / i8253 pit
r241793	r241794
1631	1602	}
1632	1603	}
1633	1604
1634		READ8_MEMBER(pc9801_state::pc9801rs_f0_r)
	1605	READ8_MEMBER(pc9801_state::a20_ctrl_r)
1635	1606	{
1636		if(offset == 0x02)
	1607	if(offset == 0x01)
1637	1608	return (m_gate_a20 ^ 1) | 0xfe;
1638		else if(offset == 0x06)
	1609	else if(offset == 0x03)
1639	1610	return (m_gate_a20 ^ 1) | (m_nmi_enable << 1);
1640	1611
1641	1612	return 0x00;
1642	1613	}
1643	1614
1644		WRITE8_MEMBER(pc9801_state::pc9801rs_f0_w)
	1615	WRITE8_MEMBER(pc9801_state::a20_ctrl_w)
1645	1616	{
1646	1617	if(offset == 0x00)
1647	1618	{
r241793	r241794
1654	1625	m_gate_a20 = 0;
1655	1626	}
1656	1627
1657		if(offset == 0x02)
	1628	if(offset == 0x01)
1658	1629	m_gate_a20 = 1;
1659	1630
1660		if(offset == 0x06)
	1631	if(offset == 0x03)
1661	1632	{
1662	1633	if(data == 0x02)
1663	1634	m_gate_a20 = 1;
r241793	r241794
1816	1787
1817	1788	WRITE8_MEMBER(pc9801_state::pc9801rs_video_ff_w)
1818	1789	{
1819		if(offset == 2)
	1790	if(offset == 1)
1820	1791	{
1821	1792	if((data & 0xf0) == 0) /* disable any PC-9821 specific HW regs */
1822	1793	m_ex_video_ff[(data & 0xfe) >> 1] = data & 1;
r241793	r241794
1916	1887
1917	1888	READ8_MEMBER(pc9801_state::grcg_gvram_r)
1918	1889	{
1919		return m_pc9801rs_grcg_r(offset & 0x7fff,(offset>>15)+1);
	1890	return upd7220_grcg_r(space, (offset + 0x8000) | (m_vram_bank << 17), mem_mask);
1920	1891	}
1921	1892
1922	1893	WRITE8_MEMBER(pc9801_state::grcg_gvram_w)
1923	1894	{
1924		m_pc9801rs_grcg_w(offset & 0x7fff,(offset>>15)+1,data);
	1895	upd7220_grcg_w(space, (offset + 0x8000) | (m_vram_bank << 17), data, mem_mask);
1925	1896	}
1926	1897
1927	1898	READ8_MEMBER(pc9801_state::grcg_gvram0_r)
1928	1899	{
1929		return m_pc9801rs_grcg_r(offset & 0x7fff,0);
	1900	return upd7220_grcg_r(space, offset | (m_vram_bank << 17), mem_mask);
1930	1901	}
1931	1902
1932	1903	WRITE8_MEMBER(pc9801_state::grcg_gvram0_w)
1933	1904	{
1934		m_pc9801rs_grcg_w(offset & 0x7fff,0,data);
	1905	upd7220_grcg_w(space, offset | (m_vram_bank << 17), data, mem_mask);
1935	1906	}
1936	1907
1937	1908	static ADDRESS_MAP_START( pc9801ux_map, AS_PROGRAM, 16, pc9801_state )
1938	1909	AM_RANGE(0x000000, 0x09ffff) AM_RAMBANK("wram")
1939		AM_RANGE(0x0a0000, 0x0a3fff) AM_READWRITE8(pc9801_tvram_r, pc9801_tvram_w, 0xffff)
	1910	AM_RANGE(0x0a0000, 0x0a3fff) AM_READWRITE8(tvram_r, tvram_w, 0xffff)
1940	1911	AM_RANGE(0x0a4000, 0x0a4fff) AM_READWRITE8(pc9801rs_knjram_r, pc9801rs_knjram_w, 0xffff)
1941	1912	AM_RANGE(0x0a8000, 0x0bffff) AM_READWRITE8(grcg_gvram_r, grcg_gvram_w, 0xffff)
1942	1913	AM_RANGE(0x0e0000, 0x0e7fff) AM_READWRITE8(grcg_gvram0_r,grcg_gvram0_w, 0xffff)
r241793	r241794
1947	1918	ADDRESS_MAP_UNMAP_HIGH
1948	1919	AM_RANGE(0x0050, 0x0057) AM_NOP // 2dd ppi?
1949	1920	AM_RANGE(0x005c, 0x005f) AM_READ(pc9821_timestamp_r) AM_WRITENOP // artic
1950		AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffff) //mode FF / <undefined>
	1921	AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0x00ff) //mode FF / <undefined>
1951	1922	AM_RANGE(0x0070, 0x007f) AM_READWRITE8(grcg_r,      grcg_w,      0x00ff) //display registers "GRCG" / i8253 pit
1952	1923	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
1953	1924	AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,        pc9801rs_a0_w,      0xffff) //upd7220 bitmap ports / display registers
1954	1925	AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffff)
1955	1926	AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
1956		AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffff)
	1927	AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(a20_ctrl_r,      a20_ctrl_w,      0x00ff)
1957	1928	AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffff)
1958	1929	AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffff) //ROM/RAM bank
1959	1930	AM_RANGE(0x3fd8, 0x3fdf) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00)
r241793	r241794
1988	1959
1989	1960	WRITE8_MEMBER(pc9801_state::pc9821_video_ff_w)
1990	1961	{
1991		if(offset == 2)
	1962	if(offset == 1)
1992	1963	{
1993	1964	m_ex_video_ff[(data & 0xfe) >> 1] = data & 1;
1994	1965
r241793	r241794
2132	2103	{
2133	2104	UINT8 res;
2134	2105
2135		if(offset)
2136		return 0xff;
2137
2138	2106	res = 0;
2139	2107
2140	2108	switch(m_ext2_ff)
r241793	r241794
2149	2117
2150	2118	WRITE8_MEMBER(pc9801_state::pc9821_ext2_video_ff_w)
2151	2119	{
2152		if(offset == 0)
2153		m_ext2_ff = data;
	2120	m_ext2_ff = data;
2154	2121	}
2155	2122
2156	2123	/*READ8_MEMBER(pc9801_state::winram_r)
r241793	r241794
2168	2135	static ADDRESS_MAP_START( pc9821_map, AS_PROGRAM, 32, pc9801_state )
2169	2136	AM_RANGE(0x00000000, 0x0009ffff) AM_RAMBANK("wram")
2170	2137	//AM_RANGE(0x00080000, 0x0009ffff) AM_READWRITE8(winram_r, winram_w, 0xffffffff)
2171		AM_RANGE(0x000a0000, 0x000a3fff) AM_READWRITE8(pc9801_tvram_r, pc9801_tvram_w, 0xffffffff)
	2138	AM_RANGE(0x000a0000, 0x000a3fff) AM_READWRITE8(tvram_r, tvram_w, 0xffffffff)
2172	2139	AM_RANGE(0x000a4000, 0x000a4fff) AM_READWRITE8(pc9801rs_knjram_r, pc9801rs_knjram_w, 0xffffffff)
2173	2140	AM_RANGE(0x000a8000, 0x000bffff) AM_READWRITE8(grcg_gvram_r, grcg_gvram_w, 0xffffffff)
2174	2141	AM_RANGE(0x000cc000, 0x000cdfff) AM_ROM AM_REGION("sound_bios",0) //sound BIOS
r241793	r241794
2193	2160	AM_RANGE(0x005c, 0x005f) AM_READ16(pc9821_timestamp_r,0xffffffff) AM_WRITENOP // artic
2194	2161	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("upd7220_chr", upd7220_device, read, write, 0x00ff00ff) //upd7220 character ports / <undefined>
2195	2162	AM_RANGE(0x0064, 0x0067) AM_WRITE8(vrtc_mask_w, 0x000000ff)
2196		AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9821_video_ff_w,  0xffffffff) //mode FF / <undefined>
	2163	AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9821_video_ff_w,  0x00ff00ff) //mode FF / <undefined>
2197	2164	AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00ff00)
2198	2165	AM_RANGE(0x0070, 0x007f) AM_READWRITE8(grcg_r,      grcg_w,      0x00ff00ff) //display registers "GRCG" / i8253 pit
2199	2166	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
r241793	r241794
2204	2171	AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffffffff)
2205	2172	AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
2206	2173	//  AM_RANGE(0x00d8, 0x00df) AMD98 (sound?) board
2207		AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffffffff)
	2174	AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(a20_ctrl_r,      a20_ctrl_w,      0x00ff00ff)
2208	2175	//  AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r,       pc9801_opn_w,       0xffffffff) //ym2203 opn / <undefined>
2209	2176	//  AM_RANGE(0x018c, 0x018f) YM2203 OPN extended ports / <undefined>
2210	2177	AM_RANGE(0x0430, 0x0433) AM_READ8(ide_hack_r, 0x000000ff)
r241793	r241794
2217	2184	AM_RANGE(0x0640, 0x064f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
2218	2185	AM_RANGE(0x0740, 0x074f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
2219	2186	//  AM_RANGE(0x08e0, 0x08ea) <undefined> / EMM SIO registers
2220		AM_RANGE(0x09a0, 0x09a3) AM_READWRITE8(pc9821_ext2_video_ff_r, pc9821_ext2_video_ff_w, 0xffffffff) // GDC extended register r/w
	2187	AM_RANGE(0x09a0, 0x09a3) AM_READWRITE8(pc9821_ext2_video_ff_r, pc9821_ext2_video_ff_w, 0x000000ff) // GDC extended register r/w
2221	2188	//  AM_RANGE(0x09a8, 0x09a8) GDC 31KHz register r/w
2222	2189	//  AM_RANGE(0x0c07, 0x0c07) EPSON register w
2223	2190	//  AM_RANGE(0x0c03, 0x0c03) EPSON register 0 r
r241793	r241794
2561	2528	*
2562	2529	****************************************/
2563	2530
2564		WRITE_LINE_MEMBER(pc9801_state::pc9801_dma_hrq_changed)
	2531	WRITE_LINE_MEMBER(pc9801_state::dma_hrq_changed)
2565	2532	{
2566	2533	m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
2567	2534
r241793	r241794
2570	2537	//  logerror("%02x HLDA\n",state);
2571	2538	}
2572	2539
2573		WRITE_LINE_MEMBER(pc9801_state::pc9801_tc_w )
	2540	WRITE_LINE_MEMBER(pc9801_state::tc_w )
2574	2541	{
2575	2542	/* floppy terminal count */
2576	2543	m_fdc_2hd->tc_w(state);
r241793	r241794
2580	2547	//  logerror("TC %02x\n",state);
2581	2548	}
2582	2549
2583		READ8_MEMBER(pc9801_state::pc9801_dma_read_byte)
	2550	READ8_MEMBER(pc9801_state::dma_read_byte)
2584	2551	{
2585	2552	address_space &program = m_maincpu->space(AS_PROGRAM);
2586	2553	offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
r241793	r241794
2591	2558	}
2592	2559
2593	2560
2594		WRITE8_MEMBER(pc9801_state::pc9801_dma_write_byte)
	2561	WRITE8_MEMBER(pc9801_state::dma_write_byte)
2595	2562	{
2596	2563	address_space &program = m_maincpu->space(AS_PROGRAM);
2597	2564	offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
r241793	r241794
2606	2573	if (!state) m_dack = channel;
2607	2574	}
2608	2575
2609		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack0_w){ /*logerror("%02x 0\n",state);*/ set_dma_channel(0, state); }
2610		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack1_w){ /*logerror("%02x 1\n",state);*/ set_dma_channel(1, state); }
2611		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack2_w){ /*logerror("%02x 2\n",state);*/ set_dma_channel(2, state); }
2612		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack3_w){ /*logerror("%02x 3\n",state);*/ set_dma_channel(3, state); }
	2576	WRITE_LINE_MEMBER(pc9801_state::dack0_w){ /*logerror("%02x 0\n",state);*/ set_dma_channel(0, state); }
	2577	WRITE_LINE_MEMBER(pc9801_state::dack1_w){ /*logerror("%02x 1\n",state);*/ set_dma_channel(1, state); }
	2578	WRITE_LINE_MEMBER(pc9801_state::dack2_w){ /*logerror("%02x 2\n",state);*/ set_dma_channel(2, state); }
	2579	WRITE_LINE_MEMBER(pc9801_state::dack3_w){ /*logerror("%02x 3\n",state);*/ set_dma_channel(3, state); }
2613	2580
2614	2581	/*
2615	2582	ch1 cs-4231a
r241793	r241794
2981	2948	MCFG_PIT8253_OUT2_HANDLER(WRITELINE(pc9801_state, write_uart_clock))
2982	2949
2983	2950	MCFG_DEVICE_ADD("i8237", AM9517A, 5000000) // unknown clock, TODO: check channels 0 - 1
2984		MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc9801_state, pc9801_dma_hrq_changed))
2985		MCFG_I8237_OUT_EOP_CB(WRITELINE(pc9801_state, pc9801_tc_w))
2986		MCFG_I8237_IN_MEMR_CB(READ8(pc9801_state, pc9801_dma_read_byte))
2987		MCFG_I8237_OUT_MEMW_CB(WRITE8(pc9801_state, pc9801_dma_write_byte))
	2951	MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc9801_state, dma_hrq_changed))
	2952	MCFG_I8237_OUT_EOP_CB(WRITELINE(pc9801_state, tc_w))
	2953	MCFG_I8237_IN_MEMR_CB(READ8(pc9801_state, dma_read_byte))
	2954	MCFG_I8237_OUT_MEMW_CB(WRITE8(pc9801_state, dma_write_byte))
2988	2955	MCFG_I8237_IN_IOR_2_CB(DEVREAD8("upd765_2hd", upd765a_device, mdma_r))
2989	2956	MCFG_I8237_OUT_IOW_2_CB(DEVWRITE8("upd765_2hd", upd765a_device, mdma_w))
2990		MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc9801_state, pc9801_dack0_w))
2991		MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc9801_state, pc9801_dack1_w))
2992		MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc9801_state, pc9801_dack2_w))
2993		MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc9801_state, pc9801_dack3_w))
	2957	MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc9801_state, dack0_w))
	2958	MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc9801_state, dack1_w))
	2959	MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc9801_state, dack2_w))
	2960	MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc9801_state, dack3_w))
2994	2961	MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE("maincpu", 0), VCC, READ8(pc9801_state,get_slave_ack) )
2995	2962	MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir7_w), GND, NULL ) // TODO: Check ir7_w
2996	2963
r241793	r241794
3261	3228	/*
3262	3229	RX - 80286 12 (no V30?)
3263	3230
3264		IPL is from ux
	3231	The bios is from a 386 model not an RX
3265	3232	*/
3266	3233
3267	3234	ROM_START( pc9801rx )
3268	3235	ROM_REGION( 0x60000, "ipl", ROMREGION_ERASEFF )
3269		ROM_LOAD( "itf_ux.rom",  0x18000, 0x08000, BAD_DUMP CRC(c7942563) SHA1(61bb210d64c7264be939b11df1e9cd14ffeee3c9) )
	3236	ROM_LOAD( "itf_rs.rom",  0x18000, 0x08000, BAD_DUMP CRC(c1815325) SHA1(a2fb11c000ed7c976520622cfb7940ed6ddc904e) )
3270	3237	ROM_LOAD( "bios_rx.rom", 0x28000, 0x018000, BAD_DUMP CRC(0a682b93) SHA1(76a7360502fa0296ea93b4c537174610a834d367) )
	3238	// fix csum
	3239	ROM_FILL(0x3fffe, 1, 0x0d)
3271	3240
3272	3241	ROM_REGION( 0x10000, "sound_bios", 0 )
3273	3242	ROM_LOAD( "sound_rx.rom",    0x000000, 0x004000, CRC(fe9f57f2) SHA1(d5dbc4fea3b8367024d363f5351baecd6adcd8ef) )
r241793	r241794
3276	3245	ROM_LOAD( "font_rx.rom",     0x000000, 0x046800, CRC(456d9fc7) SHA1(78ba9960f135372825ab7244b5e4e73a810002ff) )
3277	3246
3278	3247	LOAD_KANJI_ROMS
3279		//   LOAD_IDE_ROM
	3248	LOAD_IDE_ROM
3280	3249	ROM_END
3281	3250
3282	3251	/*
r241793	r241794
3611	3580	COMP( 1989, pc9801rs,  0       ,0,     pc9801rs, pc9801rs, pc9801_state, pc9801_kanji, "Nippon Electronic Company",   "PC-9801RS", GAME_NOT_WORKING | GAME_IMPERFECT_SOUND) //TODO: not sure about the exact model
3612	3581	COMP( 1985, pc9801vm,  pc9801ux,0,     pc9801vm, pc9801rs, pc9801_state, pc9801_kanji, "Nippon Electronic Company",   "PC-9801VM", GAME_NOT_WORKING | GAME_IMPERFECT_SOUND)
3613	3582	COMP( 1987, pc9801ux,  0       ,0,     pc9801ux, pc9801rs, pc9801_state, pc9801_kanji, "Nippon Electronic Company",   "PC-9801UX", GAME_NOT_WORKING | GAME_IMPERFECT_SOUND)
3614		COMP( 1988, pc9801rx,  pc9801ux,0,     pc9801ux, pc9801rs, pc9801_state, pc9801_kanji, "Nippon Electronic Company",   "PC-9801RX", GAME_NOT_WORKING | GAME_IMPERFECT_SOUND)
	3583	COMP( 1988, pc9801rx,  pc9801rs,0,     pc9801rs, pc9801rs, pc9801_state, pc9801_kanji, "Nippon Electronic Company",   "PC-9801RX", GAME_NOT_WORKING | GAME_IMPERFECT_SOUND)
3615	3584	COMP( 1993, pc9801bx2, pc9801rs,0,     pc9801bx2,pc9801rs, pc9801_state, pc9801_kanji, "Nippon Electronic Company",   "PC-9801BX2/U2", GAME_NOT_WORKING | GAME_IMPERFECT_SOUND)
3616	3585	COMP( 1994, pc9821,    0,       0,     pc9821,   pc9821,   pc9801_state, pc9801_kanji, "Nippon Electronic Company",   "PC-9821 (98MATE)",  GAME_NOT_WORKING | GAME_IMPERFECT_SOUND) //TODO: not sure about the exact model
3617	3586	COMP( 1993, pc9821as,  pc9821,  0,     pc9821,   pc9821,   pc9801_state, pc9801_kanji, "Nippon Electronic Company",   "PC-9821 (98MATE A)", GAME_NOT_WORKING | GAME_IMPERFECT_SOUND)

https://github.com/mamedev/mame/commit/7a3ea7ca787ba8d5c01ee4c3332f00cdf65ab9b5

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