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r33275 Friday 7th November, 2014 at 21:47:35 UTC by Carl
(mess) pc9801: cleanup and refactor(nw)

[src/mess/drivers]

pc9801.c

trunk/src/mess/drivers/pc9801.c

r241786	r241787
18	18	- some later SWs put "Invalid command byte 05" (Absolutely Mahjong on Epson logo)
19	19	- Basic games are mostly untested, but I think that upd7220 fails on those (Adventureland, Xevious)
20	20	- investigate on POR bit
21		- PC-9801RS+ should support uPD4990 RTC
	21	- 2dd bios tries to use dma channel 2
22	22
23	23	TODO (PC-9801RS):
24	24	- extra features;
r241786	r241787
29	29	- fix CPU for some clones;
30	30	- "cache error"
31	31	- undumped IDE ROM, kludged to work
32		- slave PIC never enables floppy IRQ (PC=0xffd08)
33	32	- Compatibility is untested;
34	33
35	34	TODO: (PC-486MU)
r241786	r241787
460	459	m_beeper(*this, "beeper"),
461	460	m_ram(*this, RAM_TAG),
462	461	m_gfxdecode(*this, "gfxdecode"),
463		m_palette(*this, "palette")
	462	m_palette(*this, "palette"),
	463	m_screen(*this, "screen")
464	464	{
465	465	}
466	466
r241786	r241787
487	487	optional_device<ram_device> m_ram;
488	488	required_device<gfxdecode_device> m_gfxdecode;
489	489	required_device<palette_device> m_palette;
	490	required_device<screen_device> m_screen;
490	491
491	492	virtual void video_start();
492	493	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
r241786	r241787
554	555	UINT8 m_ext2_ff;
555	556	UINT8 m_sys_type;
556	557
557		DECLARE_WRITE_LINE_MEMBER( keyboard_irq );
558	558	DECLARE_WRITE_LINE_MEMBER( write_uart_clock );
559		DECLARE_READ8_MEMBER(pc9801_xx_r);
560		DECLARE_WRITE8_MEMBER(pc9801_xx_w);
561		DECLARE_READ8_MEMBER(pc9801_00_r);
562		DECLARE_WRITE8_MEMBER(pc9801_00_w);
563		DECLARE_READ8_MEMBER(pc9801_20_r);
564		DECLARE_WRITE8_MEMBER(pc9801_20_w);
565		DECLARE_READ8_MEMBER(pc9801_30_r);
566		DECLARE_WRITE8_MEMBER(pc9801_30_w);
567		DECLARE_READ8_MEMBER(pc9801_40_r);
568		DECLARE_WRITE8_MEMBER(pc9801_40_w);
569		DECLARE_READ8_MEMBER(pc9801_50_r);
570		DECLARE_WRITE8_MEMBER(pc9801_50_w);
571		DECLARE_READ8_MEMBER(pc9801_60_r);
572		DECLARE_WRITE8_MEMBER(pc9801_60_w);
	559	DECLARE_WRITE8_MEMBER(rtc_dmapg_w);
	560	DECLARE_WRITE8_MEMBER(nmi_ctrl_w);
573	561	DECLARE_WRITE8_MEMBER(pc9801_vrtc_mask_w);
574	562	DECLARE_WRITE8_MEMBER(pc9801_video_ff_w);
575		DECLARE_READ8_MEMBER(pc9801_70_r);
576		DECLARE_WRITE8_MEMBER(pc9801_70_w);
577		DECLARE_READ8_MEMBER(pc9801rs_70_r);
578		DECLARE_WRITE8_MEMBER(pc9801rs_70_w);
579		DECLARE_READ8_MEMBER(pc9801_sasi_r);
580		DECLARE_WRITE8_MEMBER(pc9801_sasi_w);
	563	DECLARE_READ8_MEMBER(txt_scrl_r);
	564	DECLARE_WRITE8_MEMBER(txt_scrl_w);
	565	DECLARE_READ8_MEMBER(grcg_r);
	566	DECLARE_WRITE8_MEMBER(grcg_w);
581	567	DECLARE_READ8_MEMBER(pc9801_a0_r);
582	568	DECLARE_WRITE8_MEMBER(pc9801_a0_w);
583	569	DECLARE_READ8_MEMBER(pc9801_fdc_2hd_r);
r241786	r241787
588	574	DECLARE_WRITE8_MEMBER(pc9801_tvram_w);
589	575	DECLARE_READ8_MEMBER(pc9801_gvram_r);
590	576	DECLARE_WRITE8_MEMBER(pc9801_gvram_w);
591		DECLARE_READ8_MEMBER(pc9801_mouse_r);
592		DECLARE_WRITE8_MEMBER(pc9801_mouse_w);
593	577	DECLARE_WRITE8_MEMBER(pc9801rs_mouse_freq_w);
594	578	inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank,int vrambank);
595	579	inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank) { return m_pc9801rs_grcg_r(offset, vbank, m_vram_bank); }
r241786	r241787
626	610	DECLARE_WRITE8_MEMBER(pc9801rs_bank_w);
627	611	DECLARE_READ8_MEMBER(pc9801rs_f0_r);
628	612	DECLARE_WRITE8_MEMBER(pc9801rs_f0_w);
629		DECLARE_READ8_MEMBER(pc9801rs_30_r);
630	613	DECLARE_READ8_MEMBER(pc9801rs_memory_r);
631	614	DECLARE_WRITE8_MEMBER(pc9801rs_memory_w);
632	615	DECLARE_READ8_MEMBER(pc9801rs_soundrom_r);
r241786	r241787
642	625	DECLARE_WRITE8_MEMBER(pc9821_video_ff_w);
643	626	DECLARE_READ8_MEMBER(pc9821_a0_r);
644	627	DECLARE_WRITE8_MEMBER(pc9821_a0_w);
645		DECLARE_READ8_MEMBER(pc9801rs_pit_mirror_r);
646		DECLARE_WRITE8_MEMBER(pc9801rs_pit_mirror_w);
647	628	DECLARE_READ8_MEMBER(pc9801rs_access_ctrl_r);
648	629	DECLARE_WRITE8_MEMBER(pc9801rs_access_ctrl_w);
649	630	DECLARE_WRITE8_MEMBER(pc9801rs_nmi_w);
r241786	r241787
688	669	DECLARE_WRITE8_MEMBER(pc9821_ext_gvram_w);
689	670	DECLARE_READ8_MEMBER(pc9821_window_bank_r);
690	671	DECLARE_WRITE8_MEMBER(pc9821_window_bank_w);
691		DECLARE_READ32_MEMBER(pc9821_timestamp_r);
	672	DECLARE_READ16_MEMBER(pc9821_timestamp_r);
692	673	DECLARE_READ8_MEMBER(pc9821_ext2_video_ff_r);
693	674	DECLARE_WRITE8_MEMBER(pc9821_ext2_video_ff_w);
694	675
r241786	r241787
706	687	DECLARE_MACHINE_START(pc9801bx2);
707	688	DECLARE_MACHINE_START(pc9821);
708	689	DECLARE_MACHINE_START(pc9821ap2);
709
710	690	DECLARE_MACHINE_RESET(pc9801_common);
711	691	DECLARE_MACHINE_RESET(pc9801f);
712	692	DECLARE_MACHINE_RESET(pc9801rs);
r241786	r241787
714	694
715	695	DECLARE_PALETTE_INIT(pc9801);
716	696	INTERRUPT_GEN_MEMBER(pc9801_vrtc_irq);
717		//  DECLARE_INPUT_CHANGED_MEMBER(key_stroke);
718		//  DECLARE_INPUT_CHANGED_MEMBER(shift_stroke);
719	697	DECLARE_READ8_MEMBER(get_slave_ack);
720	698	DECLARE_WRITE_LINE_MEMBER(pc9801_dma_hrq_changed);
721	699	DECLARE_WRITE_LINE_MEMBER(pc9801_tc_w);
r241786	r241787
725	703	DECLARE_WRITE_LINE_MEMBER(pc9801_dack1_w);
726	704	DECLARE_WRITE_LINE_MEMBER(pc9801_dack2_w);
727	705	DECLARE_WRITE_LINE_MEMBER(pc9801_dack3_w);
728		DECLARE_READ8_MEMBER(fdc_2hd_r);
729		DECLARE_WRITE8_MEMBER(fdc_2hd_w);
730		DECLARE_READ8_MEMBER(fdc_2dd_r);
731		DECLARE_WRITE8_MEMBER(fdc_2dd_w);
732	706	DECLARE_READ8_MEMBER(ppi_sys_portc_r);
733	707	DECLARE_WRITE8_MEMBER(ppi_sys_portc_w);
734	708	DECLARE_READ8_MEMBER(ppi_fdd_porta_r);
r241786	r241787
753	727	}m_mouse;
754	728	TIMER_DEVICE_CALLBACK_MEMBER( mouse_irq_cb );
755	729
756		void pc9801_fdc_2hd_update_ready(floppy_image_device *, int);
757	730	inline UINT32 m_calc_grcg_addr(int i,UINT32 offset,int vrambank);
758	731
759	732	DECLARE_DRIVER_INIT(pc9801_kanji);
r241786	r241787
818	791	res_x = x + xi;
819	792	res_y = y;
820	793
821		if(!machine().first_screen()->visible_area().contains(res_x, res_y*2+0))
	794	if(!m_screen->visible_area().contains(res_x, res_y*2+0))
822	795	return;
823	796
824	797	pen = m_ext_gvram[(address*8+xi)+(m_vram_disp*0x40000)];
r241786	r241787
843	816
844	817	if(interlace_on)
845	818	{
846		if(machine().first_screen()->visible_area().contains(res_x, res_y*2+0))
	819	if(m_screen->visible_area().contains(res_x, res_y*2+0))
847	820	bitmap.pix32(res_y*2+0, res_x) = palette[pen + colors16_mode];
848	821	/* TODO: it looks like that PC-98xx can only display even lines ... */
849		if(machine().first_screen()->visible_area().contains(res_x, res_y*2+1))
	822	if(m_screen->visible_area().contains(res_x, res_y*2+1))
850	823	bitmap.pix32(res_y*2+1, res_x) = palette[pen + colors16_mode];
851	824	}
852	825	else
r241786	r241787
932	905	res_x = ((x+kanji_lr)*8+xi) * (m_video_ff[WIDTH40_REG]+1);
933	906	res_y = y+yi - (m_txt_scroll_reg[3] & 0xf);
934	907
935		if(!machine().first_screen()->visible_area().contains(res_x, res_y))
	908	if(!m_screen->visible_area().contains(res_x, res_y))
936	909	continue;
937	910
938	911	tile_data = 0;
r241786	r241787
973	946	if(v_line)  { tile_data|=8; }
974	947
975	948	/* TODO: proper blink rate for these two */
976		if(cursor_on && cursor_addr == tile_addr && machine().first_screen()->frame_number() & 0x10)
	949	if(cursor_on && cursor_addr == tile_addr && m_screen->frame_number() & 0x10)
977	950	tile_data^=0xff;
978	951
979		if(blink && machine().first_screen()->frame_number() & 0x10)
	952	if(blink && m_screen->frame_number() & 0x10)
980	953	tile_data^=0xff;
981	954
982	955	if(yi >= char_size)
r241786	r241787
989	962
990	963	if(m_video_ff[WIDTH40_REG])
991	964	{
992		if(!machine().first_screen()->visible_area().contains(res_x+1, res_y))
	965	if(!m_screen->visible_area().contains(res_x+1, res_y))
993	966	continue;
994	967
995	968	if(pen != -1)
r241786	r241787
1002	975	}
1003	976
1004	977
1005		#if 0
1006		READ8_MEMBER(pc9801_state::pc9801_xx_r)
	978	WRITE8_MEMBER(pc9801_state::rtc_dmapg_w)
1007	979	{
1008	980	if((offset & 1) == 0)
1009	981	{
1010		printf("Read to undefined port [%02x]\n",offset+0xxx);
1011		return 0xff;
1012		}
1013		else // odd
1014		{
1015		printf("Read to undefined port [%02x]\n",offset+0xxx);
1016		return 0xff;
1017		}
1018		}
1019
1020		WRITE8_MEMBER(pc9801_state::pc9801_xx_w)
1021		{
1022		if((offset & 1) == 0)
1023		{
1024		printf("Write to undefined port [%02x] <- %02x\n",offset+0xxx,data);
1025		}
1026		else // odd
1027		{
1028		printf("Write to undefined port [%02x] <- %02x\n",offset+0xxx,data);
1029		}
1030		}
1031
1032		#endif
1033
1034		READ8_MEMBER(pc9801_state::pc9801_00_r)
1035		{
1036		if((offset & 1) == 0)
1037		{
1038		if(offset & 0x14)
1039		printf("Read to undefined port [%02x]\n",offset+0x00);
1040		else
1041		return ((offset & 8) ? m_pic2 : m_pic1)->read(space, (offset & 2) >> 1);
1042		}
1043		else // odd
1044		{
1045		return m_dmac->read(space, (offset & 0x1e) >> 1, 0xff);
1046		}
1047
1048		return 0xff;
1049		}
1050
1051		WRITE8_MEMBER(pc9801_state::pc9801_00_w)
1052		{
1053		if((offset & 1) == 0)
1054		{
1055		if(offset & 0x14)
1056		printf("Write to undefined port [%02x] <- %02x\n",offset+0x00,data);
1057		else
1058		((offset & 8) ? m_pic2 : m_pic1)->write(space, (offset & 2) >> 1, data);
1059		}
1060		else // odd
1061		{
1062		m_dmac->write(space, (offset & 0x1e) >> 1, data, 0xff);
1063		}
1064		}
1065
1066		READ8_MEMBER(pc9801_state::pc9801_20_r)
1067		{
1068		if((offset & 1) == 0)
1069		{
1070	982	if(offset == 0)
1071		printf("Read to RTC port [%02x]\n",offset+0x20);
1072		else
1073		printf("Read to undefined port [%02x]\n",offset+0x20);
1074
1075		return 0xff;
1076		}
1077		else // odd
1078		{
1079		printf("Read to undefined port [%02x]\n",offset+0x20);
1080		return 0xff;
1081		}
1082		}
1083
1084		WRITE8_MEMBER(pc9801_state::pc9801_20_w)
1085		{
1086		if((offset & 1) == 0)
1087		{
1088		if(offset == 0)
1089	983	{
1090	984	m_rtc->c0_w((data & 0x01) >> 0);
1091	985	m_rtc->c1_w((data & 0x02) >> 1);
r241786	r241787
1094	988	m_rtc->clk_w((data & 0x10) >> 4);
1095	989	m_rtc->data_in_w(((data & 0x20) >> 5));
1096	990	if(data & 0xc0)
1097		printf("RTC write to undefined bits %02x\n",data & 0xc0);
	991	logerror("RTC write to undefined bits %02x\n",data & 0xc0);
1098	992	}
1099	993	else
1100		printf("Write to undefined port [%02x] <- %02x\n",offset+0x20,data);
	994	logerror("Write to undefined port [%02x] <- %02x\n",offset+0x20,data);
1101	995	}
1102	996	else // odd
1103	997	{
1104		//      printf("Write to DMA bank register %d %02x\n",((offset >> 1)+1) & 3,data);
	998	//      logerror("Write to DMA bank register %d %02x\n",((offset >> 1)+1) & 3,data);
1105	999	m_dma_offset[((offset >> 1)+1) & 3] = data & 0x0f;
1106	1000	}
1107	1001	}
1108	1002
1109		READ8_MEMBER(pc9801_state::pc9801_30_r)
	1003	WRITE8_MEMBER(pc9801_state::nmi_ctrl_w)
1110	1004	{
1111		if((offset & 1) == 0)
1112		{
1113		if(offset & 4)
1114		printf("Read to undefined port [%02x]\n",offset+0x30);
1115		else
1116		printf("Read to RS-232c port [%02x]\n",offset+0x30);
1117
1118		return 0xff;
1119		}
1120		else // odd
1121		{
1122		return machine().device<i8255_device>("ppi8255_sys")->read(space, (offset & 6) >> 1);
1123		}
	1005	m_nmi_ff = (offset & 2) >> 1;
1124	1006	}
1125	1007
1126		WRITE8_MEMBER(pc9801_state::pc9801_30_w)
1127		{
1128		if((offset & 1) == 0)
1129		{
1130		if(offset & 4)
1131		printf("Write to undefined port [%02x] %02x\n",offset+0x30,data);
1132		else
1133		printf("Write to RS-232c port [%02x] %02x\n",offset+0x30,data);
1134		}
1135		else // odd
1136		{
1137		machine().device<i8255_device>("ppi8255_sys")->write(space, (offset & 6) >> 1,data);
1138		}
1139		}
1140
1141		READ8_MEMBER(pc9801_state::pc9801_40_r)
1142		{
1143		if((offset & 1) == 0)
1144		{
1145		return machine().device<i8255_device>("ppi8255_prn")->read(space, (offset & 6) >> 1);
1146		}
1147		else // odd
1148		{
1149		if(offset & 4)
1150		printf("Read to undefined port [%02x]\n",offset+0x40);
1151		else
1152		{
1153		//printf("Read to 8251 kbd port [%02x] %08x\n",offset+0x40,m_maincpu->pc());
1154		if(offset == 1)
1155		{
1156		return m_keyb->rx_r(space,0);
1157		}
1158
1159		return 1 | 4 | 2;
1160		}
1161		}
1162
1163		return 0xff;
1164		}
1165
1166		WRITE8_MEMBER(pc9801_state::pc9801_40_w)
1167		{
1168		if((offset & 1) == 0)
1169		{
1170		machine().device<i8255_device>("ppi8255_prn")->write(space, (offset & 6) >> 1,data);
1171		}
1172		else // odd
1173		{
1174		if(offset & 4)
1175		printf("Write to undefined port [%02x] <- %02x\n",offset+0x40,data);
1176		else
1177		{
1178		if(offset == 1)
1179		{
1180		m_keyb->tx_w(space,0,data);
1181		return;
1182		}
1183		//printf("Write to 8251 kbd port [%02x] <- %02x\n",offset+0x40,data);
1184		}
1185		}
1186		}
1187
1188		READ8_MEMBER(pc9801_state::pc9801_50_r)
1189		{
1190		if((offset & 1) == 0)
1191		{
1192		if(offset & 4)
1193		printf("Read to undefined port [%02x]\n",offset+0x50);
1194		else
1195		printf("Read to NMI FF port [%02x]\n",offset+0x50);
1196
1197		return 0xff;
1198		}
1199		else // odd
1200		{
1201		return machine().device<i8255_device>("ppi8255_fdd")->read(space, (offset & 6) >> 1);
1202		}
1203		}
1204
1205		WRITE8_MEMBER(pc9801_state::pc9801_50_w)
1206		{
1207		if((offset & 1) == 0)
1208		{
1209		if(offset & 4)
1210		printf("Write to undefined port [%02x] %02x\n",offset+0x50,data);
1211		else
1212		m_nmi_ff = (offset & 2) >> 1;
1213
1214		}
1215		else // odd
1216		{
1217		machine().device<i8255_device>("ppi8255_fdd")->write(space, (offset & 6) >> 1,data);
1218		}
1219		}
1220
1221		READ8_MEMBER(pc9801_state::pc9801_60_r)
1222		{
1223		if((offset & 1) == 0)
1224		{
1225		return m_hgdc1->read(space, (offset & 2) >> 1); // upd7220 character port
1226		}
1227		else // odd
1228		{
1229		printf("Read to undefined port [%02x]\n",offset+0x60);
1230		return 0xff;
1231		}
1232		}
1233
1234		WRITE8_MEMBER(pc9801_state::pc9801_60_w)
1235		{
1236		if((offset & 1) == 0)
1237		{
1238		m_hgdc1->write(space, (offset & 2) >> 1,data); // upd7220 character port
1239		}
1240		else // odd
1241		{
1242		printf("Write to undefined port [%02x] <- %02x\n",offset+0x60,data);
1243		}
1244		}
1245
1246	1008	WRITE8_MEMBER(pc9801_state::pc9801_vrtc_mask_w)
1247	1009	{
1248	1010	if((offset & 1) == 0)
r241786	r241787
1251	1013	}
1252	1014	else // odd
1253	1015	{
1254		printf("Write to undefined port [%02x] <- %02x\n",offset+0x64,data);
	1016	logerror("Write to undefined port [%02x] <- %02x\n",offset+0x64,data);
1255	1017	}
1256	1018	}
1257	1019
r241786	r241787
1272	1034	case 1:
1273	1035	m_gfx_ff = 1;
1274	1036	if(data & 1)
1275		printf("Graphic f/f actually enabled!\n");
	1037	logerror("Graphic f/f actually enabled!\n");
1276	1038	break;
1277	1039	case 4:
1278	1040	if(m_gfx_ff)
r241786	r241787
1298	1060	"Display ON"        // 7
1299	1061	};
1300	1062
1301		printf("Write to video FF register %s -> %02x\n",video_ff_regnames[(data & 0x0e) >> 1],data & 1);
	1063	logerror("Write to video FF register %s -> %02x\n",video_ff_regnames[(data & 0x0e) >> 1],data & 1);
1302	1064	}
1303	1065	}
1304	1066	else // odd
1305	1067	{
1306		//printf("Write to undefined port [%02x] <- %02x\n",offset+0x68,data);
	1068	//logerror("Write to undefined port [%02x] <- %02x\n",offset+0x68,data);
1307	1069	}
1308	1070	}
1309	1071
1310	1072
1311		READ8_MEMBER(pc9801_state::pc9801_70_r)
	1073	READ8_MEMBER(pc9801_state::txt_scrl_r)
1312	1074	{
1313		if((offset & 1) == 0)
1314		{
1315		//printf("Read to display register [%02x]\n",offset+0x70);
1316		/* TODO: ok? */
1317		return m_txt_scroll_reg[offset >> 1];
1318		}
1319		else // odd
1320		{
1321		if(offset & 0x08)
1322		printf("Read to undefined port [%02x]\n",offset+0x70);
1323		else
1324		return m_pit8253->read(space, (offset & 6) >> 1);
1325		}
1326
1327		return 0xff;
	1075	//logerror("Read to display register [%02x]\n",offset+0x70);
	1076	/* TODO: ok? */
	1077	return m_txt_scroll_reg[offset >> 1];
1328	1078	}
1329	1079
1330		WRITE8_MEMBER(pc9801_state::pc9801_70_w)
	1080	WRITE8_MEMBER(pc9801_state::txt_scrl_w)
1331	1081	{
1332		if((offset & 1) == 0)
1333		{
1334		//      printf("Write to display register [%02x] %02x\n",offset+0x70,data);
1335		m_txt_scroll_reg[offset >> 1] = data;
	1082	//logerror("Write to display register [%02x] %02x\n",offset+0x70,data);
	1083	m_txt_scroll_reg[offset >> 1] = data;
1336	1084
1337		//popmessage("%02x %02x %02x %02x",m_txt_scroll_reg[0],m_txt_scroll_reg[1],m_txt_scroll_reg[2],m_txt_scroll_reg[3]);
1338		}
1339		else // odd
1340		{
1341		if(offset < 0x08)
1342		m_pit8253->write(space, (offset & 6) >> 1, data);
1343		//else
1344		//  printf("Write to undefined port [%02x] <- %02x\n",offset+0x70,data);
1345		}
	1085	//popmessage("%02x %02x %02x %02x",m_txt_scroll_reg[0],m_txt_scroll_reg[1],m_txt_scroll_reg[2],m_txt_scroll_reg[3]);
1346	1086	}
1347	1087
1348		READ8_MEMBER(pc9801_state::pc9801_sasi_r)
1349		{
1350		if((offset & 1) == 0)
1351		{
1352		//printf("Read to SASI port [%02x]\n",offset+0x80);
1353		return 0x20;
1354		}
1355		else // odd
1356		{
1357		printf("Read to undefined port [%02x]\n",offset+0x80);
1358		return 0xff;
1359		}
1360		}
1361
1362		WRITE8_MEMBER(pc9801_state::pc9801_sasi_w)
1363		{
1364		if((offset & 1) == 0)
1365		{
1366		//printf("Write to SASI port [%02x] <- %02x\n",offset+0x80,data);
1367		}
1368		else // odd
1369		{
1370		//printf("Write to undefined port [%02x] <- %02x\n",offset+0xxx,data);
1371		}
1372		}
1373
1374
1375	1088	READ8_MEMBER(pc9801_state::pc9801_a0_r)
1376	1089	{
1377	1090	if((offset & 1) == 0)
r241786	r241787
1412	1125	}
1413	1126	}
1414	1127
1415		printf("Read to undefined port [%02x]\n",offset+0xa0);
	1128	logerror("Read to undefined port [%02x]\n",offset+0xa0);
1416	1129	return 0xff;
1417	1130	}
1418	1131	}
r241786	r241787
1452	1165	return;
1453	1166	}
1454	1167	default:
1455		printf("Write to undefined port [%02x] <- %02x\n",offset+0xa0,data);
	1168	logerror("Write to undefined port [%02x] <- %02x\n",offset+0xa0,data);
1456	1169	return;
1457	1170	}
1458	1171	}
r241786	r241787
1467	1180	m_font_addr = ((data & 0x7f) << 8) | (m_font_addr & 0xff);
1468	1181	return;
1469	1182	case 0x05:
1470		//printf("%02x\n",data);
	1183	//logerror("%02x\n",data);
1471	1184	m_font_line = ((data & 0x0f) << 1);
1472	1185	m_font_lr = ((data & 0x20) >> 5) ^ 1;
1473	1186	return;
r241786	r241787
1478	1191	pcg_offset = m_font_addr << 5;
1479	1192	pcg_offset|= m_font_line;
1480	1193	pcg_offset|= m_font_lr;
1481		//printf("%04x %02x %02x %08x\n",m_font_addr,m_font_line,m_font_lr,pcg_offset);
	1194	//logerror("%04x %02x %02x %08x\n",m_font_addr,m_font_line,m_font_lr,pcg_offset);
1482	1195	if((m_font_addr & 0xff00) == 0x5600 || (m_font_addr & 0xff00) == 0x5700)
1483	1196	{
1484	1197	m_kanji_rom[pcg_offset] = data;
r241786	r241787
1488	1201	}
1489	1202	}
1490	1203
1491		//printf("Write to undefined port [%02x) <- %02x\n",offset+0xa0,data);
	1204	//logerror("Write to undefined port [%02x) <- %02x\n",offset+0xa0,data);
1492	1205	}
1493	1206	}
1494	1207
r241786	r241787
1504	1217	{
1505	1218	switch(offset & 6)
1506	1219	{
1507		case 0: return machine().device<upd765a_device>("upd765_2hd")->msr_r(space, 0, 0xff);
1508		case 2: return machine().device<upd765a_device>("upd765_2hd")->fifo_r(space, 0, 0xff);
	1220	case 0: return m_fdc_2hd->msr_r(space, 0, 0xff);
	1221	case 2: return m_fdc_2hd->fifo_r(space, 0, 0xff);
1509	1222	case 4: return 0x5f; //unknown port meaning
1510	1223	}
1511	1224	}
r241786	r241787
1516	1229	case 1: return m_sio->data_r(space, 0);
1517	1230	case 3: return m_sio->status_r(space, 0);
1518	1231	}
1519		printf("Read to undefined port [%02x]\n",offset+0x90);
	1232	logerror("Read to undefined port [%02x]\n",offset+0x90);
1520	1233	return 0xff;
1521	1234	}
1522	1235
1523	1236	return 0xff;
1524	1237	}
1525	1238
1526		void pc9801_state::pc9801_fdc_2hd_update_ready(floppy_image_device *, int)
1527		{
1528		bool ready = m_fdc_2hd_ctrl & 0x40;
1529		floppy_image_device *floppy;
1530		floppy = machine().device<floppy_connector>("upd765_2hd:0")->get_device();
1531		if(floppy && ready)
1532		ready = floppy->ready_r();
1533		floppy = machine().device<floppy_connector>("upd765_2hd:1")->get_device();
1534		if(floppy && ready)
1535		ready = floppy->ready_r();
1536
1537		m_fdc_2hd->ready_w(ready);
1538		}
1539
1540	1239	WRITE8_MEMBER(pc9801_state::pc9801_fdc_2hd_w)
1541	1240	{
1542	1241	if((offset & 1) == 0)
1543	1242	{
1544	1243	switch(offset & 6)
1545	1244	{
1546		case 0: printf("Write to undefined port [%02x] <- %02x\n",offset+0x90,data); return;
1547		case 2: machine().device<upd765a_device>("upd765_2hd")->fifo_w(space, 0, data, 0xff); return;
	1245	case 0: logerror("Write to undefined port [%02x] <- %02x\n",offset+0x90,data); return;
	1246	case 2: m_fdc_2hd->fifo_w(space, 0, data, 0xff); return;
1548	1247	case 4:
1549		printf("%02x ctrl\n",data);
	1248	//logerror("%02x ctrl\n",data);
1550	1249	if(((m_fdc_2hd_ctrl & 0x80) == 0) && (data & 0x80))
1551		machine().device<upd765a_device>("upd765_2hd")->reset();
	1250	m_fdc_2hd->soft_reset();
1552	1251
1553	1252	m_fdc_2hd_ctrl = data;
1554		pc9801_fdc_2hd_update_ready(NULL, 0);
1555	1253
1556		machine().device<floppy_connector>("upd765_2hd:0")->get_device()->mon_w(data & 0x40 ? ASSERT_LINE : CLEAR_LINE);
1557		machine().device<floppy_connector>("upd765_2hd:1")->get_device()->mon_w(data & 0x40 ? ASSERT_LINE : CLEAR_LINE);
	1254	if(data & 0x40)
	1255	{
	1256	m_fdc_2hd->set_ready_line_connected(0);
	1257	m_fdc_2hd->ready_w(0);
	1258	}
	1259	else
	1260	m_fdc_2hd->set_ready_line_connected(1);
	1261
	1262	// TODO: is the motor control bit really inverted relative to the other fdcs?
	1263	m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? ASSERT_LINE : CLEAR_LINE);
	1264	m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? ASSERT_LINE : CLEAR_LINE);
1558	1265	break;
1559	1266	}
1560	1267	}
r241786	r241787
1565	1272	case 1: m_sio->data_w(space, 0, data); return;
1566	1273	case 3: m_sio->control_w(space, 0, data); return;
1567	1274	}
1568		printf("Write to undefined port [%02x] <- %02x\n",offset+0x90,data);
	1275	logerror("Write to undefined port [%02x] <- %02x\n",offset+0x90,data);
1569	1276	}
1570	1277	}
1571	1278
r241786	r241787
1576	1283	{
1577	1284	switch(offset & 6)
1578	1285	{
1579		case 0: return machine().device<upd765a_device>("upd765_2dd")->msr_r(space, 0, 0xff);
1580		case 2: return machine().device<upd765a_device>("upd765_2dd")->fifo_r(space, 0, 0xff);
1581		case 4: return 0x40; //unknown port meaning, might be 0x70
	1286	case 0: return m_fdc_2dd->msr_r(space, 0, 0xff);
	1287	case 2: return m_fdc_2dd->fifo_r(space, 0, 0xff);
	1288	case 4:
	1289	{
	1290	int ret = (!m_fdc_2dd->subdevice<floppy_connector>("0")->get_device()->ready_r()) ? 0x10 : 0;
	1291	ret |= (m_fdc_2dd->subdevice<floppy_connector>("1")->get_device()->ready_r()) ? 0x10 : 0;
	1292	return ret | 0x40; //unknown port meaning, might be 0x70
	1293	}
1582	1294	}
1583	1295	}
1584	1296	else
1585	1297	{
1586		printf("Read to undefined port [%02x]\n",offset+0xc8);
	1298	logerror("Read to undefined port [%02x]\n",offset+0xc8);
1587	1299	return 0xff;
1588	1300	}
1589	1301
r241786	r241787
1596	1308	{
1597	1309	switch(offset & 6)
1598	1310	{
1599		case 0: printf("Write to undefined port [%02x] <- %02x\n",offset+0xc8,data); return;
1600		case 2: machine().device<upd765a_device>("upd765_2dd")->fifo_w(space, 0, data, 0xff); return;
	1311	case 0: logerror("Write to undefined port [%02x] <- %02x\n",offset+0xc8,data); return;
	1312	case 2: m_fdc_2dd->fifo_w(space, 0, data, 0xff); return;
1601	1313	case 4:
1602		printf("%02x ctrl\n",data);
	1314	logerror("%02x ctrl\n",data);
1603	1315	if(((m_fdc_2dd_ctrl & 0x80) == 0) && (data & 0x80))
1604		machine().device<upd765a_device>("upd765_2dd")->reset();
	1316	m_fdc_2dd->soft_reset();
1605	1317
1606	1318	m_fdc_2dd_ctrl = data;
1607		machine().device<floppy_connector>("upd765_2dd:0")->get_device()->mon_w(data & 0x08 ? ASSERT_LINE : CLEAR_LINE);
1608		machine().device<floppy_connector>("upd765_2dd:1")->get_device()->mon_w(data & 0x08 ? ASSERT_LINE : CLEAR_LINE);
	1319	m_fdc_2dd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
	1320	m_fdc_2dd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
1609	1321	break;
1610	1322	}
1611	1323	}
1612	1324	else
1613	1325	{
1614		printf("Write to undefined port [%02x] <- %02x\n",offset+0xc8,data);
	1326	logerror("Write to undefined port [%02x] <- %02x\n",offset+0xc8,data);
1615	1327	}
1616	1328	}
1617	1329
r241786	r241787
1719	1431	m_pc9801rs_grcg_w(offset & 0x7fff, (offset >> 15) & 3, offset >> 17, data);
1720	1432	}
1721	1433
1722		READ8_MEMBER(pc9801_state::pc9801_mouse_r)
1723		{
1724		if((offset & 1) == 0)
1725		return 0xff;
1726		else
1727		{
1728		return machine().device<i8255_device>("ppi8255_mouse")->read(space, (offset & 6) >> 1);
1729		}
1730		}
1731
1732		WRITE8_MEMBER(pc9801_state::pc9801_mouse_w)
1733		{
1734		if((offset & 1) == 0)
1735		{
1736		//return 0xff;
1737		}
1738		else
1739		{
1740		machine().device<i8255_device>("ppi8255_mouse")->write(space, (offset & 6) >> 1,data);
1741		}
1742		}
1743
1744	1434	READ8_MEMBER(pc9801_state::ide_hack_r)
1745	1435	{
1746	1436	// this makes the ide driver not do 512 to 256 byte sector translation, the 9821 looks for bit 6 of offset 0xac403 of the kanji ram to set this, the rs unknown
r241786	r241787
1875	1565	/* first device is even offsets, second one is odd offsets */
1876	1566	static ADDRESS_MAP_START( pc9801_io, AS_IO, 16, pc9801_state )
1877	1567	ADDRESS_MAP_UNMAP_HIGH
1878		AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,pc9801_00_w,0xffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
1879		AM_RANGE(0x0020, 0x0027) AM_READWRITE8(pc9801_20_r,pc9801_20_w,0xffff) // RTC / DMA registers (LS244)
1880		AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801_30_r,pc9801_30_w,0xffff) //i8251 RS232c / i8255 system port
1881		AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,pc9801_40_w,0xffff) //i8255 printer port / i8251 keyboard
1882		AM_RANGE(0x0050, 0x0057) AM_READWRITE8(pc9801_50_r,pc9801_50_w,0xffff) // NMI FF / i8255 floppy port (2d?)
1883		AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,pc9801_60_w,0xffff) //upd7220 character ports / <undefined>
	1568	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("i8237", am9517a_device, read, write, 0xff00)
	1569	AM_RANGE(0x0000, 0x000f) AM_READWRITE8(pic_r, pic_w, 0x00ff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
	1570	AM_RANGE(0x0020, 0x0027) AM_WRITE8(rtc_dmapg_w,0xffff) // RTC / DMA registers (LS244)
	1571	AM_RANGE(0x0030, 0x0037) AM_DEVREADWRITE8("ppi8255_sys", i8255_device, read, write, 0xff00) //i8251 RS232c / i8255 system port
	1572	AM_RANGE(0x0040, 0x0047) AM_DEVREADWRITE8("ppi8255_prn", i8255_device, read, write, 0x00ff)
	1573	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("keyb", pc9801_kbd_device, rx_r, tx_w, 0xff00) //i8255 printer port / i8251 keyboard
	1574	AM_RANGE(0x0050, 0x0057) AM_DEVREADWRITE8("ppi8255_fdd", i8255_device, read, write, 0xff00)
	1575	AM_RANGE(0x0050, 0x0053) AM_WRITE8(nmi_ctrl_w,0x00ff) // NMI FF / i8255 floppy port (2d?)
	1576	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("upd7220_chr", upd7220_device, read, write, 0x00ff) //upd7220 character ports / <undefined>
1884	1577	AM_RANGE(0x0064, 0x0065) AM_WRITE8(pc9801_vrtc_mask_w,0xffff)
1885	1578	AM_RANGE(0x0068, 0x0069) AM_WRITE8(pc9801_video_ff_w,0xffff) //mode FF / <undefined>
1886	1579	//  AM_RANGE(0x006c, 0x006f) border color / <undefined>
1887		AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r,pc9801_70_w,0xffff) //display registers / i8253 pit
1888		//  AM_RANGE(0x0080, 0x0083) AM_READWRITE8(pc9801_sasi_r,pc9801_sasi_w,0xffff) //HDD SASI interface / <undefined>
	1580	AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00)
	1581	AM_RANGE(0x0070, 0x007b) AM_READWRITE8(txt_scrl_r,txt_scrl_w,0x00ff) //display registers / i8253 pit
1889	1582	AM_RANGE(0x0080, 0x0081) AM_READWRITE8(sasi_data_r, sasi_data_w, 0x00ff)
1890	1583	AM_RANGE(0x0082, 0x0083) AM_READWRITE8(sasi_status_r, sasi_ctrl_w,0x00ff)
1891	1584	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801_fdc_2hd_r,pc9801_fdc_2hd_w,0xffff) //upd765a 2hd / cmt
1892	1585	AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,pc9801_a0_w,0xffff) //upd7220 bitmap ports / display registers
1893	1586	AM_RANGE(0x00c8, 0x00cd) AM_READWRITE8(pc9801_fdc_2dd_r,pc9801_fdc_2dd_w,0xffff) //upd765a 2dd / <undefined>
1894	1587	//  AM_RANGE(0x0188, 0x018b) AM_READWRITE8(pc9801_opn_r,pc9801_opn_w,0xffff) //ym2203 opn / <undefined>
1895		AM_RANGE(0x7fd8, 0x7fdf) AM_READWRITE8(pc9801_mouse_r,pc9801_mouse_w,0xffff) // <undefined> / mouse ppi8255 ports
	1588	AM_RANGE(0x7fd8, 0x7fdf) AM_DEVREADWRITE8("ppi8255_mouse", i8255_device, read, write, 0xff00)
1896	1589	ADDRESS_MAP_END
1897	1590
1898	1591	/*************************************
r241786	r241787
1967	1660	}
1968	1661	}
1969	1662
1970		printf("Unknown EMS ROM setting %02x\n",data);
	1663	logerror("Unknown EMS ROM setting %02x\n",data);
1971	1664	}
1972	1665	if(offset == 3)
1973	1666	{
r241786	r241787
1975	1668	m_vram_bank = (data & 2) >> 1;
1976	1669	else
1977	1670	{
1978		printf("Unknown EMS RAM setting %02x\n",data);
	1671	logerror("Unknown EMS RAM setting %02x\n",data);
1979	1672	}
1980	1673	}
1981	1674	}
r241786	r241787
2016	1709	m_maincpu->set_input_line(INPUT_LINE_A20, m_gate_a20);
2017	1710	}
2018	1711
2019		READ8_MEMBER(pc9801_state::pc9801rs_30_r)
	1712	READ8_MEMBER(pc9801_state::grcg_r)
2020	1713	{
2021		return pc9801_30_r(space,offset);
2022		}
2023
2024		READ8_MEMBER(pc9801_state::pc9801rs_70_r)
2025		{
2026		if(offset == 0xc)
	1714	if(offset == 6)
2027	1715	{
2028		printf("GRCG mode R\n");
	1716	logerror("GRCG mode R\n");
2029	1717	return 0xff;
2030	1718	}
2031		else if(offset == 0x0e)
	1719	else if(offset == 7)
2032	1720	{
2033		printf("GRCG tile R\n");
	1721	logerror("GRCG tile R\n");
2034	1722	return 0xff;
2035	1723	}
2036
2037		return  pc9801_70_r(space,offset);;
	1724	return txt_scrl_r(space,offset);
2038	1725	}
2039	1726
2040		WRITE8_MEMBER(pc9801_state::pc9801rs_70_w)
	1727	WRITE8_MEMBER(pc9801_state::grcg_w)
2041	1728	{
2042		if(offset == 0xc)
	1729	if(offset == 6)
2043	1730	{
2044		//      printf("%02x GRCG MODE\n",data);
	1731	//      logerror("%02x GRCG MODE\n",data);
2045	1732	m_grcg.mode = data;
2046	1733	m_grcg.tile_index = 0;
2047	1734	return;
2048	1735	}
2049		else if(offset == 0x0e)
	1736	else if(offset == 7)
2050	1737	{
2051		//      printf("%02x GRCG TILE %02x\n",data,m_grcg.tile_index);
	1738	//      logerror("%02x GRCG TILE %02x\n",data,m_grcg.tile_index);
2052	1739	m_grcg.tile[m_grcg.tile_index] = data;
2053	1740	m_grcg.tile_index ++;
2054	1741	m_grcg.tile_index &= 3;
2055	1742	return;
2056	1743	}
2057	1744
2058		pc9801_70_w(space,offset,data);
	1745	txt_scrl_w(space,offset,data);
2059	1746	}
2060	1747
2061	1748	READ8_MEMBER(pc9801_state::pc9801rs_soundrom_r)
r241786	r241787
2082	1769	else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1)      { return pc9801rs_ex_wram_r(space,offset-0x00100000); }
2083	1770	else if(offset >= 0xfffe0000 && offset <= 0xffffffff)                   { return pc9801rs_ipl_r(space,offset & 0x1ffff);      }
2084	1771
2085		//  printf("%08x\n",offset);
	1772	//  logerror("%08x\n",offset);
2086	1773	return 0x00;
2087	1774	}
2088	1775
r241786	r241787
2102	1789	else if(offset >= 0x000e0000 && offset <= 0x000e7fff)                   { m_pc9801rs_grcg_w(offset & 0x7fff,0,data);        }
2103	1790	else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1)      { pc9801rs_ex_wram_w(space,offset-0x00100000,data);    }
2104	1791	//else
2105		//  printf("%08x %08x\n",offset,data);
	1792	//  logerror("%08x %08x\n",offset,data);
2106	1793	}
2107	1794
2108	1795	READ8_MEMBER(pc9801_state::pc9810rs_fdc_ctrl_r)
r241786	r241787
2118	1805	---- ---x select irq
2119	1806	*/
2120	1807
2121		machine().device<floppy_connector>("upd765_2hd:0")->get_device()->set_rpm(data & 0x02 ? 360 : 300);
2122		machine().device<floppy_connector>("upd765_2hd:1")->get_device()->set_rpm(data & 0x02 ? 360 : 300);
	1808	m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->set_rpm(data & 0x02 ? 360 : 300);
	1809	m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->set_rpm(data & 0x02 ? 360 : 300);
2123	1810
2124		machine().device<upd765a_device>("upd765_2hd")->set_rate(data & 0x02 ? 500000 : 250000);
	1811	m_fdc_2hd->set_rate(data & 0x02 ? 500000 : 250000);
2125	1812
2126	1813	m_fdc_ctrl = data;
2127	1814	//if(data & 0xfc)
2128		//  printf("FDC ctrl called with %02x\n",data);
	1815	//  logerror("FDC ctrl called with %02x\n",data);
2129	1816	}
2130	1817
2131	1818	READ8_MEMBER(pc9801_state::pc9801rs_2hd_r)
r241786	r241787
2134	1821	{
2135	1822	switch(offset & 6)
2136	1823	{
2137		case 0: return machine().device<upd765a_device>("upd765_2hd")->msr_r(space, 0, 0xff);
2138		case 2: return machine().device<upd765a_device>("upd765_2hd")->fifo_r(space, 0, 0xff);
	1824	case 0: return m_fdc_2hd->msr_r(space, 0, 0xff);
	1825	case 2: return m_fdc_2hd->fifo_r(space, 0, 0xff);
2139	1826	case 4: return 0x44; //2hd flag
2140	1827	}
2141	1828	}
2142	1829
2143		printf("Read to undefined port [%02x]\n",offset+0x90);
	1830	logerror("Read to undefined port [%02x]\n",offset+0x90);
2144	1831
2145	1832	return 0xff;
2146	1833	}
r241786	r241787
2151	1838	{
2152	1839	switch(offset & 6)
2153	1840	{
2154		case 2: machine().device<upd765a_device>("upd765_2hd")->fifo_w(space, 0, data, 0xff); return;
	1841	case 2: m_fdc_2hd->fifo_w(space, 0, data, 0xff); return;
2155	1842	case 4:
2156	1843	if(data & 0x80)
2157		machine().device<upd765a_device>("upd765_2hd")->reset();
	1844	m_fdc_2hd->soft_reset();
2158	1845
2159		pc9801_fdc_2hd_update_ready(NULL, 0);
	1846	if(data & 0x40)
	1847	{
	1848	m_fdc_2hd->set_ready_line_connected(0);
	1849	m_fdc_2hd->ready_w(0);
	1850	}
	1851	else
	1852	m_fdc_2hd->set_ready_line_connected(1);
2160	1853
2161		machine().device<floppy_connector>("upd765_2hd:0")->get_device()->mon_w(data & 0x40 ? ASSERT_LINE : CLEAR_LINE);
2162		machine().device<floppy_connector>("upd765_2hd:1")->get_device()->mon_w(data & 0x40 ? ASSERT_LINE : CLEAR_LINE);
2163
2164		//              machine().device<floppy_connector>("upd765_2hd:0")->get_device()->mon_w(data & 0x08 ? ASSERT_LINE : CLEAR_LINE);
2165		//              machine().device<floppy_connector>("upd765_2hd:1")->get_device()->mon_w(data & 0x08 ? ASSERT_LINE : CLEAR_LINE);
	1854	//TODO: verify
	1855	if(!(m_fdc_ctrl & 4))
	1856	{
	1857	m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
	1858	m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
	1859	}
2166	1860	return;
2167	1861	}
2168	1862	}
2169	1863
2170		printf("Write to undefined port [%02x] %02x\n",offset+0x90,data);
	1864	logerror("Write to undefined port [%02x] %02x\n",offset+0x90,data);
2171	1865	}
2172	1866
2173	1867	#if 0
r241786	r241787
2186	1880	}
2187	1881	}
2188	1882
2189		printf("Read to undefined port [%02x]\n",offset+0x90);
	1883	logerror("Read to undefined port [%02x]\n",offset+0x90);
2190	1884
2191	1885	return 0xff;
2192	1886	}
r241786	r241787
2201	1895	switch(offset & 6)
2202	1896	{
2203	1897	case 2: machine().device<upd765a_device>("upd765_2hd")->fifo_w(space, 0, data, 0xff); return;
2204		case 4: printf("%02x 2DD FDC ctrl\n",data); return;
	1898	case 4: logerror("%02x 2DD FDC ctrl\n",data); return;
2205	1899	}
2206	1900	}
2207	1901
2208		printf("Write to undefined port [%02x] %02x\n",offset+0x90,data);
	1902	logerror("Write to undefined port [%02x] %02x\n",offset+0x90,data);
2209	1903	}
2210	1904	#endif
2211	1905
r241786	r241787
2226	1920	"<unknown>"         // 3
2227	1921	};
2228	1922
2229		printf("Write to extended video FF register %s -> %02x\n",ex_video_ff_regnames[(data & 0x06) >> 1],data & 1);
	1923	logerror("Write to extended video FF register %s -> %02x\n",ex_video_ff_regnames[(data & 0x06) >> 1],data & 1);
2230	1924	}
2231	1925	//else
2232		//  printf("Write to extended video FF register %02x\n",data);
	1926	//  logerror("Write to extended video FF register %02x\n",data);
2233	1927
2234	1928	return;
2235	1929	}
r241786	r241787
2299	1993	return 0xff;
2300	1994	}
2301	1995
2302		READ8_MEMBER(pc9801_state::pc9801rs_pit_mirror_r)
2303		{
2304		if((offset & 1) == 0)
2305		{
2306		printf("Read to undefined port [%04x]\n",offset+0x3fd8);
2307		return 0xff;
2308		}
2309		else // odd
2310		{
2311		if(offset & 0x08)
2312		printf("Read to undefined port [%02x]\n",offset+0x3fd8);
2313		else
2314		return m_pit8253->read(space, (offset & 6) >> 1);
2315		}
2316
2317		return 0xff;
2318		}
2319
2320		WRITE8_MEMBER(pc9801_state::pc9801rs_pit_mirror_w)
2321		{
2322		if((offset & 1) == 0)
2323		{
2324		printf("Write to undefined port [%04x] <- %02x\n",offset+0x3fd8,data);
2325		}
2326		else // odd
2327		{
2328		if(offset < 0x08)
2329		m_pit8253->write(space, (offset & 6) >> 1, data);
2330		else
2331		printf("Write to undefined port [%04x] <- %02x\n",offset+0x3fd8,data);
2332		}
2333		}
2334
2335		static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 32, pc9801_state )
2336		AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff)
2337		ADDRESS_MAP_END
2338
2339		static ADDRESS_MAP_START( pc9801rs_io, AS_IO, 32, pc9801_state )
2340		ADDRESS_MAP_UNMAP_HIGH
2341		AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,        pc9801_00_w,        0xffffffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
2342		AM_RANGE(0x0020, 0x0027) AM_READWRITE8(pc9801_20_r,        pc9801_20_w,        0xffffffff) // RTC / DMA registers (LS244)
2343		AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffffffff) //i8251 RS232c / i8255 system port
2344		AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,        pc9801_40_w,        0xffffffff) //i8255 printer port / i8251 keyboard
2345		AM_RANGE(0x0050, 0x0053) AM_WRITE8(pc9801rs_nmi_w, 0xffffffff)
2346		AM_RANGE(0x005c, 0x005f) AM_READ(pc9821_timestamp_r) AM_WRITENOP // artic
2347		AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
2348		AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffffffff)
2349		AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffffffff) //mode FF / <undefined>
2350		AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r,      pc9801rs_70_w,      0xffffffff) //display registers "GRCG" / i8253 pit
2351		AM_RANGE(0x0080, 0x0083) AM_READWRITE8(pc9801_sasi_r,      pc9801_sasi_w,      0xffffffff) //HDD SASI interface / <undefined>
2352		AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
2353		AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,        pc9801rs_a0_w,      0xffffffff) //upd7220 bitmap ports / display registers
2354		AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffffffff)
2355		AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
2356		//  AM_RANGE(0x00ec, 0x00ef) PC-9801-86 sound board
2357		AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffffffff)
2358		//  AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r,       pc9801_opn_w,       0xffffffff) //ym2203 opn / <undefined>
2359		AM_RANGE(0x0430, 0x0433) AM_READ8(ide_hack_r, 0x000000ff)
2360
2361		AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffffffff)
2362		AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffffffff) //ROM/RAM bank
2363
2364		AM_RANGE(0x0640, 0x064f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
2365		AM_RANGE(0x0740, 0x074f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
2366
2367		AM_RANGE(0x3fd8, 0x3fdf) AM_READWRITE8(pc9801rs_pit_mirror_r,        pc9801rs_pit_mirror_w,        0xffffffff) // <undefined> / pit mirror ports
2368		AM_RANGE(0x7fd8, 0x7fdf) AM_READWRITE8(pc9801_mouse_r,     pc9801_mouse_w,     0xffffffff) // <undefined> / mouse ppi8255 ports
2369		//  AM_RANGE(0xa460, 0xa463) AM_READWRITE8(pc9801_ext_opna_r,  pc9801_ext_opna_w,  0xffffffff)
2370		AM_RANGE(0xbfd8, 0xbfdf) AM_WRITE8(pc9801rs_mouse_freq_w, 0xffffffff)
2371		AM_RANGE(0xe0d0, 0xe0d3) AM_READ8(pc9801rs_midi_r, 0xffffffff)
2372		ADDRESS_MAP_END
2373
2374	1996	READ8_MEMBER(pc9801_state::pic_r)
2375	1997	{
2376	1998	return ((offset >= 4) ? m_pic2 : m_pic1)->read(space, offset & 3);
r241786	r241787
2412	2034
2413	2035	static ADDRESS_MAP_START( pc9801ux_io, AS_IO, 16, pc9801_state )
2414	2036	ADDRESS_MAP_UNMAP_HIGH
2415
2416		AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("i8237", am9517a_device, read, write, 0xff00)
2417		AM_RANGE(0x0000, 0x000f) AM_READWRITE8(pic_r, pic_w, 0x00ff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
2418		AM_RANGE(0x0020, 0x0027) AM_READWRITE8(pc9801_20_r,        pc9801_20_w,        0xffff) // RTC / DMA registers (LS244)
2419		AM_RANGE(0x0030, 0x0037) AM_DEVREADWRITE8("ppi8255_sys", i8255_device, read, write, 0xff00)
2420		AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffff) //i8251 RS232c / i8255 system port
2421		AM_RANGE(0x0040, 0x0047) AM_DEVREADWRITE8("ppi8255_prn", i8255_device, read, write, 0x00ff)
2422		AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("keyb", pc9801_kbd_device, rx_r, tx_w, 0xff00) //i8255 printer port / i8251 keyboard
2423		AM_RANGE(0x005c, 0x005f) AM_WRITENOP // time-stamp?
2424		AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("upd7220_chr", upd7220_device, read, write, 0x00ff) //upd7220 character ports / <undefined>
2425		AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffff)
	2037	AM_RANGE(0x0050, 0x0057) AM_NOP // 2dd ppi?
	2038	AM_RANGE(0x005c, 0x005f) AM_READ(pc9821_timestamp_r) AM_WRITENOP // artic
2426	2039	AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffff) //mode FF / <undefined>
2427		AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00)
2428		AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r,      pc9801rs_70_w,      0xffff) //display registers "GRCG" / i8253 pit
	2040	AM_RANGE(0x0070, 0x007f) AM_READWRITE8(grcg_r,      grcg_w,      0x00ff) //display registers "GRCG" / i8253 pit
2429	2041	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
2430	2042	AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,        pc9801rs_a0_w,      0xffff) //upd7220 bitmap ports / display registers
2431	2043	AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffff)
2432	2044	AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
2433	2045	AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffff)
2434		//  AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r,       pc9801_opn_w,       0xffff) //ym2203 opn / <undefined>
2435	2046	AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffff)
2436	2047	AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffff) //ROM/RAM bank
2437	2048	AM_RANGE(0x3fd8, 0x3fdf) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00)
2438		AM_RANGE(0x7fd8, 0x7fdf) AM_DEVREADWRITE8("ppi8255_mouse", i8255_device, read, write, 0xff00)
2439	2049	//  AM_RANGE(0xa460, 0xa463) AM_READWRITE8(pc9801_ext_opna_r,  pc9801_ext_opna_w,  0xffff)
	2050	AM_IMPORT_FROM(pc9801_io)
	2051	ADDRESS_MAP_END
2440	2052
	2053	static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 16, pc9801_state )
	2054	AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffff)
2441	2055	ADDRESS_MAP_END
2442	2056
2443		static ADDRESS_MAP_START( pc9801bx2_io, AS_IO, 32, pc9801_state )
2444		AM_IMPORT_FROM(pc9801rs_io)
2445
2446		AM_RANGE(0x841c, 0x841f) AM_READWRITE8(sdip_0_r,sdip_0_w,0xffffffff)
2447		AM_RANGE(0x851c, 0x851f) AM_READWRITE8(sdip_1_r,sdip_1_w,0xffffffff)
2448		AM_RANGE(0x861c, 0x861f) AM_READWRITE8(sdip_2_r,sdip_2_w,0xffffffff)
2449		AM_RANGE(0x871c, 0x871f) AM_READWRITE8(sdip_3_r,sdip_3_w,0xffffffff)
2450		AM_RANGE(0x881c, 0x881f) AM_READWRITE8(sdip_4_r,sdip_4_w,0xffffffff)
2451		AM_RANGE(0x891c, 0x891f) AM_READWRITE8(sdip_5_r,sdip_5_w,0xffffffff)
2452		AM_RANGE(0x8a1c, 0x8a1f) AM_READWRITE8(sdip_6_r,sdip_6_w,0xffffffff)
2453		AM_RANGE(0x8b1c, 0x8b1f) AM_READWRITE8(sdip_7_r,sdip_7_w,0xffffffff)
2454		AM_RANGE(0x8c1c, 0x8c1f) AM_READWRITE8(sdip_8_r,sdip_8_w,0xffffffff)
2455		AM_RANGE(0x8d1c, 0x8d1f) AM_READWRITE8(sdip_9_r,sdip_9_w,0xffffffff)
2456		AM_RANGE(0x8e1c, 0x8e1f) AM_READWRITE8(sdip_a_r,sdip_a_w,0xffffffff)
2457		AM_RANGE(0x8f1c, 0x8f1f) AM_READWRITE8(sdip_b_r,sdip_b_w,0xffffffff)
	2057	static ADDRESS_MAP_START( pc9801rs_io, AS_IO, 16, pc9801_state )
	2058	ADDRESS_MAP_UNMAP_HIGH
	2059	AM_RANGE(0x0050, 0x0053) AM_WRITE8(pc9801rs_nmi_w, 0xffff)
	2060	AM_RANGE(0x0430, 0x0433) AM_READ8(ide_hack_r, 0x00ff)
	2061	AM_RANGE(0x0640, 0x064f) AM_DEVREADWRITE("ide", ata_interface_device, read_cs0, write_cs0)
	2062	AM_RANGE(0x0740, 0x074f) AM_DEVREADWRITE("ide", ata_interface_device, read_cs1, write_cs1)
	2063	AM_RANGE(0xbfd8, 0xbfdf) AM_WRITE8(pc9801rs_mouse_freq_w, 0xffff)
	2064	AM_RANGE(0xe0d0, 0xe0d3) AM_READ8(pc9801rs_midi_r, 0xffff)
	2065	AM_IMPORT_FROM(pc9801ux_io)
2458	2066	ADDRESS_MAP_END
2459	2067
2460	2068	/*************************************
r241786	r241787
2497	2105	else if(offset >= 0x00f00000 && offset <= 0x00f9ffff)                   { return pc9821_ext_gvram_r(space,offset-0x00f00000); }
2498	2106	else if(offset >= 0xfffe0000 && offset <= 0xffffffff)                   { return pc9801rs_ipl_r(space,offset & 0x1ffff);      }
2499	2107
2500		//printf("%08x\n",offset);
	2108	//logerror("%08x\n",offset);
2501	2109	return 0x00;
2502	2110	}
2503	2111
r241786	r241787
2527	2135	else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1)      { pc9801rs_ex_wram_w(space,offset-0x00100000,data);    }
2528	2136	else if(offset >= 0x00f00000 && offset <= 0x00f9ffff)                   { pc9821_ext_gvram_w(space,offset-0x00f00000,data);    }
2529	2137	//else
2530		//  printf("%08x %08x\n",offset,data);
	2138	//  logerror("%08x %08x\n",offset,data);
2531	2139
2532	2140	}
2533	2141
r241786	r241787
2538	2146	m_ex_video_ff[(data & 0xfe) >> 1] = data & 1;
2539	2147
2540	2148	//if((data & 0xfe) == 0x20)
2541		//  printf("%02x\n",data & 1);
	2149	//  logerror("%02x\n",data & 1);
2542	2150	}
2543	2151
2544	2152	/* Intentional fall-through */
r241786	r241787
2551	2159	{
2552	2160	if(m_ex_video_ff[ANALOG_256_MODE])
2553	2161	{
2554		printf("256 color mode [%02x] R\n",offset);
	2162	logerror("256 color mode [%02x] R\n",offset);
2555	2163	return 0;
2556	2164	}
2557	2165	else if(m_ex_video_ff[ANALOG_16_MODE]) //16 color mode, readback possible there
r241786	r241787
2608	2216	if(offset == 1)
2609	2217	m_pc9821_window_bank = data & 0xfe;
2610	2218	else
2611		printf("PC-9821 $f0000 window bank %02x\n",data);
	2219	logerror("PC-9821 $f0000 window bank %02x\n",data);
2612	2220	}
2613	2221
2614	2222	UINT8 pc9801_state::m_sdip_read(UINT16 port, UINT8 sdip_offset)
r241786	r241787
2616	2224	if(port == 2)
2617	2225	return m_sdip[sdip_offset];
2618	2226
2619		printf("Warning: read from unknown SDIP area %02x %04x\n",port,0x841c + port + (sdip_offset % 12)*0x100);
	2227	logerror("Warning: read from unknown SDIP area %02x %04x\n",port,0x841c + port + (sdip_offset % 12)*0x100);
2620	2228	return 0xff;
2621	2229	}
2622	2230
r241786	r241787
2628	2236	return;
2629	2237	}
2630	2238
2631		printf("Warning: write from unknown SDIP area %02x %04x %02x\n",port,0x841c + port + (sdip_offset % 12)*0x100,data);
	2239	logerror("Warning: write from unknown SDIP area %02x %04x %02x\n",port,0x841c + port + (sdip_offset % 12)*0x100,data);
2632	2240	}
2633	2241
2634	2242	READ8_MEMBER(pc9801_state::sdip_0_r) { return m_sdip_read(offset, 0+m_sdip_bank*12); }
r241786	r241787
2664	2272	m_sdip_write(offset,11+m_sdip_bank*12,data);
2665	2273
2666	2274	if((offset & 2) == 0)
2667		printf("SDIP area B write %02x %02x\n",offset,data);
	2275	logerror("SDIP area B write %02x %02x\n",offset,data);
2668	2276	}
2669	2277
2670		READ32_MEMBER(pc9801_state::pc9821_timestamp_r)
	2278	READ16_MEMBER(pc9801_state::pc9821_timestamp_r)
2671	2279	{
2672		return m_maincpu->total_cycles();
	2280	return (m_maincpu->total_cycles() >> (16 * offset));
2673	2281	}
2674	2282
2675	2283	/* basically a read-back of various registers */
r241786	r241787
2686	2294	{
2687	2295	case 3: res = m_video_ff[DISPLAY_REG]; break; // display reg
2688	2296	default:
2689		printf("PC-9821: read ext2 f/f with value %02x\n",m_ext2_ff);
	2297	logerror("PC-9821: read ext2 f/f with value %02x\n",m_ext2_ff);
2690	2298	}
2691	2299
2692	2300	return res;
r241786	r241787
2704	2312
2705	2313	static ADDRESS_MAP_START( pc9821_io, AS_IO, 32, pc9801_state )
2706	2314	//  ADDRESS_MAP_UNMAP_HIGH // TODO: a read to somewhere makes this to fail at POST
2707		AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,        pc9801_00_w,        0xffffffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
2708		AM_RANGE(0x0020, 0x0027) AM_READWRITE8(pc9801_20_r,        pc9801_20_w,        0xffffffff) // RTC / DMA registers (LS244)
2709		AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffffffff) //i8251 RS232c / i8255 system port
2710		AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,        pc9801_40_w,        0xffffffff) //i8255 printer port / i8251 keyboard
	2315	AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("i8237", am9517a_device, read, write, 0xff00ff00)
	2316	AM_RANGE(0x0000, 0x000f) AM_READWRITE8(pic_r, pic_w, 0x00ff00ff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
	2317	AM_RANGE(0x0020, 0x0027) AM_WRITE8(rtc_dmapg_w,        0xffffffff) // RTC / DMA registers (LS244)
	2318	AM_RANGE(0x0030, 0x0037) AM_DEVREADWRITE8("ppi8255_sys", i8255_device, read, write, 0xff00ff00) //i8251 RS232c / i8255 system port
	2319	AM_RANGE(0x0040, 0x0047) AM_DEVREADWRITE8("ppi8255_prn", i8255_device, read, write, 0x00ff00ff)
	2320	AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("keyb", pc9801_kbd_device, rx_r, tx_w, 0xff00ff00) //i8255 printer port / i8251 keyboard
2711	2321	AM_RANGE(0x0050, 0x0053) AM_WRITE8(pc9801rs_nmi_w, 0xffffffff)
2712		AM_RANGE(0x005c, 0x005f) AM_READ(pc9821_timestamp_r) AM_WRITENOP // artic
2713		AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
	2322	AM_RANGE(0x005c, 0x005f) AM_READ16(pc9821_timestamp_r,0xffffffff) AM_WRITENOP // artic
	2323	AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("upd7220_chr", upd7220_device, read, write, 0x00ff00ff) //upd7220 character ports / <undefined>
2714	2324	AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffffffff)
2715	2325	AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9821_video_ff_w,  0xffffffff) //mode FF / <undefined>
2716		AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r,      pc9801rs_70_w,    0xffffffff) //display registers "GRCG" / i8253 pit
2717		AM_RANGE(0x0080, 0x0083) AM_READWRITE8(pc9801_sasi_r,      pc9801_sasi_w,      0xffffffff) //HDD SASI interface / <undefined>
	2326	AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00ff00)
	2327	AM_RANGE(0x0070, 0x007f) AM_READWRITE8(grcg_r,      grcg_w,      0x00ff00ff) //display registers "GRCG" / i8253 pit
2718	2328	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
2719	2329	AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9821_a0_r,        pc9821_a0_w,        0xffffffff) //upd7220 bitmap ports / display registers
2720	2330	//  AM_RANGE(0x00b0, 0x00b3) PC9861k (serial port?)
r241786	r241787
2746	2356	//  AM_RANGE(0x0c2d, 0x0c2d) cs4231 PCM board hi byte control
2747	2357	//  AM_RANGE(0x0cc0, 0x0cc7) SCSI interface / <undefined>
2748	2358	//  AM_RANGE(0x0cfc, 0x0cff) PCI bus
2749		AM_RANGE(0x3fd8, 0x3fdf) AM_READWRITE8(pc9801rs_pit_mirror_r,        pc9801rs_pit_mirror_w,        0xffffffff) // <undefined> / pit mirror ports
2750		AM_RANGE(0x7fd8, 0x7fdf) AM_READWRITE8(pc9801_mouse_r,      pc9801_mouse_w,      0xffffffff) // <undefined> / mouse ppi8255 ports
	2359	AM_RANGE(0x3fd8, 0x3fdf) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00ff00) // <undefined> / pit mirror ports
	2360	AM_RANGE(0x7fd8, 0x7fdf) AM_DEVREADWRITE8("ppi8255_mouse", i8255_device, read, write, 0xff00ff00)
2751	2361	AM_RANGE(0x841c, 0x841f) AM_READWRITE8(sdip_0_r,sdip_0_w,0xffffffff)
2752	2362	AM_RANGE(0x851c, 0x851f) AM_READWRITE8(sdip_1_r,sdip_1_w,0xffffffff)
2753	2363	AM_RANGE(0x861c, 0x861f) AM_READWRITE8(sdip_2_r,sdip_2_w,0xffffffff)
r241786	r241787
3086	2696
3087	2697	m_dmac->hack_w(state);
3088	2698
3089		//  printf("%02x HLDA\n",state);
	2699	//  logerror("%02x HLDA\n",state);
3090	2700	}
3091	2701
3092	2702	WRITE_LINE_MEMBER(pc9801_state::pc9801_tc_w )
r241786	r241787
3095	2705	m_fdc_2hd->tc_w(state);
3096	2706	// TODO: 2dd?
3097	2707
3098		//  printf("TC %02x\n",state);
	2708	//  logerror("TC %02x\n",state);
3099	2709	}
3100	2710
3101	2711	READ8_MEMBER(pc9801_state::pc9801_dma_read_byte)
r241786	r241787
3103	2713	address_space &program = m_maincpu->space(AS_PROGRAM);
3104	2714	offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
3105	2715
3106		//  printf("%08x\n",addr);
	2716	//  logerror("%08x\n",addr);
3107	2717
3108	2718	return program.read_byte(addr);
3109	2719	}
r241786	r241787
3114	2724	address_space &program = m_maincpu->space(AS_PROGRAM);
3115	2725	offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
3116	2726
3117		//  printf("%08x %02x\n",addr,data);
	2727	//  logerror("%08x %02x\n",addr,data);
3118	2728
3119	2729	program.write_byte(addr, data);
3120	2730	}
r241786	r241787
3124	2734	if (!state) m_dack = channel;
3125	2735	}
3126	2736
3127		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack0_w){ /*printf("%02x 0\n",state);*/ set_dma_channel(0, state); }
3128		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack1_w){ /*printf("%02x 1\n",state);*/ set_dma_channel(1, state); }
3129		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack2_w){ /*printf("%02x 2\n",state);*/ set_dma_channel(2, state); }
3130		WRITE_LINE_MEMBER(pc9801_state::pc9801_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma_channel(3, state); }
	2737	WRITE_LINE_MEMBER(pc9801_state::pc9801_dack0_w){ /*logerror("%02x 0\n",state);*/ set_dma_channel(0, state); }
	2738	WRITE_LINE_MEMBER(pc9801_state::pc9801_dack1_w){ /*logerror("%02x 1\n",state);*/ set_dma_channel(1, state); }
	2739	WRITE_LINE_MEMBER(pc9801_state::pc9801_dack2_w){ /*logerror("%02x 2\n",state);*/ set_dma_channel(2, state); }
	2740	WRITE_LINE_MEMBER(pc9801_state::pc9801_dack3_w){ /*logerror("%02x 3\n",state);*/ set_dma_channel(3, state); }
3131	2741
3132		READ8_MEMBER(pc9801_state::fdc_2hd_r)
3133		{
3134		return m_fdc_2hd->dma_r();
3135		}
3136
3137		WRITE8_MEMBER(pc9801_state::fdc_2hd_w)
3138		{
3139		m_fdc_2hd->dma_w(data);
3140		}
3141
3142		READ8_MEMBER(pc9801_state::fdc_2dd_r)
3143		{
3144		return m_fdc_2dd->dma_r();
3145		}
3146
3147		WRITE8_MEMBER(pc9801_state::fdc_2dd_w)
3148		{
3149		m_fdc_2dd->dma_w(data);
3150		}
3151
3152	2742	/*
3153	2743	ch1 cs-4231a
3154	2744	ch2 FDC
r241786	r241787
3210	2800	res |= (m_mouse.lx >> isporthi) & 0xf;
3211	2801	}
3212	2802
3213		//  printf("A\n");
	2803	//  logerror("A\n");
3214	2804	return res;
3215	2805	}
3216	2806
3217	2807	WRITE8_MEMBER(pc9801_state::ppi_mouse_porta_w)
3218	2808	{
3219		//  printf("A %02x\n",data);
	2809	//  logerror("A %02x\n",data);
3220	2810	}
3221	2811
3222	2812	WRITE8_MEMBER(pc9801_state::ppi_mouse_portb_w)
3223	2813	{
3224		//  printf("B %02x\n",data);
	2814	//  logerror("B %02x\n",data);
3225	2815	}
3226	2816
3227	2817	WRITE8_MEMBER(pc9801_state::ppi_mouse_portc_w)
r241786	r241787
3242	2832	****************************************/
3243	2833
3244	2834	static SLOT_INTERFACE_START( pc9801_floppies )
	2835	SLOT_INTERFACE( "525dd", FLOPPY_525_DD )
3245	2836	SLOT_INTERFACE( "525hd", FLOPPY_525_HD )
3246	2837	SLOT_INTERFACE( "35hd", FLOPPY_35_HD )
3247	2838	SLOT_INTERFACE_END
r241786	r241787
3263	2854
3264	2855	WRITE_LINE_MEMBER( pc9801_state::fdc_2dd_irq )
3265	2856	{
3266		printf("IRQ 2DD %d\n",state);
	2857	logerror("IRQ 2DD %d\n",state);
3267	2858
3268	2859	if(m_fdc_2dd_ctrl & 8)
3269	2860	{
r241786	r241787
3275	2866	{
3276	2867	/* 0xffaf8 */
3277	2868
3278		//printf("%02x %d\n",m_fdc_ctrl,state);
	2869	//logerror("%02x %d\n",m_fdc_ctrl,state);
3279	2870
3280	2871	if(m_fdc_ctrl & 1)
3281	2872	m_pic2->ir3_w(state);
r241786	r241787
3285	2876
3286	2877	WRITE_LINE_MEMBER( pc9801_state::pc9801rs_fdc_drq )
3287	2878	{
3288		//  printf("DRQ %d\n",state);
3289
3290	2879	if(m_fdc_ctrl & 1)
3291	2880	m_dmac->dreq2_w(state ^ 1);
3292	2881	else
3293		printf("DRQ %02x %d\n",m_fdc_ctrl,state);
	2882	m_dmac->dreq3_w(state ^ 1);
3294	2883	}
3295	2884
3296	2885	UINT32 pc9801_state::pc9801_286_a20(bool state)
r241786	r241787
3332	2921	{
3333	2922	MACHINE_START_CALL_MEMBER(pc9801_common);
3334	2923
3335		upd765a_device *fdc;
3336		fdc = machine().device<upd765a_device>(":upd765_2hd");
3337		if (fdc)
3338		{
3339		floppy_image_device *floppy;
3340		floppy = machine().device<floppy_connector>("upd765_2hd:0")->get_device();
3341		if(floppy)
3342		floppy->setup_ready_cb(floppy_image_device::ready_cb(FUNC(pc9801_state::pc9801_fdc_2hd_update_ready), this));
3343
3344		floppy = machine().device<floppy_connector>("upd765_2hd:1")->get_device();
3345		if(floppy)
3346		floppy->setup_ready_cb(floppy_image_device::ready_cb(FUNC(pc9801_state::pc9801_fdc_2hd_update_ready), this));
3347		}
3348
3349	2924	m_fdc_2hd->set_rate(500000);
3350	2925	m_fdc_2dd->set_rate(250000);
3351	2926	m_sys_type = 0x00 >> 6;
r241786	r241787
3412	2987	int i;
3413	2988	static const UINT8 default_memsw_data[0x10] =
3414	2989	{
3415		// set high nibble of byte 9 to 0xa and comment ROM_FILL below to boot from hdd
3416	2990	0xe1, 0x48, 0xe1, 0x05, 0xe1, 0x04, 0xe1, 0x00, 0xe1, 0x01, 0xe1, 0x00, 0xe1, 0x00, 0xe1, 0x6e
3417	2991	//          0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff
3418	2992	};
r241786	r241787
3434	3008	{
3435	3009	MACHINE_RESET_CALL_MEMBER(pc9801_common);
3436	3010
3437		/* 2dd interface ready line is ON by default */
3438		floppy_image_device *floppy;
3439		floppy = machine().device<floppy_connector>(":upd765_2hd:0")->get_device();
3440		if (floppy)
3441		floppy->mon_w(CLEAR_LINE);
3442		floppy = machine().device<floppy_connector>(":upd765_2hd:1")->get_device();
3443		if (floppy)
3444		floppy->mon_w(CLEAR_LINE);
	3011	UINT8 op_mode;
	3012	UINT8 *ROM;
	3013	UINT8 *PRG = memregion("fdc_data")->base();
	3014	int i;
3445	3015
3446		{
3447		UINT8 op_mode;
3448		UINT8 *ROM;
3449		UINT8 *PRG = memregion("fdc_data")->base();
3450		int i;
	3016	ROM = memregion("fdc_bios_2dd")->base();
	3017	op_mode = (ioport("ROM_LOAD")->read() & 2) >> 1;
3451	3018
3452		ROM = memregion("fdc_bios_2dd")->base();
3453		op_mode = (ioport("ROM_LOAD")->read() & 2) >> 1;
	3019	for(i=0;i<0x1000;i++)
	3020	ROM[i] = PRG[i+op_mode*0x8000];
3454	3021
3455		for(i=0;i<0x1000;i++)
3456		ROM[i] = PRG[i+op_mode*0x8000];
	3022	ROM = memregion("fdc_bios_2hd")->base();
	3023	op_mode = ioport("ROM_LOAD")->read() & 1;
3457	3024
3458		ROM = memregion("fdc_bios_2hd")->base();
3459		op_mode = ioport("ROM_LOAD")->read() & 1;
3460
3461		for(i=0;i<0x1000;i++)
3462		ROM[i] = PRG[i+op_mode*0x8000+0x10000];
3463		}
	3025	for(i=0;i<0x1000;i++)
	3026	ROM[i] = PRG[i+op_mode*0x8000+0x10000];
3464	3027	}
3465	3028
3466	3029	MACHINE_RESET_MEMBER(pc9801_state,pc9801rs)
r241786	r241787
3516	3079	{
3517	3080	m_mouse.freq_index ++;
3518	3081
3519		//      printf("%02x\n",m_mouse.freq_index);
	3082	//      logerror("%02x\n",m_mouse.freq_index);
3520	3083	if(m_mouse.freq_index > m_mouse.freq_reg)
3521	3084	{
3522		//          printf("irq %02x\n",m_mouse.freq_reg);
	3085	//          logerror("irq %02x\n",m_mouse.freq_reg);
3523	3086	m_mouse.freq_index = 0;
3524	3087	m_pic2->ir5_w(0);
3525	3088	m_pic2->ir5_w(1);
r241786	r241787
3527	3090	}
3528	3091	}
3529	3092
3530		WRITE_LINE_MEMBER( pc9801_state::keyboard_irq )
3531		{
3532		m_pic1->ir1_w(state);
3533		}
3534
3535	3093	static MACHINE_CONFIG_FRAGMENT( pc9801_keyboard )
3536	3094	MCFG_DEVICE_ADD("keyb", PC9801_KBD, 53)
3537		MCFG_PC9801_KBD_IRQ_CALLBACK(WRITELINE(pc9801_state, keyboard_irq))
	3095	MCFG_PC9801_KBD_IRQ_CALLBACK(DEVWRITELINE("pic8259_master", pic8259_device, ir1_w))
3538	3096	MACHINE_CONFIG_END
3539	3097
3540	3098	static MACHINE_CONFIG_FRAGMENT( pc9801_mouse )
r241786	r241787
3582	3140	MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir1_w))
3583	3141	MACHINE_CONFIG_END
3584	3142
3585
3586		static MACHINE_CONFIG_START( pc9801, pc9801_state )
3587		MCFG_CPU_ADD("maincpu", I8086, 5000000) //unknown clock
3588		MCFG_CPU_PROGRAM_MAP(pc9801_map)
3589		MCFG_CPU_IO_MAP(pc9801_io)
3590		MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3591		MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
3592
3593		MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9801f)
3594		MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9801f)
3595
	3143	static MACHINE_CONFIG_FRAGMENT( pc9801_common )
3596	3144	MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
3597	3145	MCFG_PIT8253_CLK0(MAIN_CLOCK_X1) /* heartbeat IRQ */
3598	3146	MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic8259_master", pic8259_device, ir0_w))
r241786	r241787
3605	3153	MCFG_I8237_OUT_EOP_CB(WRITELINE(pc9801_state, pc9801_tc_w))
3606	3154	MCFG_I8237_IN_MEMR_CB(READ8(pc9801_state, pc9801_dma_read_byte))
3607	3155	MCFG_I8237_OUT_MEMW_CB(WRITE8(pc9801_state, pc9801_dma_write_byte))
3608		MCFG_I8237_IN_IOR_2_CB(READ8(pc9801_state, fdc_2hd_r))
3609		MCFG_I8237_IN_IOR_3_CB(READ8(pc9801_state, fdc_2dd_r))
3610		MCFG_I8237_OUT_IOW_2_CB(WRITE8(pc9801_state, fdc_2hd_w))
3611		MCFG_I8237_OUT_IOW_3_CB(WRITE8(pc9801_state, fdc_2dd_w))
	3156	MCFG_I8237_IN_IOR_2_CB(DEVREAD8("upd765_2hd", upd765a_device, mdma_r))
	3157	MCFG_I8237_OUT_IOW_2_CB(DEVWRITE8("upd765_2hd", upd765a_device, mdma_w))
3612	3158	MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc9801_state, pc9801_dack0_w))
3613	3159	MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc9801_state, pc9801_dack1_w))
3614	3160	MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc9801_state, pc9801_dack2_w))
r241786	r241787
3626	3172	/* TODO: check this one */
3627	3173	MCFG_I8255_IN_PORTB_CB(IOPORT("DSW5"))
3628	3174
3629		MCFG_DEVICE_ADD("ppi8255_fdd", I8255, 0)
3630		MCFG_I8255_IN_PORTA_CB(READ8(pc9801_state, ppi_fdd_porta_r))
3631		MCFG_I8255_IN_PORTB_CB(READ8(pc9801_state, ppi_fdd_portb_r))
3632		MCFG_I8255_IN_PORTC_CB(READ8(pc9801_state, ppi_fdd_portc_r))
3633		MCFG_I8255_OUT_PORTC_CB(WRITE8(pc9801_state, ppi_fdd_portc_w))
3634
3635	3175	MCFG_FRAGMENT_ADD(pc9801_keyboard)
3636	3176	MCFG_FRAGMENT_ADD(pc9801_mouse)
3637	3177	MCFG_FRAGMENT_ADD(pc9801_cbus)
3638		MCFG_FRAGMENT_ADD(pc9801_sasi)
3639		MCFG_UPD1990A_ADD(UPD1990A_TAG, XTAL_32_768kHz, NULL, NULL)
3640	3178
3641	3179	MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
3642	3180
3643		MCFG_UPD765A_ADD("upd765_2hd", false, true)
	3181	MCFG_UPD765A_ADD("upd765_2hd", true, true)
3644	3182	MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE("pic8259_slave", pic8259_device, ir3_w))
3645	3183	MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq2_w)) MCFG_DEVCB_INVERT
3646		MCFG_UPD765A_ADD("upd765_2dd", false, true)
3647		MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, fdc_2dd_irq))
3648		MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq3_w)) MCFG_DEVCB_INVERT
3649	3184	MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:0", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3650	3185	MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:1", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3651		MCFG_FLOPPY_DRIVE_ADD("upd765_2dd:0", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3652		MCFG_FLOPPY_DRIVE_ADD("upd765_2dd:1", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3653	3186
	3187	MCFG_DEVICE_ADD("ppi8255_fdd", I8255, 0)
	3188	MCFG_I8255_IN_PORTA_CB(READ8(pc9801_state, ppi_fdd_porta_r))
	3189	MCFG_I8255_IN_PORTB_CB(READ8(pc9801_state, ppi_fdd_portb_r))
	3190	MCFG_I8255_IN_PORTC_CB(READ8(pc9801_state, ppi_fdd_portc_r))
	3191	MCFG_I8255_OUT_PORTC_CB(WRITE8(pc9801_state, ppi_fdd_portc_w))
	3192
3654	3193	MCFG_SOFTWARE_LIST_ADD("disk_list","pc98")
3655	3194
3656
3657		#if 0
3658		MCFG_RAM_ADD(RAM_TAG)
3659		MCFG_RAM_DEFAULT_SIZE("128K")
3660		MCFG_RAM_EXTRA_OPTIONS("256K,384K,512K,640K")
3661		#endif
3662
3663	3195	/* video hardware */
3664	3196	MCFG_SCREEN_ADD("screen", RASTER)
3665	3197	MCFG_SCREEN_REFRESH_RATE(60)
3666		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
3667	3198	MCFG_SCREEN_UPDATE_DRIVER(pc9801_state, screen_update)
3668	3199	MCFG_SCREEN_SIZE(640, 480)
3669	3200	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
r241786	r241787
3677	3208	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
3678	3209	MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
3679	3210
3680		MCFG_PALETTE_ADD("palette", 16)
3681		MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
3682		MCFG_GFXDECODE_ADD("gfxdecode", "palette", pc9801)
3683
3684	3211	MCFG_SPEAKER_STANDARD_MONO("mono")
3685	3212
3686	3213	MCFG_SOUND_ADD("beeper", BEEP, 0)
3687	3214	MCFG_SOUND_ROUTE(ALL_OUTPUTS,"mono",0.15)
	3215	MCFG_GFXDECODE_ADD("gfxdecode", "palette", pc9801)
3688	3216	MACHINE_CONFIG_END
3689	3217
	3218	static MACHINE_CONFIG_START( pc9801, pc9801_state )
	3219	MCFG_CPU_ADD("maincpu", I8086, 5000000) //unknown clock
	3220	MCFG_CPU_PROGRAM_MAP(pc9801_map)
	3221	MCFG_CPU_IO_MAP(pc9801_io)
	3222	MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
	3223	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
	3224
	3225	MCFG_FRAGMENT_ADD(pc9801_common)
	3226
	3227	MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9801f)
	3228	MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9801f)
3690	3229	#if 0
	3230	MCFG_RAM_ADD(RAM_TAG)
	3231	MCFG_RAM_DEFAULT_SIZE("128K")
	3232	MCFG_RAM_EXTRA_OPTIONS("256K,384K,512K,640K")
	3233	#endif
	3234
	3235	MCFG_UPD765A_ADD("upd765_2dd", false, true)
	3236	MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, fdc_2dd_irq))
	3237	MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq3_w)) MCFG_DEVCB_INVERT
	3238	MCFG_FLOPPY_DRIVE_ADD("upd765_2dd:0", pc9801_floppies, "525dd", pc9801_state::floppy_formats)
	3239	MCFG_FLOPPY_DRIVE_ADD("upd765_2dd:1", pc9801_floppies, "525dd", pc9801_state::floppy_formats)
	3240
	3241	MCFG_FRAGMENT_ADD(pc9801_sasi)
	3242	MCFG_UPD1990A_ADD(UPD1990A_TAG, XTAL_32_768kHz, NULL, NULL)
	3243
	3244	MCFG_DEVICE_MODIFY("i8237")
	3245	MCFG_I8237_IN_IOR_3_CB(DEVREAD8("upd765_2dd", upd765a_device, mdma_r))
	3246	MCFG_I8237_OUT_IOW_3_CB(DEVWRITE8("upd765_2dd", upd765a_device, mdma_w))
	3247
	3248	MCFG_PALETTE_ADD("palette", 16)
	3249	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
	3250	MACHINE_CONFIG_END
	3251
	3252	#if 0
3691	3253	static MACHINE_CONFIG_DERIVED( pc9801vm, pc9801 )
3692	3254	MCFG_CPU_REPLACE("maincpu",V30,10000000)
3693	3255	MCFG_CPU_PROGRAM_MAP(pc9801_map)
r241786	r241787
3697	3259	#endif
3698	3260
3699	3261	static MACHINE_CONFIG_START( pc9801rs, pc9801_state )
3700		MCFG_CPU_ADD("maincpu", I386, MAIN_CLOCK_X1*8) // unknown clock.
	3262	MCFG_CPU_ADD("maincpu", I386SX, MAIN_CLOCK_X1*8) // unknown clock.
3701	3263	MCFG_CPU_PROGRAM_MAP(pc9801rs_map)
3702	3264	MCFG_CPU_IO_MAP(pc9801rs_io)
3703	3265	MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3704	3266	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
3705	3267
	3268	MCFG_FRAGMENT_ADD(pc9801_common)
	3269
3706	3270	MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9801rs)
3707	3271	MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9801rs)
3708	3272
3709		MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
3710		MCFG_PIT8253_CLK0(MAIN_CLOCK_X1) /* heartbeat IRQ */
3711		MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic8259_master", pic8259_device, ir0_w))
3712		MCFG_PIT8253_CLK1(MAIN_CLOCK_X1) /* Memory Refresh */
3713		MCFG_PIT8253_CLK2(MAIN_CLOCK_X1) /* RS-232c */
3714		MCFG_PIT8253_OUT2_HANDLER(WRITELINE(pc9801_state, write_uart_clock))
	3273	MCFG_DEVICE_MODIFY("i8237")
	3274	MCFG_DEVICE_CLOCK(MAIN_CLOCK_X1*8); // unknown clock
3715	3275
3716		MCFG_DEVICE_ADD("i8237", AM9517A, MAIN_CLOCK_X1*8) // unknown clock
3717		MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc9801_state, pc9801_dma_hrq_changed))
3718		MCFG_I8237_OUT_EOP_CB(WRITELINE(pc9801_state, pc9801_tc_w))
3719		MCFG_I8237_IN_MEMR_CB(READ8(pc9801_state, pc9801_dma_read_byte))
3720		MCFG_I8237_OUT_MEMW_CB(WRITE8(pc9801_state, pc9801_dma_write_byte))
3721		MCFG_I8237_IN_IOR_2_CB(READ8(pc9801_state, fdc_2hd_r))
3722		MCFG_I8237_OUT_IOW_2_CB(WRITE8(pc9801_state, fdc_2hd_w))
3723		MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc9801_state, pc9801_dack0_w))
3724		MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc9801_state, pc9801_dack1_w))
3725		MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc9801_state, pc9801_dack2_w))
3726		MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc9801_state, pc9801_dack3_w))
3727		MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE("maincpu", 0), VCC, READ8(pc9801_state,get_slave_ack) )
3728		MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir7_w), GND, NULL ) // TODO: Check ir7_w
3729
3730		MCFG_DEVICE_ADD("ppi8255_sys", I8255, 0)
3731		MCFG_I8255_IN_PORTA_CB(IOPORT("DSW2"))
3732		MCFG_I8255_IN_PORTB_CB(IOPORT("DSW1"))
3733		MCFG_I8255_IN_PORTC_CB(READ8(pc9801_state, ppi_sys_portc_r))
3734		MCFG_I8255_OUT_PORTC_CB(WRITE8(pc9801_state, ppi_sys_portc_w))
3735
3736		MCFG_DEVICE_ADD("ppi8255_prn", I8255, 0)
3737		/* TODO: check this one */
3738		MCFG_I8255_IN_PORTB_CB(IOPORT("DSW5"))
3739
3740		MCFG_DEVICE_ADD("ppi8255_fdd", I8255, 0)
3741		MCFG_I8255_IN_PORTA_CB(READ8(pc9801_state, ppi_fdd_porta_r))
3742		MCFG_I8255_IN_PORTB_CB(READ8(pc9801_state, ppi_fdd_portb_r))
3743		MCFG_I8255_IN_PORTC_CB(READ8(pc9801_state, ppi_fdd_portc_r))
3744		MCFG_I8255_OUT_PORTC_CB(WRITE8(pc9801_state, ppi_fdd_portc_w))
3745
3746		MCFG_FRAGMENT_ADD(pc9801_keyboard)
3747		MCFG_FRAGMENT_ADD(pc9801_mouse)
3748	3276	MCFG_FRAGMENT_ADD(pc9801_ide)
3749	3277	MCFG_UPD4990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
3750		MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
3751	3278
3752		MCFG_UPD765A_ADD("upd765_2hd", true, true)
3753		MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_irq))
3754		MCFG_UPD765_DRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_drq))
3755		//"upd765_2dd"
3756		MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:0", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3757		MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:1", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3758
3759		MCFG_SOFTWARE_LIST_ADD("disk_list","pc98")
3760
3761		MCFG_FRAGMENT_ADD(pc9801_cbus)
3762
3763	3279	MCFG_RAM_ADD(RAM_TAG)
3764	3280	MCFG_RAM_DEFAULT_SIZE("1664K")
3765	3281	MCFG_RAM_EXTRA_OPTIONS("640K,3712K,7808K")
3766	3282
3767		MCFG_SCREEN_ADD("screen", RASTER)
3768		MCFG_SCREEN_REFRESH_RATE(60)
3769		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
3770		MCFG_SCREEN_UPDATE_DRIVER(pc9801_state, screen_update)
3771		MCFG_SCREEN_SIZE(640, 480)
3772		MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
3773
3774		MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
3775		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
3776		MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
3777		MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
3778
3779		MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
	3283	MCFG_DEVICE_MODIFY("upd7220_btm")
3780	3284	MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_grcg_2_map)
3781		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
3782	3285
3783	3286	MCFG_PALETTE_ADD("palette", 16+16)
3784	3287	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
3785		MCFG_GFXDECODE_ADD("gfxdecode", "palette", pc9801)
3786
3787		MCFG_SPEAKER_STANDARD_MONO("mono")
3788
3789		//  MCFG_SOUND_ADD("opna", YM2608, MAIN_CLOCK_X1*4) // unknown clock / divider
3790		//  MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
3791
3792		MCFG_SOUND_ADD("beeper", BEEP, 0)
3793		MCFG_SOUND_ROUTE(ALL_OUTPUTS,"mono",0.15)
3794	3288	MACHINE_CONFIG_END
3795	3289
3796	3290	static MACHINE_CONFIG_DERIVED( pc9801ux, pc9801rs )
r241786	r241787
3805	3299
3806	3300	static MACHINE_CONFIG_DERIVED( pc9801bx2, pc9801rs )
3807	3301	MCFG_CPU_REPLACE("maincpu",I486,25000000)
3808		MCFG_CPU_PROGRAM_MAP(pc9801rs_map)
3809		MCFG_CPU_IO_MAP(pc9801bx2_io)
	3302	MCFG_CPU_PROGRAM_MAP(pc9821_map)
	3303	MCFG_CPU_IO_MAP(pc9821_io)
3810	3304	MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3811	3305	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
3812	3306
3813	3307	MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9801bx2)
3814	3308	MACHINE_CONFIG_END
3815	3309
3816		static MACHINE_CONFIG_START( pc9821, pc9801_state )
3817		MCFG_CPU_ADD("maincpu", I486, 16000000) // unknown clock
	3310	static MACHINE_CONFIG_DERIVED( pc9821, pc9801rs )
	3311	MCFG_CPU_REPLACE("maincpu", I486, 16000000) // unknown clock
3818	3312	MCFG_CPU_PROGRAM_MAP(pc9821_map)
3819	3313	MCFG_CPU_IO_MAP(pc9821_io)
3820	3314	MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3821	3315	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
3822	3316
	3317	MCFG_DEVICE_MODIFY("pit8253")
	3318	MCFG_PIT8253_CLK0(MAIN_CLOCK_X2)
	3319	MCFG_PIT8253_CLK1(MAIN_CLOCK_X2)
	3320	MCFG_PIT8253_CLK2(MAIN_CLOCK_X2)
	3321
3823	3322	MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9821)
3824	3323	MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9821)
3825	3324
3826		MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
3827		MCFG_PIT8253_CLK0(MAIN_CLOCK_X2) /* heartbeat IRQ */
3828		MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic8259_master", pic8259_device, ir0_w))
3829		MCFG_PIT8253_CLK1(MAIN_CLOCK_X2) /* Memory Refresh */
3830		MCFG_PIT8253_CLK2(MAIN_CLOCK_X2) /* RS-232c */
3831		MCFG_PIT8253_OUT2_HANDLER(WRITELINE(pc9801_state, write_uart_clock))
	3325	MCFG_DEVICE_MODIFY("i8237")
	3326	MCFG_DEVICE_CLOCK(16000000); // unknown clock
3832	3327
3833		MCFG_DEVICE_ADD("i8237", AM9517A, 16000000) // unknown clock
3834		MCFG_I8237_OUT_HREQ_CB(WRITELINE(pc9801_state, pc9801_dma_hrq_changed))
3835		MCFG_I8237_OUT_EOP_CB(WRITELINE(pc9801_state, pc9801_tc_w))
3836		MCFG_I8237_IN_MEMR_CB(READ8(pc9801_state, pc9801_dma_read_byte))
3837		MCFG_I8237_OUT_MEMW_CB(WRITE8(pc9801_state, pc9801_dma_write_byte))
3838		MCFG_I8237_IN_IOR_2_CB(READ8(pc9801_state, fdc_2hd_r))
3839		MCFG_I8237_OUT_IOW_2_CB(WRITE8(pc9801_state, fdc_2hd_w))
3840		MCFG_I8237_OUT_DACK_0_CB(WRITELINE(pc9801_state, pc9801_dack0_w))
3841		MCFG_I8237_OUT_DACK_1_CB(WRITELINE(pc9801_state, pc9801_dack1_w))
3842		MCFG_I8237_OUT_DACK_2_CB(WRITELINE(pc9801_state, pc9801_dack2_w))
3843		MCFG_I8237_OUT_DACK_3_CB(WRITELINE(pc9801_state, pc9801_dack3_w))
3844		MCFG_PIC8259_ADD( "pic8259_master", INPUTLINE("maincpu", 0), VCC, READ8(pc9801_state,get_slave_ack) )
3845		MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir7_w), GND, NULL ) // TODO: Check ir7_w
3846
3847		MCFG_DEVICE_ADD("ppi8255_sys", I8255, 0)
3848		MCFG_I8255_IN_PORTA_CB(IOPORT("DSW2"))
3849		MCFG_I8255_IN_PORTB_CB(IOPORT("DSW1"))
3850		MCFG_I8255_IN_PORTC_CB(READ8(pc9801_state, ppi_sys_portc_r))
3851		MCFG_I8255_OUT_PORTC_CB(WRITE8(pc9801_state, ppi_sys_portc_w))
3852
3853		MCFG_DEVICE_ADD("ppi8255_prn", I8255, 0)
3854		/* TODO: check this one */
3855		MCFG_I8255_IN_PORTB_CB(IOPORT("DSW5"))
3856
3857		MCFG_DEVICE_ADD("ppi8255_fdd", I8255, 0)
3858		MCFG_I8255_IN_PORTA_CB(READ8(pc9801_state, ppi_fdd_porta_r))
3859		MCFG_I8255_IN_PORTB_CB(READ8(pc9801_state, ppi_fdd_portb_r))
3860		MCFG_I8255_IN_PORTC_CB(READ8(pc9801_state, ppi_fdd_portc_r))
3861		MCFG_I8255_OUT_PORTC_CB(WRITE8(pc9801_state, ppi_fdd_portc_w))
3862
3863		MCFG_FRAGMENT_ADD(pc9801_keyboard)
3864		MCFG_FRAGMENT_ADD(pc9801_mouse)
3865		MCFG_FRAGMENT_ADD(pc9801_ide)
3866		MCFG_UPD4990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
3867		MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
3868
3869		MCFG_UPD765A_ADD("upd765_2hd", false, true)
3870		MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE("pic8259_slave", pic8259_device, ir3_w))
3871		MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE("i8237", am9517a_device, dreq2_w)) MCFG_DEVCB_INVERT
3872		//"upd765_2dd"
3873		MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:0", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3874		MCFG_FLOPPY_DRIVE_ADD("upd765_2hd:1", pc9801_floppies, "525hd", pc9801_state::floppy_formats)
3875
3876		MCFG_SOFTWARE_LIST_ADD("disk_list","pc98")
3877
3878		MCFG_FRAGMENT_ADD(pc9801_cbus)
3879
3880		MCFG_RAM_ADD(RAM_TAG)
3881		MCFG_RAM_DEFAULT_SIZE("1664K")
3882		MCFG_RAM_EXTRA_OPTIONS("3712K,7808K")
3883
3884		MCFG_SCREEN_ADD("screen", RASTER)
3885		MCFG_SCREEN_REFRESH_RATE(60)
3886		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
3887		MCFG_SCREEN_UPDATE_DRIVER(pc9801_state, screen_update)
3888		MCFG_SCREEN_SIZE(640, 480)
3889		MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 200-1)
3890
3891		MCFG_DEVICE_ADD("upd7220_chr", UPD7220, 5000000/2)
3892		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_1_map)
3893		MCFG_UPD7220_DRAW_TEXT_CALLBACK_OWNER(pc9801_state, hgdc_draw_text)
3894		MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
3895
3896		MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
3897		MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_grcg_2_map)
3898		MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
3899
	3328	MCFG_DEVICE_REMOVE("palette")
3900	3329	MCFG_PALETTE_ADD("palette", 16+16+256)
3901	3330	MCFG_PALETTE_INIT_OWNER(pc9801_state,pc9801)
3902		MCFG_GFXDECODE_ADD("gfxdecode", "palette", pc9801)
3903
3904		MCFG_SPEAKER_STANDARD_MONO("mono")
3905
3906		//  MCFG_SOUND_ADD("opna", YM2608, MAIN_CLOCK_X1*4) // unknown clock / divider
3907		//  MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
3908
3909		MCFG_SOUND_ADD("beeper", BEEP, 0)
3910		MCFG_SOUND_ROUTE(ALL_OUTPUTS,"mono",0.15)
3911	3331	MACHINE_CONFIG_END
3912	3332
3913	3333	static MACHINE_CONFIG_DERIVED( pc9821ap2, pc9821)

https://github.com/mamedev/mame/commit/1f75bdc6f6627abfe42f0fbafa576c491e28d053

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