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r33263 Friday 7th November, 2014 at 13:28:05 UTC by Olivier Galibert
pci: A little more, reaches an unemulated pslldq at fd228 [O. Galibert]

[src/emu/machine]

i6300esb.c i6300esb.h pci.c pci.h

trunk/src/emu/machine/i6300esb.c

r241774	r241775
29	29	AM_RANGE(0xe4, 0xe7) AM_READWRITE16(gen1_dec_r,  gen1_dec_w,  0x0000ffff)
30	30	AM_RANGE(0xe4, 0xe7) AM_READWRITE16(lpc_en_r,    lpc_en_w,    0xffff0000)
31	31	AM_RANGE(0xe8, 0xeb) AM_READWRITE  (fwh_sel1_r,  fwh_sel1_w)
	32	AM_RANGE(0xfc, 0xff) AM_READWRITE  (unk_fc_r,    unk_fc_w)
32	33
33	34	AM_INHERIT_FROM(pci_device::config_map)
34	35	ADDRESS_MAP_END
35	36
	37	DEVICE_ADDRESS_MAP_START(internal_io_map, 32, i6300esb_lpc_device)
	38	if(lpc_en & 0x2000) {
	39	AM_RANGE(0x004c, 0x004f) AM_READWRITE8(siu_config_port_r, siu_config_port_w, 0x00ff0000)
	40	AM_RANGE(0x004c, 0x004f) AM_READWRITE8(siu_data_port_r,   siu_data_port_w,   0xff000000)
	41	}
36	42
	43	AM_RANGE(0x80, 0x83) AM_WRITE8(                  nop_w,       0x000000ff) // POST/non-existing, used for delays by the bios/os
	44	AM_RANGE(0xec, 0xef) AM_WRITE8(                  nop_w,       0x0000ff00) // Non-existing, used for delays by the bios/os
	45	ADDRESS_MAP_END
	46
	47
37	48	i6300esb_lpc_device::i6300esb_lpc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
38	49	: pci_device(mconfig, I6300ESB_LPC, "i6300ESB southbridge ISA/LPC bridge", tag, owner, clock, "i6300esb_lpc", __FILE__)
39	50	{
r241774	r241775
47	58	void i6300esb_lpc_device::device_reset()
48	59	{
49	60	pci_device::device_reset();
	61	siu_config_port = 0;
	62	siu_config_state = 0;
	63	}
	64
	65	void i6300esb_lpc_device::reset_all_mappings()
	66	{
50	67	gpio_base = 0;
51	68	gpio_cntl = 0x00;
	69	lpc_if_com_range = 0x00;
	70	lpc_if_fdd_lpt_range = 0x00;
	71	lpc_if_sound_range = 0x00;
	72	fwh_dec_en1 = 0xff;
52	73	gen1_dec = 0x0000;
53		lpc_en = 0x0000;
	74	lpc_en = 0x2000;
54	75	fwh_sel1 = 0x00112233;
55	76	}
56	77
r241774	r241775
77	98	logerror("%s: gpio_cntl = %02x\n", tag(), gpio_cntl);
78	99	}
79	100
	101	READ8_MEMBER  (i6300esb_lpc_device::lpc_if_com_range_r)
	102	{
	103	return lpc_if_com_range;
	104	}
	105
	106	WRITE8_MEMBER (i6300esb_lpc_device::lpc_if_com_range_w)
	107	{
	108	COMBINE_DATA(&lpc_if_com_range);
	109	logerror("%s: lpc_if_com_range  = %02x\n", tag(), lpc_if_com_range);
	110	}
	111
	112	READ8_MEMBER  (i6300esb_lpc_device::lpc_if_fdd_lpt_range_r)
	113	{
	114	return lpc_if_fdd_lpt_range;
	115	}
	116
	117	WRITE8_MEMBER (i6300esb_lpc_device::lpc_if_fdd_lpt_range_w)
	118	{
	119	COMBINE_DATA(&lpc_if_fdd_lpt_range);
	120	logerror("%s: lpc_if_fdd_lpt_range  = %02x\n", tag(), lpc_if_fdd_lpt_range);
	121	}
	122
	123	READ8_MEMBER  (i6300esb_lpc_device::lpc_if_sound_range_r)
	124	{
	125	return lpc_if_sound_range;
	126	}
	127
	128	WRITE8_MEMBER (i6300esb_lpc_device::lpc_if_sound_range_w)
	129	{
	130	COMBINE_DATA(&lpc_if_sound_range);
	131	logerror("%s: lpc_if_sound_range  = %02x\n", tag(), lpc_if_sound_range);
	132	}
	133
	134	READ8_MEMBER  (i6300esb_lpc_device::fwh_dec_en1_r)
	135	{
	136	return fwh_dec_en1;
	137	}
	138
	139	WRITE8_MEMBER (i6300esb_lpc_device::fwh_dec_en1_w)
	140	{
	141	fwh_dec_en1 = data | 0x80;
	142	logerror("%s: fwh_dec_en1  = %02x\n", tag(), fwh_dec_en1);
	143	}
	144
80	145	READ16_MEMBER (i6300esb_lpc_device::gen1_dec_r)
81	146	{
82	147	return gen1_dec;
r241774	r241775
110	175	logerror("%s: fwh_sel1 = %08x\n", tag(), fwh_sel1);
111	176	}
112	177
	178	READ32_MEMBER (i6300esb_lpc_device::unk_fc_r)
	179	{
	180	logerror("%s: read undocumented config reg fc\n", tag());
	181	return 0;
	182	}
	183
	184	WRITE32_MEMBER(i6300esb_lpc_device::unk_fc_w)
	185	{
	186	logerror("%s: write undocumented config reg fc (%08x)\n", tag(), data);
	187	}
	188
	189
	190
	191	READ8_MEMBER  (i6300esb_lpc_device::siu_config_port_r)
	192	{
	193	return siu_config_port;
	194	}
	195
	196	WRITE8_MEMBER (i6300esb_lpc_device::siu_config_port_w)
	197	{
	198	siu_config_port = data;
	199	switch(siu_config_state) {
	200	case 0:
	201	siu_config_state = data == 0x80 ? 1 : 0;
	202	break;
	203	case 1:
	204	siu_config_state = data == 0x86 ? 2 : data == 0x80 ? 1 : 0;
	205	if(siu_config_state == 2)
	206	logerror("%s: siu configuration active\n", tag());
	207	break;
	208	case 2:
	209	siu_config_state = data == 0x68 ? 3 : 2;
	210	break;
	211	case 3:
	212	siu_config_state = data == 0x08 ? 0 : data == 0x68 ? 3 : 2;
	213	if(!siu_config_state)
	214	logerror("%s: siu configuration disabled\n", tag());
	215	break;
	216	}
	217	}
	218
	219	READ8_MEMBER  (i6300esb_lpc_device::siu_data_port_r)
	220	{
	221	logerror("%s: siu config read port %02x\n", tag(), siu_config_port);
	222	return 0xff;
	223	}
	224
	225	WRITE8_MEMBER (i6300esb_lpc_device::siu_data_port_w)
	226	{
	227	if(siu_config_state < 2) {
	228	logerror("%s: siu config write port with config disabled (port=%02x, data=%02x)\n", tag(), siu_config_port, data);
	229	return;
	230	}
	231	logerror("%s: siu config write port %02x, %02x\n", tag(), siu_config_port, data);
	232	}
	233
	234	WRITE8_MEMBER (i6300esb_lpc_device::nop_w)
	235	{
	236	}
	237
	238	void i6300esb_lpc_device::map_bios(address_space *memory_space, UINT32 start, UINT32 end, int idsel)
	239	{
	240	// Ignore idsel, a16 inversion for now
	241	UINT32 mask = m_region->bytes() - 1;
	242	memory_space->install_rom(start, end, m_region->base() + (start & mask));
	243	}
	244
113	245	void i6300esb_lpc_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
114	246	UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
115	247	{
116		memory_space->install_rom(0xfff00000, 0xffffffff, m_region->base());
117		memory_space->install_rom(0x000f0000, 0x000fffff, m_region->base()+0xf0000);
	248	if(fwh_dec_en1 & 0x80) {
	249	map_bios(memory_space, 0xfff80000, 0xffffffff, 7);
	250	map_bios(memory_space, 0xffb80000, 0xffbfffff, 7);
	251	map_bios(memory_space, 0x000e0000, 0x000fffff, 7);
	252	}
	253	if(fwh_dec_en1 & 0x40) {
	254	map_bios(memory_space, 0xfff00000, 0xfff7ffff, 6);
	255	map_bios(memory_space, 0xffb00000, 0xffb7ffff, 6);
	256	}
	257	if(fwh_dec_en1 & 0x20) {
	258	map_bios(memory_space, 0xffe80000, 0xffefffff, 5);
	259	map_bios(memory_space, 0xffa80000, 0xffafffff, 5);
	260	}
	261	if(fwh_dec_en1 & 0x10) {
	262	map_bios(memory_space, 0xffe00000, 0xffe7ffff, 4);
	263	map_bios(memory_space, 0xffa00000, 0xffa7ffff, 4);
	264	}
	265	if(fwh_dec_en1 & 0x08) {
	266	map_bios(memory_space, 0xffd80000, 0xffdfffff, 3);
	267	map_bios(memory_space, 0xff980000, 0xff9fffff, 3);
	268	}
	269	if(fwh_dec_en1 & 0x04) {
	270	map_bios(memory_space, 0xffd00000, 0xffd7ffff, 2);
	271	map_bios(memory_space, 0xff900000, 0xff97ffff, 2);
	272	}
	273	if(fwh_dec_en1 & 0x02) {
	274	map_bios(memory_space, 0xffc80000, 0xffcfffff, 1);
	275	map_bios(memory_space, 0xff880000, 0xff8fffff, 1);
	276	}
	277	if(fwh_dec_en1 & 0x01) {
	278	map_bios(memory_space, 0xffc00000, 0xffc7ffff, 0);
	279	map_bios(memory_space, 0xff800000, 0xff87ffff, 0);
	280	}
	281
	282	io_space->install_device(0, 0xffff, *this, &i6300esb_lpc_device::internal_io_map);
118	283	}
119	284

trunk/src/emu/machine/i6300esb.h

r241774	r241775
15	15	public:
16	16	i6300esb_lpc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
17	17
	18	virtual void reset_all_mappings();
18	19	virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
19	20	UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
20	21
21	22	virtual DECLARE_ADDRESS_MAP(config_map, 32);
22	23
	24
23	25	protected:
24	26	virtual void device_start();
25	27	virtual void device_reset();
26	28
27	29	private:
	30	DECLARE_ADDRESS_MAP(internal_io_map, 32);
	31
28	32	UINT32 gpio_base, fwh_sel1;
29	33	UINT16 gen1_dec, lpc_en;
30		UINT8 gpio_cntl;
	34	UINT8 gpio_cntl, lpc_if_com_range, lpc_if_fdd_lpt_range, lpc_if_sound_range, fwh_dec_en1, siu_config_port;
	35	int siu_config_state;
31	36
32		DECLARE_READ32_MEMBER (gpio_base_r); // 58
	37	DECLARE_WRITE8_MEMBER (nop_w);
	38
	39	// configuration space registers
	40	DECLARE_READ32_MEMBER (gpio_base_r);            // 58
33	41	DECLARE_WRITE32_MEMBER(gpio_base_w);
34		DECLARE_READ8_MEMBER  (gpio_cntl_r); // 5c
	42	DECLARE_READ8_MEMBER  (gpio_cntl_r);            // 5c
35	43	DECLARE_WRITE8_MEMBER (gpio_cntl_w);
36	44
37		DECLARE_READ16_MEMBER (gen1_dec_r);  // e4
	45	DECLARE_READ8_MEMBER  (lpc_if_com_range_r);     // e0
	46	DECLARE_WRITE8_MEMBER (lpc_if_com_range_w);
	47	DECLARE_READ8_MEMBER  (lpc_if_fdd_lpt_range_r); // e1
	48	DECLARE_WRITE8_MEMBER (lpc_if_fdd_lpt_range_w);
	49	DECLARE_READ8_MEMBER  (lpc_if_sound_range_r);   // e2
	50	DECLARE_WRITE8_MEMBER (lpc_if_sound_range_w);
	51	DECLARE_READ8_MEMBER  (fwh_dec_en1_r);          // e3
	52	DECLARE_WRITE8_MEMBER (fwh_dec_en1_w);
	53	DECLARE_READ16_MEMBER (gen1_dec_r);             // e4
38	54	DECLARE_WRITE16_MEMBER(gen1_dec_w);
39		DECLARE_READ16_MEMBER (lpc_en_r);  // e6
	55	DECLARE_READ16_MEMBER (lpc_en_r);               // e6
40	56	DECLARE_WRITE16_MEMBER(lpc_en_w);
41		DECLARE_READ32_MEMBER (fwh_sel1_r);  // e8
	57	DECLARE_READ32_MEMBER (fwh_sel1_r);             // e8
42	58	DECLARE_WRITE32_MEMBER(fwh_sel1_w);
	59
	60	DECLARE_READ32_MEMBER (unk_fc_r);               // fc
	61	DECLARE_WRITE32_MEMBER(unk_fc_w);
	62
	63
	64	// i/o space registers
	65	DECLARE_READ8_MEMBER  (siu_config_port_r);      // 4e
	66	DECLARE_WRITE8_MEMBER (siu_config_port_w);
	67	DECLARE_READ8_MEMBER  (siu_data_port_r);        // 4f
	68	DECLARE_WRITE8_MEMBER (siu_data_port_w);
	69
	70	void map_bios(address_space *memory_space, UINT32 start, UINT32 end, int idsel);
43	71	};
44	72
45	73	class i6300esb_watchdog_device : public pci_device {

trunk/src/emu/machine/pci.c

r241774	r241775
4	4	const device_type PCI_BRIDGE = &device_creator<pci_bridge_device>;
5	5
6	6	DEVICE_ADDRESS_MAP_START(config_map, 32, pci_device)
	7	AM_RANGE(0x00, 0x03) AM_READ16(vendor_r,          0x0000ffff)
	8	AM_RANGE(0x00, 0x03) AM_READ16(device_r,          0xffff0000)
	9
	10	AM_RANGE(0x08, 0x0b) AM_READ  (class_rev_r)
	11	AM_RANGE(0x0c, 0x0f) AM_READ8 (cache_line_size_r, 0x000000ff)
	12	AM_RANGE(0x0c, 0x0f) AM_READ8 (latency_timer_r,   0x0000ff00)
	13	AM_RANGE(0x0c, 0x0f) AM_READ8 (header_type_r,     0x00ff0000)
	14	AM_RANGE(0x0c, 0x0f) AM_READ8 (bist_r,            0xff000000)
	15
	16	AM_RANGE(0x2c, 0x2f) AM_READ16(subvendor_r,          0x0000ffff)
	17	AM_RANGE(0x2c, 0x2f) AM_READ16(subsystem_r,          0xffff0000)
7	18	ADDRESS_MAP_END
8	19
9	20	pci_device::pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
r241774	r241775
12	23	main_id = 0xffffffff;
13	24	revision = 0x00;
14	25	pclass = 0xffffff;
15		subdevice_id = 0xffffffff;
	26	subsystem_id = 0xffffffff;
16	27	}
17	28
18		void pci_device::set_ids(UINT32 _main_id, UINT8 _revision, UINT32 _pclass, UINT32 _subdevice_id)
	29	void pci_device::set_ids(UINT32 _main_id, UINT8 _revision, UINT32 _pclass, UINT32 _subsystem_id)
19	30	{
20	31	main_id = _main_id;
21	32	revision = _revision;
22	33	pclass = _pclass;
23		subdevice_id = _subdevice_id;
	34	subsystem_id = _subsystem_id;
24	35	}
25	36
26	37	void pci_device::device_start()
r241774	r241775
31	42	{
32	43	}
33	44
	45	READ16_MEMBER(pci_device::vendor_r)
	46	{
	47	return main_id >> 16;
	48	}
	49
	50	READ16_MEMBER(pci_device::device_r)
	51	{
	52	return main_id;
	53	}
	54
	55	READ32_MEMBER(pci_device::class_rev_r)
	56	{
	57	return (pclass << 8) | revision;
	58	}
	59
	60	READ8_MEMBER(pci_device::cache_line_size_r)
	61	{
	62	return 0x00;
	63	}
	64
	65	READ8_MEMBER(pci_device::latency_timer_r)
	66	{
	67	return 0x00;
	68	}
	69
	70	READ8_MEMBER(pci_device::header_type_r)
	71	{
	72	return 0x00;
	73	}
	74
	75	READ8_MEMBER(pci_device::bist_r)
	76	{
	77	return 0x00;
	78	}
	79
	80	READ16_MEMBER(pci_device::subvendor_r)
	81	{
	82	return subsystem_id >> 16;
	83	}
	84
	85	READ16_MEMBER(pci_device::subsystem_r)
	86	{
	87	return subsystem_id;
	88	}
	89
34	90	void pci_device::scan_sub_devices(pci_device **devices, dynamic_array<pci_device *> &all, dynamic_array<pci_device *> &bridges, device_t *root)
35	91	{
36	92	}
r241774	r241775
92	148	{
93	149	}
94	150
	151	READ8_MEMBER(pci_bridge_device::header_type_r)
	152	{
	153	return 0x01;
	154	}
	155
95	156	const address_space_config *pci_bridge_device::memory_space_config(address_spacenum spacenum) const
96	157	{
97	158	return spacenum == AS_PROGRAM ? &configure_space_config : NULL;
r241774	r241775
110	171	sub_devices[i] = NULL;
111	172
112	173	for(device_t *d = bus_root()->first_subdevice(); d != NULL; d = d->next()) {
113		if(d == this)
114		continue;
115	174	const char *t = d->tag();
116	175	int l = strlen(t);
117	176	if(l <= 4 || t[l-5] != ':' || t[l-2] != '.')
r241774	r241775
123	182	for(int i=0; i<32*8; i++)
124	183	if(sub_devices[i]) {
125	184	all_devices.append(sub_devices[i]);
126		pci_bridge_device *bridge = dynamic_cast<pci_bridge_device *>(sub_devices[i]);
127		if(bridge)
128		all_bridges.append(bridge);
	185	if(sub_devices[i] != this) {
	186	pci_bridge_device *bridge = dynamic_cast<pci_bridge_device *>(sub_devices[i]);
	187	if(bridge)
	188	all_bridges.append(bridge);
	189	}
129	190	}
130	191	}
131	192
r241774	r241775
138	199	void pci_bridge_device::reset_all_mappings()
139	200	{
140	201	for(int i=0; i != all_devices.count(); i++)
141		all_devices[i]->reset_all_mappings();
	202	if(all_devices[i] != this)
	203	all_devices[i]->reset_all_mappings();
142	204	}
143	205
144	206
r241774	r241775
146	208	UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
147	209	{
148	210	for(int i = all_devices.count()-1; i>=0; i--)
149		all_devices[i]->map_device(memory_window_start, memory_window_end, memory_offset, memory_space,
150		io_window_start, io_window_end, io_offset, io_space);
	211	if(all_devices[i] != this)
	212	all_devices[i]->map_device(memory_window_start, memory_window_end, memory_offset, memory_space,
	213	io_window_start, io_window_end, io_offset, io_space);
151	214
152	215	map_extra(memory_window_start, memory_window_end, memory_offset, memory_space,
153	216	io_window_start, io_window_end, io_offset, io_space);
r241774	r241775
208	271	void pci_host_device::device_reset()
209	272	{
210	273	pci_bridge_device::device_reset();
211		for(int i=0; i != all_devices.count(); i++)
212		all_devices[i]->reset_all_mappings();
	274	reset_all_mappings();
213	275	regenerate_mapping();
214	276
215	277	config_address = 0;
r241774	r241775
217	279
218	280	void pci_host_device::regenerate_mapping()
219	281	{
	282	logerror("Regenerating mapping\n");
220	283	memory_space->unmap_readwrite(memory_window_start, memory_window_end);
221	284	io_space->unmap_readwrite(io_window_start, io_window_end);
222	285
r241774	r241775
224	287	io_window_start, io_window_end, io_offset, io_space);
225	288	}
226	289
227		void pci_host_device::regenerate_config_mapping()
228		{
229		pci_bridge_device::regenerate_config_mapping();
230		map_config(0, &space(AS_PROGRAM));
231		}
232
233	290	READ32_MEMBER(pci_host_device::config_address_r)
234	291	{
235	292	return config_address;

trunk/src/emu/machine/pci.h

r241774	r241775
6	6	#define MCFG_PCI_ROOT_ADD(_tag) \
7	7	MCFG_DEVICE_ADD(_tag, PCI_ROOT, 0)
8	8
9		#define MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subdevice_id) \
	9	#define MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id) \
10	10	MCFG_DEVICE_ADD(_tag, _type, 0) \
11		downcast<pci_device *>(device)->set_ids(_main_id, _revision, _pclass, _subdevice_id);
	11	downcast<pci_device *>(device)->set_ids(_main_id, _revision, _pclass, _subsystem_id);
12	12
13		#define MCFG_AGP_DEVICE_ADD(_tag, _type, _main_id, _revision, _subdevice_id) \
14		MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x030000, _subdevice_id)
	13	#define MCFG_AGP_DEVICE_ADD(_tag, _type, _main_id, _revision, _subsystem_id) \
	14	MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x030000, _subsystem_id)
15	15
16		#define MCFG_PCI_HOST_ADD(_tag, _type, _main_id, _revision, _subdevice_id) \
17		MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x060000, _subdevice_id)
	16	#define MCFG_PCI_HOST_ADD(_tag, _type, _main_id, _revision, _subsystem_id) \
	17	MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, 0x060000, _subsystem_id)
18	18
19	19	#define MCFG_PCI_BRIDGE_ADD(_tag, _main_id, _revision) \
20	20	MCFG_PCI_DEVICE_ADD(_tag, PCI_BRIDGE, _main_id, _revision, 0x060400, 0x00000000)
r241774	r241775
26	26	public:
27	27	pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
28	28
29		void set_ids(UINT32 main_id, UINT8 revision, UINT32 pclass, UINT32 subdevice_id);
	29	void set_ids(UINT32 main_id, UINT8 revision, UINT32 pclass, UINT32 subsystem_id);
30	30
31	31	virtual void reset_all_mappings();
32	32	virtual void map_device(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
r241774	r241775
38	38
39	39	virtual DECLARE_ADDRESS_MAP(config_map, 32);
40	40
	41	DECLARE_READ16_MEMBER(vendor_r);
	42	DECLARE_READ16_MEMBER(device_r);
	43	DECLARE_READ32_MEMBER(class_rev_r);
	44	virtual DECLARE_READ8_MEMBER(cache_line_size_r);
	45	virtual DECLARE_READ8_MEMBER(latency_timer_r);
	46	virtual DECLARE_READ8_MEMBER(header_type_r);
	47	virtual DECLARE_READ8_MEMBER(bist_r);
	48	DECLARE_READ16_MEMBER(subvendor_r);
	49	DECLARE_READ16_MEMBER(subsystem_r);
	50
41	51	protected:
42	52	enum {
43	53	M_MEM = 0,
r241774	r241775
47	57	M_PREF = 8
48	58	};
49	59
50		UINT32 main_id, subdevice_id;
	60	UINT32 main_id, subsystem_id;
51	61	UINT32 pclass;
52	62	UINT8 revision;
53	63
r241774	r241775
81	91	UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
82	92	virtual void reset_all_mappings();
83	93
	94	virtual DECLARE_READ8_MEMBER(header_type_r);
	95
84	96	protected:
85	97	pci_device *sub_devices[32*8];
86	98	dynamic_array<pci_device *> all_devices;
r241774	r241775
134	146	void config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
135	147
136	148	void regenerate_mapping();
137		virtual void regenerate_config_mapping();
138	149	};
139	150
140	151	class pci_root_device : public device_t {

https://github.com/mamedev/mame/commit/a6ce93036eb4ebfbcb89f395225767c0e23b14a0

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