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r33248 Thursday 6th November, 2014 at 22:00:48 UTC by Carl
(mess) pc9801: pipe bitmap 7220 vram access though grcg, enable ready line which fixes disk change detection (nw)
---
Also disabled reads while grcg is in rmw mode, this I'm not 100% certain about and needs more testing.
[src/mess/drivers]pc9801.c

trunk/src/mess/drivers/pc9801.c
r241759r241760
591591   DECLARE_READ8_MEMBER(pc9801_mouse_r);
592592   DECLARE_WRITE8_MEMBER(pc9801_mouse_w);
593593   DECLARE_WRITE8_MEMBER(pc9801rs_mouse_freq_w);
594   inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank);
595   inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data);
594   inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank,int vrambank);
595   inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank) { return m_pc9801rs_grcg_r(offset, vbank, m_vram_bank); }
596   inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,int vrambank,UINT8 data);
597   inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data) { m_pc9801rs_grcg_w(offset, vbank, m_vram_bank, data); }
596598   DECLARE_CUSTOM_INPUT_MEMBER(system_type_r);
597599   DECLARE_READ8_MEMBER(pc9801ux_gvram_r);
598600   DECLARE_WRITE8_MEMBER(pc9801ux_gvram_w);
599601   DECLARE_READ8_MEMBER(pc9801ux_gvram0_r);
600602   DECLARE_WRITE8_MEMBER(pc9801ux_gvram0_w);
603   DECLARE_READ8_MEMBER(upd7220_grcg_r);
604   DECLARE_WRITE8_MEMBER(upd7220_grcg_w);
601605   UINT32 pc9801_286_a20(bool state);
602606
603607   DECLARE_READ8_MEMBER(ide_hack_r);
r241759r241760
750754   TIMER_DEVICE_CALLBACK_MEMBER( mouse_irq_cb );
751755
752756   void pc9801_fdc_2hd_update_ready(floppy_image_device *, int);
753   inline UINT32 m_calc_grcg_addr(int i,UINT32 offset);
757   inline UINT32 m_calc_grcg_addr(int i,UINT32 offset,int vrambank);
754758
755759   DECLARE_DRIVER_INIT(pc9801_kanji);
756760   inline void set_dma_channel(int channel, int state);
r241759r241760
16451649   m_video_ram_2[offset+0x08000+m_vram_bank*0x20000] = data;
16461650}
16471651
1648inline UINT32 pc9801_state::m_calc_grcg_addr(int i,UINT32 offset)
1652inline UINT32 pc9801_state::m_calc_grcg_addr(int i,UINT32 offset,int vrambank)
16491653{
1650   return (offset) + (((i+1)*0x8000) & 0x1ffff) + (m_vram_bank*0x20000);
1654   return (offset) + (((i+1)*0x8000) & 0x1ffff) + (vrambank*0x20000);
16511655}
16521656
1653inline UINT8 pc9801_state::m_pc9801rs_grcg_r(UINT32 offset,int vbank)
1657inline UINT8 pc9801_state::m_pc9801rs_grcg_r(UINT32 offset,int vbank,int vrambank)
16541658{
1655   UINT8 res;
1659   UINT8 res = 0;
16561660
1657   if((m_grcg.mode & 0x80) == 0 || (m_grcg.mode & 0x40))
1658      res = m_video_ram_2[offset+vbank*0x8000+m_vram_bank*0x20000];
1659   else
1661   if(!(m_grcg.mode & 0x80))
1662      res = m_video_ram_2[offset+vbank*0x8000+vrambank*0x20000];
1663   else if(!(m_grcg.mode & 0x40))
16601664   {
16611665      int i;
16621666
r241759r241760
16641668      for(i=0;i<4;i++)
16651669      {
16661670         if((m_grcg.mode & (1 << i)) == 0)
1667            res |= (m_video_ram_2[m_calc_grcg_addr(i,offset)] ^ m_grcg.tile[i]);
1671            res |= (m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] ^ m_grcg.tile[i]);
16681672      }
16691673
16701674      res ^= 0xff;
r241759r241760
16731677   return res;
16741678}
16751679
1676inline void pc9801_state::m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data)
1680inline void pc9801_state::m_pc9801rs_grcg_w(UINT32 offset,int vbank,int vrambank,UINT8 data)
16771681{
16781682   if((m_grcg.mode & 0x80) == 0)
1679      m_video_ram_2[offset+vbank*0x8000+m_vram_bank*0x20000] = data;
1683      m_video_ram_2[offset+vbank*0x8000+vrambank*0x20000] = data;
16801684   else
16811685   {
16821686      int i;
r241759r241760
16871691         {
16881692            if((m_grcg.mode & (1 << i)) == 0)
16891693            {
1690               m_video_ram_2[m_calc_grcg_addr(i,offset)] &= ~data;
1691               m_video_ram_2[m_calc_grcg_addr(i,offset)] |= m_grcg.tile[i] & data;
1694               m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] &= ~data;
1695               m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] |= m_grcg.tile[i] & data;
16921696            }
16931697         }
16941698      }
r241759r241760
16981702         {
16991703            if((m_grcg.mode & (1 << i)) == 0)
17001704            {
1701               m_video_ram_2[m_calc_grcg_addr(i,offset)] = m_grcg.tile[i];
1705               m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] = m_grcg.tile[i];
17021706            }
17031707         }
17041708      }
17051709   }
17061710}
17071711
1712READ8_MEMBER(pc9801_state::upd7220_grcg_r)
1713{
1714   return m_pc9801rs_grcg_r(offset & 0x7fff, (offset >> 15) & 3, offset >> 17);
1715}
17081716
1717WRITE8_MEMBER(pc9801_state::upd7220_grcg_w)
1718{
1719   m_pc9801rs_grcg_w(offset & 0x7fff, (offset >> 15) & 3, offset >> 17, data);
1720}
1721
17091722READ8_MEMBER(pc9801_state::pc9801_mouse_r)
17101723{
17111724   if((offset & 1) == 0)
r241759r241760
27762789   AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram_2")
27772790ADDRESS_MAP_END
27782791
2792static ADDRESS_MAP_START( upd7220_grcg_2_map, AS_0, 8, pc9801_state )
2793   AM_RANGE(0x00000, 0x3ffff) AM_READWRITE(upd7220_grcg_r, upd7220_grcg_w) AM_SHARE("video_ram_2")
2794ADDRESS_MAP_END
27792795
27802796CUSTOM_INPUT_MEMBER(pc9801_state::system_type_r)
27812797{
r241759r241760
37303746   MCFG_FRAGMENT_ADD(pc9801_keyboard)
37313747   MCFG_FRAGMENT_ADD(pc9801_mouse)
37323748   MCFG_FRAGMENT_ADD(pc9801_ide)
3733   MCFG_UPD1990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
3749   MCFG_UPD4990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
37343750   MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
37353751
3736   MCFG_UPD765A_ADD("upd765_2hd", false, true)
3752   MCFG_UPD765A_ADD("upd765_2hd", true, true)
37373753   MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_irq))
37383754   MCFG_UPD765_DRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_drq))
37393755   //"upd765_2dd"
r241759r241760
37613777   MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
37623778
37633779   MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
3764   MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
3780   MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_grcg_2_map)
37653781   MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
37663782
37673783   MCFG_PALETTE_ADD("palette", 16+16)
r241759r241760
38473863   MCFG_FRAGMENT_ADD(pc9801_keyboard)
38483864   MCFG_FRAGMENT_ADD(pc9801_mouse)
38493865   MCFG_FRAGMENT_ADD(pc9801_ide)
3850   MCFG_UPD1990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
3866   MCFG_UPD4990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
38513867   MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
38523868
38533869   MCFG_UPD765A_ADD("upd765_2hd", false, true)
r241759r241760
38783894   MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
38793895
38803896   MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
3881   MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
3897   MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_grcg_2_map)
38823898   MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
38833899
38843900   MCFG_PALETTE_ADD("palette", 16+16+256)

https://github.com/mamedev/mame/commit/ad6fdd5ed6797f2497f480733095741e48e2bebe

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