trunk/src/mame/video/k007121.c
| r241732 | r241733 | |
|---|
| 7 | 7 | a single 64x32 one, or one of them can be moved to the side of screen, giving |
| 8 | 8 | a high score display suitable for vertical games. |
| 9 | 9 | The chip also generates clock and interrupt signals suitable for a 6809. |
| 10 | | It uses 0x2000 bytes of RAM for the tilemaps and sprites, and an additional |
| 11 | | 0x100 bytes, maybe for scroll RAM and line buffers. The maximum addressable |
| 10 | It uses 0x2000 bytes of static RAM for the tilemaps and sprite lists, and two |
| 11 | 64kx4bit DRAMs, presumably as a double frame buffer. The maximum addressable |
| 12 | 12 | ROM is 0x80000 bytes (addressed 16 bits at a time). Tile and sprite data both |
| 13 | | come from the same ROM space. |
| 13 | come from the same ROM space. Like the 005885, external circuitry can cause |
| 14 | tiles and sprites to be fetched from different ROMs (used by Haunted Castle). |
| 15 | |
| 14 | 16 | Two 256x4 lookup PROMs are also used to increase the color combinations. |
| 15 | 17 | All tilemap / sprite priority handling is done internally and the chip exports |
| 16 | 18 | 7 bits of color code, composed of 2 bits of palette bank, 1 bit indicating tile |
| r241732 | r241733 | |
|---|
| 27 | 29 | outputs: |
| 28 | 30 | - address lines for tilemap RAM (AX0-AX12) |
| 29 | 31 | - data lines for tilemap RAM (VO0-VO7) |
| 30 | | - address lines for the small RAM (FA0-FA7) |
| 31 | | - data lines for the small RAM (FD0-FD7) |
| 32 | - address lines for the DRAMs (FA0-FA7) |
| 33 | - control lines for the DRAMs (NWR0, NWR1, NRAS, NCAS, NOE) |
| 34 | - data lines for the DRAMs (FD0-FD7) |
| 32 | 35 | - address lines for the gfx ROMs (R0-R17) |
| 33 | 36 | - address lines for the tile lookup PROMs (VCF0-VCF3, VCB0-VCB3) |
| 34 | 37 | - address lines for the sprite lookup PROMs (OCB0-OCB3, OCF0-OCF3) |
trunk/src/mame/video/konamiic.txt
| r241732 | r241733 | |
|---|
| 211 | 211 | It manages sprites and 32x32 or 64x32 tilemap (only Double Dribble uses the |
| 212 | 212 | 64x32 one). |
| 213 | 213 | The chip also generates clock and interrupt signals suitable for a 6809. |
| 214 | | It uses 0x2000 bytes of RAM for the tilemaps and sprites, and an additional |
| 215 | | 0x100 bytes, maybe for scroll RAM and line buffers. The maximum addressable |
| 214 | It uses 0x2000 bytes of static RAM for the tilemaps and sprite lists, and two |
| 215 | 64kx4bit DRAMs, presumably as a double frame buffer. The maximum addressable |
| 216 | 216 | ROM is 0x20000 bytes (addressed 16 bits at a time). Tile and sprite data both |
| 217 | 217 | come from the same ROM space. Double Dribble and Jackal have external circuitry |
| 218 | 218 | to extend the limits and use separated addressing spaces for sprites and tiles. |
| r241732 | r241733 | |
|---|
| 234 | 234 | outputs: |
| 235 | 235 | - address lines for tilemap RAM (AX0-AX12) |
| 236 | 236 | - data lines for tilemap RAM (VO0-VO7) |
| 237 | | - address lines for the small RAM (FA0-FA7) |
| 238 | | - data lines for the small RAM (FD0-FD7) |
| 237 | - address lines for the DRAMs (FA0-FA7) |
| 238 | - control lines for the DRAMs (NWR0, NWR1, NRAS, NCAS, NFOE) |
| 239 | - data lines for the DRAMs (FD0-FD7) |
| 239 | 240 | - address lines for the gfx ROMs (R0-R15) |
| 240 | 241 | - address lines for the tile lookup PROMs (VCF0-VCF3, VCB0-VCB3) |
| 241 | 242 | - address lines for the sprite lookup PROMs (OCB0-OCB3, OCF0-OCF3) |