trunk/src/emu/cpu/tms0980/tms0980.c
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| 123 | 123 | #include "debugger.h" |
| 124 | 124 | #include "tms0980.h" |
| 125 | 125 | |
| 126 | | #define LOG 0 |
| 127 | 126 | |
| 128 | 127 | |
| 129 | 128 | const device_type TMS0980 = &device_creator<tms0980_cpu_device>; |
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| 236 | 235 | #define I_YNEC ( MICRO_MASK | M_YTP | M_CKN | M_NE ) |
| 237 | 236 | |
| 238 | 237 | |
| 239 | | static const UINT8 tms0980_c2_value[4] = |
| 240 | | { |
| 241 | | 0x00, 0x02, 0x01, 0x03 |
| 242 | | }; |
| 243 | | static const UINT8 tms0980_c3_value[8] = |
| 244 | | { |
| 245 | | 0x00, 0x04, 0x02, 0x06, 0x01, 0x05, 0x03, 0x07 |
| 246 | | }; |
| 247 | | static const UINT8 tms0980_c4_value[16] = |
| 248 | | { |
| 249 | | 0x00, 0x08, 0x04, 0x0C, 0x02, 0x0A, 0x06, 0x0E, 0x01, 0x09, 0x05, 0x0D, 0x03, 0x0B, 0x07, 0x0F |
| 250 | | }; |
| 238 | static const UINT8 tms0980_c2_value[4] = { 0, 2, 1, 3 }; |
| 239 | static const UINT8 tms0980_c3_value[8] = { 0, 4, 2, 6, 1, 5, 3, 7 }; |
| 240 | static const UINT8 tms0980_c4_value[16] = { 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF }; |
| 251 | 241 | static const UINT8 tms0980_bit_value[4] = { 1, 4, 2, 8 }; |
| 252 | | static const UINT8 tms0980_nbit_value[4] = { 0x0E, 0x0B, 0x0D, 0x07 }; |
| 242 | static const UINT8 tms0980_nbit_value[4] = { 0xE, 0xB, 0xD, 0x7 }; |
| 253 | 243 | |
| 254 | 244 | |
| 255 | 245 | static const UINT32 tms0980_decode[512] = |
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| 329 | 319 | }; |
| 330 | 320 | |
| 331 | 321 | |
| 332 | | static const UINT32 tms1000_default_decode[256] = { |
| 322 | static const UINT32 tms1000_default_decode[256] = |
| 323 | { |
| 333 | 324 | /* 0x00 */ |
| 334 | 325 | F_COMX, I_A8AAC, I_YNEA, I_TAM, I_TAMZA, I_A10AAC, I_A6AAC, I_DAN, |
| 335 | 326 | I_TKA, I_KNEZ, F_TDO, F_CLO, F_RSTR, F_SETR, I_IA, F_RETN, |
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| 371 | 362 | }; |
| 372 | 363 | |
| 373 | 364 | |
| 374 | | static const UINT32 tms1100_default_decode[256] = { |
| 365 | static const UINT32 tms1100_default_decode[256] = |
| 366 | { |
| 375 | 367 | /* 0x00 */ |
| 376 | 368 | I_MNEA, I_ALEM, I_YNEA, I_XMA, I_DYN, I_IYC, I_AMAAC, I_DMAN, |
| 377 | 369 | I_TKA, F_COMX, F_TDO, F_COMC, F_RSTR, F_SETR, I_KNEZ, F_RETN, |
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| 504 | 496 | |
| 505 | 497 | void tms1xxx_cpu_device::device_reset() |
| 506 | 498 | { |
| 507 | | m_pa = 0x0F; |
| 508 | | m_pb = 0x0F; |
| 499 | m_pa = 0xF; |
| 500 | m_pb = 0xF; |
| 509 | 501 | m_pc = 0; |
| 510 | 502 | m_dam = 0; |
| 511 | 503 | m_ca = 0; |
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| 620 | 612 | ( pc{5:4} == 11 && pc{0} == 1 ) => 10 |
| 621 | 613 | |
| 622 | 614 | */ |
| 623 | | static const UINT8 tms1000_next_pc[64] = { |
| 615 | static const UINT8 tms1000_next_pc[64] = |
| 616 | { |
| 624 | 617 | 0x01, 0x03, 0x05, 0x07, 0x09, 0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F, |
| 625 | 618 | 0x20, 0x22, 0x24, 0x26, 0x28, 0x2A, 0x2C, 0x2E, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3A, 0x3C, 0x3F, |
| 626 | 619 | 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1A, 0x1C, 0x1E, |
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| 711 | 704 | { |
| 712 | 705 | do |
| 713 | 706 | { |
| 714 | | // debugger_instruction_hook( this, ( ( m_pa << m_pc_size ) | m_pc ) << 1 ); |
| 715 | 707 | m_icount--; |
| 716 | 708 | switch( m_subcycle ) |
| 717 | 709 | { |
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| 811 | 803 | } |
| 812 | 804 | if ( m_decode & M_STO ) |
| 813 | 805 | { |
| 814 | | //printf("write ram %02x data %01x\n", m_ram_address, m_a ); |
| 815 | 806 | m_data->write_byte( m_ram_address, m_a ); |
| 816 | 807 | } |
| 817 | 808 | if ( m_decode & M_CKM ) |
| 818 | 809 | { |
| 819 | | //printf("write ram %02x data %01x\n", m_ram_address, m_cki_bus ); |
| 820 | 810 | m_data->write_byte( m_ram_address, m_cki_bus ); |
| 821 | 811 | } |
| 822 | 812 | } |
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| 824 | 814 | { |
| 825 | 815 | if ( m_decode & F_SBIT ) |
| 826 | 816 | { |
| 827 | | //printf("write ram %02x data %01x\n", m_ram_address, m_ram_data | tms0980_bit_value[ m_opcode & 0x03 ] ); |
| 828 | 817 | m_data->write_byte( m_ram_address, m_ram_data | tms0980_bit_value[ m_opcode & 0x03 ] ); |
| 829 | 818 | } |
| 830 | 819 | if ( m_decode & F_RBIT ) |
| 831 | 820 | { |
| 832 | | //printf("write ram %02x data %01x\n", m_ram_address, m_ram_data & tms0980_nbit_value[ m_opcode & 0x03 ] ); |
| 833 | 821 | m_data->write_byte( m_ram_address, m_ram_data & tms0980_nbit_value[ m_opcode & 0x03 ] ); |
| 834 | 822 | } |
| 835 | 823 | if ( m_decode & F_SETR ) |
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| 850 | 838 | { |
| 851 | 839 | logerror("unknown output pla mapping for status latch = %d and a = %X\n", m_status_latch, m_a); |
| 852 | 840 | } |
| 853 | | //if ( ( c_output_pla[ ( m_status_latch << 4 ) | m_a ] & 0xFF00 ) == 0xFF00 ) |
| 854 | | //printf("****** o output m_status_latch = %X, m_a = %X\n", m_status_latch, m_a); |
| 855 | | //else |
| 856 | | //printf("o output m_status_latch = %X, m_a = %X\n", m_status_latch, m_a); |
| 857 | 841 | |
| 858 | 842 | m_write_o( 0, m_o & m_o_mask, 0xffff ); |
| 859 | 843 | } |
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| 951 | 935 | m_opcode = m_program->read_byte( m_rom_address ); |
| 952 | 936 | } |
| 953 | 937 | next_pc(); |
| 954 | | if (LOG) |
| 955 | | logerror( "tms0980: read opcode %04x from %04x. Set pc to %04x\n", m_opcode, m_rom_address, m_pc ); |
| 956 | 938 | |
| 957 | 939 | /* ram address */ |
| 958 | 940 | m_ram_address = ( m_x << 4 ) | m_y; |